Address conversion method for target virtual address, processor and electronic device

Abstract

An address translation method, a processor, and an electronic device for a target virtual address. This method is used for a translation lookaside buffer, and the translation lookaside buffer stores at least one page table. The target virtual address includes a first address segment to an Nth address segment, where N is an integer greater than 1, and the first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. The method includes: according to the Kth address segment in the target virtual address, determining whether there is an associated page table stored in the translation lookaside buffer, where the associated page table is a page table stored in the translation lookaside buffer that has a correlation with the Kth address segment, 1 ≤ K < N and K is an integer; in response to there being an associated page table stored in the translation lookaside buffer, obtaining the Kth-level page table corresponding to the Kth address segment based on the associated page table to complete the query operation for the Kth-level page table, and the associated page table is different from the Kth-level page table. This method can improve the efficiency of address translation without increasing the capacity of the translation lookaside buffer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an address translation method, a processor, and an electronic device for a target virtual address. Background Art

[0002] In the field of computer technology, programmers can write programs using any virtual address (VA) within the range specified by the system. The address used by the central processing unit (CPU) when executing an application program is a virtual address. When allocating memory to a process, it is necessary to map the virtual address to a physical address (PA), and the physical address is the real physical memory access address. Distinguishing and using virtual addresses and physical addresses has become the mainstream trend in the industry. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides an address translation method for a target virtual address, which is used for a translation lookaside buffer. The translation lookaside buffer stores at least one page table. The target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. The method includes: judging whether an associated page table is stored in the translation lookaside buffer according to the Kth address segment in the target virtual address, where the associated page table is a page table stored in the translation lookaside buffer and having a correlation with the Kth address segment, 1≤K<N and K is an integer; in response to the associated page table being stored in the translation lookaside buffer, obtaining the Kth-level page table corresponding to the Kth address segment based on the associated page table to complete the query operation for the Kth-level page table, where the associated page table is different from the Kth-level page table.

[0004] For example, in the method provided by an embodiment of the present disclosure, when K≥2, the first-level page table to the (K - 1)th-level page table respectively corresponding to the first address segment to the (K - 1)th address segment are all stored in the translation lookaside buffer.

[0005] For example, in the method provided by an embodiment of the present disclosure, at least one of the page tables stored in the translation lookaside buffer includes an identification field, and the identification field includes flag information and number information. The flag information indicates whether the corresponding page table can be used for page table calculation, and the number information indicates the number of virtual addresses having a preset relationship.

[0006] For example, in a method provided in an embodiment of the present disclosure, judging whether the associated page table is stored in the translation lookaside buffer according to the Kth address segment in the target virtual address includes: judging whether the associated page table is stored in the translation lookaside buffer according to the Kth address segment in the target virtual address and based on the flag information and the number information of the page tables stored in the translation lookaside buffer.

[0007] For example, in a method provided in an embodiment of the present disclosure, according to the Kth address segment in the target virtual address and based on the flag information and the number information of the page tables stored in the translation lookaside buffer, it is determined whether the associated page table is stored in the translation lookaside buffer, including: traversing the page tables of level K stored in the translation lookaside buffer, and obtaining the corresponding page tables with the identification field in the page tables of level K; calculating the address segment range corresponding to each corresponding page table according to the flag information and the number information in the identification field included in the corresponding page table; determining whether the Kth address segment is within the address segment range corresponding to each corresponding page table; in response to the Kth address segment being within the address segment range, determining that the associated page table is stored in the translation lookaside buffer, and using the page table corresponding to the address segment range covering the Kth address segment in the corresponding page table as the associated page table; in response to the Kth address segment not being within each address segment range, determining that the associated page table does not exist in the translation lookaside buffer.

[0008] For example, in the method provided in one embodiment of the present disclosure, the address segment range corresponding to each corresponding page table is calculated based on the flag information and the number information in the identification field included in the corresponding page table, including: in response to the flag information being a valid value, taking the address value of the corresponding page table as the starting value, and taking P continuously increasing address values as the address segment range; wherein the value of the number information is P, P>1 and P is an integer.

[0009] For example, in the method provided in an embodiment of the present disclosure, the identification field further includes interval information, and the interval information indicates the size of the address interval.

[0010] For example, in a method provided in an embodiment of the present disclosure, obtaining the K-th level page table corresponding to the K-th address segment based on the associated page table includes: obtaining the K-th level page table corresponding to the K-th address segment based on the interval information and the relationship between the K-th address segment and the address value of the associated page table.

[0011] For example, in a method provided in an embodiment of the present disclosure, a K-th level page table corresponding to the K-th address segment is obtained based on the interval information and the relationship between the K-th address segment and the address value of the associated page table, including: determining the interval value between the K-th address segment and the address value of the associated page table based on the position of the K-th address segment within the address segment range corresponding to the associated page table; calculating the product of the interval information and the interval value, and adding the product to the page table value of the associated page table to obtain the K-th level page table corresponding to the K-th address segment.

[0012] For example, the method provided by an embodiment of the present disclosure also includes: judging whether a basic page table is stored in the translation lookaside buffer based on the Nth address segment in the target virtual address, wherein the basic page table is a page table stored in the translation lookaside buffer that is correlated with the Nth address segment; in response to the basic page table being stored in the translation lookaside buffer, obtaining an Nth-level page table corresponding to the Nth address segment based on the basic page table, thereby obtaining a physical address, wherein the basic page table is different from the Nth-level page table.

[0013] For example, in a method provided in an embodiment of the present disclosure, the first-level page table to the N-1-th level page table corresponding to the first address segment to the N-1-th address segment are all stored in the translation lookaside buffer.

[0014] For example, in the method provided in one embodiment of the present disclosure, judging whether the base page table is stored in the translation lookaside buffer according to the Nth address segment in the target virtual address includes: judging whether the base page table is stored in the translation lookaside buffer according to the Nth address segment in the target virtual address and based on the flag information and the number information of the page tables stored in the translation lookaside buffer.

[0015] For example, in the method provided in one embodiment of the present disclosure, the N-th level page table corresponding to the N-th address segment is obtained based on the basic page table, including: obtaining the N-th level page table corresponding to the N-th address segment according to the interval information and the relationship between the address value of the N-th address segment and the basic page table.

[0016] At least one embodiment of the present disclosure further provides a processor, including a system memory management unit. The system memory management unit includes a translation lookaside buffer (TLB), and the TLB stores at least one page table. The system memory management unit is configured to perform address translation for a target virtual address. The target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. The system memory management unit is configured to determine whether an associated page table is stored in the TLB according to the Kth address segment in the target virtual address, and in response to the associated page table being stored in the TLB, obtain the Kth-level page table corresponding to the Kth address segment based on the associated page table to complete the query operation for the Kth-level page table. Here, the associated page table is a page table stored in the TLB and having a correlation with the Kth address segment, 1 ≤ K < N and K is an integer, and the associated page table is different from the Kth-level page table.

[0017] For example, in the processor provided in an embodiment of the present disclosure, the system memory management unit is further configured to determine whether a base page table is stored in the TLB according to the Nth address segment in the target virtual address, and in response to the base page table being stored in the TLB, obtain the Nth-level page table corresponding to the Nth address segment based on the base page table, so as to obtain a physical address. Here, the base page table is a page table stored in the TLB and having a correlation with the Nth address segment, and the base page table is different from the Nth-level page table.

[0018] At least one embodiment of the present disclosure further provides an electronic device, including the processor provided in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0020] Figure 1 It is a basic working principle diagram of a system memory management unit;

[0021] Figure 2 It is a flowchart of an address translation method provided in some embodiments of the present disclosure;

[0022] Figure 3 It is a schematic diagram of a page table format provided in some embodiments of the present disclosure;

[0023] Figure 4 is Figure 2 An exemplary flow chart of step S10;

[0024] Figure 5 for Figure 2 An exemplary flow chart of step S20;

[0025] Figure 6 A flowchart of another address conversion method provided in some embodiments of the present disclosure;

[0026] Figure 7 A schematic block diagram of a processor provided for some embodiments of the present disclosure;

[0027] Figure 8 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure;

[0028] Figure 9 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] The System Memory Management Unit (SMMU) is widely used in various System on Chips (SoCs). It is primarily used to translate virtual addresses into physical addresses, that is, to convert virtual addresses into corresponding physical addresses. To achieve a single virtual-to-physical address translation, the SMMU must repeatedly access the memory (e.g., DDR) to read the page table used for the translation. This time-consuming process results in a long virtual-to-physical address translation, thus reducing SoC performance.

[0032] To improve the efficiency of address translation, a cache is typically integrated within the SMMU. The cache integrated within the SMMU is called a Translation Lookaside Buffer (TLB), also known as a page table cache or a translation bypass cache. The TLB is a type of CPU cache used by the SMMU to improve the speed of translating virtual addresses to physical addresses. The TLB typically has a fixed number of slots for storing tag page table entries that map virtual addresses to physical addresses. The search key is the virtual address, and the search result is the physical address. If the requested virtual address exists in the TLB, a very fast match is generated, and the resulting physical address can then be used to access the memory. If the requested virtual address is not in the TLB, the tag page table is used to translate the virtual address to the physical address, which requires multiple reads of the DDR and takes a long time.

[0033] Figure 1 This is a basic working principle diagram of a system storage management unit. Figure 1As shown, a pre-designed circuit functional module used in an application-specific integrated circuit (ASIC) or field programmable logic device (FPGA) is called an intellectual property core (IP core), or IP. The IP can be any logic block or functional block used in an ASIC or FPGA, such as a filter, memory controller, or interface program, and the embodiments of the present disclosure are not limited thereto. In step 1, the IP issues an operation virtual address. After receiving the virtual address, the SMMU begins to translate it. For example, the SMMU first queries its internal TLB. If the TLB hits, it can directly output the translated physical address based on the hit page table. If the TLB misses, as shown in step 2, the SMMU needs to read the page table from the DDR. After reading back the page table, the SMMU converts the virtual address into a physical address based on the contents of the page table and outputs it. The read-back page table is also cached in the TLB. If the SMMU subsequently receives the virtual address, it can directly query the TLB and convert the virtual address into a physical address for output. Finally, as shown in step 3, the SMMU issues the translated physical address, thereby executing the corresponding operation.

[0034] Solutions to improve address translation efficiency typically focus on increasing the TLB hit rate. There are two common approaches to increasing the probability of a page table hit in the TLB during virtual-to-physical address translation. One approach is to increase the capacity of the SMMU's internal TLB. Increasing the TLB capacity allows the TLB to store more page tables, thereby increasing the probability of a page table hit in the TLB during virtual-to-physical address translation, and thus improving virtual-to-physical address translation efficiency. However, this approach significantly increases chip area and power consumption, ultimately increasing chip cost, so increasing TLB capacity is limited. Another approach is to prefetch adjacent page tables into the TLB, thereby increasing the hit rate of subsequent virtual-to-physical address translations. This approach can improve the TLB hit rate to a certain extent, but prefetching page tables consumes TLB space. Since the total TLB space is limited, prefetching page tables will force other page tables out of the TLB, resulting in a minimal improvement in TLB hit efficiency.

[0035] At least one embodiment of the present disclosure provides an address translation method, processor, and electronic device for a target virtual address. This address translation method can improve address translation efficiency without increasing the capacity of the translation lookaside buffer (TLB), increasing hardware area and power consumption, and effectively improving the hit efficiency of the translation lookaside buffer and reducing the number of page table reads from memory.

[0036] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements described above.

[0037] At least one embodiment of the present disclosure provides an address translation method for a target virtual address. The address translation method is used for a translation lookaside buffer, and the translation lookaside buffer stores at least one page table. The target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. The address translation method includes: judging whether an associated page table is stored in the translation lookaside buffer according to the Kth address segment in the target virtual address, where the associated page table is a page table stored in the translation lookaside buffer and having a correlation with the Kth address segment, 1 ≤ K < N and K is an integer; in response to the associated page table being stored in the translation lookaside buffer, obtaining the Kth-level page table corresponding to the Kth address segment based on the associated page table to complete the query operation for the Kth-level page table, and the associated page table is different from the Kth-level page table.

[0038] Figure 2 It is a schematic flowchart of an address translation method provided by some embodiments of the present disclosure. As Figure 2 shown, in some embodiments, the address translation method includes the following operations.

[0039] Step S10: Judging whether an associated page table is stored in the translation lookaside buffer according to the Kth address segment in the target virtual address, where the associated page table is a page table stored in the translation lookaside buffer and having a correlation with the Kth address segment, 1 ≤ K < N and K is an integer;

[0040] Step S20: In response to the associated page table being stored in the translation lookaside buffer, obtaining the Kth-level page table corresponding to the Kth address segment based on the associated page table to complete the query operation for the Kth-level page table, where the associated page table is different from the Kth-level page table.

[0041] For example, the address translation method performs address translation for the target virtual address and is used for the translation lookaside buffer. The translation lookaside buffer is the aforementioned TLB, and the translation lookaside buffer stores at least one page table.

[0042] For example, the target virtual address is a virtual address that needs to be translated, such as a virtual address carried by some requests or instructions. The SMMU needs to translate the target virtual address into a corresponding physical address to facilitate the execution of the corresponding requests or instructions.

[0043] For example, the target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. That is, the first address segment is used to query the first-level page table, the second address segment is used to query the second-level page table, and so on, and the Nth address segment is used to query the Nth-level page table.

[0044] To perform a virtual address to physical address translation, it is usually necessary to perform lookups in multiple levels of page tables, and performing lookups in different levels of page tables depends on different bits (bits) of the virtual address. For example, in some examples, assume that the bit width of a certain virtual address is 36 bits, and this virtual address is, for example, 0xaa_bb_cc_000. "aa" is used for addressing the first-level page table, and "aa" is the first address segment; "bb" is used for addressing the second-level page table, and "bb" is the second address segment; "cc" is used for addressing the third-level page table, and "cc" is the third address segment. The page table granularity is 4KB. In this example, N = 3, and the SMMU is divided into three levels of page tables. By performing three page table lookups, the corresponding physical address can ultimately be obtained.

[0045] It should be noted that in the embodiments of the present disclosure, the number of bits of the virtual address is not limited to 36 bits and can also be any other number of bits. The address segment division method and representation method of the virtual address are not limited and can be determined according to actual needs. The page table is not limited to being divided into three levels and can also be any other number of levels. For a detailed description of multi-level page table addressing, reference can be made to conventional designs and will not be elaborated here. The value of N is not limited and can be any integer greater than 1, which can be determined according to the number of levels of the page table.

[0046] For example, in step S10, the Kth address segment can be a part of the target virtual address, that is, it can be certain bits of the target virtual address. For example, 1 ≤ K < N and K is an integer. As mentioned above, the Kth address segment is used to query the Kth-level page table. Since K < N, the Kth-level page table is not the Nth-level page table, that is, the Kth-level page table is not the last-level page table. The Kth-level page table is used to continue querying the next-level page table, and the physical address cannot be directly obtained from the Kth-level page table.

[0047] For example, the associated page table is the page table stored in the translation lookaside buffer that is relevant to the Kth address segment, and the associated page table is different from the Kth-level page table. Here, "being relevant" means that the Kth-level page table corresponding to the Kth address segment can be calculated based on this associated page table (calculate the page table value of the corresponding Kth-level page table). Even if the Kth-level page table is not stored in the translation lookaside buffer, the Kth-level page table can be calculated without querying the Kth-level page table in the memory.

[0048] The associated page table will be briefly described below with reference to examples. [[ID=##]]

[0049] For example, in some examples, for the case where the first-level page table is continuous, assuming that the 10 virtual addresses are 0x00_10_00_000, 0x01_10_00_000, 0x02_80_00_000, 0x03_70_00_000, 0x04_60_00_000, 0x05_20_00_000, 0x06_50_00_000, 0x07_40_00_000, 0x08_70_00_000, and 0x09_40_00_000, it can be seen that the highest 8 bits (indicated by italic bold) of these 10 virtual addresses are continuous, and the highest 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used to address the first-level page table. The content stored in the first-level page table is the base address of the second-level page table. Assume that the base addresses of the second-level page table are 0x0a000_0000, 0x0a010_0000, 0x0a020_0000, 0x0a030_0000, 0x0a040_0000, 0x0a050_0000, 0x0a060_0000, 0x0a070_0000, 0x0a080_0000, and 0x0a090_0000, and each base address is continuous with a 1M space between them.

[0050] After the SMMU translates the virtual address 0x00_10_00_000, the page tables corresponding to that virtual address are stored in the translation lookaside buffer. Therefore, when subsequent virtual addresses 0x01_10_00_000, 0x02_80_00_000, 0x03_70_00_000, ..., 0x09_40_00_000 need to be translated, even if the translation lookaside buffer doesn't store the first-level page tables corresponding to those virtual addresses, since the first-level page tables have certain regularities, these corresponding first-level page tables can be calculated based on the first-level page table corresponding to the virtual address 0x00_10_00_000. This allows direct lookups of the second-level and third-level page tables, eliminating the need to search the DDR for the first-level page table and reducing the latency associated with searching the first-level page table.

[0051] In this example, the first address segment in the virtual address is used to query the first-level page table, so K=1. This example shows a continuous first-level page table. For the subsequent virtual addresses 0x01_10_00_000, 0x02_80_00_000, 0x03_70_00_000, ..., 0x09_40_00_000, the first-level page tables corresponding to the first address segments of these subsequent virtual addresses can be calculated using the first-level page table corresponding to the virtual address 0x00_10_00_000. Therefore, the first-level page table corresponding to the virtual address 0x00_10_00_000 can be called an associated page table. In this example, the first address segments in each virtual address are continuous (the highest 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively). The first-level page tables corresponding to each virtual address have certain patterns, so these patterns can be used to calculate the required first-level page table.

[0052] It should be noted that the lowest 12 bits of the virtual address in the above example are not used for page table lookup, so the lowest 12 bits can be 000~fff, and the value of the lowest 12 bits does not affect the page table lookup. Therefore, each of the virtual addresses in the above examples actually represents a range of virtual addresses. For example, the virtual address 0x00_10_00_000 can actually represent 0x00_10_00_000~0x00_10_00_fff, the virtual address 0x01_10_00_000 can actually represent 0x01_10_00_000~0x01_10_00_fff, and so on. Since the value of the lowest 12 bits does not affect the page table lookup, in order to simplify the description, in the description of each example below, the lowest 12 bits of the virtual address can represent the range of 000~fff, rather than being limited to only 000.

[0053] For example, in some other examples, for the case where the second-level page table is continuous, assuming that the 10 virtual addresses are 0x08_00_01_000, 0x08_01_03_000, 0x08_02_05_000, 0x08_03_07_000, 0x08_04_09_000, 0x08_05_02_000, 0x08_06_04_000, 0x08_07_06_000, 0x08_08_08_000, and 0x08_09_00_000, it can be seen that the middle 8 bits (indicated by italic bold) of these 10 virtual addresses are continuous, and the middle 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used to address the second-level page table. The content stored in the second-level page table is the base address of the third-level page table. Assume that the base addresses of the third-level page table are 0x0b000_0000, 0x0b020_0000, 0x0b040_0000, 0x0b060_0000, 0x0b080_0000, 0x0b0a0_0000, 0x0b0c0_0000, 0x0b0e0_0000, 0x0b100_0000, and 0x0b120_0000, and each base address is continuous with a 2M space between them.

[0054] After SMMU translates the virtual address 0x08_00_01_000, the page tables of all levels corresponding to the address are stored in the translation lookaside buffer. Therefore, when address translation is required for the subsequent virtual addresses 0x08_01_03_000, 0x08_02_05_000, 0x08_03_07_000, 0x08_04_09_000, 0x08_05_02_000, 0x08_06_04_000, 0x08_07_06_000, 0x08_08_08_000, and 0x08_09_00_000, even if the translation lookaside buffer does not store the second-level page tables corresponding to the respective virtual addresses, the corresponding second-level page tables can be calculated based on the second-level page table corresponding to the virtual address 0x08_00_01_000, as the second-level page tables have certain regularities. Therefore, the third-level page table can be directly looked up, eliminating the need to look up the second-level page table in the DDR, thus reducing the delay of the second-level page table lookup.

[0055] In this example, the second address segment in the virtual address is used to query the second-level page table, so K=2. This example shows a continuous second-level page table. For the subsequent virtual addresses 0x08_01_00_000, 0x08_02_00_000, 0x08_03_00_000, ..., 0x08_09_00_000, the second-level page tables corresponding to the second address segments of these subsequent virtual addresses can be calculated using the second-level page table corresponding to the virtual address 0x08_00_01_000. Therefore, the second-level page table corresponding to the virtual address 0x08_00_01_000 can be called an associated page table. In this example, the second address segments in each virtual address are continuous (the middle 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively). The second-level page tables corresponding to each virtual address have certain patterns, so these patterns can be used to calculate the required second-level page table. It should be noted that, in this example, the highest 8 bits of the first-level page table mappings of these virtual addresses need to be consistent, so the first-level page tables corresponding to these virtual addresses can be directly queried in the translation lookaside buffer.

[0056] Therefore, in step S10, when it is necessary to query the K-th level page table according to the K-th address segment in the target virtual address, if the K-th level page table is not stored in the translation lookaside buffer, it can be determined whether the translation lookaside buffer stores a related page table.

[0057] For example, in step S20, if an associated page table is stored in the translation lookaside buffer, the K-th level page table corresponding to the K-th address segment can be obtained based on the associated page table to complete the query operation for the K-th level page table. For example, the associated page table is different from the K-th level page table. As described in the above example, the rules between the page tables can be used to perform calculations, so that the required K-th level page table (the page table value of the K-th level page table) can be calculated based on the associated page table, without having to query the K-th level page table in the memory, thereby effectively improving the efficiency of address translation.

[0058] For example, in some examples, when K≥2, the first-level page table to the K-1-th level page table corresponding to the first address segment to the K-1-th address segment are all stored in the translation lookaside buffer. That is, when it is necessary to calculate the page table value of the K-th level page table (such as the second-level page table, the third-level page table, etc.) corresponding to the K-th address segment, then the page tables of all levels before the K-th level page table (such as the first-level page table to the K-1-th level page table) are all stored in the translation lookaside buffer, that is, the first-level page table to the K-1-th level page table can be directly hit in the translation lookaside buffer. For example, in other examples, one or more of the first-level page tables to the K-1-th level page tables corresponding to the first address segment to the K-1-th address segment may not be stored in the translation lookaside buffer, which does not affect the calculation of the K-th level page table, and the embodiments of the present disclosure are not limited to this.

[0059] For example, in some examples, as described in the example above, assuming that the 10 virtual addresses are 0x08_00_01_000, 0x08_01_03_000, 0x08_02_05_000, 0x08_03_07_000, 0x08_04_09_000, 0x08_05_02_000, 0x08_06_04_000, 0x08_07_06_000, 0x08_08_08_000, and 0x08_09_00_000, it can be seen that the middle 8 bits (indicated by italic bold) of these 10 virtual addresses are consecutive, and the middle 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used to address the second-level page table, which can be calculated using certain rules. At this point, the highest 8 bits of these virtual addresses are the same, and the corresponding first-level page tables are also the same. Therefore, their first-level page tables have been stored in the translation lookaside buffer and can be directly hit in the translation lookaside buffer.

[0060] For example, in order to record the patterns of the page table and use them for calculations, it is necessary to add fields to the page table to record the pattern information. The page table can be understood as the lookup table required for translating virtual addresses into physical addresses. The page table defines the rules for translating virtual addresses into physical addresses. Figure 3 A schematic diagram of a page table format provided in some embodiments of the present disclosure. Figure 3As shown, in some examples, the page table includes page table attributes and page table values. The page table attribute (Page Table Attribute) is used to record the attributes of the page table. For example, it can be divided into two parts of bits and set at the high and low bits of the virtual address respectively. The page table value (Address) refers to the base address of the next level page table or certain bits of the physical address (when the page table is the last level page table, the page table value refers to certain bits of the physical address; otherwise, the page table value refers to the base address of the next level page table). For the usual address conversion method, the SMMU implements the conversion from virtual address to physical address based on the page table attributes and page table values.

[0061] In an embodiment of the present disclosure, the page table also includes an identification field, and this added identification field is used to record the regularity of the page table. In the case of a multi-level page table, the identification field can be added to any one or more levels of the page table, or the identification field can be added to each level of the page table. For example, the identification field includes flag information, number information, and interval information. The flag information indicates whether the corresponding page table can be used for page table calculation, that is, it is used to indicate whether the virtual address corresponding to the page table has a certain continuous corresponding relationship (such as the several corresponding relationships described in the above example). This corresponding relationship can be a first-level page table, a second-level page table, or a third-level page table. For example, the flag information can be represented by a flag. When the flag information is a valid value (for example, flag = 1), it means that the address segment of the virtual address corresponding to the page table has regularity and the corresponding page table also has regularity, so it can be used for page table calculation. When the flag information is an invalid value (for example, flag = 0), it means that the address segment of the virtual address corresponding to the page table and the corresponding page table do not have regularity, and page table calculation cannot be performed.

[0062] The number information represents the number of virtual addresses with a preset relationship. For example, count can be used to represent the number information, which is meaningful only when the flag information is a valid value (for example, flag = 1). The preset relationship is, for example, a continuous relationship. Of course, the embodiments of the present disclosure are not limited to this. The preset relationship can be a continuous relationship (sequentially continuous, continuous with intervals, etc.), a functional relationship, a multiple relationship, etc., which can be determined according to actual needs. For example, in the aforementioned example, there are 10 virtual addresses that are continuous and the corresponding page tables are regular, so the number information can be set to count = 10. Of course, the embodiments of the present disclosure are not limited to this. When there are only 3, 5 or other numbers of virtual addresses that are continuous and the corresponding page tables are regular, the number information can also be set to 3, 5 or other corresponding values, which can be determined according to actual needs.

[0063] The interval information indicates the size of the address interval, which can be represented by gap, for example. It is meaningful only when the flag information is a valid value (for example, flag = 1). The specific calculation method of the interval can be flexibly adopted in a variety of ways according to actual needs. For example, in some examples, the size of the interval is 2^gap*4KB, which represents the size of the interval between base addresses. Of course, the embodiments of the present disclosure are not limited to this, and any definition method can be used to represent and calculate the size of the address interval.

[0064] Therefore, by using the flag information, number information and interval information in the identification field, the regularity of the page table can be recorded and represented, thereby calculating the required page table.

[0065] It should be noted that, among the multiple page tables stored in the translation lookaside buffer, only a part of the page tables may include the identification field, or all the page tables may include the identification field. The embodiments of the present disclosure do not limit this. It is only necessary that at least one page table among the page tables stored in the translation lookaside buffer includes the identification field.

[0066] It should be noted that Figure 3 The page table format shown is exemplary only and non-limiting. The specific format of the page table can be determined based on actual needs and is not limited in the embodiments of the present disclosure. The representation and data format of the flag information, number information, and interval information can be determined based on actual needs and are not limited in the embodiments of the present disclosure.

[0067] The following briefly describes each piece of information in the identification field with examples.

[0068] For example, in some examples, for the case where the first-level page table is continuous, assuming that the 10 virtual addresses are 0x00_10_00_000, 0x01_10_00_000, 0x02_80_00_000, 0x03_70_00_000, 0x04_60_00_000, 0x05_20_00_000, 0x06_50_00_000, 0x07_40_00_000, 0x08_70_00_000, and 0x09_40_00_000, it can be seen that the highest 8 bits (indicated by italic bold) of these 10 virtual addresses are continuous, and the highest 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used to address the first-level page table. The content stored in the first-level page table is the base address of the second-level page table. Assume that the base addresses of the second-level page table are 0x0a000_0000, 0x0a010_0000, 0x0a020_0000, 0x0a030_0000, 0x0a040_0000, 0x0a050_0000, 0x0a060_0000, 0x0a070_0000, 0x0a080_0000, and 0x0a090_0000, and each base address is continuous with a 1M space between them. Since there is a continuous correspondence, the "flag" of the first-level page table is set to 1. The number of continuous relationships is 10, so the count is set to 10. The corresponding second-level page table base address interval is 1M, so the gap is set to 8 (2^8*4K=1M).

[0069] For example, in some other examples, for the case where the second-level page table is continuous, assuming that the 10 virtual addresses are 0x08_00_01_000, 0x08_01_03_000, 0x08_02_05_000, 0x08_03_07_000, 0x08_04_09_000, 0x08_05_02_000, 0x08_06_04_000, 0x08_07_06_000, 0x08_08_08_000, and 0x08_09_00_000, it can be seen that the middle 8 bits (indicated by italic bold) of these 10 virtual addresses are continuous, and the middle 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used to address the second-level page table. The content stored in the second-level page table is the base address of the third-level page table. Assume that the base addresses of the third-level page table are 0x0b000_0000, 0x0b020_0000, 0x0b040_0000, 0x0b060_0000, 0x0b080_0000, 0x0b0a0_0000, 0x0b0c0_0000, 0x0b0e0_0000, 0x0b100_0000, and 0x0b120_0000, and each base address is continuous with a 2M space between them. Since there is a continuous correspondence, the "flag" of the second-level page table is set to 1. The number of continuous relationships is 10, so the count is set to 10. The corresponding third-level page table base address interval is 2M, so the gap is set to 9 (2^9*4K=2M).

[0070] It should be noted that the maximum values of the count information (count) and the gap information (gap) in the above examples can be determined based on requirements and are not limited in the embodiments of the present disclosure. For example, the patterns of virtual addresses and page tables can be learned during program development, such as by program developers determining and configuring them. Therefore, this pattern information can be recorded in the identification field of the page table for subsequent use in address translation.

[0071] It should be noted that in the embodiments of the present disclosure, the patterns described in the above examples are merely illustrative and non-restrictive. The patterns between multiple virtual addresses and the patterns between multiple corresponding page tables are not limited to the methods described above and can be any predictable and calculable patterns. For example, these patterns can be sequential, continuous, intermittent, functional, or exponential. Accordingly, the identification field used to record these patterns can also include more information types to record and represent these patterns.

[0072] For example, return to Figure 2In step S10, it is determined whether an associated page table exists. Step S10 may further include: according to the Kth address segment in the target virtual address, and based on the flag information and number information of the page tables stored in the translation lookaside buffer, determining whether an associated page table is stored in the translation lookaside buffer.

[0073] Figure 4 for Figure 2 An exemplary flow chart of step S10 in FIG. Figure 4 As shown, in some examples, step S10 includes the following operations.

[0074] Step S11: traverse the page tables of level K stored in the translation lookaside buffer, and obtain a corresponding page table having an identification field in the page tables of level K;

[0075] Step S12: Calculating the address segment range corresponding to each corresponding page table according to the flag information and number information in the identification field included in the corresponding page table;

[0076] Step S13: determining whether the Kth address segment is within the address segment range corresponding to each corresponding page table;

[0077] Step S14: In response to the Kth address segment being within the address segment range, determining that an associated page table is stored in the translation lookaside buffer, and using a page table corresponding to the address segment range covering the Kth address segment in the corresponding page table as the associated page table;

[0078] Step S15: In response to the Kth address segment not being within the range of each address segment, determining that no associated page table exists in the translation lookaside buffer.

[0079] For example, in step S11, the page tables stored in the translation lookaside buffer may include one or more of a first-level page table, a second-level page table, ..., and an N-th-level page table. Some page tables may include an identification field while others do not. Therefore, it is necessary to traverse the page tables of level K stored in the translation lookaside buffer and obtain the corresponding page table with an identification field in the page tables of level K.

[0080] For example, in step S12, after obtaining the corresponding page table of level K and having an identification field, the address segment range corresponding to the corresponding page table can be calculated based on the flag information and number information in the identification field. For example, in some examples, step S12 may further include: in response to the flag information being a valid value, taking the address value of the corresponding page table as the starting value, and taking P continuously increasing address values as the address segment range. For example, the value of the number information is P, P>1 and P is an integer. For example, since these P address values increase continuously, this ensures that the high bits of the virtual address of the address segment used for querying the first-level page table to the K-1-th level page table are consistent with the high bits of the virtual address of the address segment corresponding to the associated page table.

[0081] For example, in some examples, still taking the example described above as an example, for the case where the first-level page table is continuous, K=1. Assume that the 10 virtual addresses are 0x00_10_00_000, 0x01_10_00_000, 0x02_80_00_000, 0x03_70_00_000, 0x04_60_00_000, 0x05_20_00_000, 0x06_50_00_000, 0x07_40_00_000, 0x08_70_00_000, and 0x09_40_00_000. It can be seen that the highest 8 bits (indicated by italic bold) of these 10 virtual addresses are continuous, and the highest 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used for addressing the first-level page table. Assume that the first-level page table corresponding to the virtual address 0x00_10_00_000 exists in the translation lookaside buffer, and the first-level page table is obtained by traversal. If the flag information in the identification field of the first-level page table is a valid value and the number information is 10, it means that there are 10 consecutive virtual addresses. Therefore, the address value of the first-level page table (for example, the highest 8 bits of the corresponding virtual address, that is, 00) is used as the starting value, and the 10 consecutively increasing address values are used as the address segment range. Thus, the address segment range can be obtained as 00, 01, 02, 03, ..., 09.

[0082] For example, in step S13, after the address segment ranges corresponding to the respective acquired corresponding page tables are calculated, it is determined whether the Kth address segment is within the address segment range corresponding to each corresponding page table.

[0083] For example, in step S14, if the Kth address segment is within a certain address segment range, it is determined that an associated page table is stored in the translation lookaside buffer, and the page table corresponding to the address segment range covering the Kth address segment in the corresponding page table is used as the associated page table. For example, in some examples, using the example described above, the first-level page table corresponding to the virtual address 0x00_10_00_000 exists in the translation lookaside buffer, and its address segment range is 00, 01, 02, 03, ..., 09. Assuming that the target virtual address is 0x03_70_00_000, the Kth address segment (K=1 at this time) is 03, so the Kth address segment falls within the above address segment range, and therefore it can be determined that an associated page table is stored in the translation lookaside buffer. At this time, the page table corresponding to the address segment range (that is, the first-level page table corresponding to the virtual address 0x00_10_00_000) is used as the associated page table for subsequent calculation of the K-th level page table (first-level page table) of the target virtual address 0x03_70_00_000.

[0084] For example, in step S15, if the Kth address segment is not within the range of all address segments, that is, the Kth address segment does not fall within any address segment range, then it is determined that there is no associated page table in the translation lookaside buffer. In this case, the Kth level page table cannot be calculated, so it is necessary to query the corresponding page table in the memory.

[0085] It should be noted that the above steps S11-S15 exemplarily describe the process of determining the associated page table, but the embodiments of the present disclosure are not limited thereto. Any method and process can be used to determine the associated page table, as long as the associated page table can be determined based on the information in the identification field. This can be determined according to actual needs.

[0086] For example, return to Figure 2 In step S20, a K-th level page table corresponding to the K-th address segment is obtained based on the associated page table. Step S20 may further include: obtaining a K-th level page table corresponding to the K-th address segment according to the interval information and the relationship between the address value of the K-th address segment and the associated page table.

[0087] Figure 5 for Figure 2 An exemplary flow chart of step S20 in FIG. Figure 5 As shown, in some examples, the above step S20 may include the following operations.

[0088] Step S21: determining a distance between the Kth address segment and the address value of the associated page table according to the position of the Kth address segment within the address segment range corresponding to the associated page table;

[0089] Step S22: Calculate the product of the interval information and the spacing value, and add the product to the page table value of the associated page table to obtain the K-th level page table corresponding to the K-th address segment.

[0090] For example, in step S21, the spacing value between the Kth address segment and the address value of the associated page table can be determined based on the position of the Kth address segment within the address segment range corresponding to the associated page table. For example, in some examples, using the example described above, the first-level page table corresponding to the virtual address 0x00_10_00_000 is the associated page table, and its address segment range is 00, 01, 02, 03, ..., 09, where the address value of the associated page table is 00. Assuming that the target virtual address is 0x03_70_00_000, the Kth address segment (K=1 at this time) is 03, so based on the position of the Kth address segment within the above-mentioned address segment range, it can be determined that the spacing value between the Kth address segment and the address value of the associated page table is 3. Here, the spacing value refers to the number of addresses separated between the Kth address segment and the address value of the associated page table.

[0091] For example, in step S22, the product of the spacing information and the spacing value is calculated, and the product is added to the page table value of the associated page table, thereby obtaining the K-th level page table corresponding to the K-th address segment (obtaining the page table value of the K-th level page table). For example, in some examples, using the example described above, it has been determined that the spacing value between the K-th address segment and the address value of the associated page table is 3, and based on the spacing information, it can be known that the base addresses of the second-level page tables stored in the first-level page table are continuous with a 1M space as an interval, and the base address of the second-level page table stored in the associated page table is 0x0a000_0000. Therefore, it can be calculated that 1M*3+0x0a000_0000=0x0a030_0000, thereby obtaining the K-th level page table corresponding to the K-th address segment (the page table value) as 0x0a030_0000.

[0092] Through the above method, even if the K-th level page table corresponding to the K-th address segment is not stored in the translation lookaside buffer, the K-th level page table can be calculated through the associated page table without having to query the memory, thereby effectively improving the efficiency of address translation. This address translation method can achieve intermediate-level page table prediction and calculate the base address of the next-level page table. It has a wide range of applications and has no restrictions on the number of page table levels. Therefore, it can be flexibly applied to address translation in multi-level page tables, greatly improving the efficiency of address translation.

[0093] Figure 6 A flowchart of another address conversion method provided in some embodiments of the present disclosure. Figure 6 As shown, in some embodiments, the address conversion method may further include the following operations.

[0094] Step S30: determining whether a base page table is stored in the translation lookaside buffer according to the Nth address segment in the target virtual address, wherein the base page table is a page table stored in the translation lookaside buffer that is associated with the Nth address segment;

[0095] Step S40: In response to a base page table being stored in the translation lookaside buffer, obtaining an Nth-level page table corresponding to the Nth address segment based on the base page table, thereby obtaining a physical address, wherein the base page table is different from the Nth-level page table.

[0096] For example, in step S30, the Nth address segment is the last address segment of the target virtual address. The Nth address segment is used to query the Nth level page table (that is, the last level page table). The Nth level page table stores the corresponding physical address. The basic page table is a page table stored in the translation backup buffer that is correlated with the Nth address segment. The basic page table is different from the Nth level page table. Here, "correlation" means that the page table value corresponding to the Nth address segment can be calculated based on the basic page table. Even if the Nth level page table is not stored in the translation backup buffer, the page table value of the Nth level page table can be obtained by calculation without querying the Nth level page table in the memory. For example, the relevant description of the basic page table can refer to the associated page table described above. The difference between the two is that the page table used to calculate the last level page table of the target virtual address is called the basic page table, and the page table used to calculate the non-last level page table of the target virtual address is called the associated page table.

[0097] The following is a brief description of the basic page table with examples.

[0098] For example, in some examples, when the third-level page table (e.g., the last-level page table) is continuous, because there are three levels of page tables, the actual physical addresses are stored in the third-level page table. Assume that the 10 virtual addresses are 0x08_20_00_000, 0x08_20_01_000, 0x08_20_02_000, 0x08_20_03_000, 0x08_20_04_000, 0x08_20_05_000, 0x08_20_06_000, 0x08_20_07_000, 0x08_20_08_000, and 0x08_20_09_000. As you can see, the last 8 bits (indicated by italic bold) of these 10 virtual addresses are consecutive, and the last 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09. These 8 bits are used for addressing the third-level page table, and the content stored in the third-level page table is the physical address. Assume that the physical addresses stored in the third-level page table are 0x0f_f0_00_000, 0x0f_f0_01_000, 0x0f_f0_02_000, 0x0f_f0_03_000, 0x0f_f0_04_000, 0x0f_f0_05_000, 0x0f_f0_06_000, 0x0f_f0_07_000, 0x0f_f0_08_000, and 0x0f_f0_09_000, and each physical address is continuous with a 4K space as the interval.

[0099] After SMMU translates the virtual address 0x08_20_00_000, the page tables of all levels corresponding to the address are stored in the translation lookaside buffer. Therefore, when address translation is required for the subsequent virtual addresses 0x08_20_01_000, 0x08_20_02_000, 0x08_20_03_000, 0x08_20_04_000, 0x08_20_05_000, 0x08_20_06_000, 0x08_20_07_000, 0x08_20_08_000, and 0x08_20_09_000, even if the translation lookaside buffer does not store the third-level page tables corresponding to the respective virtual addresses, since the third-level page tables have certain regularities, these corresponding third-level page tables can be calculated based on the third-level page table corresponding to the virtual address 0x08_20_00_000. Since the third-level page table is the last level page table, its page table value is the physical address. In this way, the physical address can be directly calculated, so there is no need to search the third-level page table in the memory, which saves the delay of searching the third-level page table.

[0100] In this example, the last address segment in the virtual address is used to query the Nth level page table. This example illustrates the case where the last level page table is continuous. For subsequent virtual addresses 0x08_20_01_000, 0x08_20_02_000, 0x08_20_03_000, ..., 0x08_20_09_000, the page table values (i.e., physical addresses) of the third-level page table corresponding to the last address segment of these subsequent virtual addresses can be calculated using the page table values (i.e., physical addresses) of the third-level page table corresponding to the virtual address 0x08_20_00_000. Therefore, the third-level page table corresponding to the virtual address 0x08_20_00_000 can be called the base page table. In this example, the last address segments in each virtual address are continuous, and the page table values (i.e., physical addresses) of the third-level page tables corresponding to each virtual address have certain regularities. Therefore, these regularities can be used to calculate the required page table values (i.e., physical addresses) of the third-level page table.

[0101] It should be noted that in this example, the high 16 bits of the first-level page table and the second-level page table mapping of these virtual addresses need to be consistent. Therefore, the first-level page table and the second-level page table corresponding to these virtual addresses can be directly queried in the translation lookaside buffer.

[0102] For example, in some examples, the first-level page table to the N-1th level page table corresponding to the first address segment to the N-1th address segment are all stored in the translation lookaside buffer. That is, when it is necessary to calculate the page table value of the N-th level page table (for example, the last level page table, for example, the third level page table) corresponding to the N-th address segment, then the page tables of all levels before the N-th level page table (for example, the first-level page table to the N-1th level page table) are all stored in the translation lookaside buffer, that is, the first-level page table to the N-1th level page table can be directly hit in the translation lookaside buffer. For example, in other examples, one or more of the first-level page tables to the N-1th level page tables corresponding to the first address segment to the N-1th address segment may not be stored in the translation lookaside buffer, which does not affect the calculation of the N-th level page table, and the embodiments of the present disclosure are not limited to this.

[0103] For example, in some examples, as described in the above example, assuming that the 10 virtual addresses are 0x08_20_00_000, 0x08_20_01_000, 0x08_20_02_000, 0x08_20_03_000, 0x08_20_04_000, 0x08_20_05_000, 0x08_20_06_000, 0x08_20_07_000, 0x08_20_08_000, and 0x08_20_09_000, it can be seen that the last 8 bits (indicated by italic bold) of these 10 virtual addresses are consecutive, and the last 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used to address the third-level page table (the last level page table), and the third-level page table can be calculated using certain rules. At this time, the upper 16 bits of these virtual addresses are the same, and the corresponding first-level page table and second-level page table are also the same. Therefore, the first-level page table and second-level page table have been stored in the translation lookaside buffer and can be directly hit in the translation lookaside buffer.

[0104] For example, the above step S30 may further include: determining whether a basic page table is stored in the translation lookaside buffer according to the Nth address segment in the target virtual address and based on the flag information and number information of the page tables stored in the translation lookaside buffer.

[0105] For example, in some examples, for the case where the third-level page table (the last-level page table) is continuous, assuming that the 10 virtual addresses are 0x08_20_00_000, 0x08_20_01_000, 0x08_20_02_000, 0x08_20_03_000, 0x08_20_04_000, 0x08_20_05_000, 0x08_20_06_000, 0x08_20_07_000, 0x08_20_08_000, and 0x08_20_09_000, it can be seen that the last 8 bits (indicated by italic bold) of these 10 virtual addresses are continuous, and the last 8 bits of these 10 virtual addresses are 00, 01, 02, 03, ..., 09, respectively. These 8 bits are used for addressing the third-level page table. The content stored in the third-level page table is the physical address. Assume that the physical addresses stored in the third-level page table are 0x0f_f0_00_000, 0x0f_f0_01_000, 0x0f_f0_02_000, 0x0f_f0_03_000, 0x0f_f0_04_000, 0x0f_f0_05_000, 0x0f_f0_06_000, 0x0f_f0_07_000, 0x0f_f0_08_000, 0x0f_f0_09_000, and each physical address is continuous with a 4K space as the interval. Since there is a continuous correspondence, the "flag" of the third-level page table is set to 1. The number of continuous relationships is 10, so the count is set to 10. The corresponding physical address interval is 4K, so the gap is set to 0 (2^0*4K=4K).

[0106] For example, in step S40, the step may further include: obtaining an Nth level page table corresponding to the Nth address segment according to the interval information and the relationship between the Nth address segment and the address value of the base page table. Here, the Nth level page table is the physical address.

[0107] For example, the method of calculating the Nth level page table (physical address) can be the same or similar to the method of calculating the Kth level page table described above. For example, first, the spacing value between the Nth address segment and the address value of the basic page table can be determined based on the position of the Nth address segment within the address segment range corresponding to the basic page table. Then, the product of the spacing information and the spacing value is calculated, and the product is added to the page table value of the basic page table (i.e., the physical address) to obtain the page table value (i.e., the physical address) of the Nth level page table corresponding to the Nth address segment. For specific instructions, please refer to the above instructions on calculating the Kth level page table, which will not be repeated here.

[0108] Through the above method, even if the N-th level page table corresponding to the N-th address segment is not stored in the translation backup buffer (the page table value of the N-th level page table is the physical address), the page table value (physical address) of the N-th level page table can be calculated through the basic page table without having to query in the memory, thereby effectively improving the efficiency of address conversion.

[0109] In an embodiment of the present disclosure, a prediction of a page table can be established based on the connection between the input virtual addresses and the regularity between the corresponding page tables, so that the corresponding page table can be calculated to reduce the number of times the SMMU performs page table queries in the memory and accelerate the address conversion. Even if the required page table is not stored in the translation lookaside buffer, it can be obtained by calculation, thereby improving the hit rate. Thus, the hit rate is effectively improved without increasing the capacity of the translation lookaside buffer, especially when there is a regularity between the virtual addresses and the corresponding page tables, the hit rate can be greatly improved. This address conversion method can be used for the calculation of any level of page table, can improve the efficiency of address conversion, does not need to increase the capacity of the translation lookaside buffer, will not increase the hardware area and power consumption, can effectively improve the hit efficiency of the translation lookaside buffer, and reduces the number of times the page table is read from the memory.

[0110] It should be noted that, in the embodiments of the present disclosure, the above-mentioned address conversion method may further include more or fewer steps, and the execution order of the steps is not limited, which may be determined according to actual needs.

[0111] At least one embodiment of the present disclosure further provides a processor that improves address translation efficiency without increasing the capacity of the Translation Lookaside Buffer (TLB), increasing hardware area and power consumption, effectively improving the hit efficiency of the TLB, and reducing the number of page table reads from memory.

[0112] Figure 7 This is a schematic block diagram of a processor provided in some embodiments of the present disclosure. Figure 7 As shown, in some embodiments, the processor 100 includes a system memory management unit 110. The system memory management unit 110 includes a translation lookaside buffer 111, and the translation lookaside buffer 111 stores at least one page table. For example, the processor 100 may also use Figure 1 As shown in the architecture, the system storage management unit 110 can be Figure 1 In the SMMU, the translation lookaside buffer 111 can be Figure 1 The TLB in .

[0113] The system memory management unit 110 is used for address translation for a target virtual address. For example, the target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table.

[0114] The system memory management unit 110 is configured to determine whether an associated page table is stored in the translation lookaside buffer 111 according to the Kth address segment in the target virtual address, and in response to the associated page table being stored in the translation lookaside buffer 111, obtain the Kth-level page table corresponding to the Kth address segment based on the associated page table to complete the query operation for the Kth-level page table. The associated page table is a page table stored in the translation lookaside buffer 111 that is relevant to the Kth address segment, 1 ≤ K < N and K is an integer, and the associated page table is different from the Kth-level page table.

[0115] The system memory management unit 110 is further configured to determine whether a base page table is stored in the translation lookaside buffer 111 according to the Nth address segment in the target virtual address, and in response to the base page table being stored in the translation lookaside buffer 111, obtain the Nth-level page table corresponding to the Nth address segment based on the base page table, thereby obtaining the physical address. The base page table is a page table stored in the translation lookaside buffer 111 that is relevant to the Nth address segment, and the base page table is different from the Nth-level page table.

[0116] For example, the system memory management unit 110 may execute Figure 2 steps S10 and S20 in the address translation method shown, and may further execute Figure 6 steps S30 and S40 shown. For a detailed description of the system memory management unit 110 and the translation lookaside buffer 111, reference may be made to the detailed description of the address translation method in the foregoing text, which will not be elaborated herein.

[0117] For example, the system memory management unit 110 and the translation lookaside buffer 111 may be hardware, software, firmware, and any feasible combination thereof, may be implemented using any architecture, may be a dedicated or general-purpose circuit, chip, or device, etc., or may be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the system memory management unit 110 and the translation lookaside buffer 111.

[0118] It should be noted that Figure 7The structure of the processor 100 shown is merely exemplary and non-restrictive. The processor 100 may further include other components and structures as needed, and the embodiments of the present disclosure are not limited thereto. The processor 100 may be any type of chip or circuit with processing capabilities, such as a CPU, a graphics processing unit (GPU), or a general-purpose computing on graphics processing unit (GPGPU), and the embodiments of the present disclosure are not limited thereto.

[0119] At least one embodiment of the present disclosure further provides an electronic device that can improve address translation efficiency without increasing the capacity of the translation lookaside buffer (TLB), increasing hardware area and power consumption, effectively improving the hit efficiency of the translation lookaside buffer, and reducing the number of page table reads from memory.

[0120] Figure 8 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 8 As shown, in some embodiments, the electronic device 200 includes a processor 210, which is a processor provided by any embodiment of the present disclosure, for example, Figure 7 The processor 100 is shown. The electronic device 200 may be any device with computing capabilities, such as a computer, a server, a smart phone, a tablet computer, etc., and the embodiments of the present disclosure are not limited thereto.

[0121] Figure 9 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. Figure 9 As shown, the electronic device 300 is suitable for implementing the address conversion method provided by the embodiment of the present disclosure. The electronic device 300 can be a terminal device or a server. It should be noted that Figure 9 The electronic device 300 shown is only an example and does not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0122] like Figure 9 As shown, the electronic device 300 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 31, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 32 or a program loaded from a storage device 38 to a random access memory (RAM) 33. For example, the processing device 31 may be a processor provided by any embodiment of the present disclosure, such as Figure 7The processor 100 is shown. Various programs and data required for the operation of the electronic device 300 are also stored in the RAM 33. The processing device 31, the ROM 32 and the RAM 33 are connected to each other via a bus 34. An input / output (I / O) interface 35 is also connected to the bus 34.

[0123] Typically, the following devices may be connected to the I / O interface 35: an input device 36 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 37 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 38 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 39. The communication device 39 may allow the electronic device 300 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 9 The electronic device 300 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 300 may instead implement or possess more or fewer devices.

[0124] For detailed description and technical effects of the electronic device 200 / 300, please refer to the above description of the processor, which will not be repeated here.

[0125] There are a few points to note:

[0126] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0127] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0128] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for translating a target virtual address into a translation lookaside buffer, wherein: The translation lookaside buffer stores at least one page table. The target virtual address includes multiple address segments, and the multiple address segments include a first address segment to an Nth address segment, where N is an integer greater than 1. The first address segment to the Nth address segment are respectively used to query a first-level page table to an Nth-level page table. The method includes: Based on the Kth address segment in the target virtual address, determine whether an associated page table is stored in the translation lookaside buffer according to the rule of the page table, where the associated page table is a page table stored in the translation lookaside buffer and having a correlation with the Kth address segment, 1 ≤ K < N and K is an integer; In response to the associated page table being stored in the translation lookaside buffer, obtain the Kth-level page table corresponding to the Kth address segment based on the associated page table and the rule of the page table, so as to complete the query operation for the Kth-level page table, where the associated page table is different from the Kth-level page table.

2. The method according to claim 1, wherein When K ≥ 2, the first-level page table to the (K - 1)th-level page table respectively corresponding to the first address segment to the (K - 1)th address segment are all stored in the translation lookaside buffer.

3. The method according to claim 1, wherein At least one of the page tables stored in the translation lookaside buffer includes an identification field, and the identification field includes flag information and count information. The flag information indicates whether the corresponding page table can be used for page table calculation. The count information indicates the number of virtual addresses having a preset relationship.

4. The method according to claim 3, wherein: Based on the Kth address segment in the target virtual address, determine whether an associated page table is stored in the translation lookaside buffer according to the rule of the page table, including: Based on the Kth address segment in the target virtual address, and based on the flag information and the count information of the page tables stored in the translation lookaside buffer, determine whether an associated page table is stored in the translation lookaside buffer.

5. The method according to claim 4, wherein Based on the Kth address segment in the target virtual address, and based on the flag information and the count information of the page tables stored in the translation lookaside buffer, determine whether an associated page table is stored in the translation lookaside buffer, including: Traverse the page tables of level K stored in the translation lookaside buffer, and obtain the corresponding page tables having the identification field in the page tables of level K; Calculate the address segment range corresponding to each of the corresponding page tables according to the flag information and the count information in the identification field included in the corresponding page table; Determine whether the Kth address segment is within the address segment range corresponding to each of the corresponding page tables; In response to the Kth address segment being within the address segment range, determine that an associated page table is stored in the translation lookaside buffer, and use the page table corresponding to the address segment range covering the Kth address segment in the corresponding page table as the associated page table; In response to the Kth address segment not being within each address segment range, determine that there is no associated page table in the translation lookaside buffer.

6. The method according to claim 5, wherein: Calculate the address segment range corresponding to each of the corresponding page tables according to the flag information and the count information in the identification field included in the corresponding page table, including: In response to the flag information being a valid value, taking the address value of the corresponding page table as a starting value and taking P consecutively increasing address values as the address segment range; The value of the number information is P, P>1 and P is an integer.

7. The method according to claim 6, wherein: The identification field further includes interval information, where the interval information indicates the size of the address interval.

8. The method according to claim 7, wherein: Obtaining a K-th level page table corresponding to the K-th address segment based on the associated page table and the rule of the page table, including: A K-th level page table corresponding to the K-th address segment is obtained according to the interval information and the relationship between the K-th address segment and the address value of the associated page table.

9. The method according to claim 8, wherein Obtaining a K-th level page table corresponding to the K-th address segment according to the interval information and a relationship between the K-th address segment and the address value of the associated page table, including: determining, according to a position of the Kth address segment within the address segment range corresponding to the associated page table, a distance value between the Kth address segment and an address value of the associated page table; A product of the interval information and the spacing value is calculated, and the product is added to the page table value of the associated page table to obtain a K-th level page table corresponding to the K-th address segment.

10. The method according to claim 7, further comprising: determining, based on an Nth address segment in the target virtual address, whether a base page table is stored in the translation lookaside buffer, wherein the base page table is a page table stored in the translation lookaside buffer and associated with the Nth address segment; In response to the base page table being stored in the translation lookaside buffer, an Nth-level page table corresponding to the Nth address segment is obtained based on the base page table, thereby obtaining a physical address, wherein the base page table is different from the Nth-level page table.

11. The method according to claim 10, wherein: The first-level page table to the N-1-th level page table corresponding to the first address segment to the N-1-th address segment are all stored in the translation lookaside buffer.

12. The method according to claim 10, wherein: Determining whether the base page table is stored in the translation lookaside buffer according to the Nth address segment in the target virtual address includes: According to the Nth address segment in the target virtual address and based on the flag information and the number information of the page tables stored in the translation lookaside buffer, it is determined whether the base page table is stored in the translation lookaside buffer.

13. The method according to claim 10, wherein: Obtaining an N-th level page table corresponding to the N-th address segment based on the basic page table includes: An N-th level page table corresponding to the N-th address segment is obtained according to the interval information and a relationship between the N-th address segment and the address value of the basic page table.

14. A processor comprising a system memory management unit, wherein: The system memory management unit includes a translation lookaside buffer storing at least one page table; The system storage management unit is used to perform address conversion on the target virtual address; The target virtual address includes a plurality of address segments, the plurality of address segments including a first address segment to an Nth address segment, N being an integer greater than 1, the first address segment to the Nth address segment being used to query a first-level page table to an Nth-level page table, respectively; The system storage management unit is configured to, according to the K-th address segment in the target virtual address, determine whether an associated page table is stored in the translation lookaside buffer based on the rule of the page table, and in response to the associated page table being stored in the translation lookaside buffer, obtain the K-th level page table corresponding to the K-th address segment based on the associated page table and the rule of the page table to complete the query operation for the K-th level page table, where the associated page table is a page table stored in the translation lookaside buffer that is relevant to the K-th address segment, K<N and K is an integer, and the associated page table is different from the K-th level page table.

15. The processor of claim 14, wherein: The system storage management unit is further configured to, according to the N-th address segment in the target virtual address, determine whether a base page table is stored in the translation lookaside buffer, and in response to the base page table being stored in the translation lookaside buffer, obtain the N-th level page table corresponding to the N-th address segment based on the base page table, so as to obtain the physical address, where the base page table is a page table stored in the translation lookaside buffer that is relevant to the N-th address segment, and the base page table is different from the N-th level page table.

16. An electronic device, comprising the processor according to claim 14 or 15.

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