Atomic layer etching process simulation method and device for multi-layer structure

Abstract

The present invention provides a method and device for simulating an atomic layer etching process of a multi-layer structure, comprising: defining structural information of an object to be etched, wherein the object to be etched includes a silicon substrate and a plurality of stacks of silicon germanium layers / silicon layers stacked in sequence thereon; defining etching functions of the silicon germanium layer and the silicon layer respectively; defining position coordinates and incident angle ranges of left-side emission sources and right-side emission sources at different depths; determining the number of etching particles to be incident according to etching time and structural information of the object to be etched; incidenting etching particles in sequence to the object to be etched until the etching particles are exhausted, and for each etching particle, performing the following operations: calculating a bombardment position on the object to be etched that receives the etching particles, determining atomic properties of the bombardment position, selecting different etching functions according to the atomic properties, and removing atoms at the bombardment position when removal conditions of the etching function are met, and finally obtaining a basic etching profile.

Description

Technical Field

[0001] The present invention relates to the technical field of computer simulation, and in particular to a method and device for simulating an atomic layer etching process of a multi-layer structure. Background Art

[0002] The device structure of advanced technology nodes of logic circuits is gradually developing towards a gate-all-around (GAA) structure, and atomic layer etching (ALE) is a key process. Compared with traditional etching, atomic layer etching (ALE) has the advantages of high etching selectivity, low aspect ratio dependence, good directionality, and high controllability. It is an advanced technology that can precisely control the amount of material removed.

[0003] In order to apply ALE technology to large-scale mass production, a large number of experiments are required, and ALE experiments are extremely difficult and costly. Therefore, simulation modeling has become a necessary means before ALE application, which can help study the process principles, show the influence trend of important parameters, save experimental costs and obtain valuable data. However, there is currently no relevant simulation model for multi-layer atomic layer etching process. Summary of the invention

[0004] To solve the above problems, the present invention provides a method and device for simulating the atomic layer etching process of a multi-layer structure, which can reflect the differences in etching morphologies of atomic layer etching (ALE) of a multi-layer structure due to different depths of multiple layers.

[0005] In one aspect, the present invention provides a method for simulating an atomic layer etching process of a multi-layer structure, comprising:

[0006] Defining structural information of an object to be etched, wherein the object to be etched includes a silicon substrate and a plurality of stacked layers of silicon germanium layers / silicon layers stacked in sequence thereon;

[0007] Define the etching functions of the silicon germanium layer and the silicon layer respectively;

[0008] Defining position coordinates and incident angle ranges of a left-side emission source and a right-side emission source at different depths, wherein the left-side emission source and the right-side emission source are used to irradiate etching particles from the left side and the right side, respectively;

[0009] Determining the number of etching particles to be incident according to the etching time and the structural information of the object to be etched;

[0010] Etching particles are sequentially incident on the object to be etched until the etching particles are exhausted. For each etching particle, the following operations are performed: the bombardment position on the object to be etched that receives the etching particles is calculated, the atomic properties of the bombardment position are determined, different etching functions are selected according to the atomic properties, and when the removal condition of the etching function is met, the atoms at the bombardment position are removed to finally obtain a basic etching profile.

[0011] Optionally, the structural information of the object to be etched is defined, including:

[0012] Set the position coordinates of the object to be etched, the number of layers in the stack, the critical dimensions of the stack, the thickness of the silicon germanium layer and the silicon layer in the stack, and the STI depth.

[0013] Optionally, the position coordinates and the incident angle ranges of the left-side emission source and the right-side emission source at different depths are defined, including:

[0014] According to the ratio of the depth of each stack to the STI depth, the position coordinates and the incident angle range of the left emission source and the right emission source corresponding to each stack are determined respectively.

[0015] Optionally, for each etching particle, calculating the bombardment position on the object to be etched where the etching particle is received comprises:

[0016] The position coordinates of the emission source are used as the initial coordinates of the incident etching particles;

[0017] Matching an incident angle for incident etching particles within the incident angle range of the emission source;

[0018] According to the initial coordinates of the etching particles, the incident angle and each horizontal coordinate of the object to be etched, the vertical coordinate corresponding to each horizontal coordinate is calculated to determine the bombardment position.

[0019] Optionally, for etching particles incident from the left side, each horizontal coordinate of the object to be etched is traversed from left to right, and the vertical coordinate corresponding to each horizontal coordinate is calculated;

[0020] For etching particles incident from the right side, each horizontal coordinate of the object to be etched is traversed from right to left, and the vertical coordinate corresponding to each horizontal coordinate is calculated.

[0021] Optionally, the method further comprises:

[0022] After obtaining the basic etching profile, the corner damage and upper edge damage of the silicon layer are simulated.

[0023] On the other hand, the present invention provides an atomic layer etching process simulation device for a multi-layer structure, comprising:

[0024] An initialization definition module is used to define structural information of an object to be etched, wherein the object to be etched includes a silicon substrate and a plurality of stacks of silicon germanium layers / silicon layers stacked in sequence thereon, define etching functions of the silicon germanium layer and the silicon layer, and define position coordinates and incident angle ranges of left-side emission sources and right-side emission sources at different depths, wherein the left-side emission source and the right-side emission source are used to irradiate etching particles from the left and right sides, respectively;

[0025] A particle number determination module is used to determine the number of etching particles to be incident according to the etching time and the structural information of the object to be etched;

[0026] The basic etching simulation module is used to sequentially inject etching particles into the object to be etched until the etching particles are exhausted. For each etching particle, the following operations are performed: calculating the bombardment position on the object to be etched that receives the etching particles, determining the atomic properties of the bombardment position, selecting different etching functions according to the atomic properties, and removing the atoms at the bombardment position when the removal conditions of the etching function are met, thereby finally obtaining a basic etching profile.

[0027] Optionally, the device further comprises:

[0028] The silicon damage simulation module is used to simulate the corner damage and upper edge damage of the silicon layer after obtaining the basic etching profile.

[0029] On the other hand, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for simulating the atomic layer etching process of a multi-layer structure as described above is implemented.

[0030] On the other hand, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned method for simulating an atomic layer etching process of a multi-layer structure.

[0031] The atomic layer etching process simulation method and device of the multi-layer structure provided by the present invention can reflect the difference in etching morphology between the silicon germanium layer and the silicon layer due to the different depths of multiple layers in the atomic layer etching (ALE) of the multi-layer structure. In the multi-layer structure, as the depth of the layers increases, the etching depth gradually decreases. Through the present invention, the etching morphology results can be predicted for the experiment, which is of great significance for saving experimental costs and adjusting process parameters to achieve expected success. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a flow chart of a method for simulating an atomic layer etching process of a multi-layer structure provided by an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the structure of an object to be etched according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the etching morphology of an object to be etched according to an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of an atomic layer etching process simulation device for a multi-layer structure provided by an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0039] The embodiment of the present invention provides a method for simulating an atomic layer etching process of a multi-layer structure. Figure 1 The overall flow chart of the simulation method is shown in FIG. Figure 1 As shown, the method may include steps S101-S105.

[0040] In step S101, the structural information of the object to be etched is first defined. In the present application, the object to be etched includes a silicon substrate and a plurality of stacked layers of silicon germanium layers / silicon layers stacked in sequence thereon.

[0041] refer to Figure 2 , Figure 2 is a schematic diagram of the object to be etched. It is necessary to set the position coordinates of the object to be etched, the number of layers of the stack ( Figure 2 The number of layers is 3), the key dimensions of the stack, the thickness of the SiGe layer and the silicon layer in the stack, the STI depth, and the sum of the thickness of the entire stack and the thickness of the silicon substrate is the STI depth. In the actual model, the SiGe layer and the silicon layer can be distinguished by color, for example, the SiGe layer is represented by red, the silicon layer is represented by blue, and the etched part is represented by black.

[0042] In step S102, the etching functions of the silicon germanium layer and the silicon layer are defined. Different etching functions are defined according to different atomic properties to simulate the etching process of chlorine atoms on the silicon layer and the silicon germanium layer. Different etching rates can be reflected, and different etching conditions corresponding to the silicon germanium layer and the silicon layer can be simulated. For example, the etching condition is set to whether the number of incident etching particles reaches a set threshold. When the number of etching particles reaches the set threshold, the target atoms can be removed.

[0043] In step S103, the position coordinates and incident angle ranges of the left and right emission sources at different depths are defined. The left and right emission sources are used to emit etching particles from the left and right sides of the object to be etched, respectively.

[0044] Specifically, according to the ratio of the depth of each stack to the STI depth, the position coordinates and the incident angle range of the left emission source and the right emission source corresponding to each stack are determined respectively. The incident angle range is -90° to 90°.

[0045] According to the number of layers, the particle emission source position is defined in the middle of each SiGe layer. In order to better realize the slight difference in etching in the up and down directions, two emission sources are defined on one side of each SiGe layer. Among them, when the atomic matrix height of SiGe is an even number, the two emission sources are symmetrically arranged with the center of the SiGe layer height; when the atomic matrix height of SiGe is an odd number, the two emission sources are arranged to coincide with the center of the SiGe layer. At the same time, the distance between the emission source and the side of the object to be etched is proportional to the height of the SiGe layer.

[0046] In step S104, the number of etching particles to be incident is determined according to the etching time and the structural information of the object to be etched.

[0047] Customized etching time, number of layers, and layer height will affect the number of etching particles. Corresponding to different layers of silicon germanium layer / silicon layer, the number of incident etching particles is different. The further down, the fewer the number of etching particles, and the smaller the etching depth.

[0048] In step S105, etching particles are sequentially incident on the object to be etched until the etching particles are exhausted. For each etching particle, the following operations are performed: the bombardment position on the object to be etched that receives the etching particles is calculated, the atomic properties of the bombardment position are determined, different etching functions are selected according to the atomic properties, and when the removal conditions of the etching function are met, the atoms at the bombardment position are removed to finally obtain a basic etching profile.

[0049] Optionally, for each etching particle, calculating a bombardment position on the object to be etched where the etching particle is received, specifically includes:

[0050] The position coordinates of the emission source are used as the initial coordinates of the incident etching particles;

[0051] Matching an incident angle for incident etching particles within the incident angle range of the emission source;

[0052] According to the initial coordinates of the etching particles, the incident angle and each horizontal coordinate of the object to be etched, the vertical coordinate corresponding to each horizontal coordinate is calculated to determine the bombardment position.

[0053] Furthermore, for the etching particles incident from the left side, when calculating the bombardment position, the horizontal coordinate of the bombardment position increases from left to right, that is, each horizontal coordinate of the object to be etched is traversed from left to right, and the vertical coordinate corresponding to each horizontal coordinate is calculated;

[0054] For etching particles incident from the right, when calculating the impact position, the horizontal coordinate of the impact position increases from right to left, that is, each horizontal coordinate of the object to be etched is traversed from right to left, and the vertical coordinate corresponding to each horizontal coordinate is calculated.

[0055] According to the horizontal and vertical coordinates of the bombardment position, it is judged whether the bombardment position is on the object to be etched. If so, the atomic properties of the bombardment position are further judged, that is, whether it is a silicon atom or a silicon germanium atom. Different etching functions are selected according to the atomic properties. When the removal conditions of the etching function are met, the atoms at the bombardment position are removed. If the bombardment position obtained is outside the object to be etched, it is considered an invalid bombardment.

[0056] Figure 3 The basic etching profile of the multi-layer structure obtained after simulation of the embodiment of the present invention is shown, which is the first layer, the second layer, and the third layer from bottom to top. The SiGe layer in each layer is etched, and the Si layer is basically intact. And as the depth of the layer changes, the etching depth varies greatly. The closer the layer is to the silicon substrate, the smaller the etching depth. Figure 3 In the embodiment, the maximum etching depth of the first stack is 9.2 nm, the maximum etching depth of the second stack is 11.9 nm, and the maximum etching depth of the third stack is 14.2 nm.

[0057] In particular, when the number of layers of the stack is set to 1, the case of a single stack can be simulated. The single stack structure is a special case of the multi-stack structure and will not be explained separately.

[0058] The atomic layer etching process simulation method of a multi-layer structure provided by an embodiment of the present invention can reflect the difference in etching morphology between the silicon germanium layer and the silicon layer due to the different depths of multiple layers in the atomic layer etching (ALE) of the multi-layer structure. In a multi-layer structure, as the depth of the layers increases, the etching depth gradually decreases. Through the present invention, the etching morphology results can be predicted for the experiment, which is of great significance for saving experimental costs and adjusting process parameters to achieve expected success.

[0059] It is further explained that, regardless of whether it is a single-layer or multi-layer structure, the silicon layer will have corner damage and upper edge damage during the etching process. In order to reflect the corner damage and upper edge damage of the silicon layer in the etching profile, the present application adjusts the etching function of the silicon layer, obtains the basic etching profile, and then simulates the corner damage and upper edge damage of the silicon layer.

[0060] Figure 4FIG. 1 is a schematic diagram of a multi-layer atomic layer etching process simulation device provided by an embodiment of the present invention. Figure 4 As shown, the device includes: an initialization definition module 401, a particle number determination module 402 and a basic etching simulation module 403, wherein:

[0061] Initialization definition module 401, used to define structural information of an object to be etched, the object to be etched includes a silicon substrate and a plurality of stacked layers of silicon germanium layers / silicon layers stacked in sequence thereon, define etching functions of the silicon germanium layer and the silicon layer, and define position coordinates and incident angle ranges of left-side emission sources and right-side emission sources at different depths, the left-side emission source and the right-side emission source are used to irradiate etching particles from the left and right sides, respectively;

[0062] The particle number determination module 402 is used to determine the number of etching particles to be incident according to the etching time and the structural information of the object to be etched;

[0063] The basic etching simulation module 403 is used to sequentially inject etching particles into the object to be etched until the etching particles are exhausted. For each etching particle, the following operations are performed: calculating the bombardment position on the object to be etched that receives the etching particles, determining the atomic properties of the bombardment position, selecting different etching functions according to the atomic properties, and removing the atoms at the bombardment position when the removal conditions of the etching function are met, thereby finally obtaining a basic etching profile.

[0064] Furthermore, it also includes a silicon damage simulation module, which is used to simulate the corner damage and upper edge damage of the silicon layer after obtaining the basic etching profile.

[0065] The atomic layer etching process simulation device for a multi-layer structure provided in an embodiment of the present invention is used to execute the above method embodiment. Its specific process and detailed contents can refer to the above method embodiment and will not be repeated here.

[0066] Figure 5 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 5 As shown, the electronic device may include: a processor 501, a memory 502 and a communication bus 503, wherein the processor 501 and the memory 502 communicate with each other via the communication bus 503. The processor 501 may execute program instructions in the memory 502 to implement the atomic layer etching process simulation method of the multi-layer structure provided in the above embodiments.

[0067] On the other hand, an embodiment of the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the atomic layer etching process simulation method for a multi-layer structure provided in the above embodiments.

[0068] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0069] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for simulating an atomic layer etching process of a multi-layer structure, characterized in that: include: Defining structural information of an object to be etched, wherein the object to be etched includes a silicon substrate and a plurality of stacked layers of silicon germanium layers / silicon layers stacked in sequence thereon; Define the etching functions of the silicon germanium layer and the silicon layer respectively; Defining position coordinates and incident angle ranges of a left-side emission source and a right-side emission source at different depths, wherein the left-side emission source and the right-side emission source are used to irradiate etching particles from the left side and the right side, respectively; Determining the number of etching particles to be incident according to the etching time and the structural information of the object to be etched; Etching particles are sequentially incident on the object to be etched until the etching particles are exhausted. For each etching particle, the following operations are performed: the bombardment position on the object to be etched that receives the etching particles is calculated, the atomic properties of the bombardment position are determined, different etching functions are selected according to the atomic properties, and when the removal condition of the etching function is met, the atoms at the bombardment position are removed to finally obtain a basic etching profile.

2. The method according to claim 1, characterized in that: The structural information of the object to be etched is defined, including: Set the position coordinates of the object to be etched, the number of layers in the stack, the critical dimensions of the stack, the thickness of the silicon germanium layer and the silicon layer in the stack, and the STI depth.

3. The method according to claim 2, characterized in that The position coordinates and incident angle ranges of the left and right emission sources at different depths are defined, including: According to the ratio of the depth of each stack to the STI depth, the position coordinates and the incident angle range of the left emission source and the right emission source corresponding to each stack are determined respectively.

4. The method according to claim 1, characterized in that: For each etching particle, calculating the bombardment position of the object to be etched where the etching particle is received includes: The position coordinates of the emission source are used as the initial coordinates of the incident etching particles; Matching an incident angle for incident etching particles within the incident angle range of the emission source; According to the initial coordinates of the etching particles, the incident angle and each horizontal coordinate of the object to be etched, the vertical coordinate corresponding to each horizontal coordinate is calculated to determine the bombardment position.

5. The method according to claim 4, characterized in that For the etching particles incident from the left side, traverse each horizontal coordinate of the object to be etched from left to right, and calculate the vertical coordinate corresponding to each horizontal coordinate; For etching particles incident from the right side, each horizontal coordinate of the object to be etched is traversed from right to left, and the vertical coordinate corresponding to each horizontal coordinate is calculated.

6. The method according to claim 1, characterized in that The method further comprises: After obtaining the basic etching profile, the corner damage and upper edge damage of the silicon layer are simulated.

7. An atomic layer etching process simulation device for a multi-layer structure, characterized in that: include: An initialization definition module is used to define structural information of an object to be etched, wherein the object to be etched includes a silicon substrate and a plurality of stacks of silicon germanium layers / silicon layers stacked in sequence thereon, define etching functions of the silicon germanium layer and the silicon layer, and define position coordinates and incident angle ranges of left-side emission sources and right-side emission sources at different depths, wherein the left-side emission source and the right-side emission source are used to irradiate etching particles from the left and right sides, respectively; A particle number determination module is used to determine the number of etching particles to be incident according to the etching time and the structural information of the object to be etched; The basic etching simulation module is used to sequentially inject etching particles into the object to be etched until the etching particles are exhausted. For each etching particle, the following operations are performed: calculating the bombardment position on the object to be etched that receives the etching particles, determining the atomic properties of the bombardment position, selecting different etching functions according to the atomic properties, and removing the atoms at the bombardment position when the removal conditions of the etching function are met, thereby finally obtaining a basic etching profile.

8. The device according to claim 7, characterized in that The device also includes: The silicon damage simulation module is used to simulate the corner damage and upper edge damage of the silicon layer after obtaining the basic etching profile.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method for simulating an atomic layer etching process of a multi-layer structure as described in any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for simulating an atomic layer etching process of a multi-layer structure as claimed in any one of claims 1 to 6 is implemented.

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