Quantum computing methods and systems

Abstract

This application provides a quantum computing method and system. The method includes: decomposing a target problem into multiple quantum circuits, wherein the multiple quantum circuits include at least two different configurations; implementing the multiple quantum circuits and obtaining target parameters for solving the target problem; and performing quantum computing on the target problem based on the target parameters. The above technical solution can decompose a target problem into multiple quantum circuits of different configurations and use these multiple quantum circuits to solve the target problem. Therefore, the number of qubits input to each quantum circuit in the above technical solution is relatively small, making it easier to implement and allowing for faster determination of the target parameters, thereby obtaining the solution to the target problem.

Description

Technical Field

[0001] The present application relates to the field of quantum computers, and more specifically, to quantum computing methods and systems. Background Art

[0002] Quantum computers are new computers based on quantum mechanics properties such as quantum superposition and quantum entanglement. Quantum computers can compress computing tasks that would take tens of thousands of years for classical computers into just a few hours or minutes. At the application level, quantum computers can be used in new material research and development, drug design, encryption systems, complex optimization scheduling and other fields. Currently, the world's top technology companies and countries such as China, the United States, the European Union, and the United Kingdom have invested heavily in the research of quantum computers. Summary of the invention

[0003] The embodiments of the present application provide a quantum computing method and system, which can improve the speed of solving problems using quantum computers and reduce the difficulty of implementing quantum circuits.

[0004] In a first aspect, an embodiment of the present application provides a quantum computing method, comprising: determining N quantum circuits corresponding to a target problem, wherein the N quantum circuits include at least two quantum circuits of different configurations, and N is a positive integer greater than or equal to 2; implementing the N quantum circuits to obtain target parameters for solving the target problem; and performing quantum computing on the target problem according to the target parameters.

[0005] The above technical solution can decompose the target problem into multiple quantum circuits of different configurations, and use the multiple quantum circuits of different configurations to solve the target problem. The existing solution often defines a problem as a quantum circuit. The more quantum bits the quantum circuit inputs, the more difficult it is to implement. Compared with the existing solution, the number of quantum bits input to each quantum circuit in the above technical solution is small, so it is easier to implement, and the target parameters can be determined faster, thereby obtaining the solution to the target problem.

[0006] In some embodiments, the target problem may be a problem that can be converted into an Ising model, for example, a combinatorial optimization problem.

[0007] In combination with the first aspect, in a possible implementation manner of the first aspect, implementing the N quantum circuits to obtain target parameters for solving the combinatorial optimization problem includes: using the N quantum circuits to prepare N groups of first quantum states; measuring the N groups of first quantum states to obtain N groups of first measurement results, wherein the N groups of first quantum states correspond one-to-one to the N quantum circuits; and determining the target parameters according to the N groups of first measurement results.

[0008] In combination with the first aspect, in a possible implementation manner of the first aspect, implementing the N quantum circuits to obtain target parameters for solving the target problem includes: implementing the N quantum circuits in parallel to obtain target parameters for solving the target problem.

[0009] In some embodiments, implementing the N quantum circuits in parallel to obtain target parameters for solving the target problem may include: implementing the N quantum circuits in parallel and using the N quantum circuits in parallel to prepare N groups of first quantum states; and measuring the N groups of first quantum states in parallel to obtain N groups of first measurement results.

[0010] In combination with the first aspect, in a possible implementation of the first aspect, the determining of N quantum circuits corresponding to the target problem includes: determining an Ising model corresponding to the target problem; determining a weight graph corresponding to the Ising model; determining N subgraphs according to the weight graph; determining the N quantum circuits according to the N subgraphs, the N quantum circuits and the N subgraphs Figure 1 One to one correspondence.

[0011] In combination with the first aspect, in a possible implementation method of the first aspect, the determining N subgraphs based on the weight graph includes: decomposing the weight graph to obtain M subgraphs, the M subgraphs including N different subgraph structures, M being a positive integer greater than N; performing a matching operation on the M subgraphs according to a subgraph library to obtain the N subgraphs, wherein the structures of the N subgraphs are respectively the N different subgraph structures.

[0012] The quantum circuits obtained from subgraphs with the same structure are the same. In the above technical solution, only one subgraph is reserved for each subgraph of each structure, which can reduce the total number of quantum circuits determined, so that the target parameters can be obtained more quickly according to the quantum circuits.

[0013] In combination with the first aspect, in a possible implementation of the first aspect, the decomposing the weight graph includes: decomposing the weight graph with a line depth of P, where P is a positive integer greater than or equal to 1 and less than or equal to 20.

[0014] In combination with the first aspect, in a possible implementation manner of the first aspect, before implementing the N quantum circuits, the method further includes: determining an implementation method of the N quantum circuits according to configuration information, wherein the configuration information includes one or more of the following information: the scale of the target problem, the density of the target problem, or the circuit depth when decomposing the weight graph, and the implementation method of the N quantum circuits includes implementing the N quantum circuits using a quantum processor or implementing the N quantum circuits using a simulator.

[0015] In combination with the first aspect, in a possible implementation of the first aspect, determining the target parameter for solving the target problem based on the N groups of first measurement results includes: determining a first target Hamiltonian expected value based on the N groups of first measurement results; determining an optimization parameter; determining a second target Hamiltonian expected value based on the optimization parameter and the first reference Hamiltonian expected value; determining whether the second target Hamiltonian expected value meets a preset condition; if the second target Hamiltonian expected value meets the preset condition, determining the optimization parameter to be the target parameter.

[0016] In combination with the first aspect, in a possible implementation manner of the first aspect, if the expected value of the second target Hamiltonian does not satisfy the preset condition, the N quantum circuits are updated according to the optimization parameter; N groups of second quantum states are prepared using the updated N quantum circuits and the N groups of second quantum states are measured to obtain N groups of second measurement results, and the N groups of second quantum states correspond one-to-one to the updated N quantum circuits; and the target parameter is determined according to the N groups of second measurement results.

[0017] In combination with the first aspect, in a possible implementation of the first aspect, the determining the expected value of the first target Hamiltonian according to the N groups of first measurement results includes: in the case of decomposing the weight graph to obtain K groups of subgraphs, determining the number of subgraphs included in each group of subgraphs in the K groups of subgraphs, wherein each group of subgraphs in the K groups of subgraphs includes at least two subgraphs with the same structure, and K is a positive integer greater than or equal to 1 and less than or equal to N; determining K groups of first measurement results from the N groups of first measurement results, and the K groups of first measurement results and the K groups of subgraphs are compared. Figure 1 One-to-one correspondence; determining K groups of corrected measurement results, wherein the kth group of corrected measurement results in the K groups of corrected measurement results is the product of the kth group of first measurement results in the K groups of first measurement results and the number of subgraphs included in the kth group of subgraphs in the K groups of subgraphs, k=1, ..., K; determining the expected value of the first target Hamiltonian according to the following formula:

[0018]

[0019] in, Corr_R represents the expected value of the first target Hamiltonian. k represents the kth group of calibration measurement results among the K groups of calibration measurement results, R n Indicates the nth group of first measurement results among the N groups of first measurement results excluding the K group of measurement results.

[0020] In a second aspect, an embodiment of the present application provides a quantum computing system, which includes a quantum circuit determination module, a parameter determination module and a solution module. The quantum circuit determination module is used to determine N quantum circuits corresponding to a target problem, wherein the N quantum circuits include at least two quantum circuits of different configurations, and N is a positive integer greater than or equal to 2. The parameter determination module is used to implement the N quantum circuits to obtain target parameters for solving the target problem. The solution module is used to perform quantum computing on the target problem according to the target parameters.

[0021] In some embodiments, the parameter determination module includes a quantum circuit implementation module and a parameter optimization module, the quantum circuit implementation module is used to prepare N groups of first quantum states using the N quantum circuits; the quantum circuit implementation module is also used to measure the N groups of first quantum states to obtain N groups of first measurement results, wherein the N groups of first quantum states correspond one-to-one to the N quantum circuits; the parameter optimization module is used to determine the target parameter based on the N groups of first measurement results.

[0022] In some embodiments, the quantum circuit determination module, the quantum circuit implementation module and the parameter optimization module can be implemented by a classical computer; the solution module can be implemented by a quantum computer.

[0023] In other embodiments, the quantum circuit determination module and the parameter optimization module can be implemented by a classical computer; the quantum circuit implementation module and the solution module can be implemented by a quantum computer.

[0024] The quantum circuit determination module, the parameter determination module (quantum circuit implementation module parameter optimization module) and the solution module can implement the first aspect or any possible implementation method of the first aspect.

[0025] In a fourth aspect, an embodiment of the present application provides a chip, comprising: a logic circuit, which is used to couple with an input / output interface and transmit data through the input / output interface to execute the method of the first aspect above or any possible implementation method of the first aspect.

[0026] In a fifth aspect, an embodiment of the present application provides a computer-readable medium, which stores a program code. When the computer program code runs on a computer, the computer executes the method of the first aspect above or any possible implementation method of the first aspect.

[0027] In a sixth aspect, an embodiment of the present application provides a classical computer device, which includes a memory and a classical processor, the classical processor is coupled to the memory, reads and executes instructions and / or program codes in the memory to perform the first aspect or any possible implementation of the first aspect. For example, the classical processor can execute instructions in the memory to determine N quantum circuits and target parameters. The classical processor can also control the quantum computer to implement the determined quantum circuit and measure the quantum circuit to achieve quantum computing based on the determined quantum circuit.

[0028] In a seventh aspect, an embodiment of the present application provides a quantum computer device, which includes a quantum processor, a measuring device, and a peripheral controller. The quantum processor combines the measuring device and the peripheral controller to implement the quantum computing in the first aspect or any possible implementation of the first aspect.

[0029] For example, the peripheral controller generates microwave or laser light control signals according to the control signals of the classical computer, and operates on the quantum processor to implement quantum gate operations. The measurement device is used to measure the quantum state generated by the quantum processor to obtain the quantum calculation result, that is, the solution to the target problem.

[0030] For another example, the peripheral controller generates a microwave or laser light control signal according to the control signal of the classical computer, and operates on the quantum processor to realize the N quantum circuits determined by the classical computer. The measuring device is used to measure the quantum state generated by the quantum processor to obtain the measurement results of the N quantum circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of an application scenario of the method for determining parameters provided in an embodiment of the present application.

[0032] Figure 2 is a schematic diagram of a computing system used to perform quantum computing.

[0033] Figure 3 It is a schematic diagram of a quantum computer system provided according to an embodiment of the present application.

[0034] Figure 4 is the weight graph corresponding to the Q matrix of formula 1.8.

[0035] Figure 5 Yes Figure 4 The subgraphs obtained by decomposing the weight graph shown.

[0036] Figure 6 It is a schematic flowchart of determining a subgraph in a subgraph library.

[0037] Figure 7 It is a schematic diagram of a subgraph tree.

[0038] Figure 8 is corresponding to Figure 6 Another representation of the flow chart shown.

[0039] Fig. 9 is a randomly generated subgraph tree with P equal to 1.

[0040] Fig.10 It is the problem graph of the quadratic unconstrained binary optimization problem model.

[0041] Fig.11 is a subgraph tree with P equal to 2.

[0042] Fig.12 It is a schematic diagram of a subgraph tree.

[0043] Fig.13 It is a subgraph tree that can be saved in the subgraph library.

[0044] Fig.14 It is a schematic diagram of a quantum circuit for finding the expected value corresponding to a subgraph obtained by decomposing the circuit with a circuit depth of P.

[0045] Fig.15 is and Figure 5 The quantum circuit corresponding to the subgraph shown in (a) in .

[0046] Fig.16 is and Figure 5 The quantum circuit corresponding to the subgraph shown in (b) in .

[0047] Fig.17 It is a schematic diagram of multiple parallel quantum circuits obtained by decomposing the target problem.

[0048] Fig.18 It is a schematic diagram comparing the test results of the existing technical solutions in the industry and the technical solution of the present application in the 18-bit graph coloring scenario.

[0049] Fig.19 The test results of using the technical solution of the present application with more quantum bits are shown.

[0050] Fig. 20 It is a schematic flow chart of a quantum computing method provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0052] The present application will present various aspects, embodiments or features around a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0053] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0054] In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" can sometimes be used interchangeably. It should be pointed out that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0055] In the embodiments of the present application, sometimes a subscript such as W1 may be mistakenly written as a non-subscript such as W1. When the difference is not emphasized, the meanings to be expressed are consistent.

[0056] The network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0057] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0058] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0059] Figure 1 Schematic diagram of an application scenario of the method for determining parameters provided in an embodiment of the present application. Figure 1 As shown, the application scenario can be divided into three layers, namely application layer, algorithm layer and physical layer.

[0060] The application layer represents some fields to which the method for determining parameters provided in the embodiments of the present application can be applied. The method for determining parameters provided in the present application can be applied to solve problems that can be converted into an Ising model.

[0061] The Ising model was proposed to explain the phase transition of ferromagnetic materials, that is, the magnetism of a magnet disappears when heated above a certain critical temperature, and it becomes magnetic again when cooled below the critical temperature. Due to the high degree of abstraction of the Ising model, it can be easily applied to other fields. For example, the Ising model can be applied to problems such as the stock market, racial segregation, and political choices. The Ising model can also be used to model neural network systems, thereby building machines that can adapt to the environment and continuously learn (such as Hopfield networks or Boltzmann machines, etc.).

[0062] Combinatorial optimization problems are typical problems that can be converted into Ising models. Common combinatorial optimization problems include spectrum allocation problems, route planning problems, financial analysis problems, drug development problems, graph coloring problems, work scheduling problems, etc.

[0063] The algorithm layer is used to determine the strategy for solving the task, process the data of the task according to the determined strategy, and determine the algorithm used to process the task data.

[0064] Different tasks can correspond to different strategies. The Ising model building module in the algorithm layer can determine the corresponding Ising model according to the problem to be solved.

[0065] The graph decomposition module in the algorithm layer can determine the weight graph corresponding to the Ising model, and decompose the determined weight graph to obtain multiple subgraphs.

[0066] The automatic judgment module can determine subgraphs with the same structure. Only one subgraph is retained for each subgraph structure.

[0067] The quantum compiler determines the corresponding quantum circuit and the parameters of the quantum circuit according to the determined subgraph, and sends the parameters to the quantum circuit implementation module of the physical layer.

[0068] The quantum circuit realization module is used to realize a certain quantum circuit and measure the output of the quantum circuit. The quantum circuit realization module can be realized by a quantum computing machine or a classical simulation machine. Common classical simulation machines can include circuit simulators, tensor simulators, etc.

[0069] The classic optimizer is used to optimize the parameters.

[0070] The physical layer determines the target parameters and the optimal output based on the classical optimizer, and then the optimal output obtained by the classical computer or quantum computer can be fed back to the application layer. This optimal output is the solution to the problem that needs to be solved.

[0071] Figure 2 is a schematic diagram of a computing system used to perform quantum computing. Figure 2 The system 200 shown can be divided into a quantum computer part 210 and a classical computer part 220. The quantum computer part 210 includes a quantum processor 211, a measuring device 212, and a peripheral controller 213. The classical computer part 220 includes a classical processor 221 and a memory 222. The memory 222 is used to store instructions and / or codes, and the classical processor 221 is used to run the instructions and / or codes running in the memory 222, and realize quantum computing in combination with the quantum computer part.

[0072] The classical processor 221 can determine the corresponding quantum circuit according to the acquired parameters. The classical processor 221 can control the peripheral controller 213 in the quantum computer 210 to generate control signals such as microwaves or lasers according to the determined quantum circuit, operate on the quantum processor 211, implement quantum gate operations on the quantum processor 211, and control the measurement device 212 in the quantum computer 210 to measure the quantum state generated by the quantum processor 211.

[0073] Figure 3 Schematic diagram of a quantum computer system provided according to an embodiment of the present application. Figure 3 The components in the quantum computer system 300 are divided according to their functions. Figure 3As shown, the quantum computer system 300 includes a quantum circuit determination module 310 , a parameter determination module 320 and a solution module 330 .

[0074] The quantum circuit determination module 310 is used to determine a plurality of quantum circuits corresponding to the target problem to be solved.

[0075] In some embodiments, the plurality of quantum circuits include at least two quantum circuits of different configurations. The quantum circuits of different configurations may include quantum circuits with different quantum gates, or may include quantum circuits with the same type of quantum gates but with different connection relationships between the quantum gates.

[0076] The target problem may be a combinatorial optimization problem that can be converted into an Ising module problem, such as a spectrum allocation problem, a graph coloring problem, a work scheduling problem, and the like.

[0077] The parameter determination module 320 is used to implement the multiple quantum circuits to obtain target parameters for solving the target problem.

[0078] The solution module 330 is used to perform quantum calculation on the target problem according to the target parameters determined by the parameter optimization module 322 to obtain a solution to the target problem.

[0079] In some embodiments, the parameter determination module 320 may implement the multiple quantum circuits in parallel to obtain target parameters for solving the target problem.

[0080] In some embodiments, the parameter determination module 320 may include a module quantum circuit implementation module 321 and a parameter optimization module 322 .

[0081] The quantum circuit realization module 321 is used to realize the multiple quantum circuits determined by the quantum circuit determination module 310 and measure the quantum states prepared by the quantum circuits to obtain measurement results.

[0082] The parameter optimization module 322 is used to determine the target parameters for solving the target problem according to the measurement results obtained by the quantum circuit implementation module 321.

[0083] Implementing the plurality of quantum circuits in parallel to obtain target parameters for solving the target problem may include implementing the plurality of quantum circuits in parallel and measuring quantum states prepared by the quantum circuits in parallel.

[0084] The quantum circuit determination module 310 and the parameter optimization module 322 can be implemented by a classical computer. The solution module 330 can be implemented by a quantum computer. The quantum circuit implementation module 321 can be implemented by a classical computer or a quantum computer.

[0085] The classical computers used to implement the quantum circuit determination module 310, the quantum circuit implementation module 321 and the parameter optimization module 322 can be the same classical computer or different classical computers. The quantum computers used to implement the quantum circuit implementation module 321 and the solution module 330 can also be the same quantum computer or different quantum computers.

[0086] For example, Figure 2 The quantum computer 210 shown can be used to implement Figure 3 The solution module 330 and the quantum circuit realization module 321 are shown; the classical computer 220 can be used to realize the quantum circuit determination module 310 and the parameter optimization module 322.

[0087] For example, Figure 2 The quantum computer shown can be used to implement Figure 3 The solution module 330 shown; the classical computer 220 can be used to implement the quantum circuit determination module 310, the quantum circuit implementation module 321 and the parameter optimization module 322.

[0088] Next, taking graph coloring as an example, combined with Figure 3 The system 300 shown introduces the technical solution provided by the embodiment of the present application. It can be understood that in addition to being applied to solving the graph coloring problem, the method provided by the embodiment of the present application can also be applied to solve other problems that can be converted into the Ising model.

[0089] The specific statement of the graph coloring problem is: there are s grid points in the graph, and now there are t colors. It is required to paint a grid point with a color, and adjacent grid points cannot be painted with the same color.

[0090] The binary variables in the graph coloring problem can be expressed as Formula 1.1:

[0091]

[0092] where x u,i Indicates the color of the uth grid point among the s grid points is the ith color among the colors in t. If x u,i =1, it means the color of the uth grid point is color i; if x u,i =0, it means that the color of the u-th grid point is other colors.

[0093] Since each grid point can only be painted with one color, the binary variable needs to meet the following conditions:

[0094]

[0095] At the same time, since adjacent grid points cannot be painted with the same color, the binary variable must meet the following conditions at the same time:

[0096]

[0097] Among them, (u,v) represents the edge connecting the grid point u and the grid point in the graph.

[0098] Construct an objective function with a penalty value, which is as follows:

[0099]

[0100] Where P represents the penalty value, and the value of P is a positive real number. The specific value of P is related to the actual demand. The objective function shown in Formula 1.4 ensures that the minimum value is taken when the conditions of Formula 1.2 and Formula 1.3 are met, that is, H = 0.

[0101] In order to execute quantum algorithms, new binary variables need to be introduced. The relationship between the new binary variables and the original binary variables is:

[0102]

[0103] where σ u,i is a newly introduced binary variable, σ u,i ∈{1,-1}.

[0104] The objective function shown in Formula 1.4 becomes:

[0105]

[0106] Where H0 is a constant term and does not affect the final result, so it can be ignored. Formula 1.6 satisfies the general form of the Ising model, that is:

[0107] H Ising =∑ i≠j Q ij σ i σ j +∑ k Q kk σ k , Formula 1.7

[0108] The target Hamiltonian is equal to Formula 1.7, that is, H cost =H Ising .

[0109] The Ising model shown in Equation 1.7 can be represented as a symmetric Q matrix as shown below:

[0110]

[0111] Figure 4 is the weight graph corresponding to the Q matrix of formula 1.8.

[0112] The quantum circuit determination module 310 can determine the corresponding weight graph according to the input target problem.

[0113] After determining the weight graph, the quantum circuit determination module 310 may decompose the weight graph into multiple subgraphs.

[0114] The circuit depth of the weight graph decomposed by the quantum circuit determination module 310 can be represented by P. P is a positive integer greater than or equal to 1.

[0115] For example, Figure 5 Yes Figure 4 The subgraphs obtained by decomposing the weight graph shown.

[0116] Figure 5 (a) is the case where the edge (i, j) is the starting point and P = 1. Figure 4 The subgraphs obtained by decomposing the weight graph shown.

[0117] Figure 5 (b) is the case where grid point k is the starting point and P = 1. Figure 4 The subgraphs obtained by decomposing the weight graph shown.

[0118] In some embodiments, the quantum circuit determination module 310 may determine a corresponding quantum circuit for each subgraph.

[0119] Assuming that the quantum circuit determination module 310 decomposes the weight graph to obtain M subgraphs (M is a positive integer greater than or equal to 2), the quantum circuit module 310 can determine M quantum circuits. Figure 1 In a one-to-one correspondence, each quantum circuit in the M quantum circuits is determined according to the corresponding subgraph. In other words, the quantum circuit determination module 310 can determine the first quantum circuit in the M quantum circuits according to the first subgraph in the M subgraphs; determine the second quantum circuit in the M quantum circuits according to the second subgraph in the M subgraphs, and so on.

[0120] In some other embodiments, there may be subgraphs with the same structure among the multiple subgraphs obtained after the quantum circuit determination module 310 decomposes the weight graph. In this case, the quantum circuit determination module 310 can delete the redundant subgraphs in each structure, and only retain one subgraph with different subgraph structures.

[0121] Assume that the quantum circuit determination module 310 decomposes the weight graph to obtain M subgraphs; the M subgraphs are matched to determine that the M subgraphs include N different subgraph structures. In this case, the result of decomposing the weight graph is to obtain N subgraphs, and the structures of the N subgraphs are N different subgraph structures.

[0122] For example, the quantum circuit determination module 310 can obtain 9 subgraphs after decomposing the weight graph, where Figure 1 To the son Figure 4 The structure and Figure 5 The subgraph shown in (a) is the same as Figure 5 To the son Fig. 9 The structure and Figure 5 The result obtained by the quantum circuit determination module 310 decomposing the weight graph may include only two subgraphs, namely Figure 5 In this case, the quantum circuit determination module 310 only needs to determine two quantum circuits, one quantum circuit and Figure 5 The other quantum circuit corresponds to the subgraph shown in (a) Figure 5 If the subgraphs with the same structure are not deleted, the quantum circuit determination module 310 needs to determine 9 quantum circuits, which correspond to the 9 subgraphs. Figure 1 One corresponds to the other, and the nine quantum circuits correspond to Figure 1 To the son Figure 4 The four quantum circuits are the same, corresponding to Figure 5 To the son Fig. 9 The five quantum circuits are identical.

[0123] The quantum circuit determination module 310 may use the subgraph library to perform a matching operation on the subgraph.

[0124] The quantum circuit determination module 310 can use the subgraph library to perform a matching operation on the subgraph in the following manner: after decomposing the weight graph to obtain M subgraphs, each subgraph in the M subgraphs is compared with the subgraphs in the subgraph library. If the structures of multiple subgraphs in the M subgraphs are the same as the structure of the same subgraph in the subgraph library, the subgraph can be recorded; if a subgraph in the M subgraphs does not appear in the subgraph library, or a subgraph in the subgraph library appears only once in the M subgraphs, then the subgraph is recorded.

[0125] For example, suppose the quantum circuit determination module 310 decomposes the weight graph to obtain sub-graphs. Figure 1 To the son Fig.15 The sub-graph library includes sub-graphs A to Z. Assume that the sub-graphs Figure 1 To the son Figure 8 Same as subgraph A, subgraph Fig. 9 Same as sub-graph B, sub-graph Fig.10 To the son Fig.14 Same as subgraph C, there is no subgraph in the subgraph library. Fig.15 If there is a matching subgraph, then the subgraphs that the quantum circuit determination module 310 can obtain according to the weight graph include: subgraph A (also called subgraph Figures 1 to 8 Any one of them), subgraph B, subgraph C (also called subgraph Fig.10 To the son Fig.14 Any of ) and Fig.15 , a total of 4 subgraphs.

[0126] In some embodiments, the sub-image library may be the result of the accumulation of previous tasks. For example, the initial sub-image library is empty. Figure 5 The two subgraphs shown are the subgraphs obtained by decomposing the weight graph when executing the first solution to the target problem. Figure 5 The two subgraphs shown are saved to the subgraph library. When executing the second target problem, the weight graph can be decomposed to obtain multiple subgraphs, and the obtained multiple subgraphs can be saved to the subgraph library. In this way, as the number of target problems to be solved increases, the number of subgraphs saved in the subgraph library also increases.

[0127] In addition, before saving a sub-image to the sub-image library, it may be determined whether the same sub-image has been saved in the sub-image library. If so, it is not necessary to save the sub-image; if not, the sub-image is saved.

[0128] In other embodiments, the sub-graph library may be predetermined and stored in the quantum circuit determination module 310 .

[0129] Figure 6 It is a schematic flowchart of determining a subgraph in a subgraph library.

[0130] 601. According to the value of P, first search whether a subgraph of P-1 already exists in the subgraph library.

[0131] If a subgraph of P-1 already exists, the subgraph is represented as a corresponding tree structure. For ease of description, the tree structure corresponding to the subgraph can be called a subgraph tree.

[0132] A subgraph tree is a regular graph. For example Figure 7 is a schematic diagram of a subgraph tree. Figure 7 Node 0 in the subgraph tree shown only reflects that node 1 and node 2 are connected by default.

[0133] like Figure 7 In the subgraph tree shown, the left node of a node x is labeled x+1, and the right node is labeled (d-1)×(x+1). d represents the number of edges connected to each node in the graph. Figure 7 The graph shown is a regular 3 graph, that is, d = 2. Therefore, the left and right nodes of node x are labeled x+1 and 2×(x+1) respectively.

[0134] Figure 7Each value of P in corresponds to a tree with a line depth of P+2. For example, the tree structure corresponding to P=1 is Figure 7 For nodes above the third level, the tree structure corresponding to P equals 2 is Figure 7 Nodes above level 4 in .

[0135] If there is no subgraph of P-1, you need to recursively generate the P-1 subgraph tree first.

[0136] 602, extending all nodes in the P-1 corresponding layer in the subgraph tree, so that the subgraph tree is extended to the P corresponding layer.

[0137] The values ​​of the left and right nodes of the layer corresponding to P-1 can be determined in the above manner, that is, the left node of node x is labeled x+1, and the right node is labeled (d-1)×(x+1).

[0138] 603, determine a set of connectable nodes from the layer corresponding to P.

[0139] The set of connectable points includes positive integers that are greater than or equal to the left child node index and less than or equal to the right child node index.

[0140] 604. Randomly select d-1 elements from the connectable node set, and determine a subgraph according to the selected elements.

[0141] 605, determining whether the sub-graph determined in step 604 complies with the storage rules. If the sub-graph complies with the storage rules, the sub-graph is saved in the sub-graph library; if the sub-graph does not comply with the storage rules, the sub-graph is deleted.

[0142] The entry rules may include: whether the subgraph meets the regularity requirements. If a node that does not meet the regularity requirements appears in the subgraph, the subgraph does not meet the entry rules; if all nodes in the subgraph meet the regularity requirements, the subgraph meets the entry rules. Whether the subgraph meets the regularity requirements can be called regularity screening.

[0143] The entry rules may include: whether the same subgraph already exists in the subgraph library. If the same subgraph exists in the subgraph library, the subgraph does not meet the entry rules; if the same subgraph does not exist in the subgraph library, the subgraph meets the entry rules. Whether the same subgraph already exists in the subgraph library can be called isomorphism screening.

[0144] Of course, the entry rules can also include regularity screening and isomorphism screening. If there is no identical subgraph in the subgraph library and the subgraph meets the regularity requirement, it can be determined that the subgraph meets the entry rules; if there is an identical subgraph in the subgraph library or the subgraph does not meet the regularity requirement, it can be determined that the subgraph does not meet the entry rules.

[0145] After executing step 605, the same method is continued to be used to determine the sub-image, and to determine whether the sub-image can be saved in the sub-image library.

[0146] Figure 6 In the method shown, the P-layer subgraph tree is generated based on the P-1-layer subgraph tree. In other embodiments, the P-layer subgraph tree may also be directly generated.

[0147] Figure 8 is corresponding to Figure 6 Another representation of the flow chart shown.

[0148] Next, combine Figures 9 to 13 A detailed description is given of how to determine a sub-image in a sub-image library.

[0149] Fig. 9 is a randomly generated subgraph tree with P equal to 1.

[0150] like Fig. 9 The subgraph tree shown corresponds to Fig.10 The quadratic unconstrained binary optimization problem (QUBO) model problem diagram is shown. The QUBO model is a mathematical model corresponding to the combinatorial optimization problem.

[0151] Based on Fig. 9 The subgraph tree with P equal to 1 shown in the figure can be obtained as follows Fig.11 Shown is the subgraph tree with P equal to 2.

[0152] According to Fig.11 The subgraph tree shown in Figure 2 randomly generates two random extension nodes in the corresponding layer when P is equal to 2, and the following is obtained: Fig.12 The subgraph tree shown.

[0153] For example, Fig.11 The leftmost node is numbered 3, and its two child nodes are numbered 4 and 8. Then, the set of connectable nodes of this node in the corresponding layer where P is equal to 2 is a positive integer greater than or equal to 4 and less than or equal to 8. Assuming that the randomly selected positive integers are 5 and 6, we can get the following: Fig.12 The two child nodes of the node labeled 3 in the subgraph tree shown.

[0154] For example, Fig.11 The node numbered 4 has two child nodes numbered 5 and 10. Then, the set of connectable nodes of this node in the corresponding layer with P equal to 2 is a positive integer greater than or equal to 5 and less than or equal to 10. Assuming that the randomly selected positive integers are 5 and 6, we can get the following: Fig.12The two child nodes of the node labeled 4 in the subgraph tree shown.

[0155] Final basis Fig.12 The subgraph tree shown can be obtained as Fig.13 The QUBO model problem diagram is shown.

[0156] If Fig.13 The subgraph shown passes the regularity and isomorphism screening, and can be Fig.13 Save to sub-library.

[0157] As described above, the quantum circuit determination module 310 can determine a corresponding quantum circuit for each subgraph. The quantum circuit is used to determine the expected value corresponding to the subgraph.

[0158] Fig.14 It is a schematic diagram of a quantum circuit for finding the expected value corresponding to a subgraph obtained by decomposing the circuit with a circuit depth of P.

[0159] like Fig.14 In the P-layer logic gate operation module shown, except for the different parameters γ and β, the other gate operations are the same.

[0160] Below Figure 5 As an example, the two sub-graphs shown in the figure are introduced corresponding to Figure 5 Quantum circuits of the two subgraphs shown.

[0161] Fig.15 is and Figure 5 The quantum circuit corresponding to the subgraph shown in (a) in .

[0162] Fig.15 Two-bit quantum gate operation in Indicates that a two-bit quantum gate operation is performed on quantum bit ij, and we get

[0163] Fig.15 Single-bit quantum gate operations in It means that the single-bit quantum gate operation on quantum bit k is obtained

[0164] Fig.15 Single-bit quantum gate operations in It means that the single-bit quantum gate operation on quantum bit k is obtained

[0165] Fig.16 is and Figure 5 The quantum circuit corresponding to the subgraph shown in (b) in .

[0166] Fig.16 The meaning of each quantum gate operation in Fig.15The meaning of the quantum gate operation of the quantum circuit shown is similar, and for the sake of brevity, it will not be repeated here.

[0167] Fig.15 and Fig.16 Two quantum circuits with different configurations.

[0168] The quantum circuit determination module 310 is responsible for determining the quantum circuit. The realization and measurement of the quantum circuit can be performed by the quantum circuit realization module 321.

[0169] In some embodiments, the quantum circuit determination module 310 can also determine the implementation method of the quantum circuit according to the configuration information. The configuration information can include the scale, density and circuit depth of the target problem. The implementation method of the quantum circuit can be to implement the quantum circuit through a quantum processor or to implement the quantum circuit through a simulator.

[0170] Table 1 is a schematic diagram of the corresponding relationship between configuration information and implementation methods.

[0171] Table 1

[0172] Scale(N) Line depth (P) Density (d) Implementation N<30 P<50 d>10 Line Simulator N>30 P<10 d<10 Tensor Simulator 50<N<100 P<3 d>10 NISQ Quantum Processor

[0173] As shown in Table 1, if N is greater than 50 and less than 100, P is less than 3, and d is greater than 10, then a noisy intermediate-scale quantum (NISQ) quantum processor may be used to implement the quantum circuit determined by the quantum circuit determination module 310 .

[0174] Assume that the quantum circuit determination module 310 determines N quantum circuits. Then the quantum circuit realization module 321 can realize the N quantum circuits, use the N quantum circuits to prepare N groups of first quantum states, and measure the N groups of first quantum states to obtain N groups of first measurement results, and the N groups of first quantum states correspond one to one to the N quantum circuits.

[0175] Also as Fig.15 and 16 Taking the two quantum circuits shown as an example, the quantum circuit realization module 321 can realize the two quantum circuits determined by the quantum circuit determination module 310, and the user prepares two groups of quantum states using the two quantum circuits, and measures the two groups of quantum states to obtain a first measurement result.

[0176] like Figure 5 The subgraph shown in (a) is the subgraph obtained by taking edge ij as the starting point, so in Fig.15In the quantum circuit shown, the quantum states of the two quantum bits corresponding to the edge ij need to be measured to obtain a first measurement result of the quantum circuit. The first measurement result includes two expected values, namely, the expected value of the quantum bit corresponding to i and the expected value of the quantum bit corresponding to j.

[0177] like Figure 5 The subgraph shown in (b) is a subgraph obtained by taking grid point k as the starting point, so in Fig.16 In the quantum circuit shown, the quantum state of the quantum bit corresponding to the lattice point k needs to be measured to obtain a first measurement result of the quantum circuit. The first measurement result includes an expected value, that is, the expected value of the quantum bit corresponding to k.

[0178] If the quantum circuit determination module 310 does not delete redundant subgraphs in each structure after decomposing the weight graph, the parameter optimization module 322 can synthesize the measurement results to obtain the first target Hamiltonian expected value, which can be equal to the sum of all measurement results.

[0179] Also Fig.15 and Fig.16 Assume that the quantum circuit determination module 310 decomposes the weight graph to obtain only two subgraphs, which are Figure 5 The subgraph shown in (a) and Figure 5 Then, by measuring the quantum circuits corresponding to these two subgraphs, two sets of first measurement results can be obtained. One set of first measurement results is Fig.15 The measurement results obtained by measuring the quantum circuit shown include the expected value of the quantum bit corresponding to i (which can be expressed by R i ) and the expected value of the quantum bit corresponding to j (which can be represented by R j Another set of first measurement results is as follows Fig.16 The measurement results obtained by measuring the quantum circuit shown include the expected value of the quantum bit corresponding to k (which can be expressed by R k ). In this case, the expected value of the first target Hamiltonian can be determined according to the following formula:

[0180]

[0181] in, Represents the expected value of the first target Hamiltonian.

[0182] If the quantum circuit determination module 310 deletes redundant subgraphs in each structure after decomposing the weight graph, the parameter optimization module 322 can determine the number of subgraphs included in each group of subgraphs in the K groups of subgraphs when decomposing the weight graph to obtain K groups of subgraphs, wherein each group of subgraphs in the K groups of subgraphs includes at least two subgraphs with the same structure, K is a positive integer greater than or equal to 1 and less than or equal to N; determine K groups of first measurement results from the N groups of first measurement results, and the K groups of first measurement results are consistent with the K groups of subgraphs. Figure 1 One-to-one correspondence; determining K groups of corrected measurement results, wherein the kth group of corrected measurement results in the K groups of corrected measurement results is the product of the kth group of first measurement results in the K groups of first measurement results and the number of subgraphs included in the kth group of subgraphs in the K groups of subgraphs, k=1, ..., K. Determine the expected value of the first target Hamiltonian according to the following formula:

[0183]

[0184] in, Corr_R represents the expected value of the first target Hamiltonian. K represents the kth group of calibration measurement results among the K groups of calibration measurement results, R n Indicates the nth group of first measurement results among the N groups of first measurement results excluding the K group of measurement results.

[0185] Also Fig.15 and Fig.16 Assume that the quantum circuit determination module 310 decomposes the weight graph to obtain 9 subgraphs, among which Figure 1 To the son Figure 4 Yes Figure 5 The subgraph structure shown in (a) in Figure 5 To sub-figure 9 is Figure 5 Then, by measuring the quantum circuits corresponding to these two subgraphs, two sets of first measurement results can be obtained. One set of first measurement results is Fig.15 The measurement results obtained by measuring the quantum circuit shown include the expected value of the quantum bit corresponding to i (which can be expressed by R i ) and the expected value of the quantum bit corresponding to j (which can be represented by R j Another set of first measurement results is as follows Fig.16 The measurement results obtained by measuring the quantum circuit shown include the expected value of the quantum bit corresponding to k (which can be expressed by R k ). In this case, the expected value of the first target Hamiltonian can be determined according to the following formula:

[0186]

[0187] in, Represents the expected value of the first target Hamiltonian.

[0188] After determining the expected value of the first target Hamiltonian, the parameter optimization module 322 can use a classical optimizer (e.g., an optimizer based on a linear approximation constrained optimization algorithm (COBYLA), an optimizer based on a Broyden–Fletcher–Goldfarb–Shanno algorithm (BFGS), etc.) to determine the optimization parameters, and determine the expected value of the second target Hamiltonian based on the optimization parameters and the expected value of the first target Hamiltonian. Then the optimization parameter is Correspondingly, the expected value of the second target Hamiltonian is

[0189] If the expected value of the second target Hamiltonian satisfies the preset condition, then it can be determined that the optimization parameter is the target parameter for solving the target problem.

[0190] If the expected value of the second target Hamiltonian does not meet the preset condition, the corresponding parameters in the quantum circuit are updated to the optimized parameters, the quantum circuit is continued to be measured to obtain a second measurement result, and then new optimized parameters are determined according to the second measurement result, and the above steps are repeated until the determined expected value of the second target Hamiltonian meets the preset condition.

[0191] In some embodiments, whether the second target Hamiltonian meets the preset condition can be determined based on whether the second target Hamiltonian converges. If the second target Hamiltonian expected value converges, the second target Hamiltonian expected value meets the preset condition, otherwise, it is determined that the second Hamiltonian expected value does not meet the preset condition.

[0192] After determining the target parameters, the solution module 330 can correspond to the quantum circuit of the target problem in real time (the collar circuit is the quantum circuit before decomposition, that is, the quantum circuit corresponding to the weight graph), map the target parameters to the quantum circuit, and select the bit string that minimizes the target Hamiltonian as the output solution of the target problem.

[0193] The above technical solution can decompose the target problem into Fig.17 The multiple parallel quantum circuits shown. These quantum circuits are small in scale and circuit depth, so it is convenient to use quantum processors or simulators for parallel computing. Thus, the convergence target parameters can be quickly determined. In addition, the embodiments of the present application can be used to solve larger-scale problems.

[0194] Fig.18 This is a schematic diagram comparing the results of the existing technical solutions in the industry and the technical solutions of this application in the 18-bit image coloring test. Fig.18 The solution shown in the embodiment of the present application can make the expected value converge quickly, so that the output solution of the final combinatorial problem can be determined more quickly.

[0195] Fig.19 The test results of the technical solution of the present application with more quantum bits are shown. Fig.19 As shown, even if the quantum bit increases from 40 bits to 200 bits, the number of iterations when reaching convergence using the technical solution of the present application does not increase significantly. Therefore, the embodiments of the present application can also solve larger-scale problems.

[0196] Fig. 20 It is a schematic flow chart of a quantum computing method provided according to an embodiment of the present application.

[0197] 2001. Determine N quantum circuits corresponding to the target problem, wherein the N quantum circuits include quantum circuits of two different configurations, and N is a positive integer greater than or equal to 1.

[0198] In 2002, the N quantum circuits are implemented to obtain target parameters for solving the target problem.

[0199] 2003, quantum computing was performed on the target problem according to the target parameters.

[0200] In some embodiments, the N quantum circuits may be determined by: determining an Ising model corresponding to the target problem; determining an Ising model corresponding to the target problem; determining N subgraphs according to the weight graph; determining N quantum circuits according to the N subgraphs, the N quantum circuits and the N subgraphs Figure 1 One to one correspondence.

[0201] In some embodiments, the N subgraphs are obtained by decomposing the weight graph. In other words, if the weight graph is decomposed, N subgraphs can be obtained, wherein the N subgraphs may include two or more subgraphs with the same structure.

[0202] In other embodiments, after decomposing the weight graph, M subgraphs may be obtained, wherein the M subgraphs include N different subgraph structures; and the N subgraphs are determined from the M subgraphs, wherein the N subgraph structures are distributed into the N different subgraph structures.

[0203] In some embodiments, a matching operation may be performed on the M sub-graphs according to a sub-graph library to obtain the N sub-graphs.

[0204] In some other embodiments, each subgraph in the M subgraphs may be compared with other subgraphs, and if subgraphs with the same structure are found, the extra subgraphs are deleted.

[0205] In some embodiments, the line depth when decomposing the weight map may be a positive integer greater than or equal to 1 and less than or equal to 20.

[0206] In some embodiments, the target parameter can be determined by: using the N quantum circuits to prepare N groups of first quantum states; measuring the N groups of first quantum states to obtain N groups of first measurement results, wherein the N groups of first measurement results correspond one-to-one to the N quantum circuits; and determining the target parameter based on the N groups of first measurement results.

[0207] In some embodiments, the implementation of the N quantum circuits to obtain the target parameters for solving the target problem can be implemented in parallel. In other words, the N quantum circuits can be implemented in parallel and the N groups of first quantum states can be prepared using the N quantum circuits; the N groups of first quantum states can be measured in parallel to obtain the N groups of first measurement results.

[0208] In some embodiments, the target parameter can be determined in the following manner: determine the first target Hamiltonian expected value according to the N groups of first measurement results; determine the optimization parameter; determine the second target Hamiltonian expected value according to the optimization parameter and the first target Hamiltonian expected value; determine whether the second target Hamiltonian expected value meets the preset conditions; if the second target Hamiltonian expected value meets the preset conditions, the optimization parameter is the target parameter; if the second target Hamiltonian expected value does not meet the preset conditions, update the N quantum circuits according to the optimization parameter and use the updated quantum circuits to prepare N groups of second quantum states and measure the N groups of second quantum states to obtain N groups of second measurement results, and the N groups of second quantum states correspond one to one with the updated N quantum circuits; determine the target parameter according to the N groups of second measurement results. The specific process of determining the target parameter according to the N groups of second quantum states is similar to the specific process of determining the target parameter according to the N groups of first quantum states. For the sake of brevity, it will not be repeated here.

[0209] If the quantum circuit determination module 310 deletes redundant subgraphs in each structure after decomposing the weight graph, the first target Hamiltonian expected value can be determined according to formula 2.2.

[0210] The chip in the embodiments of the present application may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or other integrated chips.

[0211] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0212] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to be executed, or a combination of hardware and software modules in the decoding processor to be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0213] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0214] According to the method provided in the embodiment of the present application, the present application also provides a computer program product, which includes: a computer program code, when the computer program code is run on a computer, the computer executes Figure 6 , Figure 8 or Fig. 20 A method according to any one of the embodiments shown.

[0215] According to the method provided in the embodiment of the present application, the present application also provides a computer-readable medium, which stores a program code, and when the program code is run on a computer, the computer executes Figure 6 , Figure 8 or Fig. 20 A method according to any one of the embodiments shown.

[0216] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0217] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0218] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0219] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0220] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0221] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0222] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A quantum computing method, characterized in that: include: Determine the Ising model corresponding to the target problem; determining a weight graph corresponding to the Ising model; According to the weight graph, determining N subgraphs; Determine N quantum circuits according to the N subgraphs, wherein the N quantum circuits correspond to the N subgraphs one by one, wherein the N quantum circuits include at least two quantum circuits of different configurations, and N is a positive integer greater than or equal to 2; Implementing the N quantum circuits to obtain target parameters for solving the target problem; Performing quantum calculation on the target problem according to the target parameters.

2. The method according to claim 1, characterized in that The implementing the N quantum circuits to obtain target parameters for solving the target problem comprises: Using the N quantum circuits to prepare N groups of first quantum states; Measuring the N groups of first quantum states to obtain N groups of first measurement results, wherein the N groups of first quantum states correspond one-to-one to the N quantum circuits; The target parameter is determined according to the N groups of first measurement results.

3. The method according to claim 2, characterized in that The implementing the N quantum circuits to obtain target parameters for solving the target problem comprises: The N quantum circuits are implemented in parallel to obtain target parameters for solving the target problem.

4. The method according to claim 1, characterized in that: The step of determining N subgraphs according to the weight graph comprises: Decomposing the weight graph to obtain M subgraphs, wherein the M subgraphs include N different subgraph structures, where M is a positive integer greater than N; A matching operation is performed on the M subgraphs according to the subgraph library to obtain the N subgraphs, wherein the structures of the N subgraphs are respectively the N different subgraph structures.

5. The method according to claim 4, characterized in that The decomposing the weight map comprises: The weight graph is decomposed with a line depth of P, where P is a positive integer greater than or equal to 1 and less than or equal to 20.

6. The method according to any one of claims 1 to 5, characterized in that Before implementing the N quantum circuits, the method further includes: Determine implementation methods of the N quantum circuits according to the configuration information, wherein the configuration information includes one or more of the following information: the scale of the target problem, the density of the target problem, or the circuit depth when the weight graph is decomposed, and the implementation methods of the N quantum circuits include using a quantum processor to implement the N quantum circuits or using a simulator to implement the N quantum circuits.

7. The method according to claim 2, characterized in that The determining the target parameter according to the N groups of first measurement results includes: Determining a first target Hamiltonian expected value according to the N groups of first measurement results; Determine optimization parameters; Determining a second target Hamiltonian expected value according to the optimization parameter and the first target Hamiltonian expected value; Determining whether the expected value of the second target Hamiltonian satisfies a preset condition; If the expected value of the second target Hamiltonian satisfies the preset condition, the optimization parameter is determined to be the target parameter.

8. The method according to claim 7, characterized in that If the expected value of the second target Hamiltonian does not satisfy the preset condition, updating the N quantum circuits according to the optimization parameters; Using the updated N quantum circuits to prepare N groups of second quantum states and measuring the N groups of second quantum states to obtain N groups of second measurement results, the N groups of second quantum states corresponding one-to-one to the updated N quantum circuits; The target parameter is determined according to the N groups of second measurement results.

9. The method according to claim 7 or 8, characterized in that Determining the first target Hamiltonian expected value according to the N groups of first measurement results includes: In the case where the weight graph is decomposed to obtain K groups of subgraphs, determining the number of subgraphs included in each group of subgraphs in the K groups of subgraphs, wherein each group of subgraphs in the K groups of subgraphs includes at least two subgraphs with the same structure, and K is a positive integer greater than or equal to 1 and less than or equal to N; Determine K groups of first measurement results from the N groups of first measurement results, wherein the K groups of first measurement results correspond one-to-one to the K groups of subgraphs; Determine K groups of corrected measurement results, wherein a kth group of corrected measurement results in the K groups of corrected measurement results is a product of a kth group of first measurement results in the K groups of first measurement results and the number of subgraphs included in a kth group of subgraphs in the K groups of subgraphs, k=1, ..., K; The expected value of the first target Hamiltonian is determined according to the following formula: in, represents the expected value of the first target Hamiltonian, Corr_R k represents the kth group of calibration measurement results among the K groups of calibration measurement results, R n Indicates the nth group of first measurement results among the N groups of first measurement results excluding the K groups of first measurement results.

10. A quantum computing system, characterized in that: include: A quantum circuit determination module, used to determine an Ising model corresponding to a target problem, determine a weight graph corresponding to the Ising model, determine N subgraphs according to the weight graph, and determine N quantum circuits according to the N subgraphs, wherein the N quantum circuits correspond to the N subgraphs one-to-one, wherein the N quantum circuits include at least two quantum circuits of different configurations, and N is a positive integer greater than or equal to 2; A parameter determination module, used for implementing the N quantum circuits to obtain target parameters for solving the target problem; A solution module is used to perform quantum calculation on the target problem according to the target parameters.

11. The system according to claim 10, characterized in that The parameter determination module includes a quantum circuit realization module and a parameter optimization module. The quantum circuit implementation module is used to prepare N groups of first quantum states using the N quantum circuits; The quantum circuit implementation module is further used to measure the N groups of first quantum states to obtain N groups of first measurement results, wherein the N groups of first quantum states correspond one-to-one to the N quantum circuits; The parameter optimization module is used to determine the target parameter according to the N groups of first measurement results.

12. The system according to claim 11, characterized in that The quantum circuit implementation module is specifically used to implement the N quantum circuits in parallel.

13. The system according to claim 11, characterized in that The quantum circuit determination module is specifically used for: Decomposing the weight graph to obtain M subgraphs, wherein the M subgraphs include N different subgraph structures, where M is a positive integer greater than N; A matching operation is performed on the M subgraphs according to the subgraph library to obtain the N subgraphs, wherein the structures of the N subgraphs are respectively the N different subgraph structures.

14. The system of claim 13, wherein: The quantum circuit determination module is specifically used to decompose the weight graph with a circuit depth of P, where P is a positive integer greater than or equal to 1 and less than or equal to 20.

15. The system according to any one of claims 10 to 14, characterized in that The quantum circuit determination module is further used to determine, before the implementation of the N quantum circuits, according to configuration information, an implementation method of the N quantum circuits, wherein the configuration information includes one or more of the following information: the scale of the target problem, the density of the target problem, or the circuit depth when the weight graph is decomposed, and the implementation method of the N quantum circuits includes implementing the N quantum circuits using a quantum processor or implementing the N quantum circuits using a simulator.

16. The system of claim 11, wherein: The parameter optimization module is specifically used for: Determining a first target Hamiltonian expected value according to the N groups of first measurement results; Determine optimization parameters; Determining a second target Hamiltonian expected value according to the optimization parameter and the first target Hamiltonian expected value; Determining whether the expected value of the second target Hamiltonian satisfies a preset condition; If the expected value of the second target Hamiltonian satisfies the preset condition, the optimization parameter is determined to be the target parameter.

17. The system of claim 16, wherein: The parameter optimization module is further configured to update the N quantum circuits according to the optimization parameters if the expected value of the second target Hamiltonian does not satisfy the preset condition; The quantum circuit implementation module is further used to prepare N groups of second quantum states using the updated N quantum circuits and measure the N groups of second quantum states to obtain N groups of second measurement results, wherein the N groups of second quantum states correspond one-to-one to the updated N quantum circuits; The parameter optimization module is further used to determine the target parameter according to the N groups of second measurement results.

18. The system according to claim 16 or 17, characterized in that The parameter optimization module is specifically used to determine the number of subgraphs included in each group of subgraphs in the K groups of subgraphs when the weight graph is decomposed to obtain K groups of subgraphs, wherein each group of subgraphs in the K groups of subgraphs includes at least two subgraphs with the same structure, and K is a positive integer greater than or equal to 1 and less than or equal to N; Determine K groups of first measurement results from the N groups of first measurement results, wherein the K groups of first measurement results correspond one-to-one to the K groups of subgraphs; Determine K groups of corrected measurement results, wherein a kth group of corrected measurement results in the K groups of corrected measurement results is a product of a kth group of first measurement results in the K groups of first measurement results and the number of subgraphs included in a kth group of subgraphs in the K groups of subgraphs, k=1, ..., K; The expected value of the first target Hamiltonian is determined according to the following formula: in, represents the expected value of the first target Hamiltonian, Corr_R k represents the kth group of calibration measurement results among the K groups of calibration measurement results, R n Indicates the nth group of first measurement results among the N groups of first measurement results excluding the K groups of first measurement results.

19. A chip, characterized in that: include: A logic circuit, wherein the logic circuit is used to be coupled to an input / output interface and transmit data through the input / output interface to execute the method according to any one of claims 1 to 9.

20. A computer readable medium, characterized in that The computer-readable medium stores a program code, and when the program code is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 9.

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