Display device

Abstract

A display device includes: pixels in a display area; gate lines in the display area and connected to the pixels; carry clock lines and scan clock lines in the display area; and gate driving circuitry distributed in the display area and connected to the carry clock lines, scan clock lines, and gate lines. The gate driving circuitry includes multiple stages, each stage being configured to output a carry clock signal supplied via a corresponding carry clock line as a carry signal, and to output a scan clock signal supplied via a corresponding scan clock line as a scan signal. Corresponding carry clock lines and corresponding scan clock lines corresponding to one of the stages are spaced apart from each other, and at least one pixel is inserted between the corresponding carry clock line and the corresponding scan clock line.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0175869, filed on December 15, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] An aspect of the embodiments of this disclosure relates to a display device. Background Technology

[0004] With increasing interest in information display and growing demand for portable information media, the need for display devices has increased significantly, and their commercialization is underway. Summary of the Invention

[0005] One or more embodiments of this disclosure relate to a display device, and more specifically, to a display device in which a non-display area is reduced or minimized.

[0006] According to one or more embodiments of this disclosure, a display device includes: a substrate including a display area; pixels in the display area; gate lines in the display area and connected to the pixels; carry clock lines and scan clock lines in the display area; and gate driving circuitry distributed in the display area and connected to the carry clock lines, scan clock lines, and gate lines. The gate driving circuitry includes multiple stages, each stage configured to, in response to a previous carry signal supplied from a previous stage, output a carry clock signal supplied via a corresponding carry clock line among the carry clock lines as a carry signal, and output a scan clock signal supplied via a corresponding scan clock line among the scan clock lines as a scan signal to a corresponding gate line among the gate lines. Corresponding carry clock lines and corresponding scan clock lines corresponding to one of the multiple stages are spaced apart from each other, and at least one pixel is inserted between the corresponding carry clock line and the corresponding scan clock line.

[0007] In an embodiment, the corresponding scan clock line may be located on the first side of a stage, and the corresponding carry clock line may be located on the second side of a stage opposite to the first side.

[0008] In an embodiment, a stage may include a plurality of transistors, and the plurality of transistors may be distributed in cell regions corresponding to at least two gate lines in the gate lines.

[0009] In this embodiment, the carry clock line may be adjacent to the previous carry clock line among the carry clock lines between stages, and the previous carry clock signal, having a 180-degree phase difference with the carry clock signal, may be applied to the previous carry clock line. Similarly, the scan clock line may be adjacent to the previous scan clock line among the scan clock lines between stages, and the previous scan clock signal, having a 180-degree phase difference with the scan clock signal, may be applied to the previous scan clock line.

[0010] In an embodiment, a stage may include: a node control circuit configured to control a first node voltage in response to a previous carry signal; a first output circuit configured to output a carry clock signal as a carry signal in response to the first node voltage; and a second output circuit configured to output a scan clock signal as a scan signal in response to the first node voltage. The first output circuit may be adjacent to a second side of a stage, the second output circuit may be adjacent to a first side of a stage, and the node control circuit may be located between the first output circuit and the second output circuit.

[0011] In an embodiment, the display device may further include: a first power line located in the display area and connected to the second output circuit; and a second power line located in the display area and connected to the first output circuit, wherein the first power line and the second power line may be located between the carry clock line and the scan clock line with respect to one stage.

[0012] In an embodiment, the gate drive circuit may further include a dummy stage; each of the plurality of stages may be configured to be initialized in response to a subsequent carry signal supplied from the next stage, and the next stage may be configured to shift the carry signal to output the subsequent carry signal; the last of the plurality of stages may be configured to receive the subsequent carry signal from the dummy stage; and, compared to the last stage, the dummy stage may be spaced further away from the edge of the display area.

[0013] In an embodiment, a dummy level may be located between the last two levels among a plurality of levels.

[0014] In an embodiment, the gate lines may extend in a first direction; the carry clock line and the scan clock line may extend in a second direction; and, in the display area, the gate lines may intersect with the carry clock line and the scan clock line.

[0015] In one embodiment, multiple stages may be divided into sub-blocks along a first direction with respect to the carry clock line; and a portion of the multiple stages may be positioned along the first direction.

[0016] In an embodiment, two carry clock lines in which two carry clock signals with a phase difference of 180 degrees are applied can be arranged in pairs, and a stage among multiple stages connected to the pair of carry clock lines can be included in a sub-block.

[0017] In one embodiment, at least a portion of the carry clock line may be connected to a first connection line extending between stages in a first direction.

[0018] In an embodiment, the display device may further include power lines located at the display area and connected to a plurality of stages, and the power lines may be positioned between a carry clock line and a scan clock line with respect to each of the plurality of stages. The power lines may be connected to second connection lines extending between stages in a first direction, and each of the second connection lines may be closer to a pixel than the first connection lines.

[0019] In an embodiment, the gate drive circuit may include three or more blocks; and each of the blocks may include at least two of a plurality of stages.

[0020] According to one or more embodiments of this disclosure, a display device includes: a substrate including a display area; pixels in the display area; gate lines in the display area and connected to the pixels; carry clock lines and scan clock lines in the display area; and gate driving circuitry distributed in the display area and connected to the carry clock lines, scan clock lines, and gate lines. The gate driving circuitry includes multiple stages, each of which is configured to, in response to a previous carry signal supplied from a previous stage, output a carry clock signal supplied via a corresponding carry clock line among the carry clock lines as a carry signal, and output a scan clock signal supplied via a corresponding scan clock line among the scan clock lines as a scan signal to a corresponding gate line among the gate lines. The gate driving circuitry further includes a dummy stage. Each of the multiple stages is configured to be initialized in response to a subsequent carry signal supplied from a subsequent stage, and the subsequent stage is configured to shift the carry signal to output the subsequent carry signal. The last of the multiple stages is configured to receive the subsequent carry signal from the dummy stage, and the dummy stage is spaced further away from the edge of the display area compared to the last stage.

[0021] In an embodiment, a dummy level may be located between the last two levels among a plurality of levels.

[0022] In an embodiment, the gate lines may extend in a first direction, and the carry clock line and scan clock line may extend in a second direction; at the display area, the gate lines may intersect with the carry clock line and scan clock line; and a portion of the multiple stages may be positioned along the first direction.

[0023] In an embodiment, two carry clock lines in a carry clock line that are applied with two carry clock signals having a phase difference of 180 degrees can form a pair, and the pair of carry clock lines can be located between two adjacent stages in a plurality of stages.

[0024] In one embodiment, at least a portion of the carry clock line may be connected to a first connection line extending between stages in a first direction.

[0025] In an embodiment, the display device may further include power lines located at the display area and connected to multiple stages. The power lines may be situated between a carry clock line and a scan clock line with respect to each of the multiple stages, and the power lines may be connected to second connection lines extending between the stages in a first direction. Each of the second connection lines may be closer to a pixel than the first connection lines. Attached Figure Description

[0026] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting exemplary embodiments with reference to the accompanying drawings.

[0027] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 yes Figure 1 A magnified plan view of region Q2.

[0029] Figure 3 It is shown Figure 1 A circuit diagram of an example of pixels included in a display device.

[0030] Figure 4 It is shown Figure 3 The waveform diagram of pixel operations.

[0031] Figure 5 It is shown Figure 3 A cross-sectional view of an example pixel.

[0032] Figure 6 This shows the drive. Figure 3 A block diagram of the gate driving circuit for the pixel.

[0033] Figure 7 It is shown Figure 6 A waveform diagram of an example of the clock signal used in a gate drive circuit.

[0034] Figure 8A It is shown Figure 6 A diagram showing an example of the stages included in a gate drive circuit.

[0035] Figure 8B It is shown Figure 6A diagram showing an example of the stages included in a gate drive circuit.

[0036] Figure 8C It is shown Figure 8A and / or Figure 8B A diagram showing an example of the node control circuitry included in the stage.

[0037] Figure 8D It is shown Figure 6 A diagram showing an example of a dummy level included in a gate drive circuit.

[0038] Figure 8E It is shown Figure 6 Waveform diagram of the operation of the gate drive circuit.

[0039] Figure 9 It is shown Figure 1 A diagram showing an example of a display panel included in a display device.

[0040] Figure 10A It is shown Figure 9 The first block included in the display panel is an example diagram.

[0041] Figure 10B It is shown Figure 9 The first block included in the display panel is an example diagram.

[0042] Figure 11 It is shown Figure 9 A diagram showing an example of control lines included in the display panel.

[0043] Figure 12 It is shown Figure 9 The display panel includes an example diagram of the levels.

[0044] Figure 13 It is shown Figure 9 The display panel includes an example diagram of the levels.

[0045] Figure 14 It is shown Figure 1 A diagram showing an example of a display panel included in a display device. Detailed Implementation

[0046] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Accordingly, processes, elements, and techniques unnecessary for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description may not be repeated.

[0047] When a particular embodiment can be implemented differently, the particular process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or in the reverse order of the described sequence.

[0048] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature as shown in the drawings to another element(s). It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “below,” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0049] In the accompanying drawings, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a Cartesian coordinate system, and can be interpreted more generally. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0050] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0051] It will be understood that when an element or layer is referred to as being “on,” “coupled to,” or “connected to” another element or layer, it may be directly on, coupled to, or connected to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being “electrically connected” to another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, and / or may be indirectly connected to the other layer, region, or element, with one or more intervening layers, regions, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0052] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” and “having” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. Expressions such as “at least one of”, when placed after a list of elements, modify the entire list of elements without modifying any individual elements in the list. For example, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0053] As used herein, the terms “substantially,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree and are intended to describe the inherent biases of measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.” As used herein, the terms “use” and “be used” may be considered synonymous with the terms “utilize” and “be exploited,” respectively. Moreover, the term “exemplary” indicates an example or illustration.

[0054] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, the various components of these devices may be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Further, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard storage devices such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as, for example, CD-ROMs, flash drives, etc. Additionally, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present disclosure.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense.

[0056] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A magnified plan view of region Q2.

[0057] refer to Figure 1 and Figure 2 The display device 1000 (e.g., a video wall display device) can display images based on image data. The display device 1000 can display images on a third-party DR3.

[0058] The display device 1000 may include a plurality of display panels 100 (e.g., sub-display devices).

[0059] The display device 1000 can be formed by connecting two or more display panels 100 to each other. Although Figure 1 The diagram shows multiple display panels 100 connected in a 2×2 arrangement, but the arrangement and number of display panels 100 included in the display device 1000 are not limited thereto.

[0060] In embodiments of this disclosure, the display panels 100 included in the display device 1000 may be mounted in a rack and in close contact with each other, or may be connected to each other through separate coupling units.

[0061] In some embodiments, a buffer may be disposed between the display panels 100 to prevent or substantially prevent damage to the display panels 100 due to impact. However, this disclosure is not limited thereto. For example, transparent tape or transparent resin may be disposed between the display panels 100 as coupling units for connecting the display panels 100 to each other.

[0062] By placing such coupling units and / or buffers between display panels 100, at least a distance WD can exist between display panels 100. When the distance WD between adjacent display panels 100 is greater than the distance WP between adjacent pixels PXL of display panels 100 by a reference distance or more (e.g., a predetermined reference or more), the boundary between display panels 100 may be visually identifiable, resulting in poor visibility.

[0063] In some embodiments, the display panel 100 may output images that are different from each other independently. In some embodiments, the display panel 100 may output a single image that is shared by each other, for example, by dividing the image into multiple parts and then outputting the multiple parts.

[0064] In an embodiment, the display device 1000 may include a first display panel 101, a second display panel 102, a third display panel 103, and a fourth display panel 104. The display device 1000 may include a plurality of pixels PXL disposed in each of the display panels 100.

[0065] The first display panel 101 may include a plurality of pixels PX1 disposed at the display area DA (e.g., center or top) of the substrate SUB. The second display panel 102 may include a plurality of pixels PX2 disposed at the display area DA (e.g., center or top) of the substrate SUB. The third display panel 103 may include a plurality of pixels PX3 disposed at the display area DA (e.g., center or top) of the substrate SUB. The fourth display panel 104 may include a plurality of pixels PX4 disposed at the display area DA (e.g., center or top) of the substrate SUB. Reference will be made below. Figures 3 to 5 A more detailed description of the pixel PXL.

[0066] At the display area DA (e.g., center or top) of each of the display panels 100, gate lines and data lines connected to the pixel PXL, as well as a driver (e.g., gate drive circuit) for driving the pixel PXL, can be provided.

[0067] Furthermore, each of the display panels 100 may include a non-display area other than the display area DA. The non-display area may be provided at at least one side of the display area DA (e.g., the center or top). The non-display area may be provided in a smaller area (e.g., a very small area) compared to the area of ​​the display area DA. In some embodiments, no non-display area may be provided.

[0068] In embodiments, the distance WS between pixels PXL located at the outermost portion (e.g., center or top) of different display panels 100 can be less than or equal to the distance WP between adjacent pixels PXL of a display panel 100. For example, the distance WS between a pixel PX1 located at the outermost portion (e.g., center or top) of a first display panel 101 and a pixel PX2 located at the outermost portion (e.g., center or top) of a second display panel 102 can be less than or equal to the distance WP between adjacent pixels PX1 of the first display panel 101. For example, the distance WS between a pixel PX1 located at the outermost portion (e.g., center or top) of a first display panel 101 and a pixel PX3 located at the outermost portion (e.g., center or top) of a third display panel 103 can be less than or equal to the distance WP between adjacent pixels PX1 of the first display panel 101. In embodiments, the distances between adjacent pixels PXL of the display device 1000 can be the same or substantially the same.

[0069] In this case, the user can recognize the display panel 100 of the display device 1000 as a screen, rather than a separate screen.

[0070] In order to arrange the pixels PXL of the display device 1000 such that the distance between adjacent pixels PXL is equal or substantially equal, or in other words, in order to minimize or reduce the non-display area that may exist at the outermost portion (e.g., center or top) of each of the display panels 100, the gate driving circuits configured to drive the pixels PXL can be distributed (e.g., dispersed) at the display area DA (e.g., center or top). Reference will be made below. Figure 9 A more detailed example layout of the gate drive circuit is described.

[0071] Figure 3 It is shown Figure 1 A circuit diagram of an example of pixels included in a display device. Figure 4 It is shown Figure 3 The waveform diagram of pixel operations.

[0072] refer to Figure 3 The pixel PXL may include first to third thin-film transistors M1, M2 and M3 (e.g., switching elements and transistors), a storage capacitor Cst and a light-emitting element LD. Each of the first to third thin-film transistors M1, M2 and M3 may be formed by an N-type transistor.

[0073] The first thin-film transistor M1 may include a gate electrode connected to the gate node Na, an electrode (e.g., a first electrode) connected to the first power line VDD, and another electrode (e.g., a second electrode) connected to the source node Nb. The first thin-film transistor M1 may be referred to as a driving transistor.

[0074] The second thin-film transistor M2 may include a gate electrode connected to a scan line SC (e.g., a first gate line), an electrode connected to a data line DL, and another electrode connected to a gate node Na. The second thin-film transistor M2 may be referred to as a switching transistor or a scan transistor, etc. The scan line SC may be connected to the following reference... Figure 6 A more detailed description of the gate drive circuitry. The data line DL can be connected to the following reference. Figure 9 A more detailed description of the data driver.

[0075] The third thin-film transistor M3 may include a gate electrode connected to the sensing scan line SS (e.g., the second gate line), an electrode connected to the sensing line RL, and another electrode connected to the source node Nb. The third thin-film transistor M3 may be referred to as an initialization transistor or a sensing transistor, etc. The sensing scan line SS may be connected to the following reference... Figure 6 A more detailed description of the gate drive circuitry. The sensing line RL can be connected to the following reference. Figure 9 A more detailed description of the data driver.

[0076] The storage capacitor Cst may include one electrode connected to the gate node Na and another electrode connected to the source node Nb.

[0077] The light-emitting element (LD) may include an anode connected to the source node Nb and a cathode connected to a second power line VSS (e.g., a second power supply). The LD may be a light-emitting diode that can comprise a material having an inorganic crystal structure and has an ultra-small size, for example, corresponding to dimensions ranging from nanometers to micrometers. The LD may be an ultra-small light-emitting diode manufactured by etching or by growth. However, this disclosure is not limited thereto, and the LD may be an organic light-emitting diode.

[0078] A first electrical voltage can be supplied to a first electrical line VDD, and a second electrical voltage can be supplied to a second electrical line VSS. The first and second electrical voltages are voltages used for the operation of pixel PXL. The first electrical voltage can have a higher voltage level than the second electrical voltage.

[0079] refer to Figure 4 During the first sub-period PS1, a scan signal SCAN (e.g., a first scan pulse) with an on-state voltage level can be applied to scan line SC, and a sensing scan signal SEN (e.g., a first sensing scan pulse) with an on-state voltage level can be applied to sensing scan line SS. Furthermore, a data signal VDATA corresponding to a grayscale value (e.g., a predetermined or specific grayscale value) can be applied to data line DL. For example, the data signal VDATA may have a first valid data voltage V_D1.

[0080] In this configuration, in response to the scan signal SCAN, the second thin-film transistor M2 can be turned on, and the data signal VDATA can be supplied to the first electrode of the storage capacitor Cst. Furthermore, in response to the sensing scan signal SEN, the third thin-film transistor M3 can be turned on, and the first reference voltage applied to the sensing line RL can be supplied to the second electrode of the storage capacitor Cst. Therefore, the voltage corresponding to the difference between the data signal VDATA and the first reference voltage can be stored in the storage capacitor Cst. Subsequently, when the second thin-film transistor M2 and the third thin-film transistor M3 are turned off, the amount of drive current flowing through the first thin-film transistor M1 can be determined in response to the voltage stored in the storage capacitor Cst (e.g., the first effective data voltage V_D1), and during the period other than the first sub-period PS1, the light-emitting element LD can emit light with a brightness corresponding to the amount of drive current.

[0081] Figure 4The scan signal SCAN and the sensing scan signal SEN shown can have the same waveform. Therefore, in an embodiment, the scan signal SCAN can be applied to the sensing scan line SS as the sensing scan signal SEN. In other words, in some embodiments, the sensing scan signal SEN can be omitted, and the scan signal SCAN can be applied to both the scan line SC and the sensing scan line SS.

[0082] Figure 5 It is shown Figure 3 A cross-sectional view of an example pixel.

[0083] refer to Figure 5 The pixel PXL may include a substrate layer BSL, a pixel circuit component PCL, and a display element component DPL. For ease of explanation, Figure 5 Show Figure 3 The first thin-film transistor M1 is shown among the first to third thin-film transistors M1, M2 and M3.

[0084] The substrate layer (BSL) can be a rigid substrate or a soft (e.g., flexible) substrate. As an example, the substrate layer (BSL) may comprise a rigid material or a flexible material. The substrate layer (BSL) can be referenced above. Figure 1 The substrate SUB described corresponds to this.

[0085] The pixel circuit component PCL may include a buffer layer BFL, a first thin film transistor M1, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a bridging pattern BRP, a power line PLE, a first contactor CNT1, a second contactor CNT2, and a passivation layer PSV.

[0086] A buffer layer (BFL) can be located on the substrate layer (BSL). The buffer layer (BFL) can prevent or substantially prevent impurities from diffusing from the outside. The buffer layer (BFL) can include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and / or alumina (AlO) x (at least one of various suitable materials).

[0087] The first thin-film transistor M1 may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0088] The semiconductor layer SCL may be located on the buffer layer BFL. The semiconductor layer SCL may include an oxide semiconductor. However, this disclosure is not limited thereto, and the semiconductor layer SCL may include polycrystalline silicon or amorphous silicon.

[0089] The semiconductor layer SCL may include a first contact region that contacts the source electrode SE and a second contact region that contacts the drain electrode DE.

[0090] Each of the first contact region and the second contact region can be a semiconductor pattern doped with impurities. The region between the first contact region and the second contact region can be a channel region. The channel region can be an intrinsic semiconductor pattern without doping (e.g., undoped).

[0091] The gate insulating layer GI can be provided on the semiconductor layer SCL. The gate insulating layer GI can include inorganic materials. For example, the gate insulating layer GI can include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following. In an embodiment, the gate insulating layer GI may include an organic material.

[0092] The gate electrode GE can be located on the gate insulating layer GI. The position of the gate electrode GE can correspond to the position of the channel region of the semiconductor layer SCL. For example, the gate electrode GE can be disposed on the channel region of the semiconductor layer SCL, with the gate insulating layer GI inserted between the gate electrode GE and the channel region.

[0093] The first interlayer insulating layer ILD1 can be located on the gate electrode GE. Similar to the gate insulating layer GI, the first interlayer insulating layer ILD1 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following.

[0094] The source electrode SE and the drain electrode DE can be located on the first interlayer insulating layer ILD1. The source electrode SE can pass through (e.g., penetrate) the gate insulating layer GI and the first interlayer insulating layer ILD1 to contact the first contact area of ​​the semiconductor layer SCL, and the drain electrode DE can pass through (e.g., penetrate) the gate insulating layer GI and the first interlayer insulating layer ILD1 to contact the second contact area of ​​the semiconductor layer SCL.

[0095] The second interlayer insulating layer ILD2 can be located on the source electrode SE and the drain electrode DE. Similar to the first interlayer insulating layer ILD1 and the gate insulating layer GI, the second interlayer insulating layer ILD2 can include an inorganic material. The inorganic material can include one or more of the materials forming the first interlayer insulating layer ILD1 and the gate insulating layer GI, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following. In an embodiment, the second interlayer insulating layer ILD2 may include an organic material.

[0096] A bridging pattern BRP can be provided on the second interlayer insulation layer ILD2. The bridging pattern BRP can be electrically connected to the drain electrode DE through a contact hole that passes through (e.g., penetrates) the second interlayer insulation layer ILD2.

[0097] The power line PLE can be placed on the second interlayer insulation layer (ILD2). The power line PLE can be referenced above. Figure 3 The second power line VSS is described, and the second power can be supplied to the power line PLE.

[0098] The passivation layer PSV can be located on the second interlayer insulation layer ILD2. The passivation layer PSV can cover the bridging pattern BRP and the power line PLE.

[0099] The passivation layer PSV can be provided as an organic insulating layer, an inorganic insulating layer, or an inorganic insulating layer and an organic insulating layer disposed on an inorganic insulating layer.

[0100] The first contactor CNT1, which is electrically connected to the area of ​​the bridging pattern BRP, and the second contactor CNT2, which is electrically connected to the area of ​​the power line PLE, can be provided at the passivation layer PSV (e.g., in the middle or on top).

[0101] The display element component DPL may include a bank pattern BNP, a first electrode EL1, a second electrode EL2, a first insulating layer INS1, a light-emitting element LD, a first contact electrode CNE1, a second contact electrode CNE2, a second insulating layer INS2, a bank BNK, and a third insulating layer INS3.

[0102] The embankment pattern BNP can protrude upwards, and the first electrode EL1 and the second electrode EL2 can be arranged on the embankment pattern BNP to form a reflective partition wall. The reflective partition wall can be formed to improve the light efficiency of the light-emitting element LD.

[0103] The first electrode EL1 can be disposed on the passivation layer PSV to cover the embankment pattern BNP. The first electrode EL1 can be applied with the above reference. Figure 3 The path of the voltage of the first power line VDD is described, and it can also be the path that can provide electrical information to the light-emitting element LD.

[0104] The second electrode EL2 can be disposed on the passivation layer PSV to cover the embankment pattern BNP. The second electrode EL2 can be applied to the above reference. Figure 3The voltage path of the second power line VSS is described.

[0105] The first electrode EL1 and the second electrode EL2 can reflect the light emitted from the light-emitting element LD in the display direction, thereby improving the luminous efficiency of the light-emitting element LD. In this case, the display direction can be the third direction DR3.

[0106] The first insulating layer INS1 may be located on the passivation layer PSV to cover the first electrode EL1 and the second electrode EL2. Similar to the second interlayer insulating layer ILD2, the first insulating layer INS1 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following.

[0107] At least a portion of the first insulating layer INS1 may be disposed on the first contactor CNT1, the second contactor CNT2, the first electrode EL1 and / or the second electrode EL2 to stabilize the electrical connection and reduce external influences.

[0108] The light-emitting element LD can be located on the first insulating layer INS1. For example, the first insulating layer INS1 can have a groove (e.g., a predetermined groove), at least a portion of the light-emitting element LD can contact one end formed by the groove, and another portion of the light-emitting element LD can contact the other end formed by the groove.

[0109] The light-emitting element (LD) can be located on the first insulating layer INS1 between the first electrode EL1 and the second electrode EL2. The light-emitting element (LD) can have a small size corresponding to a range from nanometer to micrometer.

[0110] A light-emitting element (LD) may include a first semiconductor layer, a second semiconductor layer, an active layer, and an insulating layer. The first semiconductor layer may include a semiconductor layer of a suitable type (e.g., a predetermined type), and the second semiconductor layer may include a semiconductor layer of a different type than the first semiconductor layer. For example, the first semiconductor layer may include an N-type semiconductor layer, and the second semiconductor layer may include a P-type semiconductor layer.

[0111] Each of the first semiconductor layer and the second semiconductor layer may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.

[0112] The active layer can be located between the first semiconductor layer and the second semiconductor layer. The active layer can have a single quantum well structure or a multiple quantum well structure.

[0113] When an electric field of appropriate voltage (e.g., a predetermined voltage) or higher is applied to the two ends of the light-emitting element LD, electron-hole pairs can recombine in the active layer to emit light.

[0114] The second insulating layer INS2 may be located on the light-emitting element LD. The second insulating layer INS2 may be formed to cover the region corresponding to the active layer of the light-emitting element LD. The second insulating layer INS2 may include at least one of organic and inorganic materials.

[0115] According to an embodiment, at least a portion of the second insulating layer INS2 may be located on the rear surface of the light-emitting element LD. While the second insulating layer INS2 is formed on the light-emitting element LD, the portion of the second insulating layer INS2 formed on the rear surface of the light-emitting element LD may fill the empty gap between the first insulating layer INS1 and the light-emitting element LD.

[0116] The first contact electrode CNE1 and the second contact electrode CNE2 may be located on the first insulating layer INS1. The first contact electrode CNE1 and the second contact electrode CNE2 may be electrically connected to the first electrode EL1 and the second electrode EL2 through contact holes formed in the first insulating layer INS1.

[0117] The first contact electrode CNE1 and the second contact electrode CNE2 may comprise at least one of a variety of suitable conductive materials comprising indium tin oxide (ITO), indium zinc oxide (IZO), and / or indium tin zinc oxide (ITZO).

[0118] The electrical signal provided by the first electrode EL1 can be transmitted to the light-emitting element LD through the first contact electrode CNE1. Therefore, the light-emitting element LD can emit light in response to the transmitted electrical signal.

[0119] The electrical signal provided by the second electrode EL2 can be transmitted to the light-emitting element LD through the second contact electrode CNE2.

[0120] A embankment BNK can be a structure that defines the emission region of a pixel PXL. The emission region can refer to the area in which light is emitted from the light-emitting element LD. For example, the embankment BNK can be located at the boundary region between adjacent pixels PXL (e.g., in the middle or above) to surround the light-emitting element LD of the pixel PXL.

[0121] The third insulating layer INS3 can be disposed on the embankment BNK, the first contact electrode CNE1, the second contact electrode CNE2, and the second insulating layer INS2. The third insulating layer INS3 can include any of the organic and inorganic materials. The third insulating layer INS3 can protect the display element component DPL from external influences.

[0122] In this embodiment, the color conversion layer and / or color filter may be disposed on the third insulating layer INS3.

[0123] The color conversion layer may include color conversion particles corresponding to a desired color (e.g., a predetermined or specific color). The color conversion layer may include color conversion particles that convert light emitted from a first color by a light-emitting element (LD) disposed in a pixel PXL into light of a second color (or a specific color). For example, when the light-emitting element (LD) in pixel PXL emits blue light, the color conversion layer may include quantum dot color conversion particles that convert the light emitted by the light-emitting element (LD) into red or green light.

[0124] Color filters can selectively transmit light emitted from a color conversion layer (e.g., light converted to a specific color). Color filters can include red, green, and blue color filters.

[0125] Figure 6 This shows the drive. Figure 3 A block diagram of the gate driving circuit for a pixel. Figure 7 It is shown Figure 6 A waveform diagram of an example of the clock signal used in a gate drive circuit.

[0126] refer to Figure 6 The gate drive circuit 120 may include multiple stages ST1 to STn, where n is a positive integer.

[0127] Levels ST1 to STn can be connected to scan lines SC1 to SCn (and / or sensing scan lines SS1 to SSn) and carry lines CR1 to CRn, respectively. One of the scan lines SC1 to SCn and one of the sensing scan lines SS1 to SSn can be connected to the referenced above. Figure 3 The described scan line SC corresponds to the sensing scan line SS.

[0128] In addition, ST1 to STn can be connected to the corresponding clock line and control line CSS among multiple clock lines CLKS1 to CLKS8.

[0129] Clock lines CLKS1 to CLKS8 may include first clock lines CLKS1 to eighth clock lines CLKS8. Each of the first clock lines CLKS1 to eighth clock lines CLKS8 may include a scan clock line and a carry clock line, which will be described in more detail below. However, this disclosure is not limited thereto, and the number of clock lines CLKS1 to CLKS8 may be modified in various ways. For example, the clock lines may include only the first clock lines CLKS1 to sixth clock lines CLKS6, and may not include the seventh clock line CLKS7 and the eighth clock line CLKS8.

[0130] The clock signals applied to the first clock line CLKS1 through the eighth clock line CLKS8 can have different phases than each other. For example... Figure 7 As shown, the first scan clock signals SC_CK1 to the eighth scan clock signal SC_CK8 (and the first carry clock signals CR_CK1 to the eighth carry clock signals CR_CK8) applied to the first clock line CLKS1 to the eighth clock line CLKS8 may have the same or substantially the same period, and may have a phase difference (e.g., a predetermined or specific phase) (e.g., a phase difference of one-eighth of a period). For example, each of the first scan clock signals SC_CK1 to the eighth scan clock signal SC_CK8 (and the first carry clock signals CR_CK1 to the eighth carry clock signals CR_CK8) may have a period of 8 horizontal time intervals of 8H, and may have a logic low level (or a first voltage level and a cutoff voltage level, etc.) during four horizontal time intervals of 4H. For example, the second scan clock signal SC_CK2 may have a phase delayed from the first scan clock signal SC_CK1 (e.g., a phase delayed by one horizontal time interval of 1H). Some of the scan clock signals from the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 may have waveforms that are complementary to (or have a 180-degree phase difference with) the other scan clock signals (e.g., the remaining scan clock signals) in the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8. For example, during the period when the first scan clock signal SC_CK1 has a logic low level (or a first voltage level and a cutoff voltage level, etc.), the fifth scan clock signal SC_CK5 may have a logic high level (or a second voltage level and a turn-on voltage level, etc.). During the period when the fifth scan clock signal SC_CK5 has a logic low level, the first scan clock signal SC_CK1 may have a logic high level. In other words, the first scan clock signal SC_CK1 and the fifth scan clock signal SC_CK5 may have waveforms that are complementary to each other. Similarly, the second scan clock signal SC_CK2 and the sixth scan clock signal SC_CK6 can have complementary waveforms, the third scan clock signal SC_CK3 and the seventh scan clock signal SC_CK7 can have complementary waveforms, and the fourth scan clock signal SC_CK4 and the eighth scan clock signal SC_CK8 can have complementary waveforms. As will be described in more detail below, the first clock lines CLKS1 to the eighth clock lines CLKS8 can be arranged in the display area DA (e.g., see...). Figure 1(e.g., in the middle or above). In order to mitigate or prevent the effects (e.g., noise) of the clock signals (e.g., pulses with a voltage level of about 25V to 30V) applied to the first clock line CLKS1 to the eighth clock line CLKS8 on the pixel PXL, the clock lines CLKS1 to CLKS8 to be applied with clock signals having complementary waveforms can be arranged in a pair.

[0131] Each of the first carry clock signal CR_CK1 to the eighth carry clock signal CR_CK8 may have a waveform that is the same as or substantially the same as the waveform of the corresponding scan clock signal among the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8, or may have a waveform that is different from the waveform of the corresponding scan clock signal.

[0132] The control line CSS may include a power line for applying drive power to the operation of each of stages ST1 to STn. In an embodiment, the control line CSS may further include a reset control line for resetting stages ST1 to STn.

[0133] The first stage ST1 can be connected to the first clock line CLKS1, the second stage ST2 can be connected to the second clock line CLKS2, the third stage ST3 can be connected to the third clock line CLKS3, the fourth stage ST4 can be connected to the fourth clock line CLKS4, the fifth stage ST5 can be connected to the fifth clock line CLKS5, the sixth stage ST6 can be connected to the sixth clock line CLKS6, the seventh stage ST7 can be connected to the seventh clock line CLKS7, and the eighth stage ST8 can be connected to the eighth clock line CLKS8. Similar to the clock lines from the first stage ST1 to the eighth stage ST8, stages after the eighth stage ST8 can be connected to the corresponding clock lines from the first clock line CLKS1 to the eighth clock line CLKS8. For example, the nth stage STn can be connected to the eighth clock line CLKS8.

[0134] In one or more embodiments, each of stages ST1 to STn may use a clock signal to shift a start signal provided via the start signal line STVP or a previous carry signal provided from the previous stage to generate a corresponding carry signal and a corresponding scan signal (and / or a corresponding sensing scan signal).

[0135] For example, the first stage ST1 can use a first clock signal (e.g., a first carry clock signal CR_CK1 and a first scan clock signal SC_CK1) provided via a first clock line CLKS1 to shift the start signal to generate a first carry signal and a first scan signal (and a first sensing scan signal). The first carry signal can be supplied to the first carry line CR1, and the first scan signal can be supplied to the first scan line SC1. The fifth stage ST5 can use a fifth clock signal (e.g., a fifth carry clock signal CR_CK5 and a fifth scan clock signal SC_CK5) provided via a fifth clock line CLKS5 to shift the first carry signal supplied from the first stage ST1 (e.g., the stage preceding the fifth stage ST5) to generate a fifth carry signal and a fifth scan signal (and a fifth sensing scan signal). The fifth carry signal can be supplied to the fifth carry line CR5, and the fifth scan signal can be supplied to the fifth scan line SC5. Similar to stage 5 (ST5), stage 6 (ST6) can use a sixth clock signal (e.g., the sixth carry clock signal CR_CK6 and the sixth scan clock signal SC_CK6) provided via the sixth clock line CLKS6 to shift a second carry signal (e.g., the second carry signal provided via the second carry line CR2) supplied from stage 2 (e.g., the stage preceding stage 6 (ST6)) to generate a sixth carry signal and a sixth scan signal (and a sixth sensing scan signal). The sixth carry signal can be supplied to the sixth carry line CR6, and the sixth scan signal can be supplied to the sixth scan line SC6. Stage n (STn) can use an eighth clock signal (e.g., the eighth carry clock signal CR_CK8 and the eighth scan clock signal SC_CK8) provided via the eighth clock line CLKS8 to shift an n-4th carry signal (e.g., the n-4th carry signal provided via the n-4th carry line CRn-4) supplied from stage n-4 (e.g., the stage preceding stage n (STn)) to generate an nth carry signal and an nth scan signal (and an nth sensing scan signal). The nth carry signal can be supplied to the nth carry line CRn, and the nth scan signal can be supplied to the nth scan line SCn.

[0136] In an embodiment, each of stages ST1 to STn can be initialized or reset in response to a subsequent carry signal supplied from the next stage. Here, the next stage can be a stage configured to receive a carry signal supplied from the corresponding stage as a previous carry signal.

[0137] For example, the first stage ST1 is initialized or reset in response to a fifth carry signal supplied from the fifth stage ST5 (e.g., the stage following the first stage ST1). The second stage ST2 can be initialized or reset in response to a sixth carry signal supplied from the sixth stage ST6 (e.g., the stage following the second stage ST2).

[0138] To initialize or reset the nth stage STn, etc. (e.g., the last stage), the gate drive circuit 120 may further include at least one dummy stage ST_D.

[0139] For example, such as Figure 6 As shown, the dummy stage ST_D can be connected to the fourth clock line CLKS4 and the control line CSS, and can use the fourth clock signal supplied through the fourth clock line CLKS4 (e.g., the fourth carry clock signal CR_CK4 and the fourth scan clock signal SC_CK4) to shift the nth carry signal to generate a dummy carry signal. In some embodiments, the dummy stage ST_D can further generate a dummy scan signal (and a dummy sense scan signal).

[0140] The dummy carry signal is supplied to the nth stage STn via the dummy carry line CR_D. The nth stage STn can be initialized or reset in response to the dummy carry signal.

[0141] Figure 8A It is shown Figure 6 A diagram illustrating an example of stages included in a gate drive circuit. Because Figure 6 The levels ST1 to STn (and the dummy level ST_D) shown can be identical or substantially identical (or similar) to each other, so each of the levels ST1 to STn (and the dummy level ST_D) can have the same characteristics as... Figure 8A The structures of the levels STi (where i is a positive integer less than or equal to n) shown in the figure are the same or substantially the same (or similar), and therefore their redundant descriptions can be omitted.

[0142] refer to Figure 8A The STi level may include node control circuit SST1, first output circuit SST2, and second output circuit SST3. The clock line CLKS may include carry clock line CR_CLK and scan clock line SC_CLK. The clock line CLKS can be referenced above. Figure 6 This corresponds to any one of the first clock lines CLKS1 to the eighth clock line CLKS8. (See above reference.) Figure 7 The corresponding carry clock signals from the first carry clock signal CR_CK1 to the eighth carry clock signal CR_CK8 and the corresponding scan clock signals from the first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 can be applied to the carry clock line CR_CLK and the scan clock line SC_CLK, respectively.

[0143] The node control circuit SST1 can control the node voltage (e.g., the first node voltage) of the first node Q and the node voltage (e.g., the second node voltage) of the second node QB based on the previous carry signal provided via the previous carry line CRp (where p is a positive integer) of the previous stage (or the start signal provided via the start signal line STVP). For example, when the previous carry signal has a logic low level (or a cutoff voltage level), the node control circuit SST1 can control the second node QB such that the second node voltage of the second node QB has a logic high level (or a turn-on voltage level), and can control the first node Q such that the first node voltage of the first node Q is maintained or substantially maintained at a logic low level. For example, when the previous carry signal has a logic high level, the node control circuit SST1 can control the first node Q such that the first node voltage of the first node Q has a logic high level, and can control the second node QB such that the second node voltage of the second node QB is maintained or substantially maintained at a logic low level.

[0144] In an embodiment, the node control circuit SST1 can initialize the node voltage (e.g., the first node voltage) of the first node Q based on a carry signal (or a dummy carry signal) provided by the carry line CRq (where q is a positive integer) of the next stage. The node control circuit SST1 can initialize the node voltage of the first node Q using the carry signal, such that stage STi outputs carry and scan signals with logic high levels during the corresponding horizontal time period, and stage STi does not output carry and scan signals with logic high levels after the corresponding horizontal time period (e.g., outputs carry and scan signals with logic low levels).

[0145] In some embodiments, the node control circuit SST1 can control the node voltage (e.g., the first node voltage) of the first node Q and the node voltage (e.g., the second node voltage) of the second node QB based on a separate reset signal supplied from an external device.

[0146] The first output circuit SST2 can respond to the first node voltage of the first node Q by outputting the carry clock signal applied to the carry clock line CR_CLK as a carry signal through the second output terminal OUT2 (or carry line CRi). Responding to the second node voltage of the second node QB, the first output circuit SST2 can cause the carry signal to fall completely, be held, or substantially held at a second logic low level (or a second low voltage applied to the second low voltage line VGL2 (or the second power supply line)). The first output circuit SST2 may include a third transistor T3 and a fourth transistor T4. The third transistor T3 may include a first electrode connected to the carry clock line CR_CLK, a second electrode connected to the second output terminal OUT2, and a gate electrode connected to the first node Q. The fourth transistor T4 may include a first electrode connected to the second output terminal OUT2, a second electrode connected to the second low voltage line VGL2, and a gate electrode connected to the second node QB. The first output circuit SST2 may further include a second capacitor C2 connected between the gate electrode of the third transistor T3 and the second output terminal OUT2 to boost the logic high level carry signal.

[0147] The second output circuit SST3 can output the scan clock signal supplied via the scan clock line SC_CLK as a scan signal to the first output terminal OUT1 (or scan line SCi) in response to the first node voltage of the first node Q. In response to the second node voltage of the second node QB, the second output circuit SST3 can cause the scan signal to fall completely, be held, or substantially held at a first logic low level (or a first low voltage applied to the first low voltage line VGL1 (or the first power supply line)). The second output circuit SST3 may include a first transistor T1 and a second transistor T2. The first transistor T1 may include a first electrode connected to the scan clock line SC_CLK, a second electrode connected to the first output terminal OUT1, and a gate electrode connected to the first node Q. The second transistor T2 may include a first electrode connected to the first output terminal OUT1, a second electrode connected to the first low voltage line VGL1, and a gate electrode connected to the second node QB. Furthermore, the second output circuit SST3 may further include a first capacitor C1 connected between the gate electrode of the first transistor T1 and the first output terminal OUT1 to boost the logic high-level scan signal.

[0148] Because the waveforms of the scan signal and the carry signal can be different from each other, a scan clock line SC_CLK different from the carry clock line CR_CLK can be used, and a second output circuit SST3 different from the first output circuit SST2 can be provided at stage STi (e.g., in the middle or at the top). To prevent or substantially prevent interference between the output of the first output circuit SST2 (e.g., the carry signal) and the output of the second output circuit SST3 (e.g., the scan signal), a first low-voltage line VGL1 and a second low-voltage line VGL2 can be used.

[0149] although Figure 8A The stage STi includes a first output circuit SST2 configured to output a carry signal and a second output circuit SST3 configured to output a scan signal, but this disclosure is not limited thereto. For example, the stage STi may further include a third output circuit configured to output a sense scan signal independently of the scan signal. The third output circuit may be implemented in the same or substantially the same manner as the second output circuit SST3.

[0150] Figure 8B It is shown Figure 6 A diagram showing an example of the stages included in a gate drive circuit. Figure 8B The illustration shows a parallel with another embodiment. Figure 8A The corresponding diagram for the STi level.

[0151] refer to Figure 8A and Figure 8B Level STi_1 may include node control circuit SST1_1, first output circuit SST2_1, and second output circuit SST3_1. Because node control circuit SST1_1, first output circuit SST2_1, and second output circuit SST3_1 can be respectively connected to a reference... Figure 8A The node control circuit SST1, the first output circuit SST2, and the second output circuit SST3 are the same or substantially the same (or similar), so their redundant descriptions need not be repeated.

[0152] The first output circuit SST2_1 may include a third transistor T3, a fourth transistor T4, and a second capacitor C2. The fourth transistor T4 may include a first electrode connected to the second output terminal OUT2, a second electrode connected to the first node Q, and a gate electrode connected to the carry clock line CR_CLK. The fourth transistor T4 of the first output circuit SST2_1 can be turned on in response to a carry clock signal supplied via the carry clock line CR_CLK, and can use the node voltage of the first node Q (or a low voltage configured to cause the node voltage of the first node Q to drop completely, for example...). Figure 8C The second low voltage applied to the second low voltage line VGL2 (as shown in the diagram) causes the carry signal to drop completely.

[0153] The second output circuit SST3_1 may include a first transistor T1, a second transistor T2, and a first capacitor C1. The second transistor T2 may include a first electrode connected to the first output terminal OUT1, a second electrode connected to the first low-voltage line VGL1, and a gate electrode connected to the inverting scan clock line SC_CLKB. Here, the inverting scan clock line SC_CLKB may refer to a line to which an inverted clock signal with a waveform complementary to (or having a 180-degree phase difference with) the clock signal applied to the scan clock line SC_CLK is applied. For example, when the first scan clock signal SC_CK1 (see, for example, see...) Figure 7 When the scan clock signal SC_CLK is applied, the fifth scan clock signal SC_CK5 can be applied to the inverted scan clock line SC_CLKB. The second transistor T2 can be turned on in response to the inverted clock signal supplied through the inverted scan clock line SC_CLKB, and the scan signal can be fully degraded using the first low voltage applied to the first low voltage line VGL1.

[0154] As mentioned above, Figure 8B The coupling configuration between the first output circuit SST2_1 and the second output circuit SST3_1 shown in the figure may differ from that in the figure. Figure 8A The coupling configuration between the first output circuit SST2 and the second output circuit SST3 is shown in the figure. In other words, the coupling configuration between the first output circuit SST2_1 (or the first output circuit SST2) and the second output circuit SST3_1 (or the second output circuit SST3) can be modified differently within the range in which scan signals and carry signals can be output.

[0155] Figure 8C It is shown Figure 8A and / or Figure 8B A diagram illustrating an example of node control circuitry included in the stage. More detailed... Figure 8C Show Figure 8B The node control circuit SST1_1 (and / or) included in the STi_1 level Figure 8A The node control circuit SST1 is included in the STi level.

[0156] refer to Figures 8A to 8C The node control circuit SST1_1 may include a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0157] The seventh transistor T7 may include a first electrode connected to the previous carry line CRp, a second electrode connected to the first node Q, and a gate electrode connected to the previous carry line CRp. In response to a previous carry signal (e.g., a previous carry signal with a logic high level) supplied through the previous carry line CRp, the seventh transistor T7 may supply the previous carry signal to the first node Q. In this case, the first node Q may change to a logic high level, or may be held or substantially held at a logic high level.

[0158] The fifth transistor T5 may include a first electrode connected to the first node Q, a second electrode connected to the second low-voltage line VGL2, and a gate electrode connected to the start signal line STVP. The fifth transistor T5 can be turned on in response to a start signal supplied via the start signal line STVP, and can connect the second low-voltage line VGL2 to the first node Q. In this case, the first node Q can have a logic low level by applying a second low voltage to the second low-voltage line VGL2. In other words, the first node Q can be initialized or reset. That is, the first node Q can be initialized or reset using the start signal applied to the start signal line STVP as an initialization signal (or reset signal).

[0159] Similar to the fifth transistor T5, the sixth transistor T6 may include a first electrode connected to the first node Q, a second electrode connected to the second low-voltage line VGL2, and a gate electrode connected to the carry-before line CRq. The sixth transistor T6 can be turned on in response to a carry-before signal supplied via the carry-before line CRq, and can connect the second low-voltage line VGL2 to the first node Q. In other words, the first node Q can be changed from a logic high level to a logic low level or reset by a carry-before signal supplied via the carry-before line CRq.

[0160] Figure 8C The fifth transistor T5 to the seventh transistor T7 are shown for controlling the node voltage of the first node Q using a previous carry signal, a start signal (or a reset signal), and a subsequent carry signal; however, this disclosure is not limited thereto. The coupling configuration of the fifth transistor T5 to the seventh transistor T7 can be modified differently. Furthermore, in embodiments, the node control circuit SST1_1 may further include one or more transistors configured to maintain or substantially maintain the node voltage of the first node Q at a suitable voltage level (e.g., a predetermined or specific voltage level, such as a logic high or logic low level).

[0161] In an embodiment, the node control circuit SST1_1 may further include one or more transistors configured to selectively drive only pixels of a specific level (or pixels connected to a specific pixel row thereto). For example, as Figure 8CAs shown, the node control circuit SST1_1 may further include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a third capacitor C3.

[0162] The eleventh transistor T11 may include a first electrode connected to the second electrode of the twelfth transistor T12, a second electrode connected to the first node Q, and a gate electrode connected to the second control signal line S2. Here, the second control signal line S2 may be included in the control line CSS (e.g., see...). Figure 6 )middle.

[0163] The twelfth transistor T12 may include a first electrode connected to the high voltage line VGH, a second electrode connected to the first electrode of the eleventh transistor T11, and a gate electrode connected to the third node S.

[0164] The thirteenth transistor T13 may include a first electrode connected to the carry line CRi, a second electrode connected to the third node S, and a gate electrode connected to the first control signal line S1. Here, the first control signal line S1 may be included in the control line CSS (e.g., see...). Figure 6 )middle.

[0165] The third capacitor C3 can be formed or connected between the high-voltage line VGH and the third node S.

[0166] When the selection signal (or stage selection signal) is applied to the first control signal line S1, the carry signal applied to the carry line CRi can be applied to the third node S through the thirteenth transistor T13. For example, when the corresponding stage outputs a logic high carry signal, the logic high carry signal can be applied to the third node S, the third capacitor C3 can store the logic high carry signal, and the twelfth transistor T12 can be turned on. Because other stages besides the corresponding stage can output logic low carry signals, the twelfth transistor T12 in other stages can remain off. In other words, when the selection signal (or stage selection signal) is applied to the first control signal line S1, only the stage that outputs the carry signal can be selected.

[0167] Subsequently, when the selection drive signal is applied to the second control signal line S2, the eleventh transistor T11 can be turned on. When the twelfth transistor T12 is turned on, the high voltage applied to the high voltage line VGH can be applied to the first node Q through the eleventh transistor T11 and the twelfth transistor T12. In this case, as referenced... Figure 8A As described, the corresponding stage can output a scan signal in response to the node voltage of the first node Q. Because the twelfth transistor T12 in all stages except the selected stage remains off, the other stages may not output a scan signal.

[0168] For reference Figure 8C As described, the node control circuit SST1_1 can control the node voltage of the first node Q based on the previous carry signal, the start signal (or the reset signal), and the next carry signal. Furthermore, regarding drive selection, the node control circuit SST1_1 can further control the node voltage of the first node Q based on control signals applied through the first control signal line S1 and the second control signal line S2.

[0169] Figure 8D It is shown Figure 6 A diagram showing an example of a dummy level included in a gate drive circuit.

[0170] refer to Figure 8A , Figure 8B and Figure 8D The dummy level ST_D may include node control circuit SST1_2 and first output circuit SST2_2. In other words, because the dummy level ST_D is not connected to the scan line, the second output circuit SST3, which is configured to output the scan signal, may not be included in the dummy level ST_D.

[0171] Because the node control circuit SST1_2 and the first output circuit SST2_2 can be respectively connected to the above reference. Figure 8A The node control circuit SST1 and the first output circuit SST2 are the same or substantially the same (or similar), so their redundant descriptions need not be repeated.

[0172] The first output circuit SST2_2 may include a third transistor T3, a fourth transistor T4, and a second capacitor C2. The fourth transistor T4 may include a first electrode connected to the second output terminal OUT2, a second electrode connected to the second low-voltage line VGL2, and a gate electrode connected to the start signal line STVP. The fourth transistor T4 of the first output circuit SST2_2 can be turned on in response to a start signal supplied via the start signal line STVP, and can use the node voltage of the first node Q (or a low voltage configured to cause the node voltage of the first node Q to drop completely, such as...). Figure 8C The second low voltage (the second low voltage applied to the second low voltage line VGL2 shown in the figure) is used to make the carry signal drop completely.

[0173] The dummy stage ST_D does not output a scan signal. Therefore, even if a logic high-level carry signal is output up to stages ST1 through STn (e.g., see...), the dummy stage ST_D does not output a scan signal. Figure 6The output scan signal allows the gate drive circuit 120 to be driven normally. Furthermore, because the dummy stage ST_D does not need to receive the carry signal from the next stage, it can be initialized or reset using the start signal supplied via the start signal line STVP as a reset signal. In this case, because the dummy stage ST_D does not include a circuit structure for resetting based on the carry signal, it can be further simplified and can be set between other stages (e.g., see...). Figure 9 ).

[0174] Figure 8E It is shown Figure 6 Waveform diagram of the operation of the gate drive circuit.

[0175] refer to Figure 6 and Figures 8A to 8E The start signal S_STVP can be applied to the start signal line STVP. The first scan clock signal SC_CK1 can be applied to the first scan clock line. The second scan clock signal SC_CK2 can be applied to the second scan clock line. The first carry clock signal CR_CK1 can be applied to the first carry clock line. The second carry clock signal CR_CK2 can be applied to the second carry clock line. The first control signal S_S1 can be applied to the first control signal line S1. The second control signal S_S2 can be applied to the second control signal line S2. The first carry signal S_CR1 can be output through the first carry line CR1. The second carry signal S_CR2 can be output through the second carry line CR2. The first scan signal S_SC1 can be output through the first scan line SC1. The second scan signal S_SC2 can be output through the second scan line SC2.

[0176] A frame can include an active period P_ACTIVE and a blank period P_BLANK.

[0177] At the first time point TP1, the start signal S_STVP can have a logic high pulse. In this case, each of stages ST1 to STn (and the dummy stage ST_D) can be initialized (see, for example, see...). Figure 8A The node control circuit SST1 or Figure 8B The node control circuit SST_1).

[0178] The first control signal S_S1 can be a logic high-level pulse. In this case, refer to the above... Figure 8C The thirteenth transistor T13 can be turned on, and the third node S can be initialized by a logic low carry signal CRi. In other words, the third node S of each of stages ST1 to STn can be initialized. For example, the third node S of the stage selected in the previous frame can be initialized.

[0179] In response to the logic high-level start signal S_STVP, during the active period P_ACTIVE, the first scan clock signal SC_CK1 and the second scan clock signal SC_CK2 (and other scan clock signals not shown, see [link]) are executed. Figure 7 It can alternate between logic high and logic low levels.

[0180] At the second time point TP2, the first scan signal S_SC1 can be logic high in response to the first scan clock signal SC_CK1, and the first carry signal S_CR1 can be logic high in response to the first carry clock signal CR_CK1. At the third time point TP3, the second scan signal S_SC2 can be logic high in response to the second scan clock signal SC_CK2, and the second carry signal S_CR2 can be logic high in response to the second carry clock signal CR_CK2. In other words, during the active period P_ACTIVE, carry signals with logic high levels can be output sequentially, and scan signals with logic high levels can be output sequentially.

[0181] At a specific point in time during the active period P_ACTIVE, the first control signal S_S1 can be at a logic high level. For example, as Figure 8E As shown, at the fourth time point TP4, the first control signal S_S1 can have a logic high level.

[0182] In this case, the first stage ST1 of the first carry signal S_CR1, configured to output logic high, can be selected. (See reference) Figure 8C For example, the third node S in the first stage ST1 can be changed to have a logic high level in response to the first carry signal S_CR1, and the node voltage of the third node S can be maintained or substantially maintained at a logic high level by the third capacitor C3.

[0183] Subsequently, during the blank period P_BLANK, the second control signal S_S2 can have a logic high pulse, and only the scan clock signal corresponding to the selected level can have a logic high.

[0184] For example, such as Figure 8E As shown, at the fifth time point TP5, the second control signal S_S2 can have a logic high pulse. In this case, the eleventh transistor T11 in the first stage ST1 can be turned on, and the first node Q in the first stage ST1 can be changed to a logic high level. Because the first scan clock signal SC_CK1 has a logic low level, the first scan signal S_SC1 can have a logic low level (e.g., see...). Figure 8A and Figure 8BThe second output circuits SST3 and SST3_1).

[0185] At time point TP6, only the first scan clock signal SC_CK1 can have a logic high level. In this case, because the first stage ST1 outputs the first scan clock signal SC_CK1 as the first scan signal S_SC1, the first scan signal S_SC1 can have a logic high level.

[0186] As described above, the gate drive circuit 120 can sequentially output the scan signal and carry signal during the active period P_ACTIVE, and can output the scan signal only through the selected stage during the blank period P_BLANK.

[0187] Figure 9 It is shown Figure 1 An example diagram of a display panel included in a display device. Because Figure 1 The display panels 100 shown may be identical or substantially identical (or similar) to each other, so reference will be made to them. Figure 9 A more detailed description of one of the display panels 100. In other words, Figure 1 Each of the first display panel 101, second display panel 102, third display panel 103, and fourth display panel 104 shown may have the same characteristics as... Figure 9 The structure of the display panel 100 shown is the same or substantially the same, and therefore, its redundant description need not be repeated.

[0188] refer to Figure 1 and Figure 9 The display panel 100 can be connected to the data driver 140 via a connecting film COF. Furthermore, the display panel 100 can receive clock and control signals from external devices (e.g., timing controllers and / or power supplies) via a printed circuit board (PCB) and the connecting film COF.

[0189] like Figure 9 As shown, the data driver 140 can be implemented as an integrated circuit to be mounted on the central portion of the connecting film COF. The data driver 140 can receive image data from an external device via the printed circuit board (PCB) and the connecting film COF, and can generate a data voltage corresponding to the grayscale values ​​(or data values) included in the image data. The data driver 140 can pass through the connecting film COF to the display panel 100 (e.g., via data lines DL in the display panel 100, see...). Figure 10A The data voltage is transmitted to the pixel PXL (for example, see...). Figure 10AControl lines (or transmission lines) extending from the printed circuit board (PCB) and connecting the display panels 100 to each other can be arranged adjacent to the short side of the connecting film COF in the first direction DR1, and control signals can be transmitted to the display panel 100 through the control lines CSS.

[0190] The connection film COF may consist of only one conductive layer, and the control line CSS (or transmission line) may not intersect with the data line DL extending from the data driver 140 to be disposed between the display panels 100. On the other hand, in order for the control line CSS and the data line DL to intersect each other at the connection film COF (e.g., in the middle or on top), the connection film COF may include at least two conductive layers, but in this case, the manufacturing cost of the connection film COF may increase.

[0191] like Figure 9 As shown, the display panel 100 can be connected to multiple connection films COF and multiple data drivers 140. However, this disclosure is not limited thereto, and the display panel 100 can be connected to one connection film COF and one data driver 140 or any suitable number of connection films COF and data drivers 140.

[0192] The display panel 100 may include gate drive circuitry 120 that can be distributed at the display area DA (e.g., center or top) (see, for example, see...). Figure 6 (See above for reference) Figure 1 and Figure 2 In order to minimize or reduce the non-display area of ​​the display panel 100, the gate driving circuit 120 can be distributed at the display area DA (e.g., in the middle or at the top). In other words, the components of the gate driving circuit 120 can be distributed along the display area DA.

[0193] In one or more embodiments, the gate drive circuit 120 may include a plurality of blocks BLK1 and BLK2 (or sub-gate drive circuits).

[0194] For example, such as Figure 9 As shown, the gate drive circuit 120 may include a first BLK1 adjacent to one side of the display panel 100 and a second BLK2 adjacent to the other side of the display panel 100.

[0195] Each of the first BLK1 and the second BLK2 can be connected to scan lines SC1 to SCn included in the display panel 100. The first BLK1 and the second BLK2 can supply scan signals to scan lines SC1 to SCn at the same or substantially the same timing. Because scan signals are supplied from the left and right sides of the display panel 100 through the first BLK1 and the second BLK2, the delay and attenuation of the scan signals caused by the load on scan lines SC1 to SCn can be mitigated (e.g., reduced).

[0196] Because the first BLK1 and the second BLK2 are identical or substantially identical (or similar) to each other except for their positions, the first BLK1 will be described in more detail below, and redundant descriptions of the second BLK2 will not be repeated.

[0197] The first BLK1 can include the above reference. Figure 6 The levels ST1 to STn are described. Furthermore, the first block BLK1 may further include dummy levels ST_D1 to ST_D4. Each of the dummy levels ST_D1 to ST_D4 can be referenced above. Figure 6 The description corresponds to the dummy level ST_D.

[0198] Each of levels ST1 to STn can be distributed across multiple scan lines SC1 to SCn passing through its set cell region UA ​​(e.g., a cell region UA ​​where multiple pixel rows and multiple pixel columns intersect) (e.g., middle or top). Figure 9 As shown, the first stage ST1 can be located at the cell region UA ​​through which the first to fourth scan lines SC1 to SC4 are positioned (e.g., in the middle or above). In other words, stages ST1 to STn can be located at the cell region UA ​​corresponding to each of the four corresponding scan lines (e.g., in the middle or above). However, this disclosure is not limited thereto. Considering the number and capacitance of the transistors and capacitors forming stages ST1 to STn, each of stages ST1 to STn can be located in the corresponding cell region UA ​​corresponding to two, three, five, or more scan lines.

[0199] Levels ST1 to STn can be divided into multiple sub-blocks BLK_S1 to BLK_S4, and can be set in regions spaced apart from each other (e.g., separated) (e.g., in the middle or on top). Figure 9 As shown, levels ST1 to STn can be divided into first sub-blocks BLK_S1 to fourth sub-blocks BLK_S4. See below for reference. Figure 10A In more detail, stages ST1 to STn can be divided by clock lines (e.g., carry clock line or scan clock line), and can be based on the above reference. Figure 6The eight clock lines CLKS1 to CLKS8 described are divided into four sub-blocks BLK_S1 to BLK_S4. However, this disclosure is not limited thereto, and levels ST1 to STn can be divided into eight sub-blocks or two sub-blocks.

[0200] The first sub-block BLK_S1 may include level 1 ST1, level 5 ST5, level 9 ST9, level n-7 STn-7, and level n-3 STn-3. In other words, the first sub-block BLK_S1 may include links to the references above. Figure 6 The stage described is either the first clock line CLKS1 or the fifth clock line CLKS5.

[0201] In an embodiment, levels ST1, ST5, ST9, STn-7, and STn-3 may be spaced apart from each other at the first sub-block BLK_S1 (e.g., in the middle or above). For example, the first level ST1 and the fifth level ST5 may be spaced apart from each other (e.g., in the second direction DR2) to have space between them that allows at least one line to extend between the first level ST1 and the fifth level ST5 in the first direction DR1. Therefore, reference will be made to... Figures 9 to 11 The connection lines described in more detail can be set between at least some of the stages ST1 to STn.

[0202] In addition, the first sub-block BLK_S1 may further include the first dummy level ST_D1.

[0203] Compared to the (n-3)th level STn-3, which is the last level of the first sub-block BLK_S1, the first dummy level ST_D1 can be set to be further away from the edge of the display panel 100. For example... Figure 9 As shown, the first dummy level ST_D1 can be set between the (n-3)th level STn-3 and the (n-7)th level STn-7.

[0204] Similarly, the second sub-block BLK_S2 may include each of its members connected to the reference above. Figure 6 The second clock line CLKS2 or the sixth clock line CLKS6 describes the second stage ST2, the sixth stage ST6, the tenth stage ST10, the (n-6)th stage STn-6, the (n-2)th stage STn-2, and the second dummy stage ST_D2. The third sub-block BLK_S3 may include each of these connected to the reference above. Figure 6 The third clock line CLKS3 or the seventh clock line CLKS7 describes the third stage ST3, the seventh stage ST7, the eleventh stage ST11, the (n-5)th stage STn-5, the (n-1)th stage STn-1, and the third dummy stage ST_D3. The fourth sub-block BLK_S4 may include each of these connected to the reference above. Figure 6The fourth clock line CLKS4 or the eighth clock line CLKS8 is described as having the fourth stage ST4, the eighth stage ST8, the eleventh stage ST12, the (n-4)th stage STn-4, the nth stage STn, and the fourth dummy stage ST_D4.

[0205] When levels ST1 to STn are divided into the first sub-block BLK_S1 to the fourth sub-block BLK_S4, refer to the above. Figure 6 The described clock lines CLKS1 to CLKS8 can be distributed and arranged adjacent to their corresponding sub-blocks, and interference between clock lines CLKS1 to CLKS8 (e.g., capacitance due to their overlap) can be reduced. More specifically, since stages ST1 to STn are sufficiently spaced apart from each other at their corresponding sub-blocks (e.g., in the middle or on top) in the second direction DR2, space can be ensured for the connection lines of clock lines CLKS1 to CLKS8 (and control line CSS) (e.g., connection lines extending from DR1 in the first direction).

[0206] Furthermore, since each of the first sub-blocks BLK_S1 to the fourth sub-blocks BLK_S4 includes only a stage with a shared carry signal (e.g., providing a previous carry signal or a subsequent carry signal), the carry signal line configured to transmit the carry signal between the first sub-blocks BLK_S1 to the fourth sub-blocks BLK_S4 can be omitted (e.g., removed), and the parasitic capacitance of the carry signal line can also be reduced.

[0207] although Figure 9 The first level ST1 to the fourth level ST4 are shown arranged in the same row (e.g., in the middle or above), but this disclosure is not limited thereto. For example, the first level ST1 to the fourth level ST4 may be arranged to be staggered in the first direction DR1.

[0208] Figure 10A It is shown Figure 9 The first block included in the display panel is an example diagram. Figure 10A schematically shown Figure 9 A magnified view of the display panel 100 focusing on clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8.

[0209] refer to Figure 9 and Figure 10A Clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 may include first scan clock lines SC_CLK1 to eighth scan clock lines SC_CLK8 and first carry clock lines CR_CLK1 to eighth carry clock lines CR_CLK8. (See above reference.) Figure 7The first scan clock signal SC_CK1 to the eighth scan clock signal SC_CK8 described herein can be applied to the first scan clock line SC_CLK1 to the eighth scan clock line SC_CLK8 respectively, and the first carry clock signal CR_CK1 to the eighth carry clock signal CR_CK8 can be applied to the first carry clock line CR_CLK1 to the eighth carry clock line CR_CLK8 respectively.

[0210] Clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 can extend to the connecting film COF or can be connected to the transmission lines on the connecting film COF, and can be connected from external devices (e.g., via the reference above). Figure 9 The described printed circuit board (PCB) receives clock signals from a timing controller.

[0211] At least some of the clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 can be distributed at the display panel 100 (e.g., in the middle or at the top) via a first connecting line CNL1 extending in the first direction DR1. The clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 can cross the scan lines SC1 to SC12 at the display area DA (e.g., in the middle or at the top).

[0212] In one or more embodiments, two clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8, to which two clock signals with a 180-degree phase difference are applied, can be arranged as a pair. As described above, since the noise caused by the two clock signals with a 180-degree phase difference can cancel each other out, the impact of the clock lines on adjacent pixels PXL can be reduced. In embodiments, scan clock lines SC_CLK1 to SC_CLK8 can be arranged adjacent to one side of the corresponding sub-block, and carry clock lines CR_CLK1 to CR_CLK8 can be arranged adjacent to the other side of the corresponding sub-block.

[0213] For example, the first carry clock line CR_CLK1 and the fifth carry clock line CR_CLK5 of the first sub-block BLK_S1 can extend in the second direction DR2 between the first sub-block BLK_S1 and the second sub-block BLK_S2 to form a pair. Furthermore, the second scan clock line SC_CLK2 and the sixth scan clock line SC_CLK6 of the second sub-block BLK_S2 can extend in the second direction DR2 between the first sub-block BLK_S1 and the second sub-block BLK_S2 to form a pair. In an embodiment, the second scan clock line SC_CLK2 and the sixth scan clock line SC_CLK6 can be spaced apart from the first carry clock line CR_CLK1 and the fifth carry clock line CR_CLK5, and at least one pixel PXL is inserted between the second scan clock line SC_CLK2 and the sixth scan clock line SC_CLK6 and the first carry clock line CR_CLK1 and the fifth carry clock line CR_CLK5.

[0214] Similarly, between the second sub-block BLK_S2 and the third sub-block BLK_S3, the second carry clock line CR_CLK2 and the sixth carry clock line CR_CLK6 of the second sub-block BLK_S2 can be arranged in pairs, and the third scan clock line SC_CLK3 and the seventh scan clock line SC_CLK7 of the third sub-block BLK_S3 can be arranged in pairs. Between the third sub-block BLK_S3 and the fourth sub-block BLK_S4, the third carry clock line CR_CLK3 and the seventh carry clock line CR_CLK7 can be arranged in pairs, and the fourth scan clock line SC_CLK4 and the eighth scan clock line SC_CLK8 can be arranged in pairs. On one side of the fourth sub-block BLK_S4 (e.g., in the middle or at the top), the fourth carry clock line CR_CLK4 and the eighth carry clock line CR_CLK8 can be arranged in pairs. On one side of the first sub-block BLK_S1 (e.g., in the middle or at the top), the first scan clock line SC_CLK1 and the fifth scan clock line SC_CLK5 can be arranged in pairs.

[0215] Clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8, distributed and arranged between the first sub-blocks BLK_S1 to the fourth sub-blocks BLK_S4 (e.g., or on their corresponding sides (e.g., in the middle or on top)), can be connected to the connecting film COF via the first connecting line CNL1. In other words, even if the arrangement of clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 in the connecting film COF remains unchanged, the clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 in the display panel 100 can also be set between pixels PXL (or between data lines) using the first connecting line CNL1.

[0216] For example, such as Figure 10AAs shown, the second scan clock line SC_CLK2 and the third scan clock line SC_CLK3 can be connected to the connecting film COF via the first connection line CNL1 between the first stage ST1 and the fifth stage ST5. For example, the fourth scan clock line SC_CLK4 and the sixth scan clock line SC_CLK6 can be connected to the connecting film COF via the first connection line CNL1 between the fifth stage ST5 and the ninth stage ST9.

[0217] although Figure 10A Two first connection lines CNL1 are shown positioned between two corresponding levels, but this disclosure is not limited thereto. For example, one first connection line CNL1 or three or more first connection lines CNL1 may be positioned between two corresponding levels.

[0218] Furthermore, despite Figure 10A The clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 are shown to be routed sequentially, but this disclosure is not limited thereto. As mentioned above, signals with complementary waveforms can be routed together. For example, the second scan clock line SC_CLK2 and the sixth scan clock line SC_CLK6 can be connected to the first connection line CNL1 between the first stage ST1 and the fifth stage ST5.

[0219] As described above, clock lines to which clock signals with complementary waveforms are applied can be arranged in pairs. Therefore, the impact of the clock lines on the pixel PXL can be reduced. Furthermore, clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 can be connected to the connecting film COF via a first connecting line CNL1 disposed between the stages. Therefore, a structure (e.g., a connecting film including at least two conductive layers to realize lines intersecting each other) for positioning (e.g., arranging) clock lines SC_CLK1 to SC_CLK8 and CR_CLK1 to CR_CLK8 between data lines DL at the connecting film COF (e.g., in the middle or on top) can be omitted, and the display device 1000 can be reduced in size (e.g., see...). Figure 1 The manufacturing cost of ).

[0220] Figure 10B It is shown Figure 9 The first block included in the display panel is an example diagram. Figure 10B schematically shown Figure 9 A magnified view of the focus control line CSS of the display panel 100.

[0221] refer to Figure 9 and Figure 10B The control line CSS may include a first low-voltage line VGL1 and a second low-voltage line VGL2. The first low-voltage line VGL1 and the second low-voltage line VGL2 may be referenced above. Figures 8A to 8DThe first low voltage line VGL1 and the second low voltage line VGL2 are described.

[0222] The first low-voltage line VGL1 and the second low-voltage line VGL2 can extend to the connecting film COF, or can be connected to the transmission line on the connecting film COF, and can be from an external device (e.g., via the above reference). Figure 9 The described printed circuit board (PCB) receives a low voltage (or electrical voltage) from the power source.

[0223] The first low-voltage line VGL1 and the second low-voltage line VGL2 can be distributed in the display panel 100 by a second connecting line CNL2 extending in the first direction DR1.

[0224] The first low-voltage line VGL1 and the second low-voltage line VGL2 may pass through stages ST1, ST5, and ST9 in the first sub-block BLK_S1. However, this disclosure is not limited thereto. For example, with respect to the first sub-block BLK_S1, the first low-voltage line VGL1 and the second low-voltage line VGL2 may be configured to be adjacent to at least one side of stages ST1, ST5, ST9 to STn-7 and STn-3.

[0225] Similarly, the first low voltage line VGL1 and the second low voltage line VGL2 can pass through stages ST2, ST6 and ST10 in the second sub-block BLK_S2, the first low voltage line VGL1 and the second low voltage line VGL2 can pass through stages ST3, ST7 and ST11 in the third sub-block BLK_S3, and the first low voltage line VGL1 and the second low voltage line VGL2 can pass through stages ST4, ST8 and ST12 in the fourth sub-block BLK_S4.

[0226] For example, the first low-voltage line VGL1 can be connected to the connecting membrane COF via a second connecting line CNL2 extending between the first stage ST1 and the fifth stage ST5. Furthermore, the first low-voltage line VGL1 can be connected to the connecting membrane COF via a second connecting line CNL2 extending between the sixth stage ST6 and the tenth stage ST10. Similarly, the second low-voltage line VGL2 can be connected to the connecting membrane COF via second connecting lines CNL2 extending between the first stage ST1 and the fifth stage ST5, and between the sixth stage ST6 and the tenth stage ST10. In this manner, each of the first low-voltage line VGL1 and the second low-voltage line VGL2 can be arranged to connect to all stages ST1 to ST12.

[0227] In an embodiment, compared to the corresponding first connection line CNL1, the second connection line CNL2 adjacent to the corresponding first connection line CNL1 can be set to be closer (e.g., closer) to the corresponding pixel PXL (or the corresponding level). In other words, the corresponding first connection line CNL1 can be arranged between two adjacent second connection lines CNL2.

[0228] like Figure 10B As shown, compared to the first connection line CNL1 extending between the first stage ST1 and the fifth stage ST5, the second connection line CNL2 connected to the first low-voltage line VGL1 can be arranged adjacent to (e.g., closer to) the first stage ST1 (or the pixel PXL connected to the fourth scan line SC4). Similarly, compared to the first connection line CNL1 extending between the first stage ST1 and the fifth stage ST5, the second connection line CNL2 connected to the second low-voltage line VGL2 can be arranged adjacent to (e.g., closer to) the fifth stage ST5 (or the pixel PXL connected to the fifth scan line SC5). In other words, the first connection line CNL1 can be arranged between at least one pair of second connection lines CNL2. In this case, the second connection line CNL2, to which a DC low voltage is applied, can shield the first connection line CNL1, to which an AC clock signal is applied, and can suppress or prevent coupling between the first connection line CNL1 and the pixel PXL.

[0229] although Figure 10B The illustration shows two second connection lines CNL2 positioned between two corresponding levels, but this disclosure is not limited thereto. Three or more second connection lines CNL2 may be positioned between two corresponding levels.

[0230] Furthermore, despite Figure 10B The second connecting line CNL2 is shown to be partially disposed at the display panel 100 (e.g., in the middle or at the top), but this disclosure is not limited thereto. For example, the second connecting line CNL2 may extend from a first end to a second end of the display panel 100 in a second direction DR2, and the second connecting line CNL2 may use a level as a basic unit to form a mesh structure.

[0231] When the control signal lines used for the common control levels ST1 to ST12 are further included in the control line CSS, it is similar to Figure 10B The first low voltage line VGL1 and the second low voltage line VGL2 shown in the figure have corresponding control signal lines that can be distributed in the display panel 100 via connecting lines.

[0232] As described above, the control line CSS (or the first low-voltage line VGL1 and the second low-voltage line VGL2) can be connected to the connecting film COF via the second connecting line CNL2 disposed between stages ST1 to ST12. Therefore, the structure for positioning the control line CSS between the data lines DL in the connecting film COF (e.g., a connecting film including at least two conductive layers to achieve lines crossing each other) is not required.

[0233] Figure 11 It is shown Figure 9 A diagram showing an example of control lines included in the display panel. Figure 11 The arrangement of the control lines for the first sub-block BLK_S1 is shown schematically.

[0234] refer to Figure 9 and Figure 11 Pixels PXL can be arranged in pixel rows ROW (e.g., pixel rows ROW1 to ROW15) and pixel columns COL (e.g., pixel columns COL1 to COL22).

[0235] The first sub-block BLK_S1 can be arranged between the sixth pixel column COL6 and the twelfth pixel column COL12. However, this disclosure is not limited to... Figure 11 The diagram shown in the figure illustrates that the arrangement of the first sub-block BLK_S1 can be modified in various ways.

[0236] Low-voltage line VGL1-1 (1-1) can extend between the first pixel column COL1 and the second pixel column COL2, along the second direction DR2. Low-voltage line VGL1-1 (1-1) can be connected to an external device (e.g., a connecting film COF and / or pads, etc.). Low-voltage line VGL1-2 (1-2) can extend between the ninth pixel column COL9 and the tenth pixel column COL10, along the second direction DR2. Low-voltage lines VGL1-1 (1-1) and VGL1-2 (1-2) can be connected to each other via a first low-voltage connection line VGL1_C extending between the sixth pixel row ROW6 and the seventh pixel row ROW7, along the first direction DR1. Low-voltage lines VGL1-1 (1-1) and VGL1-2 (1-2) can form the above reference. Figure 10B The first low-voltage line VGL1 is described, and the first low-voltage connection line VGL1_C can be included in the reference above. Figure 10B The second connecting line CNL2 is described.

[0237] Scan clock line SC_CLK1-1 (first scan) can extend between the second pixel column COL2 and the third pixel column COL3, along the second direction DR2. Scan clock line SC_CLK1-1 can be connected to an external device (e.g., a connecting film COF and / or pads). Scan clock line SC_CLK1-2 (first scan) can extend between the sixth pixel column COL6 and the seventh pixel column COL7, along the second direction DR2. Scan clock lines SC_CLK1-1 and SC_CLK1-2 can be connected to each other via a first scan clock connection line SC_CLK1_C extending between the second pixel row ROW2 and the third pixel row ROW3, ​​along the first direction DR1. Scan clock lines SC_CLK1-1 and SC_CLK1-2 can form the above reference. Figure 10A The first scan clock line SC_CLK1 is described, and the first scan clock connection line SC_CLK1_C can be included in the reference above. Figure 10A The first connecting line CNL1 is described.

[0238] Scan clock line SC_CLK5-1 (5-1) can extend between the third pixel column COL3 and the fourth pixel column COL4, along the second direction DR2. Scan clock line SC_CLK5-1 can be connected to an external device (e.g., a connecting film COF and / or pads). Scan clock line SC_CLK5-2 (5-2) can extend between the sixth pixel column COL6 and the seventh pixel column COL7, along the second direction DR2. Scan clock lines SC_CLK5-1 and SC_CLK5-2 can be connected to each other via a fifth scan clock connection line SC_CLK5_C extending between the second pixel row ROW2 and the third pixel row ROW3, ​​along the first direction DR1. Scan clock lines SC_CLK5-1 and SC_CLK5-2 can form the above reference. Figure 10A The fifth scan clock line SC_CLK5 is described above, and the fifth scan clock connection line SC_CLK5_C can be included in the reference above. Figure 10A The first connecting line CNL1 is described.

[0239] In this embodiment, the first-third scan clock line SC_CLK1-3 can extend between the third pixel column COL3 and the fourth pixel column COL4, along the second direction DR2, to correspond to the fifth-first scan clock line SC_CLK5-1, and can be connected to the first scan clock connection line SC_CLK1_C. Furthermore, the fifth-third scan clock line SC_CLK5-3 can extend between the second pixel column COL2 and the third pixel column COL3, along the second direction DR2, to correspond to the first-first scan clock line SC_CLK1-1, and can be connected to the fifth scan clock connection line SC_CLK5_C. In this case, the first scan clock line SC_CLK1 and the fifth scan clock line SC_CLK5 can be arranged in pairs throughout the display panel. The first scan clock line SC_CLK1 and the fifth scan clock line SC_CLK5 can reduce the impact on adjacent pixels by transmitting complementary scan clock signals.

[0240] The first start signal line STVP1 can extend between the thirteenth pixel column COL13 and the fourteenth pixel column COL14, along the second direction DR2. The first start signal line STVP1 can be connected to an external device (e.g., a connecting film COF and / or pads). The second start signal line STVP2 can extend between the seventh pixel column COL7 and the eighth pixel column COL8, along the second direction DR2. The first start signal line STVP1 and the second start signal line STVP2 can be connected to each other via a start signal connection line STVP_C extending along the first direction DR1 between the twelfth pixel row ROW12 and the thirteenth pixel row ROW13.

[0241] Carry-1 clock line CR_CLK1-1 can extend between the fourteenth pixel column COL14 and the fifteenth pixel column COL15, along the second direction DR2. Carry-1 clock line CR_CLK1-1 can be connected to an external device (e.g., a connecting film COF and / or pads, etc.). Carry-1 clock line CR_CLK1-2 can extend between the eleventh pixel column COL11 and the twelfth pixel column COL12, along the second direction DR2. Carry-1 clock line CR_CLK1-1 and Carry-1 clock line CR_CLK1-2 can be connected to each other via a first carry clock connection line CR_CLK1_C extending along the first direction DR1 between the tenth pixel row ROW10 and the eleventh pixel row ROW11. Carry-1 clock line CR_CLK1-1 and Carry-1 clock line CR_CLK1-2 can form the above reference. Figure 10A The first carry clock line CR_CLK1 is described, and the first carry clock connection CR_CLK1_C can be included in the reference above. Figure 10AThe first connecting line CNL1 is described.

[0242] Carry clock line CR_CLK5-1 (5-1) can extend between the fifteenth pixel column COL15 and the sixteenth pixel column COL16, along the second direction DR2. Carry clock line CR_CLK5-1 can be connected to an external device (e.g., a connecting film COF and / or pads). Carry clock line CR_CLK5-2 (5-2) can extend between the eleventh pixel column COL11 and the twelfth pixel column COL12, along the second direction DR2. Carry clock lines CR_CLK5-1 and CR_CLK5-2 can be connected to each other via a fifth carry clock connection line CR_CLK5_C extending between the tenth pixel row ROW10 and the eleventh pixel row ROW11, along the first direction DR1. Carry clock lines CR_CLK5-1 and CR_CLK5-2 can form the above reference. Figure 10A The fifth carry clock line CR_CLK5 is described, and the fifth carry clock connection CR_CLK5_C can be included in the reference above. Figure 10A The first connecting line CNL1 is described.

[0243] In this embodiment, the first-to-third carry clock line CR_CLK1-3 can extend along the second direction DR2 between the fifteenth pixel column COL15 and the sixteenth pixel column COL16 to correspond to the fifth-to-first carry clock line CR_CLK5-1, and can be connected to the first carry clock connection line CR_CLK1_C. Furthermore, the fifth-to-third carry clock line CR_CLK5-3 can extend along the second direction DR2 between the fourteenth pixel column COL14 and the fifteenth pixel column COL15 to correspond to the first-to-first carry clock line CR_CLK1-1, and can be connected to the fifth carry clock connection line CR_CLK5_C. In this case, the first carry clock line CR_CLK1 and the fifth carry clock line CR_CLK5 can be arranged in pairs throughout the display panel.

[0244] The first high-voltage line VGH1 can extend between the seventeenth pixel column COL17 and the eighteenth pixel column COL18 in the second direction DR2. The first high-voltage line VGH1 can be connected to an external device. The second high-voltage line VGH2 can extend between the seventh pixel column COL7 and the eighth pixel column COL8 in the second direction DR2. The first high-voltage line VGH1 and the second high-voltage line VGH2 can be connected to each other via a high-voltage connection line VGH_C extending between the twelfth pixel row ROW12 and the thirteenth pixel row ROW13 in the first direction DR1.

[0245] Low-voltage line 2-1, VGL2-1, can extend between the eighteenth pixel column COL18 and the nineteenth pixel column COL19, along the second direction DR2. Low-voltage line 2-1, VGL2-1, can be connected to an external device. Low-voltage line 2-2, VGL2-2, can extend between the tenth pixel column COL10 and the eleventh pixel column COL11, along the second direction DR2. Low-voltage lines 2-1, VGL2-1, and 2-2, VGL2-2, can be connected to each other via a second low-voltage connection line VGL2_C extending between the eighth pixel row ROW8 and the ninth pixel row ROW9, along the first direction DR1. Low-voltage lines 2-1, VGL2-1, and 2-2, VGL2-2, can form the above reference. Figure 10B The second low-voltage line VGL2 is described, and the second low-voltage connection line VGL2_C can be included in the reference above. Figure 10B The second connecting line CNL2 is described.

[0246] Control signal line S1-1 can extend between the nineteenth pixel column COL19 and the twentieth pixel column COL20, along the second direction DR2. Control signal line S1-1 can be connected to an external device. Control signal line S1-2 can extend between the eighth pixel column COL8 and the ninth pixel column COL9, along the second direction DR2. Control signal line S1-1 and control signal line S1-2 can be connected to each other via a first control signal connection line S1_C extending between the fourteenth pixel row ROW14 and the fifteenth pixel row ROW15, along the first direction DR1. Control signal line S1-1 and control signal line S1-2 can form the above reference. Figure 8C The first control signal line S1 is described.

[0247] Control signal line S2-1 (2-1) can extend between the twentieth pixel column COL20 and the twenty-first pixel column COL21, along the second direction DR2. Control signal line S2-1 can be connected to an external device. Control signal line S2-2 (2-2) can extend between the eighth pixel column COL8 and the ninth pixel column COL9, along the second direction DR2. Control signal line S2-1 and control signal line S2-2 can be connected to each other via a second control signal connection line S2_C extending between the fourteenth pixel row ROW14 and the fifteenth pixel row ROW15, along the first direction DR1. Control signal line S2-1 and control signal line S2-2 can form the above reference. Figure 8C The second control signal line S2 is described.

[0248] As described above, control lines connected to external devices (e.g., low-voltage line VGL1-1, etc., 1-1) can be spaced apart from each other outside the first sub-block BLK_S1, with at least one pixel PXL inserted between the control lines. Furthermore, control lines connected to external devices (e.g., low-voltage line VGL1-1, 1-1, etc.) can be connected to control lines (e.g., low-voltage line VGL1-2, 1-2, etc.) within the first sub-block BLK_S1 via connecting lines (e.g., first low-voltage connecting line VGL1_C, etc.). Simultaneously, control lines configured to transmit complementary signals (e.g., first scan clock line SC_CLK1 and fifth scan clock line SC_CLK5, first carry clock line CR_CLK1 and fifth carry clock line CR_CLK5) can be arranged in pairs.

[0249] Figure 12 It is shown Figure 9 The display panel includes an example diagram of the levels. Because Figure 9 The stages ST1 to STn shown are identical or substantially identical (or similar) to each other except for their arrangement, so the fifth stage ST5 will be described in more detail below, and redundant descriptions of the other stages will not be repeated.

[0250] refer to Figure 6 , Figure 8A , Figure 8B and Figures 9 to 12 The fifth level ST5 can be distributed at the cell region UA ​​(e.g., in the middle or above) that the fifth to eighth scan lines SC5 to SC8 cross (e.g., extend through).

[0251] The fifth scan clock line SC_CLK5 can be set together with the first scan clock line SC_CLK1, adjacent to one side of the fifth level ST5 (or adjacent to one side of the cell region UA). The fifth carry clock line CR_CLK5 can be set together with the first carry clock line CR_CLK1, adjacent to the other side of the fifth level ST5 (or adjacent to the other side of the cell region UA). For example, as referenced above... Figure 11As described above, when compared with the first scan clock line SC_CLK1 and the fifth scan clock line SC_CLK5, and the first carry clock line CR_CLK1 and the fifth carry clock line CR_CLK5, the high voltage line VGH, the first low voltage line VGL1, and the second low voltage line VGL2 can be located inside the cell region UA ​​(e.g., in the middle or above) and can be set through the fifth level ST5 (or cell region UA) (e.g., set to extend through the fifth level ST5 (or cell region UA)). Other control lines used to control the node voltage of the first node Q of the fifth level ST5 (e.g., the start signal line STVP, the first control signal line S1, and the second control signal line S2 extending in the second direction DR2) can also be set through the fifth level ST5 (e.g., set to extend through the fifth level ST5). The high voltage line VGH, the first low voltage line VGL1, the second low voltage line VGL2, the start signal line STVP, the first control signal line S1, and the second control signal line S2 can be set to be spaced apart from each other, with at least one pixel PXL inserted between them. However, this disclosure is not limited thereto.

[0252] Regarding the fifth scan clock line SC_CLK5, the second output circuit SST3 can be located adjacent to one side of cell region UA ​​(e.g., in the middle or at the top). Regarding the fifth carry clock line CR_CLK5, the first output circuit SST2 can be located adjacent to the other side of cell region UA ​​(e.g., in the middle or at the top). The node control circuit SST1 can be located between the first output circuit SST2 and the second output circuit SST3 at cell region UA ​​(e.g., in the middle or at the top).

[0253] like Figure 12 As shown, the first transistor T1 and the first capacitor C1 of the second output circuit SST3 can be distributed in the regions corresponding to the two pixels PXL (e.g., in the middle or on top). Considering the load of the fifth scan line SC5, the first transistor T1 can include multiple sub-transistors connected in parallel. The multiple sub-transistors can be arranged between different pixels PXL.

[0254] Each of the sub-transistors may include a semiconductor layer, a gate electrode overlapping the semiconductor layer, and a first electrode and a second electrode (or source / drain electrode). Figure 12 In the diagram, the gate electrode of the sub-transistor is shown by a dashed line, and the source / drain electrodes are shown by solid lines.

[0255] As referenced above Figure 8A and Figure 8BThe gate electrode of each of the sub-transistors can be connected to the first line forming the first node Q, the first electrode of each of the sub-transistors can be connected to the fifth scan clock line SC_CLK5, and the second electrode of each of the sub-transistors can be connected to the fifth scan line SC5.

[0256] To ensure sufficient capacitance, the first capacitor C1 may include a layer disposed thereon on the gate electrode of the first transistor T1 (e.g., as referenced above). Figure 5 The described gate electrode GE is the same layer as the layer on which the first electrode and the second electrode are formed (e.g., the same layer as the one referenced above). Figure 5 The layers on which the source electrode SE and drain electrode DE are described are the same as those on the layer described above, and / or the layer on which the fifth scan clock line SC_CLK5 is set (e.g., the same as the layer described above). Figure 5 The capacitor electrodes are described on the same layer as the bridging pattern BRP.

[0257] The third transistor T3 of the first output circuit SST2 can be positioned between two pixels PXL. (See reference above.) Figure 8B The gate electrode of the third transistor T3 can be connected to the first line forming the first node Q, the first electrode of the third transistor T3 can be connected to the fifth carry clock line CR_CLK5, and the second electrode of the third transistor T3 can be connected to the fifth carry line CR5. Similarly, the fourth transistor T4 of the first output circuit SST2 can be positioned between two pixels PXL. (Refer to the above...) Figure 8B The gate electrode of the fourth transistor T4 can be connected to the fifth carry clock line CR_CLK5, the second electrode of the fourth transistor T4 can be connected to the first line forming the first node Q, and the first electrode of the fourth transistor T4 can be connected to the fifth carry line CR5.

[0258] The second capacitor C2 may include layers respectively disposed on the gate electrode of the third transistor T3, on which the gate electrode is formed (e.g., as referenced above). Figure 5 The described gate electrode GE is the same layer as the layer thereon, and the first and second electrodes are formed thereon in the same layer (e.g., the same layer as the one referenced above). Figure 5 The capacitor electrodes described are on the same layer as the source electrode SE and the drain electrode DE.

[0259] The fifth carry line CR5 can extend between the node control circuit SST1 and the first output circuit SST2, along the second direction DR2. Regarding the fifth carry line CR5, the first carry line CR1, which is applied with a previous carry signal (e.g., the first carry signal), and the ninth carry line CR9, which is applied with a subsequent carry signal (e.g., the ninth carry signal), can be arranged adjacent to the fifth carry line CR5.

[0260] As described above, the levels can be distributed among pixels PXL at the cell region UA ​​(e.g., in the middle or at the top). Furthermore, to minimize or reduce the number of lines traversing between the node control circuit SST1, the first output circuit SST2, and the second output circuit SST3 within the level, the second output circuit SST3 can be located on one side of the level (e.g., in the middle or at the top), the first output circuit SST2 can be located on the other side of the level (e.g., in the middle or at the top), and the node control circuit SST1 can be located between the first output circuit SST2 and the second output circuit SST3.

[0261] Figure 13 It is shown Figure 9 The display panel includes an example diagram of the levels. Because Figure 9 The dummy classes ST_D1 to ST_D4 shown are identical or substantially identical (or similar) to each other except for their arrangement position, so the first dummy class ST_D1 will be described in more detail below, and redundant descriptions of the other dummy classes can be avoided. Figure 13 The first dummy level ST_D1 shows the (n-7)th level STn-7 and the (n-3)th level STn-3. Furthermore, since the circuit construction of the (n-3)th level STn-3 can be the same as or substantially the same as (or similar to) the circuit construction of the (n-7)th level STn-7, the circuit construction of the (n-7)th level STn-7 is described in more detail below, and redundant descriptions of the (n-3)th level STn-3 are avoided.

[0262] refer to Figure 6 and Figures 9 to 13 The first dummy level ST_D1 can be set between the (n-7)th level STn-7 and the (n-3)th level STn-3.

[0263] The (n-7)th level STn-7 can be distributed at the cell region UA ​​(e.g., in the middle or above) that is traversed (e.g., extended through) by the (n-7th scan line SCn-7 to the (n-4th scan line SCn-4). The (n-3)th level STn-3 can be distributed at the cell region UA ​​(e.g., in the middle or above) that is traversed (e.g., extended through) by the (n-3rd scan line SCn-3). Because the (n-7th level STn-7) (and the (n-3rd level STn-3) are related to the above reference Figure 12 The description of level 5 ST5 is the same as or substantially the same (or similar), so its redundant description need not be repeated. Level n-7 STn-7 can be connected to the first scan clock line SC_CLK1 and the first carry clock line CR_CLK1.

[0264] The first dummy level ST_D1 can be distributed between the (n-7)th level STn-7 and the (n-3)th level STn-3. However, this disclosure is not limited thereto, and the first dummy level ST_D1 can be located in the region corresponding to the (n-4)th scan line SCn-4 (e.g., in the middle or above).

[0265] Similar to level n-7 STn-7, the first dummy level ST_D1 may include a dummy node control circuit, a first dummy output circuit SST2', and a second dummy output circuit SST3'. In this embodiment, the second dummy output circuit SST3' may be omitted.

[0266] The second dummy output circuit SST3' can be arranged adjacent to one side of the first dummy level ST_D1, the first dummy output circuit SST2' can be arranged adjacent to the other side of the first dummy level ST_D1, and the dummy node control circuit can be arranged between the first dummy output circuit SST2' and the second dummy output circuit SST3'.

[0267] Similar to the second output circuit SST3, the second dummy output circuit SST3' may include a first transistor T1, a second transistor T2, and a first capacitor C1 distributed between pixels PXL. The first transistor T1 may be located between the (n-7)th scan line SCn-7 and the (n-6)th scan line SCn-6, and may also be located between the second output circuit SST3 at the (n-7)th level STn-7 and the node control circuit SST1. The second transistor T2 may be located between the (n-5)th scan line SCn-5 and the (n-4)th scan line SCn-4, and may be located adjacent to the first scan clock line SC_CLK1. The first capacitor C1 may be located between the first transistor T1 and the second transistor T2. Because the second dummy output circuit SST3' does not output a scan signal, the first transistor T1 of the second dummy output circuit SST3' may not be connected to a scan line. In an embodiment, the first transistor T1 of the second dummy output circuit SST3' may be formed to have a smaller size (or a smaller channel size) than the size of the second output circuit SST3.

[0268] Similar to the first output circuit SST2, the first dummy output circuit SST2' may include a third transistor T3 and a second capacitor C2 disposed between pixels PXL. The gate electrode of the third transistor T3 may be connected to a first line forming the first node Q of the first dummy stage ST_D1, the first electrode of the third transistor T3 may be connected to the first carry clock line CR_CLK1, and the second electrode of the third transistor T3 may be connected to the first dummy carry line CR_D1. The third transistor T3 may be disposed between the (n-7)th scan line SCn-7 and the (n-6)th scan line SCn-6, and may also be disposed between the first output circuit SST2 of the (n-7)th stage STn-7 and the node control circuit SST1. The second capacitor C2 may be disposed between the (n-6)th scan line SCn-6 and the (n-5)th scan line SCn-5.

[0269] The first dummy carry line CR_D1 can be extended in the second direction DR2, and the first dummy carry signal can be transmitted to the (n-3)th level STn-3.

[0270] The dummy node control circuit can receive the n-3 carry signal from the n-3 carry line CRn-3 branch extending from the n-3rd level STn-3 to the n-7th level STn-7 on the second direction DR2, and can control the node voltage of the first node Q of the first dummy level ST_D1 based on the n-3 carry signal.

[0271] As described above, dummy levels can be set between the last two levels (or the last two levels of the corresponding sub-blocks). Therefore, a separate space (e.g., a non-display area) for arranging dummy levels can be avoided, and the amount of space in the display area DA can be minimized or reduced (e.g., see [reference]). Figure 1 The non-display area outside.

[0272] Figure 14 It is shown Figure 1 A diagram showing an example of a display panel included in a display device. Figure 14 Is with Figure 9 The corresponding diagram.

[0273] refer to Figure 9 and Figure 14 In addition to the first BLK1 and the second BLK2, the gate drive circuit 120 may further include a third BLK3.

[0274] Similar to the first BLK1 and the second BLK2, the third BLK3 can be connected to the scan lines SC1 to SCn included in the display panel 100, and can supply scan signals to the scan lines SC1 to SCn.

[0275] The third BLK3 can include the above reference. Figure 6The description refers to stages ST1 to STn and dummy stages ST_D1 to ST_D4. Because the arrangement and coupling relationships of stages ST1 to STn and dummy stages ST_D1 to ST_D4 in the third BLK3 block are similar to those described above. Figure 9 The arrangement and coupling relationship of stages ST1 to STn in the first block BLK1 described are the same or substantially the same (or similar) to those of the dummy stages ST_D1 to ST_D4, so their redundant description need not be repeated.

[0276] For reference, because the size of the first BLK1 and the second BLK2 is increased, and the first BLK1 and the second BLK2 are distributed in the display area DA of the display panel 100 (e.g., in the middle or at the top), the possibility of increased parasitic capacitance or defects related to other signal lines (e.g., data lines) is high.

[0277] Therefore, the gate drive circuit 120 can be provided with a first BLK1 to a third BLK3, and the first BLK1 to the third BLK3 can be individually inspected for defects during the manufacturing process of the display panel 100 (e.g., whether the scan signal output from the corresponding block is delayed and / or the waveform is changed). Among the first BLK1 to the third BLK3, two blocks BLK1 and BLK2 without defects can be used to drive the display panel 100. For example, for a block among the first BLK1 to the third BLK3 that is not selected (e.g., the third BLK3 where a defect occurs), the transmission line in the corresponding connecting film COF can be cut or disconnected.

[0278] although Figure 14 Three blocks BLK1 to BLK3 are shown arranged in the display panel 100, but this disclosure is not limited thereto. For example, four or more blocks may be arranged in the display panel 100.

[0279] A display device according to one or more embodiments of the present disclosure may include gate driving circuits distributed (e.g., dispersed) at a display area (e.g., in the middle or on top), and clock lines connected to stages included in the gate driving circuits may be distributed (e.g., dispersed) at the display area (e.g., in the middle or on top) and connected to an external device (e.g., a connecting film) via first connection lines disposed between the stages. Therefore, a separate non-display area for setting the gate driving circuits may not be used or necessary, and the non-display area of ​​the display device may be minimized or reduced.

[0280] Furthermore, since clock lines that are applied with clock signals having a 180-degree phase difference can be arranged in pairs, the influence of clock lines placed between pixels on the pixels can be reduced.

[0281] Furthermore, the power lines configured to supply power to the stages can be distributed (e.g., dispersed) using second connection lines disposed between stages, and the second connection lines to which DC power is applied can shield the first connection lines to which clock signals are applied in AC form. Therefore, coupling between the first connection lines and the pixels can be suppressed or prevented.

[0282] Although some exemplary embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made to the exemplary embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it should be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: The substrate including the display area; Pixels in the display area; A grid line located in the display area and connected to the pixel; Carry clock line and scan clock line in the display area; as well as The gate drive circuits are distributed across the display area and connected to the carry clock line, the scan clock line, and the gate lines. The gate drive circuit includes multiple stages, each of which is configured to, in response to a previous carry signal supplied from the previous stage, output a carry clock signal supplied through a corresponding carry clock line among the carry clock lines as a carry signal, and output a scan clock signal supplied through a corresponding scan clock line among the scan clock lines as a scan signal to the corresponding gate line among the gate lines. The corresponding carry clock line and the corresponding scan clock line, which correspond to one of the plurality of levels, are spaced apart from each other, and at least one of the pixels is inserted between the corresponding carry clock line and the corresponding scan clock line.

2. The display device according to claim 1, wherein: The corresponding scan clock line is located on the first side of the stage, and The corresponding carry clock line is located on the second side opposite to the first side of the stage.

3. The display device according to claim 2, wherein, The stage includes a plurality of transistors, and the plurality of transistors are distributed in cell regions corresponding to at least two of the gate lines.

4. The display device according to claim 2, wherein: The carry clock line is adjacent to the previous carry clock line among the carry clock lines in the stages, and the previous carry clock signal, which has a 180-degree phase difference with the carry clock signal, is applied to the previous carry clock line. The scan clock line is adjacent to the previous scan clock line in the stage, and the previous scan clock signal with a 180-degree phase difference from the scan clock signal is applied to the previous scan clock line.

5. The display device according to claim 4, wherein, The level includes: A node control circuit configured to control the first node voltage in response to the previous carry signal; A first output circuit configured to output the carry clock signal as the carry signal in response to the first node voltage; and A second output circuit configured to output the scan clock signal as the scan signal in response to the first node voltage. The first output circuit is adjacent to the second side of the first stage. Wherein, the second output circuit is adjacent to the first side of the first stage, and The node control circuit is located between the first output circuit and the second output circuit.

6. The display device according to claim 5, further comprising: The first power line is located in the display area and connected to the second output circuit; as well as The second power supply line is located in the display area and connected to the first output circuit. The first power line and the second power line are located between the carry clock line and the scan clock line with respect to the stage.

7. The display device according to any one of claims 1-6, wherein: The gate drive circuit further includes a dummy stage; Each of the plurality of stages is configured to be initialized in response to a subsequent carry signal supplied from the subsequent stage, and the subsequent stage is configured to shift the carry signal to output the subsequent carry signal; The last of the plurality of levels is configured to receive the subsequent carry signal from the dummy level; and Compared to the last level, the dummy level is further away from the edge of the display area.

8. The display device according to claim 7, wherein, The dummy level is located between the last two levels among the plurality of levels.

9. The display device according to any one of claims 1-6, wherein: The grid lines extend in a first direction; The carry clock line and the scan clock line extend in the second direction; and In the display area, the gate line intersects with the carry clock line and the scan clock line.

10. The display device according to claim 9, wherein: The multiple levels are divided into sub-blocks along the first direction with respect to the carry clock line; and A portion of the multiple levels is positioned along the first direction.

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