Enhanced gradient seeding scheme during programming operations in memory subsystems

Abstract

The present disclosure relates to an enhanced gradient seeding scheme during a program operation in a memory sub-system. Control logic in a memory device initiates a program operation on a memory array, the program operation including a seeding phase. During the seeding phase, the control logic causes a seed voltage to be applied to strings of memory cells in a data block of the memory array and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, where each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines including a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source side of the first plurality of memory cells in the string of memory cells during the seeding phase, where the second positive voltage is less than the first positive voltage.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to an enhanced gradient seeding scheme during programming operations in a memory subsystem. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a memory device comprising: a memory array; and control logic operably coupled to the memory array to perform operations including: initiating a programming operation on the memory array, the programming operation including a seeding phase; causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation; causing a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell in a first plurality of memory cells in the string of memory cells, the first plurality of word lines including selected word lines associated with the programming operation; and causing a second positive voltage to be applied during the seeding phase to one or more second word lines of one or more second memory cells on the source side of the first plurality of memory cells in the string of memory cells, coupled to one or more second memory cells, wherein the second positive voltage is less than the first positive voltage.

[0004] In another aspect, this disclosure relates to a method comprising: initiating a programming operation on a memory array, the programming operation including a seeding phase; causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation; causing a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell in the first plurality of memory cells of the memory cell string, the first plurality of word lines including selected word lines associated with the programming operation; and causing a second positive voltage to be applied during the seeding phase to one or more second word lines on the source side of the first plurality of memory cells in the memory cell string coupled to one or more second memory cells, wherein the second positive voltage is less than the first positive voltage.

[0005] In another aspect, this disclosure relates to a memory device comprising: a first memory cell string in a first sub-block of a memory cell block, the first sub-block including a selected sub-block, wherein the first memory cell string includes a first plurality of memory cells coupled to a plurality of word lines; and a second memory cell string in a second sub-block of the memory cell block, the second sub-block including a non-selected sub-block, wherein the second memory cell string includes a second plurality of memory cells coupled to the plurality of word lines coupled to the first memory cell string, wherein a first subset of the plurality of word lines is configured to receive a first positive voltage signal during a seeding phase of a programming operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of the first subset of the second plurality of memory cells in the second memory cell string, the first subset of the plurality of word lines including a selected word line associated with the programming operation, and wherein one or more second word lines are configured to receive a second positive voltage signal during the seeding phase of the programming operation, wherein the one or more second word lines are coupled to one or more of the second plurality of memory cells on the source side of the first subset of the second plurality of memory cells in the second memory cell string. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2A This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2B This is a schematic diagram illustrating a string of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 3 This is a timing diagram of the operation of a memory device during the seeding phase of a programming operation, according to some embodiments of the present disclosure.

[0011] Figure 4 This is a diagram illustrating the channel potential of a string of memory cells during the seeding phase of a programming operation according to some embodiments of the present disclosure.

[0012] Figure 5 This is a flowchart of an example method for implementing an enhanced gradient seeding scheme during programming operations in a memory subsystem according to some embodiments of the present disclosure.

[0013] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] This disclosure relates to an enhanced gradient seeding scheme during programming operations in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may contain high-density non-volatile memory devices in which data needs to be retained when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a data block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. Each data block may contain several sub-blocks, each sub-block being defined by a set of associated pillars (e.g., one or more vertical conductive traces) extending from a shared bit line. A memory page (also referred to herein as a “page”) stores one or more bits of binary data corresponding to data received from the host system. To achieve high density, strings of memory cells in non-volatile memory devices can be configured to comprise several memory cells comprising pillars that at least partially surround a channel material. The memory cells can be coupled to access lines, often referred to as "word lines," which are typically fabricated together with the memory cells to form a string array within a memory block. The compactness of some non-volatile memory devices, such as 3D flash NAND memory, means that word lines are common to many memory cells within a memory block.

[0016] During a programming operation, selected memory cells are programmed by applying a programming voltage to a selected word line. Because the word line is common to multiple memory cells, non-selected memory cells may experience the same programming voltage as the selected memory cells. If not otherwise preprocessed, non-selected memory cells may be affected by the programming voltage on the common word line. These programming voltage effects can include conditions that store charge in non-selected memory cells intended to retain stored data. This programming voltage effect is called a "programming perturbation" or "programming interference" effect. Programming interference effects may render the charge stored in non-selected memory cells completely unreadable, or, although still appearing readable, the contents of the memory cells may be read as data values ​​different from the expected data values ​​stored before the programming voltage was applied.

[0017] The presence of residual electrons, such as those captured or otherwise retained within the polysilicon channel of the charge storage structure after earlier operations (e.g., previous programming operations), can cause programming interference effects. At the end of a programming verification operation, for example, the pass voltage (Vpass) applied to the unprogrammed word lines slopes down, and word lines with high threshold voltages on the source side are cut off before those with lower threshold voltages. Therefore, electrons are captured within the polysilicon channel at the word lines with lower threshold voltages (i.e., between the cut word lines) and become residual electrons. Since the polysilicon channels (i.e., columnar channel regions) in some non-volatile memory devices are floating channels that may not be connected to a block ground body, there is typically no path for residual electrons in the channel region to discharge except by discharging to the source of the memory string. Some programming operations typically include a seeding phase, in which a seed voltage (e.g., 2 volts) is applied across the string, and a ground voltage (e.g., 0 volts) is applied to all word lines intersecting the string, including selected word lines. Using a ground voltage during the seeding phase keeps the source-side word line open, and residual electrons remain trapped on the source side of the selected word line at the end of the seeding phase. These residual electrons can cause programming interference in several ways. For example, when the pass voltage or programming voltage ramps up in subsequent programming operations, the selected word line may be affected by hot electrons (“hot e”), where a large voltage difference between the gate and source causes residual electrons to be injected from the drain depletion region into the floating gate. Additionally, this voltage difference can induce an electrostatic field of sufficient magnitude to alter the charge on the selected word line, causing the contents of the memory cell to be unintentionally programmed or erroneously read. Furthermore, the electrostatic field may generate localized electron-hole pairs in the channel region, creating more electrons that can be injected into the selected word line.

[0018] This disclosure addresses the above and other drawbacks by implementing an enhanced gradient seeding scheme during programming operations in a memory subsystem. In one embodiment, control logic of a memory device in the memory subsystem initiates a programming operation on the memory device, such that a seeding voltage is applied to a string of memory cells in a data block of the memory device during the seeding phase of the programming operation, and a first positive voltage is applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell in the first plurality of memory cells in the string, and the first plurality of word lines include a selected word line associated with the programming operation. The control logic further causes a second positive voltage to be applied during the seeding phase to one or more second word lines coupled to one or more second memory cells on the source side of the first plurality of memory cells in the string. In one embodiment, this second positive voltage is less than the first positive voltage. Because the second positive voltage is less than the first positive voltage, a less abrupt potential gradient exists in the word lines descending along the string away from the selected word lines. This reduces the electron potential barrier at those memory cells coupled to the corresponding word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and toward the drain side of the string. Therefore, most (if not all) of the residual electrons can be removed from the channels of the string during the seeding stage, so that when a high programming voltage is subsequently applied to the selected word line, the residual electrons are not present and will not be injected into the selected word line.

[0019] Additionally, at the end of the seeding phase, the corresponding voltages applied to the various word lines are ramped down before the programming voltage is applied. In one embodiment, the control logic causes a first positive voltage applied to a selected word line and at least one adjacent word line on the source side to ramp down to an intermediate voltage (i.e., less than the first positive voltage but greater than ground), while the remaining word lines ramp down to ground. This prevents the channel from being cut off and thus retains residual electron flow from the channel to the drain, further reducing the injection of those electrons into the selected word line during subsequent programming operations. Furthermore, the control logic can cause the corresponding bias voltages applied to the word lines coupled to one or more non-active memory cells in the string to ramp down to ground after a delay period at the end of the seeding phase. In one embodiment, the delay period includes a time period after the first positive voltage has ramped down to at least one of the intermediate voltage or ground. This prevents the channel potential from becoming negative and retains the benefits gained during the seeding phase. Therefore, when using the techniques described herein, programming interference effects can be significantly reduced, thereby improving the programming performance of memory devices in the memory subsystem.

[0020] Figure 1This section describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device containing memory and processing power.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and write-in-place memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can perform bit storage based on variations in volume resistance by combining a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages that refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0036] In one embodiment, memory device 130 includes a memory device programming management component 113 that can monitor, control, and / or manage data access operations, such as programming operations, performed on the non-volatile memory device (e.g., memory device 130) of memory subsystem 110. For example, a programming operation may include several phases, such as a seeding phase, a pass voltage ramping phase, a programming voltage ramping phase, and a programming recovery phase. A programming verification operation, including a programming verification phase and a programming verification recovery phase, may follow the programming operation, subsequently initiating a subsequent programming operation. The programming management component 113 is responsible for ensuring that certain voltages are applied (or indicating which voltages are applied) to memory device 130 during the programming operation. In some types of memory devices, such as devices configured with QLC memory, multi-pass programming algorithms can be used. In a multi-pass programming algorithm, memory cells coupled to one or more word lines of a selected string are initially programmed to coarse values ​​in a first pass, and then reprogrammed to more finely tuned values ​​in a second pass. The seeding phase of this programming operation typically involves a general increase in the channel voltage of the suppressed strings (i.e., strings to which memory cells are not programmed) in memory device 130 to counteract programming interference caused by the use of high-voltage programming pulses. The seeding voltage applied to the strings (e.g., on the bit lines) couples the source, drain, and channel of the strings at a higher voltage level, thus better suppressing programming interference. Because a relatively high voltage is applied during the programming voltage ramp-up phase, the programming recovery phase allows the device to recover from the high-voltage mode. Generally, during the programming recovery phase, all signals ramp down to a lower voltage level.

[0037] In one embodiment, the programming management component 113 causes a word line driver to apply a seeding voltage to a string of memory cells in a data block of the memory device 130 during the seeding phase of a programming operation, and causes the word line driver to apply a series of positive voltages to the word lines of the data block during the seeding phase. Each of those word lines is coupled to a corresponding memory cell in the string. In one embodiment, a first number of the word lines are biased at a high bias voltage (e.g., 3 to 5 V) to help turn on the corresponding memory cells during the seeding phase, allowing trapped residual electrons to flow out of the channel. Those word lines may include at least one word line adjacent to a selected word line on the drain side of the channel (i.e., a word line previously programmed using a coarse data pattern as part of a multi-pass programming algorithm). Failure to bias this word line may cause the coarse data pattern to hinder seeding on the string. Additionally, the programming management component 113 may cause the word line driver to apply a lower bias voltage to other word lines of the data block (i.e., those word lines adjacent to word lines that receive a high bias voltage on the source side of the memory string). These lower bias voltages can be "gradually reduced" (i.e., gradually approaching ground voltage as the word line moves further away from the selected word line) to smooth the potential gradient along the channel.

[0038] Additionally, before applying the programming voltage, the programming management component 113 ramps down the seed voltage and word line bias voltage at the end of the seeding phase. In one embodiment, the programming management component 113 ramps down the high bias voltage applied to the selected word line and at least one adjacent word line on the source side to an intermediate voltage (i.e., less than the first positive voltage but greater than the ground voltage), while the remaining word lines ramp down to the ground voltage. This prevents the channel from being cut off and thus retains residual electron flow from the channel to the drain, and further reduces the injection of those electrons into the selected word line during subsequent programming operations. Furthermore, the programming management component 113 may cause the corresponding bias voltage applied to the word lines coupled to one or more non-active memory cells in the string to ramp down to the ground voltage after a delay period at the end of the seeding phase. In one embodiment, the delay period includes a time period after the first positive voltage has ramped down to at least one of the intermediate voltage or the ground voltage. Further details regarding the operation of the programming management component 113 are described below.

[0039] In some embodiments, the memory subsystem controller 115 includes at least a portion of the programming management component 113. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the programming management component 113 is part of the host system 110, application programming, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the programming management component 113 and is configured to perform the functionality described herein. In such embodiments, the programming management component 113 may be implemented using hardware or as firmware, stored on the memory device 130, and executed by control logic (e.g., the programming management component 113) to perform operations related to the enhanced gradient seeding scheme described herein.

[0040] Figure 2A The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1 A simplified block diagram of communication between a second device and a memory subsystem controller 115 (of the memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0041] Memory device 130 includes a memory cell array 204 logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 204 ( Figure 2A (Not shown in the text) can be programmed to be one of at least two target data states.

[0042] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode the address signals. Address signals are received and decoded to access the memory cell array 204. The memory device 130 also includes an input / output (I / O) control circuitry 260 for managing inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. Address register 214 communicates with I / O control circuitry 260, row decoding circuitry 208, and column decoding circuitry 210 to latch the address signals before decoding. Command register 224 communicates with I / O control circuitry 260 and local media controller 135 to latch incoming commands.

[0043] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 204 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses. In one embodiment, the local media controller 134 includes a programming management component 113 that can implement the enhanced gradient seeding scheme described herein during programming operations on memory device 130.

[0044] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data according to the boot command of the local media controller 135 to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 270 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry system 260 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry system 260 for output to memory subsystem controller 115; then, new data can be transferred from data register 270 to cache register 218. Cache register 218 and / or data register 270 may form a page buffer of memory device 130 (e.g., may form a portion thereof). The page buffer may further include sensing devices (in...) Figure 2A(Not shown in the diagram) The status register 222 can sense the data status of the memory cells, for example, by sensing the status of the data lines connected to the memory cells of the memory cell array 204. The status register 222 can communicate with the I / O control circuitry system 260 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0045] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 236, and outputs data to memory subsystem controller 115 via I / O bus 236.

[0046] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 236 at the I / O control circuitry system 260, and then written to the command register 224. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 236 at the I / O control circuitry system 260, and then written to the address register 214. Data can be received via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices at the I / O control circuitry system 260, and then written to the cache register 218. Data can then be written to the data register 270 for programming the memory cell array 204.

[0047] In one embodiment, cache register 218 may be omitted, and data may be written directly to data register 270. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0048] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 2A The memory device 130. It should be understood that, reference Figure 2A The functionality of the various block components described may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2A The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2A The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0049] Figure 2B This is a schematic diagram illustrating a string 200 of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, string 200 represents a portion of memory device 130, such as a portion from memory cell array 204, as... Figure 2A As shown in the diagram. String 200 includes a plurality of memory cells 212 (i.e., charge storage devices), for example, up to 32 memory cells (or more) in some embodiments. String 200 includes a source-side select transistor, referred to as source-select gate 220 (SGS) (typically an n-channel transistor), coupled between the memory cells 212 and a common source 226 at one end of string 200. The common source 226 may comprise, for example, a co-doped semiconductor material and / or other conductive material. At the other end of string 200, a drain-side select transistor, referred to as drain-select gate 230 (SGD) (typically an n-channel transistor), and a gate-induced drain leakage (GIDL) generator 240 (GG) (typically an n-channel transistor) are coupled between one of the memory cells 212 and a data line 234, which is typically referred to in the art as a “bit line”. The common source 226 can be coupled to a reference voltage (e.g., ground voltage or simply "ground" [Gnd]) or a voltage source (e.g., a charge pump circuit or power supply, which may be selectively configured to, for example, a specific voltage suitable for optimizing programming operations).

[0050] Each memory cell 212 may include, for example, a floating gate transistor or a charge trapping transistor, and may include a single-level memory cell or a multi-level memory cell. The floating gate may be referred to as charge storage structure 235. The memory cell 212, source-select gate 220, drain-select gate 230, and GIDL generator 240 may be controlled by signals on their respective control gates 250.

[0051] Control signals may be applied by or directed by the programming management component 113, for example, applied to a select line (not shown) to select a string, or applied to an access line (not shown) to select a memory cell 212. In some cases, control gates may form part of a select line (for selecting a device) or an access line (for a cell). Drain select gate 230 receives a voltage that causes drain select gate 230 to select or deselect string 200. In one embodiment, each corresponding control gate 250 is connected to a separate word line (i.e., an access line) so that each device or memory cell can be controlled individually. String 200 may be one of a plurality of memory cell strings in a block of memory cells in memory device 130. For example, when a plurality of memory cell strings exist, each memory cell 212 in string 200 may be connected to a corresponding shared word line, and a corresponding memory cell in each of the plurality of strings is also connected to the corresponding shared word line. Therefore, if a selected memory cell in one of the plurality of strings is being programmed, the corresponding non-selected memory cell 212 in string 200 connected to the same word line as the selected cell may experience the same programming voltage, potentially causing programming interference. Therefore, in one embodiment, the programming management component 113 causes the word line driver to apply a seed voltage to bit line 234 during the seeding phase of the programming operation, and causes two or more positive voltages to be applied during the seeding phase to word lines of certain control gates 250 connected to the devices and / or cells 212 in string 200. As described herein, these voltages may include high bias voltages and gradually decrease to lower bias voltages in an incremental manner depending on the word line to which they are applied. Thus, most (if not all) of the residual electrons can be cleared from the channels of string 200 during the seeding phase, such that when a high programming voltage is subsequently applied to the selected word line, the residual electrons are absent and not injected into the selected word line.

[0052] Figure 3 This is a timing diagram 300 of the operation of a memory device during the seeding phase of a programming operation, according to some embodiments of the present disclosure. During a programming operation performed on a non-volatile memory device (e.g., memory device 130), certain phases may be encountered, including a seeding phase (which is typically followed by a programming phase) and a programming verification phase. The seeding phase typically involves an overall increase in the channel voltage of the suppressed string in memory device 130 to counteract programming interference caused by the use of a high-voltage programming pulse. During subsequent phases, a pass voltage (Vpass) is applied to the word line of memory device 130 to further increase the channel voltage of the associated channel, and a programming voltage is applied to a selected word line (e.g., WLn) of memory device 130 to program a certain level of charge to selected memory cells on the word line representing a desired value.

[0053] Timing diagram 300 illustrates various sub-stages of the seeding phase of a programming operation according to one embodiment. In this embodiment, different signals are applied to various means in the memory device 130 in each of the illustrated sub-stages. During sub-stage 310, programming management component 113 causes a signal 301 having a seeding voltage (e.g., 3 volts) to be applied to bit line 234 of string 200. In one embodiment, programming management component 113 sends a signal to word line driver (or some other component) instructing the driver to apply signal 301 to bit line 234. Signal 301 may remain at the seeding voltage throughout the entire seeding operation encompassing all sub-stages 310, 320, and 330. After sub-stage 330, signal 301 returns to ground voltage (e.g., 0V). During sub-phase 310, programming management component 113 further causes signal 302 to be applied to drain-select gate 230, and signal 303 (e.g., 3 to 4V) to be applied to one or more inactive word lines (e.g., "virtual" word lines coupled to means in string 200 not used for storing data). Signal 302 (e.g., 5V) activates drain-select gate 230 (e.g., "turns it on"), thereby allowing seed voltage to flow from bit line 234 through drain-select gate 230 to various data word lines connected to string 200. In one embodiment, data word lines include one or more word lines connected to the remaining memory cells 212 of string 200. These cells 212 are typically used to store data, such as data from host system 120. Signals 302 and 303 remain high during sub-phase 320, and programming management component 113 causes signals 302 and 303 to return to ground voltage during sub-phase 330. Therefore, compared to the case when other signals (e.g., signals 305 to 307) ramp down, signals 302 and 303 ramp down after a delay period (e.g., the length of sub-stage 320). In one embodiment, the length of the delay period is sufficient to allow those other signals to stabilize to at least one of an intermediate voltage (e.g., 1 to 4 V) or ground voltage before signals 302 and 303 ramp down.

[0054] In one embodiment, programming management component 113 causes a signal 304 having a ground voltage (i.e., 0V) to be applied to certain word lines of string 200 during the seeding phase. For example, programming management component 113 may cause signal 304 to be applied to word line (WLn+2) and above, which is above selected word line (WLn) in string 200 throughout sub-phases 310, 320, and 330.

[0055] In one embodiment, the programming management component 113 may cause a positive voltage to be applied to certain word lines of string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212. The positive voltage reduces the electron barrier at said certain word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and toward the drain (i.e., bit line 234). As illustrated in timing diagram 300, during sub-phase 310, the programming management component 113 may cause a signal 305 with a positive voltage (e.g., 3 to 5 V) to be applied to a selected word line (i.e., the word line being programmed (WLn)) and at least one word line (WLn+1) above the selected word line in the string (i.e., the word line located between WLn and the drain select gate 230). This positive voltage ensures that the channel potential is primarily determined by the seeding voltage (e.g., 3 V). This higher channel potential creates a significant drain-induced barrier reduction (DIBL) effect on the adjacent source-side word lines (i.e., the immediately following word lines down the string (WLn-1 and WLn-2)), allowing more residual electrons to flow to the drain side. During sub-phase 320, the programming management component 113 causes signal 305 to ramp down to an intermediate voltage (e.g., 1 to 4 V). This intermediate voltage can be any voltage lower than the high voltage applied during sub-phase 310 and the ground voltage. Additionally, the programming management component 113 can cause signal 306 with a positive voltage (e.g., 3 to 5 V) to be applied to the adjacent source-side word lines (i.e., WLn-1 and WLn-2). This positive voltage also reduces the electron barrier in these word lines. During sub-phase 320, the programming management component 113 causes signal 306 to ramp down to ground voltage (e.g., 0 V). In one embodiment, the programming management component 113 can cause different voltages to be applied to WLn-1 and WLn-2. For example, a higher voltage can be applied to WLn-1 and a lower voltage can be applied to WLn-2 because WLn-1 receives more threshold voltage reduction due to the DIBL effect than WLn-2. In another embodiment, the same voltage can be applied to both WLn-1 and WLn-2.

[0056] In one embodiment, the programming management component 113 causes a signal 307 having a positive voltage (e.g., 2 to 4 V) to be applied to the next source-side word line (i.e., WLn-3), and causes a signal 308 having a positive voltage (e.g., 1 to 2 V) to be applied to the next source-side word line (i.e., WLn-4). These positive voltages also reduce the electron barrier in these word lines. As illustrated, each subsequent voltage is lower than the previous voltage, causing the voltage to gradually decrease (i.e., gradually approaching ground voltage as the word line moves further away from the selected word line WLn) to smooth the potential gradient along the channel. During sub-phase 320, the programming management component 113 causes signals 307 and 308 to slope down to ground voltage (e.g., 0 V). In one embodiment, the programming management component 113 causes a signal 309 having a ground voltage (i.e., 0 V) ​​to be applied to the remaining word lines in string 200 (WLn5 and below) and to the source-select gate 220 throughout sub-phases 310, 320, and 330. It should be understood that the specific voltage levels described herein are merely examples, and different voltage levels may be used in other embodiments. In another embodiment, when programming from the source side to the drain side, the orientation of the string as described above is reversible, such that the word line voltage gradually decreases as the word line moves further away from the selected word line WLn and toward the drain.

[0057] Figure 4 This is a diagram illustrating the channel potential 400 of a string of memory cells during the seeding phase of a programming operation according to some embodiments of the present disclosure. In one embodiment, string 200 corresponds to... Figure 2B The string 200 described herein, and the seeding scheme used corresponds to Figure 3The timing diagram 300 is illustrated above. As described above, string 200 includes a drain-select-gate (SGD) device and several memory cells, each connected to a separate word line (WL). In one embodiment, one or more of the memory cells are connected to inactive or “virtual” word lines (DWL) and are not typically used for storing data. At least one of the memory cells in string 200 may be connected to a selected word line (i.e., the word line being programmed (WLn)), and each of the remaining memory cells on the source side of the selected word line may be connected to a word line referred to as a data word line (WLn-1, WLn-2, ​​...). In one embodiment, one or more memory cells connected to word lines (e.g., WLn+1, WLn+2, ...) may be present on the drain side of the selected word line, which may be a virtual word line or a data word line. Depending on the embodiment, any number of data word lines may be present. In one embodiment, string 200 represents an unselected sub-block of a data block of memory cells in memory device 130. As described above, a data block may include additional sub-blocks with additional memory cell strings. For example, string 450 may represent a selected sub-block of the same data block and may similarly include several memory cells and / or other devices coupled to the same word lines as the corresponding memory cells and / or other devices of string 200.

[0058] In one embodiment, each device in string 200 has an associated threshold voltage (Vt), which represents the voltage at which each device switches from an "off" state to an "on" state, or from an "on" state to an "off" state. For example, a drain-select-gate device (SGD) may have a threshold voltage of 3V, a memory cell connected to a virtual word line (DWL) may have a threshold voltage of -1V, WLn+2 and the selected word line WLn may have a threshold voltage of -2V, memory cells connected to WLn-1 to WLn-4 may have threshold voltages between -2V and 5V, and a memory cell connected to WLn-5 may have a threshold voltage of 5V. In one embodiment, the channel potential 400 of string 200 represents the difference between the voltage applied at the control gate of each device (i.e., the gate voltage (Vg)) and a representative threshold voltage. In one embodiment, a first representative threshold voltage exists on the drain side of the selected word line (WLn), and a second representative threshold voltage exists on the source side of the selected word line (WLn). Each representative threshold voltage can be the highest threshold voltage on the drain side and the source side, respectively. Therefore, in the illustrated embodiment, the first representative threshold voltage on the drain side can be -2V associated with the memory device connected to WLn+2, and the second representative threshold voltage on the source side can be 5V associated with the memory devices connected to WLn-1 and WLn-2.

[0059] As mentioned above Figure 3As described, in one embodiment, the programming management component 113 allows different voltage signals to be applied to the gate terminals of different devices during the seeding phase of the programming operation. These voltage signals may be referred to as corresponding gate voltages (Vg). Figure 4 As described, in one embodiment, the programming management component 113 may cause a positive voltage to be applied to certain word lines of the string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212. For example, the programming management component 113 may cause a first positive voltage (e.g., 5V) to be applied to a selected word line (i.e., WLn), at least one word line above the selected word line in the string (e.g., WLn+1), and at least one word line below the selected word line in the string (e.g., WLn-1, WLn-2). The programming management component 113 may further cause a second positive voltage (e.g., 3V) to be applied to at least one data word line on the source side (e.g., WLn-3), and cause a third positive voltage (e.g., 1V) to be applied to at least one additional data word line on the source side (e.g., WLn-4). These positive voltages reduce the electronic barrier at the corresponding memory cell, thereby allowing any residual electrons 420 trapped on the source side to flow through the barrier and to the drain (i.e., bit line 234).

[0060] Figure 5 This is a flowchart illustrating an example method of implementing an enhanced gradient seeding scheme during programming operations in a memory subsystem according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The programming management component 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 505, a programming operation is initiated. For example, processing logic (e.g., processor 117 or local media controller 135) may initiate a programming operation on a memory device (e.g., memory device 130). In one embodiment, the programming operation includes a seeding phase, a programming phase, and a programming verification phase. In some embodiments, each of these phases may be repeated multiple times in a loop during a single programming operation. The seeding phase typically involves an overall increase in the channel voltage of the suppressed string in memory device 130 to counteract programming interference caused by the use of high-voltage programming pulses.

[0062] At operation 510, a seed voltage is applied to the string of memory cells. For example, the processing logic may cause the seed voltage to be applied to the string of memory cells in the data block of the memory device during the seeding phase of a programming operation. During the seeding phase, the programming management component 113 causes a signal 301 having a seed voltage (e.g., 3 volts) to be applied to bit line 234 of string 200. Signal 301 may be maintained at the seed voltage throughout the seeding phase. In one embodiment, the seed voltage is higher than the seed voltage used in the seeding phase of other programming operations in order to increase the channel potential of string 200.

[0063] At operation 515, a positive voltage is applied to certain word lines. For example, the processing logic may cause a first positive voltage to be applied to a first plurality of word lines of a data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell in a first plurality of memory cells in a string of memory cells, the first plurality of word lines including selected word lines associated with a programming operation. In one embodiment, the programming management component 113 may cause the first positive voltage to be applied to certain word lines of string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212. For example, in one embodiment, the programming management component 113 may cause a first positive voltage to be applied to one or more third word lines (e.g., WLn+1) coupled to the drain side of a first memory cell in a memory cell string, to a selected word line (i.e., WLn), and to one or more fourth word lines (e.g., WLn-1 and WLn-2) coupled to the source side of a first memory cell in a memory cell string. The first positive voltage may reduce the electronic barrier at those word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and toward the drain (i.e., bit line 234).

[0064] At operation 520, a positive voltage is applied to certain word lines. For example, the processing logic may cause a second positive voltage to be applied during the seeding phase to one or more second word lines of one or more second memory cells coupled to one or more second memory cells on the source side of a first plurality of memory cells in the memory cell string, wherein the second positive voltage is less than the first positive voltage. In one embodiment, the programming management component 113 may cause a second positive voltage to be applied to certain word lines of string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212. For example, in one embodiment, the programming management component 113 may cause a second positive voltage to be applied to one or more second word lines (e.g., WLn-3). The second positive voltage may reduce the electron potential barrier at those word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234), but because the second positive voltage is less than the first positive voltage, it will smooth the potential gradient.

[0065] At operation 525, a positive voltage is applied to certain word lines. For example, the processing logic may cause a third positive voltage to be applied during the seeding phase to one or more fifth word lines of one or more third memory cells coupled to the source side of one or more second memory cells in the memory cell string, wherein the third positive voltage is less than the second positive voltage. In one embodiment, the programming management component 113 may cause a third positive voltage to be applied to certain word lines of string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212. For example, in one embodiment, the programming management component 113 may cause a third positive voltage to be applied to one or more fifth word lines (e.g., WLn-4). The third positive voltage reduces the electron barrier at those word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234), but because the third positive voltage is less than the first and second positive voltages, it smooths the potential gradient.

[0066] At operation 530, a ground voltage is applied to certain word lines. For example, the processing logic may cause the ground voltage to be applied to a second plurality of word lines of a data block during the seeding phase, wherein each of the second plurality of word lines is coupled to a corresponding memory cell in a second plurality of memory cells in a string, wherein the second plurality of memory cells are adjacent to one or more third memory cells on the source side of the memory cell string. In one embodiment, the programming management component 113 may cause the ground voltage to be applied to certain word lines of string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212. For example, in one embodiment, the programming management component 113 may cause the ground voltage to be applied to a second plurality of word lines (e.g., WLn-5 and below).

[0067] At operation 535, a corresponding bias voltage is applied to certain word lines. For example, the processing logic may cause the corresponding bias voltage to be applied during the seeding phase to word lines coupled to one or more non-active memory cells on the drain side of a first plurality of memory cells in the select gate device and memory cell string. In one embodiment, the programming management component 113 may cause the corresponding bias voltage to be applied to certain word lines of string 200 during the seeding phase, wherein a positive voltage may be experienced at the control gate 250 of the corresponding memory cell 212 or device. For example, in one embodiment, the programming management component 113 may cause the corresponding bias voltage to be applied to word lines coupled to the select gate device (SGD) and to any word lines coupled to non-active memory cells (e.g., "virtual" word lines). Depending on the embodiment, the corresponding bias voltages may have the same or different values.

[0068] At operation 540, the voltage applied to certain word lines is ramped down. For example, the processing logic may cause a first positive voltage applied to selected word lines and one or more third word lines to ramp down to an intermediate voltage at the end of the seeding phase, wherein the intermediate voltage is less than the first positive voltage and greater than the ground voltage. In one embodiment, the programming management component 113 may cause a first positive voltage applied to certain word lines of string 200 during the seeding phase to ramp down to an intermediate voltage. For example, in one embodiment, the programming management component 113 may cause a first positive voltage to be applied to selected word lines (i.e., WLn) and one or more third word lines (e.g., WLn+1) to ramp down to an intermediate voltage (e.g., 1 to 4V).

[0069] At operation 545, the voltage applied to certain word lines is ramped down. For example, the processing logic may cause a first positive voltage applied to one or more fourth word lines, a second positive voltage applied to one or more second word lines, and a third positive voltage applied to one or more fifth word lines to ground at the end of the seeding phase. In one embodiment, the programming management component 113 may cause the first, second, and third positive voltages applied to certain word lines of string 200 during the seeding phase to ramp down to ground. For example, in one embodiment, the programming management component 113 may cause a first positive voltage applied to one or more fourth word lines (e.g., WLn-1 and WLn-2), a second positive voltage applied to one or more second word lines (e.g., WLn-3), and a third positive voltage applied to one or more fifth word lines (e.g., WLn-4) to ramp down to ground (e.g., 0V).

[0070] At operation 550, the voltage applied to certain word lines is ramped down. For example, the processing logic may cause the corresponding bias voltage applied to word lines coupled to the select gate device and one or more non-active memory cells to ramp down to ground after a delay period at the end of the seeding phase, wherein the delay period includes a time period after at least one of the first positive voltage, the second positive voltage, and the third positive voltage has ramped down to an intermediate voltage or ground. In one embodiment, the programming management component 113 may cause the corresponding bias voltage applied to certain word lines of string 200 during the seeding phase to ramp down to ground after the delay period. For example, in one embodiment, the programming management component 113 may cause the corresponding bias voltage applied to word lines coupled to the select gate device (i.e., SGD) and coupled to any non-active memory cell (e.g., virtual word line) to ramp down to ground (e.g., 0V) after the delay period.

[0071] Figure 6 An example machine is described as representing computer system 600, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the programming management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0072] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0073] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0074] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0075] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more instruction sets 626 or software embodying any one or more of the methods or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage media. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0076] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The programming management component 113 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0077] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0078] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0079] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0080] The algorithms and demonstrations presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0081] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0082] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: Memory array; as well as Control logic, which is operatively coupled to the memory array, performs operations including the following: A programming operation is initiated on the memory array, the programming operation including a seeding phase; This causes the seeding voltage to be applied to the string of memory cells in the data block of the memory array during the seeding phase of the programming operation; A first positive voltage is applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell in a first plurality of memory cells in the memory cell string, the first plurality of word lines including a selected word line associated with the programming operation, at least one word line adjacent to the selected word line on the drain side of the selected word line, and at least one word line adjacent to the selected word line on the source side of the selected word line. as well as A second positive voltage is applied during the seeding phase to the source side of the first plurality of memory cells in the memory cell string and coupled to one or more second word lines of one or more second memory cells, wherein the second positive voltage is less than the first positive voltage.

2. The memory device of claim 1, wherein the selected word line is coupled to a first memory cell among the first plurality of memory cells, and wherein the first plurality of word lines for which the first positive voltage is applied to the data block comprises: This causes the first positive voltage to be applied to the drain side of the first memory cell in the memory cell string and coupled to one or more third word lines of the first plurality of memory cells.

3. The memory device of claim 2, wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises: This causes the first positive voltage to be applied to the source side of the first memory cell in the memory cell string and coupled to one or more fourth word lines of the first plurality of memory cells.

4. The memory device of claim 3, wherein the control logic is configured to perform operations further comprising: A third positive voltage is applied during the seeding phase to the source side of one or more second memory cells in the memory cell string and coupled to one or more fifth word lines of one or more third memory cells, wherein the third positive voltage is less than the second positive voltage.

5. The memory device of claim 4, wherein the control logic is configured to perform operations further comprising: This causes a ground voltage to be applied to a second plurality of word lines of the data block during the seeding phase, each of the second plurality of word lines being coupled to a corresponding memory cell in a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to one or more third memory cells on the source side of the string of memory cells.

6. The memory device of claim 5, wherein the control logic is configured to perform operations further comprising: This causes a corresponding bias voltage to be applied during the seeding phase to word lines coupled to one or more inactive memory cells on the drain side of the first plurality of memory cells in the select gate device and the memory cell string.

7. The memory device of claim 6, wherein the control logic is configured to perform operations further comprising: The first positive voltage applied to the selected word line and to the one or more third word lines is reduced to an intermediate voltage at the end of the seeding phase, wherein the intermediate voltage is less than the first positive voltage and greater than the ground voltage; and The first positive voltage applied to the one or more fourth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more fifth word lines are reduced to the ground voltage at the end of the sowing phase.

8. The memory device of claim 7, wherein the control logic is configured to perform operations further comprising: The corresponding bias voltage applied to the word line coupled to the select gate device and the one or more non-active memory cells is sloped down to the ground voltage after a delay period at the end of the seeding phase, wherein the delay period includes a time period after the first positive voltage, the second positive voltage and the third positive voltage have sloped down to at least one of the intermediate voltage or the ground voltage.

9. A method for a memory device, comprising: Initiating a programming operation on a memory array, the programming operation including a seeding phase; This causes the seeding voltage to be applied to the string of memory cells in the data block of the memory array during the seeding phase of the programming operation; A first positive voltage is applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell in a first plurality of memory cells in the memory cell string, the first plurality of word lines including a selected word line associated with the programming operation, at least one word line adjacent to the selected word line on the drain side of the selected word line, and at least one word line adjacent to the selected word line on the source side of the selected word line. as well as A second positive voltage is applied during the seeding phase to the source side of the first plurality of memory cells in the memory cell string and coupled to one or more second word lines of one or more second memory cells, wherein the second positive voltage is less than the first positive voltage.

10. The method of claim 9, wherein the selected word line is coupled to a first memory cell among the first plurality of memory cells, and wherein the first plurality of word lines for which the first positive voltage is applied to the data block comprises: This causes the first positive voltage to be applied to the drain side of the first memory cell in the memory cell string and coupled to one or more third word lines of the first plurality of memory cells.

11. The method of claim 10, wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises: This causes the first positive voltage to be applied to the source side of the first memory cell in the memory cell string and coupled to one or more fourth word lines of the first plurality of memory cells.

12. The method of claim 11, further comprising: A third positive voltage is applied during the seeding phase to the source side of one or more second memory cells in the memory cell string and coupled to one or more fifth word lines of one or more third memory cells, wherein the third positive voltage is less than the second positive voltage.

13. The method of claim 12, further comprising: This causes a ground voltage to be applied to a second plurality of word lines of the data block during the seeding phase, each of the second plurality of word lines being coupled to a corresponding memory cell in a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to one or more third memory cells on the source side of the string of memory cells.

14. The method of claim 13, further comprising: This causes a corresponding bias voltage to be applied during the seeding phase to word lines coupled to one or more inactive memory cells on the drain side of the first plurality of memory cells in the select gate device and the memory cell string.

15. The method of claim 14, further comprising: The first positive voltage applied to the selected word line and to the one or more third word lines is reduced to an intermediate voltage at the end of the seeding phase, wherein the intermediate voltage is less than the first positive voltage and greater than the ground voltage; as well as The first positive voltage applied to the one or more fourth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more fifth word lines are reduced to the ground voltage at the end of the sowing phase.

16. The method of claim 15, further comprising: The corresponding bias voltage applied to the word line coupled to the select gate device and the one or more non-active memory cells is sloped down to the ground voltage after a delay period at the end of the seeding phase, wherein the delay period includes a time period after the first positive voltage, the second positive voltage and the third positive voltage have sloped down to at least one of the intermediate voltage or the ground voltage.

17. A memory device comprising: A first memory cell string, located in a first sub-block of a memory cell block, the first sub-block comprising a selected sub-block, wherein the first memory cell string includes a first plurality of memory cells coupled to a plurality of word lines; and A second memory cell string, located in a second sub-block of the memory cell block, the second sub-block including a non-selected sub-block, wherein the second memory cell string includes a second plurality of memory cells coupled to the plurality of word lines coupled to the first memory cell string, wherein a first subset of the plurality of word lines is configured to receive a first positive voltage signal during a seeding phase of a programming operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of the first subset of the second plurality of memory cells in the second memory cell string, the first subset of the plurality of word lines including a selected word line associated with the programming operation, at least one word line adjacent to the selected word line on the drain side of the selected word line, and at least one word line adjacent to the selected word line on the source side of the selected word line, and wherein one or more second word lines are configured to receive a second positive voltage signal during the seeding phase of the programming operation, wherein the one or more second word lines are coupled to one or more of the second plurality of memory cells on the source side of the first subset of the second plurality of memory cells in the second memory cell string.

18. The memory device of claim 17, wherein one or more third word lines adjacent to the one or more second word lines are configured to receive a third positive voltage, wherein the one or more third word lines adjacent to the one or more second word lines are coupled to one or more of the second plurality of memory cells on the source side of the memory cell coupled to the one or more second word lines, wherein the third positive voltage is less than the second positive voltage.

19. The memory device of claim 18, wherein a first portion of the first subset of the plurality of word lines is configured such that the first positive voltage signal applied during the seeding phase slopes down to an intermediate voltage signal at the end of the seeding phase, wherein the intermediate voltage signal is less than the first positive voltage signal and greater than a ground voltage signal, and wherein a second portion of the first subset of the plurality of word lines is configured such that the first positive voltage signal applied during the seeding phase slopes down to the ground voltage at the end of the seeding phase.

20. The memory device of claim 19, wherein word lines coupled to the select gate device and one or more inactive memory cells in the second memory cell string are configured such that a corresponding voltage signal applied during the seeding phase slopes down to the ground voltage after a delay period at the end of the seeding phase, wherein the delay period includes a time period after the first positive voltage has sloped down to at least one of the intermediate voltage or the ground voltage.

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