Thin film transistor including compositionally graded gate dielectric and methods of forming the same

Abstract

Thin film transistors including a compositionally graded gate dielectric and methods of forming the same are provided. A thin film transistor can be fabricated by forming a gate electrode in an insulating layer over a substrate; forming a gate dielectric over the gate electrode and the insulating layer; forming an active layer over the gate electrode; and forming a source electrode and a drain electrode in contact with respective portions of a top surface of the active layer. A surface oxygen concentration in a respective one of the gate dielectric and the active layer can be increased by introducing oxygen atoms into a surface region of at least one of the gate dielectric and the active layer.

Description

Technical Field

[0001] This disclosure generally relates to thin-film transistors including compositionally graded gate dielectrics and methods for forming the same. Background Technology

[0002] Thin-film transistors (TFTs) made of oxide semiconductors are an attractive option for back-end process (BEOL) integration because TFTs can be processed at low temperatures and therefore do not damage previously manufactured devices. For example, manufacturing conditions and techniques may not damage previously manufactured front-end process (FEOL) and middle-end process (MEOL) devices. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a semiconductor device is provided, including a thin-film transistor located on a substrate, wherein the thin-film transistor includes: an insulating layer having a gate electrode embedded therein and covering the substrate; a stack of a gate dielectric and an active layer covering the gate electrode, wherein the gate dielectric includes a compositionally graded gate dielectric material, wherein the atomic concentration of oxygen atoms in the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and a source electrode and a drain electrode, the source electrode and the drain electrode being in contact with corresponding portions of the top surface of the active layer.

[0004] According to another aspect of the embodiments of this application, a semiconductor device is provided, including a thin-film transistor located on a substrate, wherein the thin-film transistor includes: a gate electrode overlying the substrate; a stack of a gate dielectric and an active layer overlying the gate electrode, wherein a top surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from a horizontal plane including the top surface of the active layer downwards to at least 20% of the vertical thickness of the active layer; and a source electrode and a drain electrode in contact with corresponding portions of the top surface of the active layer.

[0005] According to another aspect of the embodiments of this application, a method for forming a semiconductor device including a thin-film transistor is provided. The method includes: forming a gate electrode in an insulating layer above a substrate; forming a gate dielectric over the gate electrode and the insulating layer; forming an active layer over the gate electrode; and forming a source electrode and a drain electrode, the source electrode and the drain electrode contacting corresponding portions of the top surface of the active layer. The method includes: increasing the surface oxygen concentration in the gate dielectric and the active layer by introducing oxygen atoms into a surface region of at least one of the gate dielectric and the active layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a vertical cross-sectional view of a first exemplary structure following the formation of a complementary metal-oxide-semiconductor (CMOS) transistor, a first metal interconnect structure formed in an underlying dielectric layer, an insulating spacer layer, and an optional etch-stop dielectric layer, according to embodiments of the present disclosure.

[0008] Figure 2A This is a top view of a portion of a first exemplary structure after the formation of an insulating layer, according to a first embodiment of the present disclosure.

[0009] Figure 2B It is along Figure 2A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0010] Figure 2C It is along Figure 2A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0011] Figure 3A This is a top view of a region of a first exemplary structure after a recessed region has been formed in an insulating layer according to a first embodiment of the present disclosure.

[0012] Figure 3B It is along Figure 3A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0013] Figure 3C It is along Figure 3A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0014] Figure 4A This is a top view of a region of a first exemplary structure after the formation of the bottom gate electrode, according to a first embodiment of the present disclosure.

[0015] Figure 4B It is along Figure 4A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0016] Figure 4C It is along Figure 4A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0017] Figure 5AThis is a top view of a region of a first exemplary structure after the formation of a continuous gate dielectric layer, according to a first embodiment of the present disclosure.

[0018] Figure 5B It is along Figure 5A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0019] Figure 5C It is along Figure 5A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0020] Figure 6A This is a top view of a region of a first exemplary structure after the formation of a continuous compositionally graded gate dielectric sublayer and a continuous homogeneous gate dielectric sublayer, according to a first embodiment of the present disclosure.

[0021] Figure 6B It is along Figure 6A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0022] Figure 6C It is along Figure 6A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0023] Figure 7A This is a top view of a region of a first exemplary structure after the formation of a stack of a homogeneous gate dielectric sublayer, a compositionally graded gate dielectric sublayer, and an active layer, according to a first embodiment of the present disclosure.

[0024] Figure 7B It is along Figure 7A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0025] Figure 7C It is along Figure 7A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0026] Figure 8A This is a top view of a region of a first exemplary structure following the formation of a compositionally graded semiconductor metal oxide region, according to a first embodiment of the present disclosure.

[0027] Figure 8B It is along Figure 8A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0028] Figure 8C It is along Figure 8A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0029] Figure 8D One aspect of this disclosure is shown, including Figures 8A-8C An exemplary vertical atomic concentration distribution of oxygen atoms within the stack of the bottom gate electrode, bottom gate dielectric, and active layer in the first exemplary structure.

[0030] Figure 9A This is a top view of a region of a first exemplary structure after the formation of an electrode-level dielectric layer, according to a first embodiment of the present disclosure.

[0031] Figure 9B It is along Figure 9A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0032] Figure 9C It is along Figure 9A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0033] Figure 10A This is a top view of a region of a first exemplary structure after the formation of the source cavity, drain cavity, and bottom gate contact via cavity, according to a first embodiment of the present disclosure.

[0034] Figure 10B It is along Figure 10A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0035] Figure 10C It is along Figure 10A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0036] Figure 11A This is a top view of a region of a first exemplary structure after the formation of the source electrode, drain electrode, and back electrode contact via structure according to a first embodiment of the present disclosure.

[0037] Figure 11B It is along Figure 11A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0038] Figure 11C It is along Figure 11A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0039] Figure 12A This is a top view of a region of a second exemplary structure after the formation of the top gate dielectric and the top gate electrode, according to a second embodiment of the present disclosure.

[0040] Figure 12B It is along Figure 12A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0041] Figure 12C It is along Figure 12A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0042] Figure 13A This is a top view of a region of a second exemplary structure after the formation of an electrode-level dielectric layer, according to a second embodiment of the present disclosure.

[0043] Figure 13B It is along Figure 13A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0044] Figure 13C It is along Figure 13A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0045] Figure 14A This is a top view of the region of a second exemplary structure after the formation of the source cavity, drain cavity, gate cavity and bottom gate contact via cavity, according to a second embodiment of the present disclosure.

[0046] Figure 14B It is along Figure 14A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0047] Figure 14C It is along Figure 14A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0048] Figure 15A This is a top view of a region of a second exemplary structure after the formation of the source electrode, drain electrode, and back electrode contact via structure according to a second embodiment of the present disclosure.

[0049] Figure 15B It is along Figure 15A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0050] Figure 15C It is along Figure 15A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0051] Figure 16A This is a top view of a region of a third exemplary structure after the formation of the bottom gate dielectric and the active layer, according to a third embodiment of the present disclosure.

[0052] Figure 16B It is along Figure 16A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0053] Figure 16C It is along Figure 16A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0054] Figure 17A This is a top view of a region of a third exemplary structure following the formation of a compositionally graded semiconductor metal oxide region, according to a third embodiment of the present disclosure.

[0055] Figure 17B It is along Figure 17A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0056] Figure 17C It is along Figure 17A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0057] Figure 17D One aspect of this disclosure is shown, including Figures 17A-17C An exemplary vertical atomic concentration distribution of oxygen atoms within the stack of the bottom gate electrode, bottom gate dielectric, and active layer in the third exemplary structure.

[0058] Figure 18A This is a top view of a region of a third exemplary structure according to a third embodiment of the present disclosure after the formation of an electrode-level dielectric layer and source cavity, drain cavity, gate cavity and bottom gate contact via cavity.

[0059] Figure 18B It is along Figure 18A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0060] Figure 18C It is along Figure 18A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0061] Figure 19A This is a top view of a region of a third exemplary structure after the formation of the source electrode, drain electrode, and bottom gate contact via structure, according to a third embodiment of the present disclosure.

[0062] Figure 19B It is along Figure 19A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0063] Figure 19C It is along Figure 19A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0064] Figure 20A This is a top view of the region of an alternative configuration of a third exemplary structure after the formation of the source electrode, drain electrode, and bottom gate contact via structure, according to a third embodiment of the present disclosure.

[0065] Figure 20B It is along Figure 20A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0066] Figure 20C It is along Figure 20A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0067] Figure 21A This is a top view of a region of a fourth exemplary structure according to a fourth embodiment of the present disclosure after the formation of a stack of a homogeneous gate dielectric sublayer, a compositionally graded gate dielectric sublayer, and an active layer.

[0068] Figure 21B It is along Figure 21A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane B-B'.

[0069] Figure 21C It is along Figure 21A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane C-C'.

[0070] Figure 22A This is a top view of a region of a fourth exemplary structure after the formation of an electrode-level dielectric layer, according to a fourth embodiment of the present disclosure.

[0071] Figure 22B It is along Figure 22A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane B-B'.

[0072] Figure 22C It is along Figure 22A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane C-C'.

[0073] Figure 23A This is a top view of a region of a fourth exemplary structure after the formation of the source cavity, drain cavity, gate cavity, and bottom gate contact via cavity, according to a fourth embodiment of the present disclosure.

[0074] Figure 23B It is along Figure 23A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane B-B'.

[0075] Figure 23C It is along Figure 23A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane C-C'.

[0076] Figure 24A This is a top view of a region of a fourth exemplary structure after the formation of the source electrode, drain electrode, and back electrode contact via structure according to a fourth embodiment of the present disclosure.

[0077] Figure 24B It is along Figure 24A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane B-B'.

[0078] Figure 24C It is along Figure 24A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane C-C'.

[0079] Figure 25A This is a top view of a region of a fifth exemplary structure after the formation of the top gate dielectric and the top gate electrode, according to a fifth embodiment of the present disclosure.

[0080] Figure 25B It is along Figure 25A A vertical cross-sectional view of the fifth exemplary structure in the vertical plane B-B'.

[0081] Figure 25C It is along Figure 25A A vertical cross-sectional view of the fifth exemplary structure in the vertical plane C-C'.

[0082] Figure 26A This is a top view of a region of a fifth exemplary structure according to a fifth embodiment of the present disclosure after the formation of the electrode level dielectric layer, source cavity, drain cavity, gate cavity, and bottom gate contact via cavity.

[0083] Figure 26B It is along Figure 26A A vertical cross-sectional view of the fifth exemplary structure in the vertical plane B-B'.

[0084] Figure 26C It is along Figure 26A A vertical cross-sectional view of the fifth exemplary structure in the vertical plane C-C'.

[0085] Figure 27A This is a top view of a region of a fifth exemplary structure after the formation of the source electrode, drain electrode, and back electrode contact via structure according to a fifth embodiment of the present disclosure.

[0086] Figure 27B It is along Figure 27A A vertical cross-sectional view of the fifth exemplary structure in the vertical plane B-B'.

[0087] Figure 27C It is along Figure 27A A vertical cross-sectional view of the fifth exemplary structure in the vertical plane C-C'.

[0088] Figure 28 This is a vertical cross-sectional view of an exemplary structure after the formation of a memory cell, according to an embodiment of the present disclosure.

[0089] Figure 29 This is a flowchart illustrating the general processing steps for manufacturing the semiconductor device of this disclosure. Detailed Implementation

[0090] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0091] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) to facilitate the description of the relationship between one element or feature shown in the figures and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly. Elements with the same reference numerals refer to the same element and are assumed to have the same material composition and the same thickness range unless otherwise explicitly stated.

[0092] Typically, the structures and methods disclosed herein can be used to form semiconductor structures including at least one thin-film transistor (e.g., multiple thin-film transistors). The thin-film transistor can be formed on any substrate, which may be an insulating substrate, a conductive substrate, or a semiconductor substrate. In embodiments utilizing a conductive or semiconductor substrate, at least one insulating layer may be used to provide electrical isolation between the thin-film transistor and the underlying substrate. In embodiments using a semiconductor substrate such as a single-crystal silicon substrate, a field-effect transistor using a portion of the semiconductor substrate as a semiconductor channel can be formed on the semiconductor substrate, and a metal interconnect structure embedded in an interconnect level dielectric layer can be formed on the field-effect transistor. The thin-film transistor can be formed on top of the field-effect transistor including the single-crystal semiconductor channel and the metal interconnect structure, referred to herein as the lower metal interconnect structure.

[0093] According to one aspect of this disclosure, at least one oxygen-saturated surface region can be formed in the active layer and / or the gate dielectric. At least one oxygen-saturated surface region can be formed by oxidizing the surface region of the gate dielectric and / or by oxidizing the surface region of the active layer (which includes the polycrystalline semiconductor channel of the corresponding thin-film transistor). The increased atomic concentration of oxygen atoms within the oxidized surface portion of the gate dielectric and / or the oxidized surface portion of the active layer can prevent the diffusion of metal elements (e.g., indium atoms) through these portions. Therefore, the methods and structures of this disclosure can prevent changes in the material composition within the active layer and detrimental properties of the transistor characteristics of the thin-film transistor. Various aspects of embodiments of this disclosure will now be described in detail.

[0094] refer to Figure 1 This illustration shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate such as a commercial silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least on its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate or a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate comprising a single-crystal silicon material.

[0095] A shallow trench isolation structure 720 comprising a dielectric material such as silicon oxide can be formed in the upper portion of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, can be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field-effect transistors 701 can be formed on the top surface of the semiconductor material layer 9. For example, each field-effect transistor 701 may include a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may comprise a single-crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source electrode 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain electrode 738.

[0096] In embodiments where a memory cell array is subsequently formed at the dielectric layer, the field-effect transistor 701 may include circuitry providing functionality to operate the memory cell array. Specifically, devices in the peripheral region may be configured to control programming, erasing, and sensing (reading) operations of the memory cell array. For example, devices in the peripheral region may include sensing circuitry and / or programming circuitry. Devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), collectively referred to as CMOS circuitry 700.

[0097] One or more field-effect transistors 701 in the CMOS circuit 700 may include a semiconductor channel 735 comprising a portion of a semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 comprises a single-crystal semiconductor material such as single-crystal silicon, then the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit 700 may include a single-crystal semiconductor channel such as a single-crystal silicon channel. In one embodiment, the plurality of field-effect transistors 701 in the CMOS circuit 700 may include corresponding nodes that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently. For example, the plurality of field-effect transistors 701 in the CMOS circuit 700 may include corresponding source electrodes 732 or corresponding drain electrodes 738 that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently.

[0098] In one embodiment, the CMOS circuit 700 may include a programming control circuit configured to control the gate voltage of a group of field-effect transistors 701 for programming corresponding ferroelectric memory cells and controlling the gate voltage of thin-film transistors to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse that programs a corresponding ferroelectric dielectric layer in a selected ferroelectric memory cell to a first polarization state, wherein the polarization in the ferroelectric dielectric layer points to a first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse that programs the ferroelectric dielectric layer in the selected ferroelectric memory cell to a second polarization state, wherein the polarization in the ferroelectric dielectric layer points to a second electrode of the selected ferroelectric memory cell.

[0099] In one embodiment, substrate 8 may include a monocrystalline silicon substrate, and field-effect transistor 701 may include a corresponding portion of the monocrystalline silicon substrate as a semiconductor channel. As used herein, a "semiconductor" device refers to an element with a conductivity ranging from 1.0 x 10⁻⁶. - 6 S / cm up to 1.0x10 5Components in the range of S / cm. As used herein, "semiconductor material" refers to a material in which the electrical conductivity is in the absence of electrical dopants, ranging from 1.0 x 10⁻⁶. -6 S / cm up to 1.0x10 5 Within the range of S / cm, and after appropriate doping with electrodopersive agents, it is possible to produce samples with values ​​from 1.0 S / cm to 1.0 x 10⁻⁶. 5 Doped materials with conductivity in the range of S / cm.

[0100] According to one aspect of this disclosure, the field-effect transistor 701 may subsequently be electrically connected to the drain and gate electrodes of an access transistor comprising an active layer to be formed above the field-effect transistor 701. In one embodiment, a subset of the field-effect transistor 701 may subsequently be electrically connected to at least one of the drain and gate electrodes. For example, the field-effect transistor 701 may include a first word line driver and a second word line driver, the first word line driver being configured to apply a first gate voltage to a first word line through a first subset of the underlying metal interconnect structure to be formed, and the second word line driver being configured to apply a second gate voltage to a second word line through a second subset of the underlying metal interconnect structure. Furthermore, the field-effect transistor 701 may include a bit line driver configured to apply a bit line bias voltage to a bit line to be formed subsequently, and a sense amplifier configured to detect current flowing through the bit line during a read operation.

[0101] Various metal interconnect structures formed within the dielectric layer can then be formed on the substrate 8 and on the semiconductor device thereon (e.g., field-effect transistor 701). In an illustrative example, the dielectric layer may include, for example, a first dielectric layer 601 (which may be a layer surrounding contact structures connected to the source and drain (sometimes referred to as contact-level dielectric layer 601)), a first interconnect-level dielectric layer 610, and a second interconnect-level dielectric layer 620. The metal interconnect structures may include a device contact via structure 612 formed in the first dielectric layer 601 and contacting corresponding components of the CMOS circuit 700, a first metal line structure 618 formed in the first interconnect-level dielectric layer 610, a first metal via structure 622 formed in the lower portion of the second interconnect-level dielectric layer 620, and a second metal line structure 628 formed in the upper portion of the second interconnect-level dielectric layer 620.

[0102] Each of the dielectric layers (601, 610, 620) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal fillers within the disclosed intended scope may also be used. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 may be formed as an integrated wire and via structure by a dual damascene process. The dielectric layers (601, 610, 620) are referred to herein as the lower dielectric layer. The metal interconnect structures (612, 618, 622, 628) formed within the lower dielectric layer are referred to herein as lower metal interconnect structures.

[0103] Although this disclosure is described using an embodiment in which a thin-film transistor is formed on the second interconnect dielectric layer 620, embodiments in which memory cell arrays can be formed at different metal interconnect layers are clearly contemplated herein. Furthermore, although this disclosure is described using an embodiment in which a semiconductor substrate is used as substrate 8, embodiments in which an insulating substrate or a conductive substrate is used as substrate 8 are clearly contemplated herein.

[0104] The collection of all dielectric layers formed prior to the formation of the thin-film transistor array or ferroelectric memory cell array is collectively referred to as the lower dielectric layer (601, 610, 620). The collection of all metal interconnect structures formed within the lower dielectric layer (601, 610, 620) is referred to herein as the first metal interconnect structure (612, 618, 622, 628). Typically, the first metal interconnect structures (612, 618, 622, 628) formed within at least one lower dielectric layer (601, 610, 620) can be formed on a semiconductor material layer 9 located in the substrate 8.

[0105] According to one aspect of this disclosure, thin-film transistors (TFTs) can subsequently be formed in a metal interconnect layer overlying a metal interconnect layer comprising a lower dielectric layer (601, 610, 620) and a first metal interconnect structure (612, 618, 622, 628). In one embodiment, a planar dielectric layer having a uniform thickness can be formed over the lower dielectric layer (601, 610, 620). The planar dielectric layer is referred to herein as an insulating spacer layer 635. The insulating spacer layer 635 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and can be deposited by chemical vapor deposition. The thickness of the insulating spacer layer 635 can range from 20 nm to 300 nm, but smaller and larger thicknesses can also be used.

[0106] Typically, an interconnect-level dielectric layer (e.g., a lower dielectric layer (601, 610, 620)) containing a metal interconnect structure (e.g., a first metal interconnect structure (612, 618, 622, 628)) can be formed on the semiconductor device. An insulating spacer layer 635 can be formed on the interconnect-level dielectric layer.

[0107] In one embodiment, substrate 8 may include a monocrystalline silicon substrate, and a lower dielectric layer (601, 610, 620) with embedded lower metal interconnect structures (612, 618, 622, 628) may be located above the monocrystalline silicon substrate. A field-effect transistor 701, comprising a corresponding portion of the monocrystalline silicon substrate as a channel, may be embedded within the lower dielectric layer (601, 610, 620). The field-effect transistor may then be electrically connected to at least one of the gate, source, and drain electrodes of one or more thin-film transistors to be subsequently formed.

[0108] An etch-stop dielectric layer 636 may optionally be formed over the insulating spacer layer 635. The etch-stop dielectric layer 636 includes an etch-stop dielectric material that provides greater etch resistance to etch chemicals during a subsequent anisotropic etch process that etches the dielectric material subsequently deposited on the etch-stop dielectric layer 636. For example, the etch-stop dielectric layer 636 may include silicon carbonitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide. The thickness of the etch-stop dielectric layer 636 may range from 2 nm to 40 nm, for example from 4 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0109] refer to Figures 2A-2CThe diagram illustrates a region of a first exemplary structure that corresponds to a region of a thin-film transistor to be subsequently formed. Although this disclosure uses a single instance of a thin-film transistor to describe it, it should be understood that multiple instances of thin-film transistors may be formed simultaneously in any of the exemplary structures of this disclosure.

[0110] An insulating layer 42 may be formed over the insulating spacer layer 635 and an optional etch-stop dielectric layer 636. The insulating layer 42 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. Other dielectric materials are within the scope of this disclosure. The thickness of the insulating layer 42 may range from 20 nm to 300 nm, but smaller and larger thicknesses may also be used. A plurality of thin-film transistors may then be formed over the insulating layer 42. In one embodiment, the plurality of thin-film transistors may be arranged along a first horizontal direction hd1 and a second horizontal direction hd2, the second horizontal direction hd2 being perpendicular to the first horizontal direction hd1.

[0111] refer to Figures 3A-3C A photoresist layer (not shown) may be applied over the top surface of the insulating layer 42 and may be photolithographically patterned to form an opening in the illustrated region. In one embodiment, the opening may be a rectangular opening having a pair of lateral sidewalls along a first horizontal direction and a pair of longitudinal sidewalls along a second horizontal direction hd2. An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer into the upper portion of the insulating layer 42. A recessed region 11 may be formed in the upper portion of the insulating layer 42. The recessed region 11 is also referred to as a bottom gate trench.

[0112] In one embodiment, the width of the recessed region 11 along the first horizontal direction hd1 can range from 20 nm to 300 nm, but smaller and larger widths are also possible. In one embodiment, the length of the recessed region 11 along the second horizontal direction hd2 can range from 30 nm to 3,000 nm, but smaller or larger lengths are also possible. The depth of the recessed region 11 can be the same as the thickness of the insulating layer 42. Therefore, the top surface of the optional etch stop dielectric layer 636 or the top surface of the insulating spacer layer 635 (in embodiments where the etch stop dielectric layer 636 is not used) can be exposed in the recessed region 11. The photoresist layer can then be removed, for example, by ashing.

[0113] refer to Figures 4A-4CAt least one conductive material may be deposited in the recessed region 11. The at least one conductive material may include, for example, a metal barrier liner material (e.g., TiN, TaN, and / or WN) and a metal filler material (e.g., Cu, W, Mo, Co, Ru, etc.). Other suitable metal liners and metal fillers within the disclosed intended scope may also be used. Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the insulating layer 42 by a planarization process, which may include a chemical mechanical polishing (CMP) process and / or a recess etching process. The planarization process may use either a chemical mechanical polishing process or a recess etching process. A bottom gate electrode 15 may be formed in the recessed region 11. The bottom gate electrode 15 may be the sole electrode of the thin-film transistor to be subsequently formed, or, in embodiments where a top gate electrode is subsequently formed, one of the two gate electrodes of the thin-film transistor. The top surface of the bottom gate electrode 15 may lie within the same horizontal plane as the top surface of the insulating layer 42.

[0114] refer to Figures 5A-5C A continuous gate dielectric layer 210C can be deposited as a continuous material layer over the insulating layer 42 and the bottom gate electrode 15. In some embodiments, the gate dielectric layer 210C is a continuous homogeneous gate dielectric layer. The continuous gate dielectric layer 210C can be formed by depositing at least one gate dielectric material. The gate dielectric material may include a dielectric metal oxide layer (e.g., aluminum oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, mixtures thereof, etc.) or a stack of multiple dielectric metal oxide layers. Other gate dielectric materials are within the scope of this disclosure. The gate dielectric material can be deposited by atomic layer deposition or chemical vapor deposition. In one embodiment, the gate dielectric material of the continuous gate dielectric layer 210C can be deposited as a homogeneous dielectric oxide material with oxygen deficiency. For example, the atomic concentration of oxygen atoms within the gate dielectric material of the continuous gate dielectric layer 210C can range from 90% to 99.9%, such as from 95% to 99.7%, which is necessary to provide harmony among all the metal elements within the gate dielectric material of the continuous gate dielectric layer 210C. In other words, the oxygen deficiency within the gate dielectric material of the continuous gate dielectric layer 210C can range from 0.1% to 10%, such as from 0.3% to 5%, but smaller and larger oxygen deficiencies can also be used. The thickness of the continuous gate dielectric layer 210C can range from 1.5 nm to 12 nm, such as from 2 nm to 6 nm, but smaller and larger thicknesses can also be used.

[0115] refer to Figures 6A-6CThe top surface portion of the continuous gate dielectric layer 210C can be oxidized by introducing oxygen atoms therein. In one embodiment, the introduction of oxygen atoms can be performed by a first thermal annealing process carried out in an oxygen-containing environment at an elevated temperature. The first thermal annealing process can use, for example, a furnace annealing process. The oxygen-containing environment can include at least one oxygen source gas with a partial pressure ranging from 1 mTorr to 760 Torr (e.g., from 10 mTorr to 100 Torr). The oxygen source gas can include, for example, O2, O3, NO2, NO, H2O, or combinations thereof. An inert gas such as argon may or may not be used during the first thermal annealing process. The elevated temperature can range from 300 degrees Celsius to 425 degrees Celsius, and the duration of the first thermal annealing process can range from 1 minute to 1 hour, but shorter and longer durations are also possible.

[0116] In another embodiment, the introduction of oxygen atoms can be performed using a first plasma oxidation process employing an oxygen-containing plasma generated from an oxygen-containing source gas. The oxygen-containing source gas may include, for example, O2, O3, NO2, NO, H2O, or combinations thereof.

[0117] The top surface portion of the continuous gate dielectric layer 210C, where additional oxygen atoms are provided, can be transformed into a continuous composition gradient gate dielectric sublayer 12C. The lower portion of the continuous gate dielectric layer 210C, where the atomic concentration of oxygen atoms does not increase, has a homogeneous material composition and is referred to herein as the continuous homogeneous gate dielectric sublayer 10C. In one embodiment, the surface oxygen concentration in the continuous gate dielectric layer 210C can be increased by introducing oxygen atoms into the surface region of the continuous gate dielectric layer 210C.

[0118] Typically, the concentration of oxygen atoms is highest at the top surface of the continuous composition graded gate dielectric sublayer 12C and gradually decreases with decreasing distance from the horizontal plane including the top surface of the continuous composition graded gate dielectric sublayer 12C. Therefore, the composition graded gate dielectric material within the continuous composition graded gate dielectric sublayer 12C has a vertical composition gradient, such that the concentration of oxygen atoms within the continuous composition graded gate dielectric sublayer 12C gradually decreases with decreasing vertical distance from the horizontal plane including the top surface of the continuous composition graded gate dielectric sublayer 12C.

[0119] In one embodiment, the composition-gradient gate dielectric material of the continuous composition-gradient gate dielectric sublayer 12C comprises a composition-gradient dielectric metal oxide material and / or is substantially composed of a composition-gradient dielectric metal oxide material. In one embodiment, the composition-gradient dielectric metal oxide material of the continuous composition-gradient gate dielectric sublayer 12C is selected from alumina, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, mixtures thereof, and stacks thereof. In one embodiment, an oxygen concentration gradient may be formed throughout the entire volume of the continuous gate dielectric layer 210C. In this embodiment, the volume of the continuous homogeneous gate dielectric sublayer 10C becomes zero (i.e., the continuous homogeneous gate dielectric sublayer 10C disappears), and the entire continuous gate dielectric layer 210C may be transformed into the continuous composition-gradient gate dielectric sublayer 12C. An optional combination of the continuous homogeneous gate dielectric sublayer 10C and the continuous composition-gradient gate dielectric sublayer 12C constitutes a continuous gate dielectric layer (10C, 12C).

[0120] refer to Figures 7A-7C The active layer 20 may be formed over a continuously graded gate dielectric sublayer 12C. In some embodiments, the active layer 20 may be a semiconductor metal oxide layer. In one embodiment, the semiconductor material includes a suitable dopant (which may be a p-type or n-type dopant) and is provided at a density ranging from 1.0 S / m to 1.0 x 10⁻⁶. 5 Materials with conductivity in the range specified. Exemplary semiconductor materials that can be used for semiconductor metal oxide layers include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Other suitable semiconductor materials are within the scope of this disclosure. In one embodiment, the semiconductor material of a continuous semiconductor metal oxide layer may include indium gallium zinc oxide.

[0121] The active layer 20 may comprise a polycrystalline semiconductor material or an amorphous semiconductor material that can be subsequently annealed to a polycrystalline semiconductor material having a larger average grain size. The active layer 20 may be formed by the deposition and patterning of a continuous semiconductor metal oxide layer. For example, the continuous semiconductor metal oxide layer may be deposited by physical vapor deposition, but other suitable deposition processes may be used. The thickness of the continuous semiconductor metal oxide layer may range from 1 nm to 100 nm, for example from 2 nm to 50 nm and / or from 4 nm to 15 nm, but smaller and larger thicknesses may also be used.

[0122] A photoresist layer 27 may be applied over a continuous semiconductor metal oxide layer and may be photolithographically patterned to form discrete patterned photoresist material portions spanning a corresponding bottom gate electrode 15 along a first horizontal direction hd1. In one embodiment, each patterned portion of the photoresist layer may have a rectangular or rounded rectangular horizontal cross-sectional shape. The pattern in the photoresist layer 27 may be transferred through a continuous semiconductor metal oxide layer, a continuous composition-gradient gate dielectric sublayer 12C, and a continuous homogeneous gate dielectric sublayer 10C by performing an anisotropic etching process. Each patterned portion of the continuous semiconductor metal oxide layer includes an active layer 20. Each patterned portion of the composition-gradient gate dielectric sublayer 12C includes a composition-gradient gate dielectric sublayer 12. Each patterned portion of the continuous homogeneous gate dielectric sublayer 10C includes a homogeneous gate dielectric sublayer 10. The stack of the homogeneous gate dielectric sublayer 10 and the composition-gradient gate dielectric sublayer 12 constitutes a bottom gate dielectric 110. The bottom gate dielectric 110 can be formed on and directly on the bottom gate electrode 15 and the insulating layer 42. The active layer 20 can be formed on the bottom gate electrode 15. The photoresist layer 27 can then be removed, for example, by ashing.

[0123] In one embodiment, each active layer 20 may have a rectangular or rounded rectangular horizontal cross-sectional shape. In one embodiment, each active layer 20 may have a lateral dimension in the range of 60 nm to 1,000 nm (e.g., from 100 nm to 300 nm) along a first horizontal direction hd1, but smaller and larger lateral dimensions may also be used. In one embodiment, each active layer 20 may have a lateral dimension in the range of 20 nm to 500 nm (e.g., from 40 nm to 250 nm) along a second horizontal direction hd2, but smaller and larger lateral dimensions may also be used. The ratio of the lateral dimension of each active layer 20 along the first horizontal direction hd1 to the lateral dimension along the second horizontal direction hd2 may be in the range of 0.5 to 4 (e.g., from 1 to 2), but smaller and larger ratios may also be used. Typically, the vertical stacking of the bottom gate electrode 15, the bottom gate dielectric 110, and the active layers 20 may be formed on top of a lower dielectric layer (601, 610, 620) overlying the substrate 8. The sidewalls of the bottom gate dielectric 110 and the active layer 20 can be vertically aligned, that is, they can be located in the same vertical plane.

[0124] refer to Figures 8A-8CThe surface portion of the active layer 20 can be oxidized by introducing oxygen atoms into it. In one embodiment, oxygen atoms can be introduced by a second thermal annealing process performed at an elevated temperature in an oxygen-containing environment. The second thermal annealing process can be, for example, a furnace annealing process. The oxygen-containing environment can include at least one oxygen source gas with a partial pressure ranging from 1 mTorr to 760 Torr (e.g., from 10 mTorr to 100 Torr). The oxygen source gas can include, for example, O2, O3, NO2, NO, H2O, or combinations thereof. An inert gas such as argon may or may not be used during the second thermal annealing process. The elevated temperature can range from 300 degrees Celsius to 425 degrees Celsius, and the duration of the second thermal annealing process can range from 1 minute to 1 hour, but shorter and longer durations are also possible.

[0125] During the second thermal annealing process, oxygen atoms can diffuse from the top surface region of the bottom gate dielectric 110 into the bottom surface portion 20B of the active layer 20. In this embodiment, the bottom surface portion 20B of the active layer 20 may have a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance away from the interface with the bottom gate dielectric 110. In one embodiment, the bottom gate dielectric 110 comprises a compositionally graded gate dielectric material (within the compositionally graded gate dielectric sublayer 12), wherein the atomic concentration of oxygen atoms within the bottom gate dielectric 110 decreases with a vertical distance downward from the interface between the bottom gate dielectric 110 and the active layer 20, and the bottom surface portion 20B of the active layer 20 has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance upward from the interface with the bottom gate dielectric 110 to at least 20% of the vertical thickness t of the active layer 20.

[0126] In another embodiment, the introduction of oxygen atoms can be performed using an oxygen-containing plasma generated from an oxygen-containing source gas via a second plasma oxidation process. The oxygen-containing source gas may include, for example, O2, O3, NO2, NO, H2O, or combinations thereof.

[0127] The surface portion of the active layer 20 where additional oxygen atoms are provided can be transformed into a composition-gradient semiconductor metal oxide region 20G. The lower portion of the active layer 20 where the atomic concentration of oxygen atoms does not increase has a homogeneous material composition and is referred to herein as a homogeneous semiconductor metal oxide region 20H. The bottom surface portion 20B of the active layer 20 can have a composition gradient such that the atomic concentration of oxygen decreases with increasing vertical distance from the interface with the bottom gate dielectric 110. In one embodiment, the surface oxygen concentration in the active layer 20 can be increased by introducing oxygen atoms into the surface region of the active layer 20.

[0128] Typically, the atomic concentration of oxygen atoms is highest at the physically exposed surface of the composition-graded semiconductor metal oxide region 20G and gradually decreases with distance from the physically exposed surface of the composition-graded semiconductor metal oxide region 20G. Therefore, the composition-graded gate dielectric material within the horizontal extension of the composition-graded semiconductor metal oxide region 20G has a vertical compositional gradient, such that the atomic concentration of oxygen atoms within the horizontal extension of the composition-graded semiconductor metal oxide region 20G decreases with a vertical distance downwards from the horizontal plane including the top surface of the composition-graded semiconductor metal oxide region 20G. The composition-graded gate dielectric material within the vertical extension of the composition-graded semiconductor metal oxide region 20G has a lateral compositional gradient, such that the atomic concentration of oxygen atoms within the vertical extension of the composition-graded semiconductor metal oxide region 20G decreases with a lateral distance from the corresponding sidewall of the composition-graded semiconductor metal oxide region 20G.

[0129] In one embodiment, the composition-gradient gate dielectric material of the composition-gradient semiconductor metal oxide region 20G comprises and / or is substantially composed of a composition-gradient semiconductor metal oxide material. In one embodiment, the composition-gradient semiconductor metal oxide material of the composition-gradient semiconductor metal oxide region 20G is selected from indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. The combination of the homogeneous semiconductor metal oxide region 20H, the composition-gradient semiconductor metal oxide region 20G, and the bottom surface portion 20B constitutes the active layer 20.

[0130] Figure 8D An exemplary vertical atomic concentration distribution of oxygen atoms is shown within a stack including a bottom gate electrode 15, a bottom gate dielectric 110, and an active layer 20. By introducing oxygen atoms into the surface region of at least one of the gate dielectric (e.g., the bottom gate dielectric 110) and the active layer 20, the surface oxygen concentration in the respective one of the gate dielectric (e.g., the bottom gate dielectric 110) and the active layer 20 can be increased.

[0131] Typically, oxygen atoms can be introduced into the top surface portion of the active layer 20 by performing a surface oxidation process selected from a plasma oxidation process using oxygen-containing plasma and a thermal annealing process in an oxygen-containing environment. In this embodiment, the top surface portion of the active layer 20 (which is a horizontally extending region of the composition-gradient semiconductor metal oxide region 20G) has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal surface including the top surface of the active layer downwards to at least 20% of the vertical thickness t of the active layer 20.

[0132] In the illustrative example, the active layer 20 comprises an indium gallium zinc oxide material, and the oxygen deficiency within the active layer 20 increases with a vertical distance downward from the horizontal surface including the top surface of the active layer to at least 20% of the vertical thickness t of the active layer 20. In one embodiment, the sidewall surface portion of the active layer 20 (which is a vertically extending region of the composition-graded semiconductor metal oxide region 20G) has a lateral compositional gradient such that the atomic concentration of oxygen atoms decreases with a lateral distance inward from the respective sidewall of the active layer 20. The bottom gate dielectric 110 comprises a composition-graded gate dielectric material (within the composition-graded gate dielectric sublayer 12), wherein the atomic concentration of oxygen atoms within the bottom gate dielectric 110 decreases with a vertical distance downward from the interface between the bottom gate dielectric 110 and the active layer 20. The amount of oxygen atoms diffusing from the top surface of the composition-graded gate dielectric sublayer 12 to the bottom surface portion 20B of the active layer 20 decreases with distance from the interface between the bottom gate dielectric 110 and the active layer 20. Therefore, the bottom surface portion 20B of the active layer 20 has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness t of the active layer 20.

[0133] In one embodiment, the active layer 20 comprises a compound semiconductor material including at least two metallic elements (e.g., indium, gallium, and zinc) and oxygen. In one embodiment, the active layer 20 comprises indium gallium zinc oxide and / or is substantially composed of indium gallium zinc oxide, and the oxygen deficiency within the active layer 20 increases with a vertical distance from the interface with the bottom gate dielectric 110 upwards at least 20% of the vertical thickness t of the active layer 20.

[0134] The peak atomic concentration of oxygen atoms within the active layer 20 may occur at the physically exposed surface of the composition-graded semiconductor metal oxide region 20G. In an embodiment where the bottom gate dielectric 110 includes a composition-graded gate dielectric sublayer 12, the peak atomic concentration of oxygen atoms within the active layer 20 may occur at the bottom surface portion 20B of the active layer 20, which is in contact with the top surface of the composition-graded gate dielectric sublayer 12. In this embodiment, the material composition of the active layer 20 can be ideally matched at the physically exposed surface and at the interface with the composition-graded gate dielectric sublayer 12 (i.e., it can have zero oxygen deficiency).

[0135] refer to Figures 9A-9CA dielectric layer 48 may be deposited over the active layer 20, the bottom gate electrode 15, and the insulating layer 41. The dielectric layer 48 is also referred to herein as an electrode-level dielectric layer. The dielectric layer 48 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a stack thereof. Other dielectric materials are within the scope of this disclosure. Optionally, the dielectric layer 48 may be planarized to provide a flat top surface. The dielectric material of the dielectric layer 48 may be planarized such that a planarized horizontal top surface of the dielectric layer 48 is formed within a horizontal plane including the top surface of the top gate electrode 34. The thickness of the insulating layer 42, measured above the active layer 20, may range from 50 nm to 500 nm, for example from 100 nm to 250 nm, but smaller and larger thicknesses may also be used. The assembly of the insulating layer 42 and the dielectric layer 48 is referred to herein as a thin-film transistor-level (TFT-level) dielectric layer 40, i.e., a dielectric layer located at the thin-film transistor level.

[0136] refer to Figures 10A-10C A photoresist layer (not shown) may be applied over the TFT-level dielectric layer 40 and may be photolithographically patterned to form discrete openings therein. The pattern of the discrete openings in the photoresist layer may be transferred through the dielectric layer 48 and the top gate dielectric 30 by at least one etching process to form a source cavity 51, a drain cavity 59, and a bottom gate contact via cavity 19. The at least one etching process may include a first anisotropic etching process that selectively etches the material of the dielectric layer 48 relative to the material of the top gate dielectric 30, and an isotropic etching process or a second anisotropic etching process that selectively etches the material of the top gate dielectric 30 relative to the material of the active layer 20.

[0137] Source cavity 51 and drain cavity 59 may be formed at opposite ends of active layer 20 and may be laterally spaced apart from each other along a first horizontal direction hd1. In one embodiment, the end sidewalls of active layer 20 extending laterally along a second horizontal direction hd2 and a pair of sidewall segments of active layer 20 extending laterally along the first horizontal direction hd1 may be physically exposed at the bottom of each of source cavity 51 and drain cavity 59. A rectangular portion of the top surface of active layer 20 may be physically exposed at the bottom of each of source cavity 51 and drain cavity 59. The top surface of bottom gate electrode 15 may be physically exposed at the bottom of back electrode contact via cavity 19. The photoresist layer may then be removed, for example, by ashing.

[0138] refer to Figures 11A-11CAt least one conductive material may be deposited in the cavities (51, 19, 59) and above the TFT-level dielectric layer 40. The at least one conductive material may include a metal liner material and a metal filler material. The metal liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the disclosed scope may also be used.

[0139] Excess portions of at least one conductive material can be removed from a horizontal plane above the top surface of the TFT-level dielectric layer 40 using a planarization process, which may employ CMP and / or recess etching. Other suitable planarization processes may also be used. Each remaining portion of the source cavity 51 filled with at least one conductive material constitutes a source electrode 52. Each remaining portion of the drain cavity 59 filled with at least one conductive material constitutes a drain electrode 56. Each remaining portion of the back electrode contact via cavity 19 filled with at least one conductive material constitutes a back electrode contact via structure 18, which contacts the top surface of the bottom gate electrode 15.

[0140] In one embodiment, each source electrode 52 may include a source metal liner 53 as the remainder of the metal liner material and a source metal filler portion 54 as the remainder of the metal filler material. Each drain electrode 56 may include a drain metal liner 57 as the remainder of the metal liner material and a drain metal filler portion 58 as the remainder of the metal filler material. Each back electrode contact via structure 18 may include a bottom gate contact metal liner 16 as the remainder of the metal liner material and a bottom gate contact metal filler portion 17 as the remainder of the metal filler material.

[0141] The active layer 20 and a set of electrode structures (52, 15, 56) can be formed within the TFT-level dielectric layer 40. The top surface of the source electrode 52, drain electrode 56, and back electrode contact via structure 18 can be located within a horizontal plane including the top surface of the TFT-level dielectric layer 40 (i.e., can be coplanar with this horizontal plane). Typically, the source electrode 52 and drain electrode 56 can be formed directly on the end portions of the active layer 20.

[0142] Typically, an insulating layer 42 is embedded with a gate electrode (e.g., bottom gate electrode 15) and overlaid on the substrate 8. A stack of a gate dielectric (e.g., bottom gate dielectric 110) and an active layer 20 is overlaid on the gate electrode (e.g., bottom gate electrode 15). Source electrodes 52 and drain electrodes 56 may be formed in contact with corresponding portions of the top surface of the active layer 20.

[0143] refer to Figures 12A-12C By forming the top gate dielectric 30 and the top gate electrode 35, it is possible to... Figures 8A-8C The first exemplary structure yields a second exemplary structure according to a second embodiment of the present disclosure. Typically, a top gate dielectric layer and a top gate electrode material layer can be deposited on the active layer 20. The top gate dielectric layer can comprise any material that can be used for a continuous homogeneous gate dielectric sublayer 10C, and can have a thickness ranging from 1.5 nm to 12 nm (e.g., from 2 nm to 6 nm), but smaller and larger thicknesses are also possible. The top gate electrode material layer comprises at least one conductive material, which can be any material that can be used for the bottom gate electrode 15. The thickness of the top gate electrode material layer can range from 50 nm to 300 nm (e.g., from 100 nm to 200 nm), but smaller and larger thicknesses are also possible.

[0144] A photoresist layer (not shown) may be applied over the top gate electrode material layer and may be photolithographically patterned to form discrete photoresist material portions. The pattern in the photoresist material portions may be transferred by performing an anisotropic etching process through the top gate electrode material layer and the top gate dielectric layer, which may be selective for the material of the active layer 20. Each patterned portion of the top gate electrode material layer constitutes a top gate electrode 35. Each patterned portion of the top gate dielectric layer constitutes a top gate dielectric 30. The photoresist layer may subsequently be removed, for example, by ashing. The top gate electrode 35 traverses the active layer 20 along a second horizontal direction hd2. The top gate dielectric 30 is in contact with a portion of the top surface of the active layer 20 (e.g., the top surface of the composition-gradient semiconductor metal oxide region 20G). The top gate electrode 35 is overlaid on and in contact with the top gate dielectric 30.

[0145] refer to Figures 13A-13C It can be executed Figures 9A-9C The processing steps are used to form dielectric layer 48. The dielectric material of dielectric layer 48 can be planarized such that the planarized horizontal top surface of dielectric layer 48 is formed in a horizontal plane including the top surface of top gate electrode 35. The assembly of insulating layer 42 and dielectric layer 48 is referred to herein as thin film transistor-level (TFT-level) dielectric layer 40, i.e., a dielectric layer located at the thin film transistor level.

[0146] refer to Figures 14A-14C It can be executed Figures 10A-10C The processing steps are to form a source cavity 51, a drain cavity 59, and a back electrode contact via cavity 19 that penetrate the dielectric layer 48.

[0147] refer to Figures 15A-15C It can be executed Figures 11A-11C The processing steps form the source electrode 52, drain electrode 56, and back electrode contact via structure 18. The active layer 20 and a set of electrode structures (52, 15, 35, 56) can be formed within the TFT-level dielectric layer 40. The top surfaces of the source electrode 52, drain electrode 56, top gate electrode 35, and back electrode contact via structure 18 can be located within a horizontal plane including the top surface of the TFT-level dielectric layer 40 (i.e., can be coplanar with this horizontal plane).

[0148] refer to Figures 16A-16C The third exemplary structure according to the third embodiment of this disclosure can be obtained from the following manner: Figures 5A-5C The first exemplary structure is obtained by: forming a continuous semiconductor metal oxide layer, forming a patterned photoresist layer 27 on the continuous semiconductor metal oxide layer, and transferring the pattern in the photoresist layer 27 through the continuous semiconductor metal oxide layer and the continuous gate dielectric layer 210C. The continuous semiconductor metal oxide layer may have the same thickness and the same material composition as in the first embodiment. Therefore, the continuous semiconductor metal oxide layer may have any material composition as... Figures 7A-7C The active layer 20 in the first exemplary structure. The pattern in the photoresist layer 27 may be the same as in the first embodiment. The transfer of the pattern in the photoresist layer 27 through the continuous semiconductor metal oxide layer and the continuous gate dielectric layer 210C can be performed using at least one anisotropic etching process. Each patterned portion of the continuous semiconductor metal oxide layer includes the active layer 20. Each patterned portion of the continuous gate dielectric layer 210C constitutes the bottom gate dielectric 210. The photoresist layer 27 may subsequently be removed, for example, by an ashing process. In one embodiment, the entire bottom gate dielectric 210 may have a homogeneous material composition.

[0149] refer to Figures 17A-17C It can be executed Figures 8A-8C The process steps are as follows. Therefore, the surface portion of the active layer 20 can be oxidized by introducing oxygen atoms therein. In one embodiment, the introduction of oxygen atoms can be performed by a thermal annealing process carried out in an oxygen-containing environment at an elevated temperature, which can be the same as the second thermal annealing process described above. In another embodiment, the introduction of oxygen atoms can be performed by a plasma oxidation process, which can be the same as the second plasma oxidation process described above.

[0150] The surface portion of the active layer 20 where additional oxygen atoms are provided is transformed into a composition-gradient semiconductor metal oxide region 20G. The lower portion of the active layer 20 where the atomic concentration of oxygen atoms is not increased has a homogeneous material composition and is referred to herein as a homogeneous semiconductor metal oxide region 20H. In one embodiment, the surface oxygen concentration in the active layer 20 can be increased by introducing oxygen atoms into the surface region of the active layer 20.

[0151] Typically, the atomic concentration of oxygen atoms is highest at the physically exposed surface of the composition-graded semiconductor metal oxide region 20G and gradually decreases with distance from the physically exposed surface of the composition-graded semiconductor metal oxide region 20G. Therefore, the composition-graded gate dielectric material within the horizontal extension of the composition-graded semiconductor metal oxide region 20G has a vertical compositional gradient, such that the atomic concentration of oxygen atoms within the horizontal extension of the composition-graded semiconductor metal oxide region 20G decreases with a vertical distance downwards from the horizontal plane including the top surface of the composition-graded semiconductor metal oxide region 20G. The composition-graded gate dielectric material within the vertical extension of the composition-graded semiconductor metal oxide region 20G has a lateral compositional gradient, such that the atomic concentration of oxygen atoms within the vertical extension of the composition-graded semiconductor metal oxide region 20G decreases with a lateral distance from the corresponding sidewall of the composition-graded semiconductor metal oxide region 20G.

[0152] In one embodiment, the composition-gradient gate dielectric material of the composition-gradient semiconductor metal oxide region 20G comprises and / or is substantially composed of a composition-gradient semiconductor metal oxide material. In one embodiment, the composition-gradient semiconductor metal oxide material of the composition-gradient semiconductor metal oxide region 20G is selected from indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. The combination of the homogeneous semiconductor metal oxide region 20H and the composition-gradient semiconductor metal oxide region 20G constitutes the active layer 20.

[0153] Figure 17D An exemplary vertical atomic concentration distribution of oxygen atoms is shown within a stack including a bottom gate electrode 15, a bottom gate dielectric 210, and an active layer 20. The surface oxygen concentration in the active layer 20 can be increased by introducing oxygen atoms into the surface region of the active layer 20.

[0154] Typically, oxygen atoms can be introduced into the top surface portion of the active layer 20 by performing a surface oxidation process selected from a plasma oxidation process using oxygen-containing plasma and a thermal annealing process in an oxygen-containing environment. In this embodiment, the top surface portion of the active layer 20 (which is a horizontally extending region of the composition-gradient semiconductor metal oxide region 20G) has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal surface including the top surface of the active layer downwards to at least 20% of the vertical thickness t of the active layer 20.

[0155] In the illustrative example, the active layer 20 comprises indium gallium zinc oxide, and the oxygen deficiency within the active layer 20 increases with a vertical distance downward from the horizontal surface including the top surface of the active layer to at least 20% of the vertical thickness t of the active layer 20. In one embodiment, the sidewall surface portion of the active layer 20 (which is a vertically extending region of the composition-gradient semiconductor metal oxide region 20G) has a lateral compositional gradient such that the atomic concentration of oxygen atoms decreases with a lateral distance inward from the respective sidewall of the active layer 20.

[0156] The peak atomic concentration of oxygen atoms within the active layer 20 may occur at the physically exposed surface of the composition-gradient semiconductor metal oxide region 20G. In this embodiment, the material composition of the active layer 20 at the physically exposed surface can be ideally saturated (i.e., it can have zero oxygen deficiency).

[0157] refer to Figures 18A-18C It can be executed Figures 10A-10C The process steps are used to form the source cavity 51, drain cavity 59 and back electrode contact via cavity 19 that penetrate the dielectric layer 48.

[0158] refer to Figures 19A-19C It can be executed Figures 11A-11C The process steps are used to form the source electrode 52, drain electrode 56, and back electrode contact via structure 18. The active layer 20 and a set of electrode structures (52, 15, 56) can be formed within the TFT-level dielectric layer 40. The top surfaces of the source electrode 52, drain electrode 56, and back electrode contact via structure 18 can be located within the horizontal plane including the top surface of the TFT-level dielectric layer 40 (i.e., can be coplanar with this horizontal plane).

[0159] refer to Figures 20A-20C An alternative configuration of the third exemplary structure is shown, which can be obtained from the third exemplary structure by forming a stack of top gate dielectric 30 and top gate electrode 35. Figures 12A-12C The process steps can be Figures 17A-17C The process steps are performed afterward to form a stack of top gate dielectric 30 and top gate electrode 35. Subsequently, the following steps can be performed: Figures 18A-19C The process steps to form Figures 20A-20C An alternative configuration of the third exemplary structure shown.

[0160] refer to Figures 21A-21C The fourth exemplary structure according to the fourth embodiment of this disclosure can be derived from the following methods: Figures 7A-7C The first exemplary structure is obtained by removing the photoresist layer 27 and performing an annealing process that causes oxygen to diffuse outward from the composition-gradient gate dielectric sublayer 12 into the active layer 20. Oxygen atoms diffuse from the composition-gradient gate dielectric sublayer 12 into the bottom surface portion 20B of the active layer 20. In this embodiment, the bottom surface portion 20B of the active layer 20 may have a compositional gradient such that the atomic concentration of oxygen atoms decreases with increasing vertical distance from the interface with the composition-gradient gate dielectric sublayer 12. In one embodiment, the bottom gate dielectric 110 includes a compositionally graded gate dielectric material (within the compositionally graded gate dielectric sublayer 12), wherein the atomic concentration of oxygen atoms within the bottom gate dielectric 110 decreases with a vertical distance downward from the interface between the bottom gate dielectric 110 and the active layer 20, and the bottom surface portion 20B of the active layer 20 has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance upward from the interface with the bottom gate dielectric 110 to at least 20% of the vertical thickness t of the active layer 20.

[0161] refer to Figures 22A-22C It can be executed Figures 9A-9C The process steps are used to form dielectric layer 48. The dielectric material of dielectric layer 48 can be planarized to provide a horizontal top surface. The assembly of insulating layer 42 and dielectric layer 48 is referred to herein as thin-film transistor-level (TFT-level) dielectric layer 40, i.e., a dielectric layer located at the thin-film transistor level.

[0162] refer to Figures 23A-23C It can be executed Figures 10A-10C The process steps are used to form the source cavity 51, drain cavity 59 and back electrode contact via cavity 19 that penetrate the dielectric layer 48.

[0163] refer to Figures 24A-24C It can be executed Figures 11A-11C The process steps are used to form the source electrode 52, drain electrode 56, and back electrode contact via structure 18. The active layer 20 and a set of electrode structures (52, 15, 56) can be formed within the TFT-level dielectric layer 40. The top surfaces of the source electrode 52, drain electrode 56, and back electrode contact via structure 18 can be located within the horizontal plane including the top surface of the TFT-level dielectric layer 40 (i.e., can be coplanar with this horizontal plane).

[0164] refer to Figures 25A-25C By forming the top gate dielectric 30 and the top gate electrode 35, it is possible to... Figures 21A-21C The fourth exemplary structure yields the fifth exemplary structure according to the fifth embodiment of this disclosure. Typically, a top gate dielectric layer and a top gate electrode material layer can be deposited on the active layer 20. The top gate dielectric layer can include any material that can be used for a continuous homogeneous gate dielectric sublayer 10C, and can have a thickness ranging from 1.5 nm to 12 nm (e.g., from 2 nm to 6 nm), but smaller and larger thicknesses are also possible. The top gate electrode material layer includes at least one conductive material, which can be any material that can be used for the bottom gate electrode 15. The thickness of the top gate electrode material layer can range from 50 nm to 300 nm (e.g., from 100 nm to 200 nm), but smaller and larger thicknesses are also possible.

[0165] A photoresist layer (not shown) may be applied over the top gate electrode material layer and may be photolithographically patterned to form discrete photoresist material portions. The pattern in the photoresist material portions may be transferred by performing an anisotropic etching process through the top gate electrode material layer and the top gate dielectric layer, which may be selective for the material of the active layer 20. Each patterned portion of the top gate electrode material layer constitutes a top gate electrode 35. Each patterned portion of the top gate dielectric layer constitutes a top gate dielectric 30. The photoresist layer may subsequently be removed, for example, by ashing. The top gate electrode 35 traverses the active layer 20 along a second horizontal direction hd2. The top gate dielectric 30 contacts a portion of the top surface of the active layer 20, such as the top surface of the composition-gradient semiconductor metal oxide region 20G. The top gate electrode 35 is overlaid on and in contact with the top gate dielectric 30.

[0166] refer to Figures 26A-26C It can be executed Figures 9A-9C The process steps are used to form the dielectric layer 48. This can be performed. Figures 10A-10C The process steps are used to form the source cavity 51, drain cavity 59 and back electrode contact via cavity 19 that penetrate the dielectric layer 48.

[0167] refer to Figures 27A-27C It can be executed Figures 11A-11C The process steps are used to form the source electrode 52, drain electrode 56, and back electrode contact via structure 18. The active layer 20 and a set of electrode structures (52, 15, 35, 56) can be formed within the TFT-level dielectric layer 40. The top surfaces of the source electrode 52, drain electrode 56, top gate electrode 35, and back electrode contact via structure 18 can be located within a horizontal plane including the top surface of the TFT-level dielectric layer 40 (i.e., can be coplanar with this horizontal plane).

[0168] refer to Figure 28 This illustrates an exemplary structure after the formation of a thin-film transistor. This exemplary structure can be derived from... Figures 11A-11C The first exemplary structure shown Figures 15A-15C The second exemplary structure shown Figures 19A-20C The third exemplary structure shown Figures 24A-24C The fourth exemplary structure shown, or Figures 27A-27C The fifth exemplary structure shown is obtained. For example, a second metal via structure 632 can be formed on a corresponding structure in the second metal line structure 628, simultaneously with, before or after the formation of the source electrode 52, drain electrode 56, optional top gate electrode 35 and back electrode contact via structure 18, penetrating the TFT-level dielectric layer 40 and insulating spacer layer 635.

[0169] A dielectric layer, referred to herein as a third-line dielectric layer 637, may be deposited on the TFT-level dielectric layer 40. A third metal line structure 638 may be formed in the third-line dielectric layer 637, which is located on a corresponding structure in the metal structure (52, 56, 35, 18) embedded within the TFT-level dielectric layer 40.

[0170] Additional metal interconnect structures embedded in the additional dielectric layer can then be formed on top of the thin-film transistor and the third interconnect dielectric layer 637. In an illustrative example, the dielectric layer may include, for example, a fourth interconnect dielectric layer 640, a fifth interconnect dielectric layer 650, etc. The additional metal interconnect structures may include a fourth metal line 648 and a third metal via structure (not shown) embedded in the fourth interconnect dielectric layer 640, a fifth metal line structure 658 and a fourth metal via structure 652 embedded in the fifth interconnect dielectric layer 650, etc.

[0171] Optionally, the memory cells 150 may be formed below, above, or on the same horizontal plane as the thin-film transistors. In embodiments where the thin-film transistors are formed as a two-dimensional periodic array, the memory cells 150 may be formed as a two-dimensional periodic array of memory cells 150. Each memory cell 150 may include a portion of a magnetic tunnel junction, a ferroelectric tunnel junction, a phase-change memory material, or a vacancy-modulated conductive oxide material. Furthermore, each memory cell 150 may include a first electrode 126 and a second electrode 158, the first electrode 126 comprising a metallic material and the second electrode 158 comprising a metallic material and protecting the lower data storage portion of the memory cell 150. The memory element is disposed between the first electrode 126 (i.e., the bottom electrode) and the second electrode 158 (i.e., the top electrode).

[0172] In an illustrative example, in an embodiment where the memory cell 150 includes a magnetic tunnel junction, the memory cell 150 may include a layer stack from bottom to top including a first electrode 126, a metal seed layer 128 for promoting the crystallization growth of an overlying material layer, a synthetic antiferromagnetic (SAF) structure 140, a tunnel barrier layer 146, a free magnetization layer 148, and a second electrode 158. While this disclosure is described using embodiments in which thin-film transistors are used as access transistors for the memory cell 150, embodiments in which thin-film transistors are used as logic devices, as components of peripheral circuitry for a memory array, or for any other semiconductor circuitry are expressly contemplated herein.

[0173] In one embodiment, substrate 8 comprises a monocrystalline silicon substrate. Lower dielectric layers (601, 610, 620) with embedded lower metal interconnect structures (612, 618, 622, 628) may be located between the monocrystalline silicon substrate and insulating layer 42. Field-effect transistors 701, including corresponding portions of the monocrystalline silicon substrate as channels, may be embedded within the lower dielectric layers (601, 610, 620) and may be electrically connected to at least one of the gate electrode (15, 35), source electrode 52, and drain electrode 56.

[0174] Figure 29 This is a flowchart illustrating the general process steps for manufacturing the semiconductor device of this disclosure. Refer to step 2910 and... Figures 1-4C , Figures 12A-12C , Figures 16A-16C , Figures 20A-20C , Figures 21A-21C and Figures 25A-25C A gate electrode (e.g., bottom gate electrode 15) can be formed in the insulating layer 42 above the substrate 8. Refer to step 2920 and... Figures 5A-7C , Figures 12A-12C , Figures 16A-16C , Figures 20A-20C , Figures 21A-21C and Figures 25A-25C A gate dielectric (e.g., a bottom gate dielectric (110 or 210)) may be formed over the gate electrode (e.g., bottom gate electrode 15) and the insulating layer 42. Refer to optional step 2930 and... Figures 6A-6C , Figures 12A-12C , Figures 20A-20C , Figures 21A-21C and Figures 25A-25C The surface oxygen concentration in the gate dielectric (e.g., bottom gate dielectric 110) can be increased by introducing oxygen atoms into the surface region of the gate dielectric (thus forming a composition-gradient gate dielectric sublayer 12).

[0175] Refer to step 2940 and Figures 7A-8D , Figures 12A-12C , Figures 20A-20C , Figures 21A-21C and Figures 25A-25C An active layer 20 can be formed over the gate electrode (e.g., the bottom gate electrode 15). Refer to optional step 2950 and... Figures 8A-8D , Figures 12A-12C and Figures 17A-17D The surface oxygen concentration in the active layer 20 can be increased by introducing oxygen atoms into the surface region of the active layer 20 (e.g., the composition-gradient semiconductor metal oxide region 20G). Refer to step 2960 and... Figures 8A-11C , Figures 12A-15C , Figures 16A-19C , Figures 20A-20C , Figures 22A-24C and Figures 26A-27C Source electrode 52 and drain electrode 56 can be formed in contact with corresponding portions of the top surface of active layer 20. Typically, at least one of steps 2930 and 2950 is performed. In one embodiment, steps 2930 and 2950 are performed. In another embodiment, step 2930 is performed, and step 2950 is omitted. In yet another embodiment, step 2930 is omitted, and step 2950 is performed. Typically, the surface oxygen concentration in the gate dielectric (e.g., bottom gate dielectric 110) and the corresponding portion of the active layer 20 can be increased by introducing oxygen atoms into the surface region of at least one of the gate dielectric and active layer 20.

[0176] Common Reference Figures 1-29 Furthermore, according to various embodiments of the present disclosure, a semiconductor device is provided comprising a thin-film transistor located on a substrate 8. The thin-film transistor includes: an insulating layer 42 having a gate electrode (e.g., a bottom gate electrode 15) embedded therein and superimposed on the substrate 8; a stack of a gate dielectric (e.g., a bottom gate dielectric 110) and an active layer 20 superimposed on the gate electrode, wherein the gate dielectric includes a compositionally graded gate dielectric material (including a compositionally graded gate dielectric sublayer 12), wherein the atomic concentration of oxygen atoms within the gate dielectric layer (e.g., the bottom gate dielectric 110) decreases with a vertical distance downward from the interface between the gate dielectric layer and the active layer 20; and a source electrode 52 and a drain electrode 56 in contact with corresponding portions of the top surface of the active layer 20.

[0177] In one embodiment, the bottom surface portion 20B of the active layer 20 has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance upward from the interface to at least 20% of the vertical thickness t of the active layer 20. In one embodiment, the active layer 20 comprises a compound semiconductor material containing at least two metal elements and oxygen and / or is substantially composed of a compound semiconductor material containing at least two metal elements and oxygen. In one embodiment, the active layer 20 comprises indium gallium zinc oxide; and the oxygen deficiency within the active layer 20 increases with a vertical distance upward from the interface to at least 20% of the vertical thickness t of the active layer 20.

[0178] In one embodiment, the composition-gradient gate dielectric material includes a composition-gradient dielectric metal oxide material. In one embodiment, the composition-gradient dielectric metal oxide material is selected from aluminum oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, mixtures thereof, and stacks thereof.

[0179] In one embodiment, the top surface portion of the active layer 20 has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal surface including the top surface of the active layer 20 downwards to at least 20% of the vertical thickness t of the active layer 20.

[0180] In one embodiment, the active layer 20 comprises indium gallium zinc oxide; and the oxygen deficiency within the active layer 20 increases with a vertical distance downward from the horizontal surface including the top surface of the active layer 20 to at least 20% of the vertical thickness t of the active layer 20. In one embodiment, the sidewall surface portion of the active layer 20 (including the vertically extending region of the composition-gradient semiconductor metal oxide region 20G) has a lateral compositional gradient such that the atomic concentration of oxygen atoms decreases with a lateral distance inward from the respective sidewall of the active layer 20.

[0181] In one embodiment, the semiconductor device includes: a top gate dielectric 30 in contact with a portion of the top surface of the active layer 20; and a top gate electrode 35 superimposed on the top gate dielectric 30.

[0182] According to another aspect of this disclosure, a semiconductor device is provided, comprising a thin-film transistor located on a substrate 8. The thin-film transistor includes: an insulating layer 42 in which a gate electrode (e.g., a bottom gate electrode 15) is embedded and superimposed on the substrate 8; a stack of a gate dielectric (e.g., a bottom gate dielectric (110 or 220)) and an active layer 20 superimposed on the gate electrode (e.g., the bottom gate electrode 15), wherein a top surface portion of the active layer 20 (e.g., a composition-gradient semiconductor metal oxide region 20G) has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from a horizontal plane including the top surface of the active layer 20 downwards to at least 20% of the vertical thickness t of the active layer 20; and a source electrode 52 and a drain electrode 56 in contact with corresponding portions of the top surface of the active layer 20.

[0183] In one embodiment, the active layer 20 comprises an indium gallium zinc oxide material; and the oxygen deficiency within the active layer 20 increases with a vertical distance from the horizontal surface including the top surface of the active layer 20 downwards to at least 20% of the vertical thickness t of the active layer 20.

[0184] In one embodiment, the sidewall surface portion of the active layer 20 (including the vertically extending region of the composition-gradient semiconductor metal oxide region 20G) has a lateral composition gradient such that the atomic concentration of oxygen atoms decreases with the lateral distance inward from the respective sidewall of the active layer 20.

[0185] In one embodiment, the semiconductor device includes: a top gate dielectric 30 in contact with a portion of the top surface of the active layer 20; and a top gate electrode 35 superimposed on the top gate dielectric 30.

[0186] In one embodiment, the gate dielectric (e.g., the bottom gate dielectric 110) comprises a compositionally graded gate dielectric material (within the compositionally graded gate dielectric sublayer 12), wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric (e.g., the bottom gate dielectric 110) and the active layer 20; and the bottom surface portion 20B of the active layer 20 has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance upward from the interface to at least 20% of the vertical thickness t of the active layer 20.

[0187] Various embodiments of this disclosure can be used to reduce the outward diffusion of metal elements, such as indium, from the active layer 20 by providing a surface layer of semiconductor or dielectric metal oxide material with an ideal sizing. The oxygen vacancy density in the ideally sizing semiconductor or dielectric metal oxide material is very low, and therefore, the porosity within the surface layer of the ideally sizing semiconductor or dielectric metal oxide material for promoting metal element diffusion is low. Preventing metal diffusion from the active layer 20 prevents compositional changes within the active layer 20, and therefore helps maintain constant device characteristics of the thin-film transistor throughout its entire operational lifetime.

[0188] Here are some examples.

[0189] Example 1. A semiconductor device including a thin-film transistor located on a substrate, wherein the thin-film transistor comprises:

[0190] An insulating layer, wherein a gate electrode is embedded in the insulating layer and is covered on the substrate;

[0191] A stack of a gate dielectric and an active layer, the stack covering the gate electrode, wherein the gate dielectric comprises a compositionally graded gate dielectric material, and wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and

[0192] The source electrode and the drain electrode are in contact with corresponding portions of the top surface of the active layer.

[0193] Example 2. The semiconductor device according to Example 1, wherein the bottom surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

[0194] Example 3. The semiconductor device according to Example 2, wherein the active layer comprises a compound semiconductor material containing at least two metal elements and oxygen.

[0195] Example 4. The semiconductor device according to Example 3, wherein:

[0196] The active layer comprises indium gallium zinc oxide; and

[0197] The oxygen deficiency within the active layer increases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

[0198] Example 5. The semiconductor device according to Example 1, wherein the composition-gradient gate dielectric material comprises a composition-gradient dielectric metal oxide material.

[0199] Example 6. The semiconductor device according to Example 5, wherein the composition-gradient dielectric metal oxide material is selected from: aluminum oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, mixtures thereof, and stacks thereof.

[0200] Example 7. The semiconductor device of claim 1, wherein the top surface portion of the active layer has a composition gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

[0201] Example 8. The semiconductor device according to Example 7, wherein:

[0202] The active layer comprises indium gallium zinc oxide; and

[0203] The oxygen deficiency within the active layer increases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

[0204] Example 9. The semiconductor device according to Example 7, wherein the sidewall surface portion of the active layer has a lateral composition gradient such that the atomic concentration of oxygen atoms decreases with a lateral distance inward from the respective sidewall of the active layer.

[0205] Example 10. The semiconductor device according to Example 7 further includes:

[0206] The top gate dielectric contacts a portion of the top surface of the active layer; and

[0207] The top gate electrode is overlaid on the top gate dielectric.

[0208] Example 11. A semiconductor device including a thin-film transistor located on a substrate, wherein the thin-film transistor comprises:

[0209] A gate electrode is superimposed on the substrate;

[0210] A stack of a gate dielectric and an active layer, the stack covering the gate electrode, wherein the top surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from a horizontal surface including the top surface of the active layer downwards to at least 20% of the vertical thickness of the active layer; and

[0211] The source electrode and the drain electrode are in contact with corresponding portions of the top surface of the active layer.

[0212] Example 12. The semiconductor device according to Example 11, wherein:

[0213] The active layer comprises indium gallium zinc oxide; and

[0214] The oxygen deficiency within the active layer increases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

[0215] Example 13. The semiconductor device according to Example 11, wherein the sidewall surface portion of the active layer has a lateral composition gradient such that the atomic concentration of oxygen atoms decreases with a lateral distance inward from the respective sidewall of the active layer.

[0216] Example 14. The semiconductor device according to Example 11 further includes:

[0217] The top gate dielectric contacts a portion of the top surface of the active layer; and

[0218] The top gate electrode is overlaid on the top gate dielectric.

[0219] Example 15. The semiconductor device according to Example 11, wherein:

[0220] The gate dielectric includes a compositionally graded gate dielectric material, wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and

[0221] The bottom surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

[0222] Example 16. A method of forming a semiconductor device including a thin-film transistor, the method comprising:

[0223] A gate electrode is formed in an insulating layer above the substrate;

[0224] A gate dielectric is formed on the gate electrode and the insulating layer;

[0225] An active layer is formed on the gate electrode; and

[0226] A source electrode and a drain electrode are formed, and the source electrode and the drain electrode are in contact with corresponding portions of the top surface of the active layer.

[0227] The method includes increasing the surface oxygen concentration in the gate dielectric and the active layer by introducing oxygen atoms into the surface region of at least one of the gate dielectric and the active layer.

[0228] Example 17. The method according to Example 16, wherein the method includes: introducing oxygen atoms into a top surface portion of the gate dielectric by performing a first thermal annealing process in an oxygen-containing environment before forming the active layer on the gate dielectric.

[0229] Example 18. The method according to Example 17, wherein the method includes: performing a second thermal annealing process after forming the active layer, wherein:

[0230] Oxygen atoms diffuse from the top surface region of the gate dielectric to the bottom surface portion of the active layer;

[0231] The gate dielectric includes a compositionally graded gate dielectric material, wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and

[0232] The bottom surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

[0233] Example 19. The method according to Example 16, wherein the method includes: introducing oxygen atoms into a top surface portion of the active layer by performing a surface oxidation process selected from:

[0234] Plasma oxidation processes using oxygen-containing plasma; and

[0235] A hot annealing process performed in an oxygen-containing environment.

[0236] Example 20. The method according to Example 19, wherein the top surface portion of the active layer has a composition gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

[0237] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device comprising a thin-film transistor located on a substrate, wherein, The thin-film transistor includes: An insulating layer, wherein a gate electrode is embedded in the insulating layer and is covered on the substrate; A stack of a gate dielectric and an active layer, the stack covering the gate electrode, wherein the gate dielectric comprises a compositionally graded gate dielectric material, and wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and The source electrode and the drain electrode are in contact with corresponding portions of the top surface of the active layer. The source electrode is in direct contact with the following portions: a first surface segment of the top surface of the insulating layer, a first end portion of a pair of longitudinal sidewalls of the gate dielectric, the entire area of ​​the first lateral sidewall of a pair of lateral sidewalls of the gate dielectric, a first end portion of a pair of longitudinal sidewalls of the active layer, the entire area of ​​the first lateral sidewall of a pair of lateral sidewalls of the active layer, and a first end portion of the top surface of the active layer. The drain electrode is in direct contact with the following portions: a second surface portion of the top surface of the insulating layer, a second end portion of a pair of longitudinal sidewalls of the gate dielectric, the entire area of ​​the second lateral sidewall of a pair of lateral sidewalls of the gate dielectric, a second end portion of a pair of longitudinal sidewalls of the active layer, the entire area of ​​the second lateral sidewall of a pair of lateral sidewalls of the active layer, and a second end portion of the top surface of the active layer.

2. The semiconductor device according to claim 1, wherein, The bottom surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

3. The semiconductor device according to claim 2, wherein, The active layer comprises a compound semiconductor material containing at least two metal elements and oxygen.

4. The semiconductor device according to claim 3, wherein: The active layer comprises indium gallium zinc oxide; and The oxygen deficiency within the active layer increases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

5. The semiconductor device according to claim 1, wherein, The composition-gradient gate dielectric material includes composition-gradient dielectric metal oxide materials.

6. The semiconductor device according to claim 5, wherein, The graded dielectric metal oxide material is selected from: aluminum oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, mixtures thereof, and stacks thereof.

7. The semiconductor device according to claim 1, wherein, The top surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

8. The semiconductor device according to claim 7, wherein: The active layer comprises indium gallium zinc oxide; and The oxygen deficiency within the active layer increases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

9. The semiconductor device according to claim 7, wherein, The sidewall surface portion of the active layer has a lateral composition gradient, such that the atomic concentration of oxygen atoms decreases with the lateral distance from the corresponding sidewall of the active layer inward.

10. The semiconductor device according to claim 7, further comprising: The top gate dielectric is in contact with a portion of the top surface of the active layer; as well as The top gate electrode is overlaid on the top gate dielectric.

11. A semiconductor device comprising a thin-film transistor disposed on a substrate, wherein, The thin-film transistor includes: An insulating layer, wherein a gate electrode is embedded in the insulating layer and is covered on the substrate; A stack of a gate dielectric and an active layer, the stack covering the gate electrode, wherein the top surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from a horizontal surface including the top surface of the active layer downwards to at least 20% of the vertical thickness of the active layer; and The source electrode and the drain electrode are in contact with corresponding portions of the top surface of the active layer. The source electrode is in direct contact with the following portions: a first surface portion of the top surface of the insulating layer, a first end portion of a pair of longitudinal sidewalls of the gate dielectric, the entire area of ​​the first lateral sidewall of a pair of lateral sidewalls of the gate dielectric, a first end portion of a pair of longitudinal sidewalls of the active layer, the entire area of ​​the first lateral sidewall of a pair of lateral sidewalls of the active layer, and a first end portion of the top surface of the active layer. The drain electrode is in direct contact with the following portions: a second surface portion of the top surface of the insulating layer, a second end portion of a pair of longitudinal sidewalls of the gate dielectric, the entire area of ​​the second lateral sidewall of a pair of lateral sidewalls of the gate dielectric, a second end portion of a pair of longitudinal sidewalls of the active layer, the entire area of ​​the second lateral sidewall of a pair of lateral sidewalls of the active layer, and a second end portion of the top surface of the active layer.

12. The semiconductor device according to claim 11, wherein: The active layer comprises indium gallium zinc oxide; and The oxygen deficiency within the active layer increases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

13. The semiconductor device according to claim 11, wherein, The sidewall surface portion of the active layer has a lateral composition gradient, such that the atomic concentration of oxygen atoms decreases with the lateral distance from the corresponding sidewall of the active layer inward.

14. The semiconductor device of claim 11, further comprising: The top gate dielectric is in contact with a portion of the top surface of the active layer; as well as The top gate electrode is overlaid on the top gate dielectric.

15. The semiconductor device according to claim 11, wherein: The gate dielectric includes a compositionally graded gate dielectric material, wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and The bottom surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

16. A method of forming a semiconductor device including a thin-film transistor, the method comprising: A gate electrode is formed in an insulating layer above the substrate; A gate dielectric is formed on the gate electrode and the insulating layer; An active layer is formed on the gate electrode; as well as A source electrode and a drain electrode are formed, and the source electrode and the drain electrode are in contact with corresponding portions of the top surface of the active layer. The method includes increasing the surface oxygen concentration in at least one of the gate dielectric and the active layer by introducing oxygen atoms into the surface region of the gate dielectric and the active layer. The source electrode is in direct contact with the following portions: a first surface portion of the top surface of the insulating layer, a first end portion of a pair of longitudinal sidewalls of the gate dielectric, the entire area of ​​the first lateral sidewall of a pair of lateral sidewalls of the gate dielectric, a first end portion of a pair of longitudinal sidewalls of the active layer, the entire area of ​​the first lateral sidewall of a pair of lateral sidewalls of the active layer, and a first end portion of the top surface of the active layer. The drain electrode is in direct contact with the following portions: a second surface portion of the top surface of the insulating layer, a second end portion of a pair of longitudinal sidewalls of the gate dielectric, the entire area of ​​the second lateral sidewall of a pair of lateral sidewalls of the gate dielectric, a second end portion of a pair of longitudinal sidewalls of the active layer, the entire area of ​​the second lateral sidewall of a pair of lateral sidewalls of the active layer, and a second end portion of the top surface of the active layer.

17. The method according to claim 16, wherein, The method includes introducing oxygen atoms into a top surface portion of the gate dielectric by performing a first thermal annealing process in an oxygen-containing environment before forming the active layer on the gate dielectric.

18. The method according to claim 17, wherein, The method includes: performing a second thermal annealing process after forming the active layer, wherein: Oxygen atoms diffuse from the top surface region of the gate dielectric to the bottom surface portion of the active layer; The gate dielectric includes a compositionally graded gate dielectric material, wherein the atomic concentration of oxygen atoms within the gate dielectric decreases with a vertical distance downward from the interface between the gate dielectric and the active layer; and The bottom surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the interface upwards to at least 20% of the vertical thickness of the active layer.

19. The method of claim 16, wherein, The method includes introducing oxygen atoms into a top surface portion of the active layer by performing a surface oxidation process selected from the following: Plasma oxidation processes using oxygen-containing plasma; and A hot annealing process performed in an oxygen-containing environment.

20. The method according to claim 19, wherein, The top surface portion of the active layer has a compositional gradient such that the atomic concentration of oxygen atoms decreases with a vertical distance from the horizontal plane including the top surface of the active layer down to at least 20% of the vertical thickness of the active layer.

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