Semiconductor storage device

Abstract

The present invention provides a semiconductor memory device that can appropriately control the operation timing according to the environment during use, such as changes in power supply voltage and temperature. The semiconductor memory device includes a temperature sensor for detecting the temperature of the semiconductor memory device, a voltage detection unit for detecting the power supply voltage of the semiconductor memory device, such as a ring oscillator and a counter, and a control unit for controlling the operation timing in the semiconductor memory device according to the temperature detected by the temperature sensor after the power is turned on and the power supply voltage detected by the voltage detection unit after the power is turned on to meet specific conditions.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device. Background Art

[0002] In semiconductor memory devices, such as dynamic random access memory (DRAM), as the signal transmission speed increases, it is necessary to appropriately control the operation timing.

[0003] For example, in the technology described in Patent Document 1, after the power is turned on, the signal output from the ring oscillator of the semiconductor memory device having PVT (process / power supply voltage / temperature) variation-related characteristics can control the operation timing (start time and hold time) of the internal clock according to the number of rising edges and falling edges of the above-mentioned output signal.

[0004] [Prior technical literature]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2018 / 0144781. Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] By the way, the ring oscillator has the following characteristics. When the power supply voltage is higher or the temperature is higher, the number of rising edges or falling edges of the output signal becomes more; when the power supply voltage of the ring oscillator is lower or the temperature is lower, the number of rising edges or falling edges of the output signal becomes less. Therefore, based on the number of rising edges or falling edges of the signal output from the ring oscillator, it is difficult to control the operation timing to meet the performance requirements (specifications) for various scenarios (e.g., low voltage at low temperature, high voltage at low temperature, low voltage at high temperature, high voltage at high temperature, etc.) of the environment (e.g., temperature and power supply voltage, etc.) when the semiconductor memory device is used.

[0008] Furthermore, in the technology described in Patent Document 1, since the operation timing of the internal clock is controlled only once after the power is turned on, it may be difficult to appropriately control the operation timing according to the time change of the environment when the semiconductor memory device is used.

[0009] In view of the above problems, an object of the present invention is to provide a semiconductor memory device that can appropriately control the operation timing according to the environment during use.

[0010] In order to solve the above-mentioned problems, the present invention provides a semiconductor memory device, including a temperature sensor for detecting the temperature of the above-mentioned semiconductor memory device, a voltage detection unit for detecting the power supply voltage of the above-mentioned semiconductor memory device, and a control unit for controlling the operation timing in the above-mentioned semiconductor memory device according to the temperature detected by the above-mentioned temperature sensor after the power is turned on, and the power supply voltage detected by the above-mentioned voltage detection unit after the power is turned on, so as to meet specific conditions.

[0011] According to the present invention, since the operation timing in the semiconductor memory device is controlled to meet specific conditions according to the temperature detected by the temperature sensor after the power is turned on and the power voltage detected by the voltage detection unit after the power is turned on, the operation timing can be controlled to meet specific conditions (for example, performance requirements, etc.) for various scenarios of temperature and power voltage (for example, low voltage at low temperature, high voltage at low temperature, low voltage at high temperature, high voltage at high temperature, etc.). Therefore, for example, compared with the case where the operation timing is controlled only based on the number of rising edges or falling edges of the signal output from the ring oscillator, the operation timing according to the environment during use can be more appropriately controlled, and therefore, a semiconductor memory device with improved performance for improving the transmission speed, etc. can be realized. Furthermore, according to the present invention, for example, since the operation timing can be controlled at any timing after each power is turned on, the operation timing can be appropriately controlled according to the time change of the environment when the semiconductor memory device is used.

[0012] In the above invention, in the power-on sequence executed when the power supply of the semiconductor memory device is turned on, the operation sequence of the semiconductor memory device can be controlled.

[0013] According to the present invention, the operation timing can be appropriately controlled based on the temperature and power supply voltage of the semiconductor memory device during the period from when the power supply is turned on to when the normal operation of the semiconductor memory device begins.

[0014] In the above invention, when a specific command is input to the semiconductor memory device, the control unit may control the operation timing of the semiconductor memory device.

[0015] According to the present invention, for example, each time a specific instruction is input into the above-mentioned semiconductor memory device, the operation timing is appropriately controlled based on the temperature and power supply voltage of the semiconductor memory device when the instruction is input. Therefore, the operation timing can be appropriately controlled in accordance with the time changes of the environment when the semiconductor memory device is used.

[0016] In the above invention, before executing the specific command, the control unit may control the operation timing of the semiconductor memory device.

[0017] According to the present invention, since a specific instruction can be executed based on the controlled operation sequence, the instruction can be appropriately executed according to the environment at the time of use.

[0018] In the above invention, when the semiconductor memory device includes a memory that requires a refresh operation, the control section may control the operation timing of the semiconductor memory device while the memory performs the refresh operation.

[0019] According to the present invention, for example, since the operation timing is appropriately controlled based on the temperature and power supply voltage of the semiconductor memory device when the update instruction is executed each time the memory update operation is executed, the operation timing can be appropriately controlled in accordance with the time change of the environment when the semiconductor memory device is used. Furthermore, according to the present invention, since the operation timing can be controlled during the execution of the update operation (that is, when a specific instruction (for example, a valid instruction such as a read instruction and a write instruction) is not executed), the operation timing can be controlled without interfering with the specific instruction being executed.

[0020] In the above invention, the control unit can control the operation timing using the temperature detected by the temperature sensor, the power supply voltage detected by the voltage detection unit, and a lookup table corresponding to the delay amount of the operation timing in the semiconductor memory device.

[0021] According to the present invention, the delay amount of the operation timing corresponding to the detected temperature and power supply voltage is extracted from the lookup table, and the operation timing can be simply and appropriately controlled based on the extracted delay amount of the operation timing.

[0022] In the above invention, the voltage detection unit may detect the power supply voltage based on the number of switching times of a signal output from a specific ring oscillator operated by the power supply voltage.

[0023] According to the present invention, for example, the more times the signal output from the ring oscillator switches, the higher the detected power supply voltage; and the fewer times the signal switches, the lower the detected power supply voltage, so the operation timing can be appropriately controlled using the signal switching times.

[0024] Here, a high power supply voltage of a semiconductor memory device has the same effect as a high processing speed of the semiconductor memory device; a low power supply voltage of a semiconductor memory device has the same effect as a slow processing speed of the semiconductor memory device. Therefore, detecting that the power supply voltage of a semiconductor memory device is high is actually detecting that the processing speed of the semiconductor memory device is fast; detecting that the power supply voltage of a semiconductor memory device is low is actually detecting that the processing speed of the semiconductor memory device is slow. Furthermore, in the following description, it should be noted that the processing of a semiconductor memory device (e.g., high speed, medium speed, or low speed) can be described together with the corresponding power supply voltage (e.g., high voltage, medium voltage, or low voltage).

[0025] [Effects of the invention]

[0026] According to the semiconductor memory device of the present invention, the operation timing can be more appropriately controlled according to the use environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram showing the configuration of a control unit of a semiconductor memory device according to the first embodiment of the present invention.

[0028] Figure 2 This is a timing diagram of the voltage changes of various signals in the control unit.

[0029] Figure 3 (a) to (c) are example diagrams of the configuration of the query table.

[0030] Figure 4 This is a graph showing the time variation of the signal voltage of each part in the control unit when a specific command is input.

[0031] Figure 5 (a) to (b) are example diagrams of the control state of the operation timing corresponding to the power supply voltage at a high temperature, and (c) to (d) are example diagrams of the control state of the operation timing corresponding to the power supply voltage at a low temperature.

[0032] Figure 6 FIG. 1 is a diagram showing an example configuration of a semiconductor storage device according to a second embodiment of the present invention.

[0033] Figure 7 FIG. 1 is a diagram showing an example configuration of a semiconductor storage device according to a third embodiment of the present invention.

[0034] Figure 8 This is a timing diagram of the voltage changes of various signals in the control unit.

[0035] Fig. 9 This is a timing diagram showing the voltage changes of various signals in the control unit when the refresh operation is performed.

[0036] Explanation of symbols:

[0037] 10. Control Unit

[0038] 11~Power on timing control unit

[0039] 12~Timing control unit

[0040] 13~First Oscillator

[0041] 14~Ring Oscillator

[0042] 15~Counter

[0043] 16~Query table

[0044] 17~Timing setting section

[0045] 18. Temperature sensor

[0046] 19~Second Oscillator

[0047] VDD~Power supply voltage

[0048] PCHRDY~Pre-chip preparation signal

[0049] OSC~Oscillating signal

[0050] CHRDY~Chip preparation signal

[0051] CNTEN~Signal output to ring oscillator 14

[0052] PACT - A signal from the command decoder indicating that a specific command has been input into the semiconductor memory device.

[0053] TRMEN~Signal for effective timing control processing

[0054] CALC: A signal for requesting an operation timing corresponding to the temperature and power supply voltage of a semiconductor memory device.

[0055] TMP<1:0>: A signal indicating the temperature range input from the temperature sensor 18.

[0056] CHG - signal output to the timing setting unit 17

[0057] RINGO~Oscillating signal

[0058] CNT<4:0>~Signal indicating the count value

[0059] PTIM<4:0>~Signal input from lookup table 16

[0060] TIM<4:0>~Signal to set operation timing

[0061] tWLS~Set time

[0062] tWLH~hold time

[0063] SRTRIG~Signal used to trigger update operation

[0064] SREF~ indicates a signal that requires an update operation to be performed DETAILED DESCRIPTION

[0065] Hereinafter, a semiconductor memory device according to embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments.

[0066] [Example 1]

[0067] Figure 1 This is a block diagram of the configuration of the control section of the semiconductor memory device related to the first embodiment of the present invention. The semiconductor memory device related to the embodiment of the present invention includes a control section 10, an interface section (not shown) for sending and receiving signals (e.g., chip selection signal, data signal, data strobe signal, clock signal, etc.) between external devices (e.g., memory controller, etc.), and a memory array (not shown) having a plurality of memory cells arranged in a matrix. The control section 10, the interface section, and the memory array are each composed of a dedicated hardware device and a logic circuit.

[0068] Based on a write request received from an external device of the interface section, the control section 10 controls data writing to the memory array. Furthermore, based on a read request received from an external device of the interface section, the control section 10 controls data reading from the memory array. Further, according to the temperature detected by the temperature sensor 18 (to be described below) after the power is turned on, and the power supply voltage detected by the voltage detection section (to be described below) after the power is turned on, the control section 10 controls the operation timing within the semiconductor memory device to meet specific conditions (for example, performance requirements).

[0069] Furthermore, in the power-on sequence implemented when the semiconductor memory device is powered on, the control unit 10 can control the operation sequence in the semiconductor memory device. Therefore, from the time when the power is turned on to the time when the normal operation of the semiconductor memory device begins, the operation sequence can be appropriately controlled based on the temperature and power supply voltage of the semiconductor memory device.

[0070] Furthermore, when a specific command (e.g., a valid command such as a read command and a write command) is input to the semiconductor memory device, the control unit 10 controls the operation timing in the semiconductor memory device. Therefore, since the operation timing is appropriately controlled based on the temperature and power supply voltage of the semiconductor memory device when the specific command is input each time, the operation timing can be appropriately controlled in accordance with the time change of the environment when the semiconductor memory device is used.

[0071] Furthermore, before executing a specific command, the control unit 10 may control the operation sequence in the semiconductor memory device. Thus, since the specific command can be executed based on the controlled operation sequence, the command can be appropriately executed according to the environment when used.

[0072] Furthermore, the control unit 10 can control the operation timing by using the temperature detected by the temperature sensor 18, the power supply voltage detected by the voltage detection unit (to be described below), and the lookup table 16 (to be described below) corresponding to the delay amount of the operation timing in the semiconductor memory device. Therefore, the delay amount of the operation timing corresponding to the detected temperature and power supply voltage is extracted from the lookup table 16, and the operation timing can be simply and appropriately controlled based on the extracted delay amount of the operation timing.

[0073] Furthermore, based on the number of switching times of the signal outputted by the specific ring oscillator 14 (described below) that operates according to the power supply voltage, the voltage detection unit (described below) can detect the power supply voltage. Thus, for example, since the more the number of switching times of the signal outputted from the ring oscillator 14 is, the higher the detected power supply voltage is, and the fewer the number of switching times of the signal is, the lower the detected power supply voltage is, the operation timing can be appropriately controlled using the number of signal switching times.

[0074] Furthermore, in this embodiment, the control unit 10 controls the setup time (Write leveling setup time, tWLS) and the hold time (Write leveling hold time, tWLH) of the clock signal when requesting data writing.

[0075] Reference Figure 1 , the configuration of the control unit 10 will be described. The control unit 10 includes a power-on timing control unit 11, a timing control unit 12, a first oscillator 13, a ring oscillator 14, a counter 15, a lookup table 16, a timing setting unit 17, and a temperature sensor 18. In addition, for the sake of simplicity, the peripheral configuration of the semiconductor memory device (for example, the configuration for controlling the instruction decoder, the memory array, and the interface unit, etc.) is not shown.

[0076] When the semiconductor memory device is powered on and the external power supply voltage VDD is applied, the power-on sequence control unit 11 executes a specific power-on sequence. Here, the power-on sequence includes, for example, generating an initial internal power supply based on the external power supply voltage VDD, reading a trimming code for adjusting the internal power supply voltage, and adjusting the internal power supply voltage based on the external power supply voltage VDD and the trimming code. Furthermore, when the power-on sequence is completed, the power-on sequence control unit 11 outputs a pre-wafer preparation signal PCHRDY indicating the end of the power-on sequence to the sequence control unit 12.

[0077] When the pre-wafer preparation signal PCHRDY is input, the timing control section 12 outputs a signal TRMEN for valid timing control processing to the first oscillator 13. Furthermore, the timing control section 12 outputs a signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18. Furthermore, the timing control section 12 outputs a signal CALC of an operation timing required according to the temperature and power supply voltage of the semiconductor memory device to the lookup table 16.

[0078] Furthermore, the timing control section 12 outputs a signal CHG for setting the required operation timing to the timing setting section 17. Furthermore, when the signal CHG is output to the timing setting section 17, the timing control section 12 outputs a chip preparation signal CHRDY indicating that the semiconductor memory device is in an access state (chip preparation state (standby state)) to other devices or circuits (not shown) in the control section 10.

[0079] Furthermore, when a signal PACT indicating that a specific command has been input to the semiconductor memory device is input from a command decoder (not shown), the timing control section 12 outputs a signal CHG to the timing setting section 17 .

[0080] While the high-level signal TRMEN is input from the timing control unit 12 , the first oscillator 13 generates an oscillation signal OSC at specific intervals and outputs the oscillation signal OSC to the timing control unit 12 and the ring oscillator 14 .

[0081] The ring oscillator 14 is configured to operate by an external power supply or an internal power supply voltage (power supply voltage), and outputs an oscillation signal RINGO having a frequency corresponding to the power supply voltage to the counter 15 during the input of the high-level signal TRMEN from the timing control section 12. Here, the ring oscillator 14 is configured to output a high-frequency (that is, a high switching number) oscillation signal RINGO as the power supply voltage is higher. Furthermore, in order to control the correct operation timing, the ring oscillator 14 may also be composed of the same device or circuit as the device or circuit to be controlled by the operation timing (for example, an input buffer in the interface section or a circuit to which a signal output from the input buffer is input, etc.), and operate using the same power supply.

[0082] When the oscillation signal RINGO is input from the ring oscillator 14, the counter 15 counts the number of switching times of the oscillation signal RINGO. Then, the counter 15 outputs the signal CNT<4:0> indicating a specific number of bits (here, 5 bits) of the count value to the lookup table 16. Furthermore, during the period from the timing control unit 12 to the ring oscillator 14 when the high-level signal CNTEN is newly input, the value of the signal CNT<4:0> can be maintained in the counter 15. Furthermore, in the present embodiment, the ring oscillator 14 and the counter 15 are examples of the "voltage detection unit" of the present invention.

[0083] During the input of the high-level signal TRMEN from the timing control unit 12, the lookup table 16 outputs the signal PTIM<4:0> indicating the delay amount of the operation timing (here, the setup time (tWLS) and the hold time (tWLH)) of a specific number of bits (here, 5 bits) to the timing setting unit 17 according to the signal CNT<4:0> input from the counter 15 and the signal TMP<1:0> indicating the specific number of bits (here, 2 bits) of the temperature range input from the temperature sensor 18. The configuration example of the lookup table is as follows.

[0084] When a high-level signal TRMEN is input from the timing control unit 12, the timing setting unit 17 outputs the signal PTIM<4:0> input from the lookup table 16 as a signal TIM<4:0> for setting a specific number of bits (here, 5 bits) of the operation timing to a device or circuit (for example, a delay circuit, etc.) for controlling the operation timing of the device or circuit that is the control object of the operation timing.

[0085] When a high-level signal TRMEN is input from the timing control unit 12, the temperature sensor 18 detects the temperature of the semiconductor memory device and outputs a signal TMP<1:0> of a specific number of bits (here, 2 bits) corresponding to the temperature range (e.g., high temperature, medium temperature, low temperature, etc.) corresponding to the detected temperature to the timing setting unit 17. Furthermore, when a signal PACT is input from a command decoder (not shown) indicating that a specific command has been input to the semiconductor memory device, the temperature sensor 18 detects the temperature of the semiconductor memory device and inputs the signal TMP<1:0> to the timing setting unit 17. Furthermore, the value of the signal TMP<1:0> can be maintained in the temperature sensor 18 during the period from the timing control unit 12 to the new input of the high-level signal CNTEN.

[0086] Next, the operation of the semiconductor memory device of this embodiment will be described with reference to Figure 2 illustrate. Figure 2 This is a graph showing the time variation of the voltage of each signal in the control unit.

[0087] First, when the pre-chip preparation signal PCHRDY indicating the end of the power-on sequence is input, the timing control unit 12 outputs a high-level signal TRMEN to the first oscillator 13. During the input of the high-level signal TRMEN, the first oscillator 13 generates an oscillation signal OSC at a specific interval and outputs it to the timing control unit 12 and the ring oscillator 14.

[0088] At time t1, the timing control unit 12 outputs a high-level signal CNTEN to the ring oscillator 14 and the temperature sensor 18. During the period of outputting the high-level signal CNTEN, the ring oscillator 14 outputs an oscillation signal RINGO having a frequency corresponding to the power supply voltage to the counter 15. Furthermore, the counter 15 counts the number of switching times of the oscillation signal RINGO, and outputs a signal CNT<4:0> indicating the count value to the lookup table 16.

[0089] Here, in this embodiment, the switching times of the oscillation signal RINGO are classified into one of a specific number (here, 3) of temperature ranges according to the temperature range corresponding to the temperature of the semiconductor memory device detected by the temperature sensor 18. Figure 2 In the example, when the value of the signal CNT<4:0> is 12, the power supply voltage of the semiconductor storage device is classified as low voltage (slow-speed processing), when the value of the signal CNT<4:0> is 16, the power supply voltage of the semiconductor storage device is classified as medium voltage (medium-speed processing), and when the value of the signal CNT<4:0> is 21, the power supply voltage of the semiconductor storage device is high voltage (high-speed processing).

[0090] Furthermore, when the high-level signal CNTEN is input from the timing control unit 12 , the temperature sensor 18 detects the temperature of the semiconductor memory device and outputs a signal TMP<1:0> indicating a temperature range (eg, high temperature, medium temperature, low temperature) corresponding to the detected temperature to the lookup table 16 .

[0091] Next, at time t2, the timing control unit 12 outputs a high-level signal CALC to the lookup table 16. The lookup table 16 determines the delay amount based on the signal CNT<4:0> input from the counter 15 and the signal TMP<4:0> indicating the temperature range input from the temperature sensor 18.

[0092] Here, refer to Figure 3 , an example of a method for determining the delay amount will be described. Figure 3 (a) to (c) are configuration diagrams of the query table 16. Figure 3 As shown in (a), the value of each signal PTIM<4:0> in Table 16 is searched ( Figure 3 In (a), 0 to 31) will correspond to a delay amount. Figure 3 In the example (a), as the value of the signal PTIM<4:0> increases from 0 to 15, the delay increases in the positive direction; as the value of the signal PTIM<4:0> increases from 16 to 31, the delay increases in the negative direction. Figure 3In (a), x is an arbitrary positive number. Furthermore, in this embodiment, according to the delay in the positive direction, the setup time (tWLS) of the clock signal is improved; according to the delay in the negative direction, the hold time (tWLH) of the clock signal is improved.

[0093] Furthermore, as Figure 3 shown in (b), for each specified number (here, 3) of temperature ranges and each specified number (here, 3) of voltage ranges in the lookup table 16, they correspond to the value of the signal CNT<4:0>. Furthermore, in Figure 3 (b), y1, y2, y3, and y4 (y1 < y2 < y3 < y4) are arbitrary numbers. Here, for example, when the value of the signal TMP<1:0> is 0b01 and the value of the signal CNT<4:0> is 16, the power supply voltage is judged to be medium voltage. Furthermore, when the value of the signal TMP<1:0> is 0b11 and the value of the signal CNT<4:0> is 21, the power supply voltage is judged to be high voltage.

[0094] Furthermore, as Figure 3 shown in (c), for each specified number (here, 3) of temperature ranges and each specified number (here, 3) of voltage ranges in the lookup table 16, they correspond to the value of the signal PTIM<4:0>. In Figure 3 (c), when the temperature of the semiconductor memory device is low (when the value of the signal TMP<1:0> is 0b00), the lower the power supply voltage, the larger the absolute value of the delay amount; when the temperature of the semiconductor memory device is high (when the value of the signal TMP<1:0> is 0b11), the higher the power supply voltage, the larger the absolute value of the delay amount.

[0095] Here, as described above, when the value of the signal TMP<1:0> is 0b01 and the value of the signal CNT<4:0> is 16 (that is, at medium voltage), it is determined that the value of the signal PTIM<4:0> is 0 ( Figure 3 in (a), 0 ps). Furthermore, when the value of the signal TMP<1:0> is 0b11 and the value of the signal CNT<4:0> is 21 (that is, at high voltage), it is determined that the value of the signal PTIM<4:0> is 5 ( Figure 3 in (a), +5x ps).

[0096] Therefore, according to the signal CNT<4:0> input from the counter 15 and the signal TMP<1:0> representing the temperature range input from the temperature sensor 18, the delay amount is determined.

[0097] Return to Figure 2At time t3, the timing control unit 12 outputs the high-level signal CHG to the timing setting unit 17. The timing setting unit 17 outputs the signal PTIM<4:0> input from the lookup table 16 as a signal TIM<4:0> for setting the operation timing to a device or circuit (e.g., a delay circuit, etc.) for controlling the operation timing of the device or circuit that is the control target of the operation timing.

[0098] Furthermore, the timing control unit 12 outputs a chip preparation signal CHRDY indicating that the semiconductor memory device is in an access state (chip preparation state (standby state)) to other devices or circuits (not shown) in the control unit 10 .

[0099] Therefore, in the power-on sequence performed when the power supply of the semiconductor memory device is turned on, the operation sequence in the semiconductor memory device can be controlled.

[0100] Receiver, reference Figure 4 An example of controlling the operation timing within the semiconductor memory device when a specified command is input will be described. Figure 4 This is a timing diagram showing the voltage changes of various signals in the control unit when a specific instruction is input.

[0101] First, it is assumed that the semiconductor memory device is in a standby state. In this state, the timing control unit 12 outputs a high-level signal CNTEN to the temperature sensor 18 at arbitrary intervals.

[0102] At time t11, when a signal PACT indicating that a specific command has been input to the semiconductor memory device is input from a command decoder (not shown), the timing control unit 12 outputs a high-level signal CALC to the lookup table 16. Based on the signal CNT<4:0> input from the counter 15 and the signal TMP<4:0> indicating the temperature range input from the temperature sensor 18, the lookup table 16 outputs a signal PTIM<4:0> indicating the determined delay amount to the timing setting unit 17.

[0103] Next, at time t12, the timing control section 12 outputs the high-level signal CHG to the timing setting section 17. The timing setting section 17 outputs the signal TIM<4:0> to a device or circuit (eg, a delay circuit) for controlling the operation timing of the device or circuit to be controlled.

[0104] Furthermore, at time t13 , when the timing control unit 12 starts to execute the designated command, it can control other devices or circuits in the control unit 10 .

[0105] Therefore, when a designated command is input, the operation timing within the semiconductor memory device can be controlled.

[0106] Figure 5 An example of a control mode of the operation timing of the semiconductor memory device according to the first embodiment is shown. Figure 5 (a) to (b) are example diagrams of the control state of the operation timing corresponding to the power supply voltage at high temperature. Figure 5 (c) to (d) are exemplary diagrams of control states of operation timing corresponding to power supply voltage at low temperatures.

[0107] like Figure 5 As shown in (a), when the semiconductor memory device is at high temperature, the higher the power supply voltage is, the less the setting time tWLS can meet the performance requirements. Here, as described above, at high temperature, by controlling the operation timing so that the absolute value of the delay amount increases as the power supply voltage increases, the setting time tWLS can meet the performance requirements even if the power supply voltage increases. Figure 5 As shown in (b), the hold time tWLH can also meet the performance requirements.

[0108] Furthermore, if Figure 5 As shown in (d), when the semiconductor memory device is at a low temperature, it is assumed that the lower the voltage power supply, the retention time tWLH cannot meet the performance requirements. Here, as described above, at a low temperature, by controlling the operation timing so that the absolute value of the delay amount increases as the power supply voltage decreases, the retention time tWLH can meet the performance requirements even if the power supply voltage decreases. Here, as Figure 5 As shown in (c), setting the time tWLS can also meet the performance requirements.

[0109] As described above, according to the semiconductor memory device of the present embodiment, since the operation timing in the semiconductor memory device is controlled to meet the performance requirement (specific condition) according to the temperature detected by the temperature sensor 18 after the power is turned on and the power supply voltage detected by the ring oscillator 14 and the counter 15 (voltage detection unit) after the power is turned on, the operation timing can be controlled to meet the specific condition (for example, performance requirement, etc.) for various scenarios of temperature and power supply voltage (for example, low voltage at low temperature, high voltage at low temperature, low voltage at high temperature, high voltage at high temperature, etc.). Therefore, for example, compared with the case where the operation timing is controlled based only on the number of rising edges or falling edges of the signal output from the ring oscillator 14, the operation timing according to the environment at the time of use can be more appropriately controlled, and therefore, a semiconductor memory device with improved performance applied to increase the transmission speed, etc. can be realized. Furthermore, according to the semiconductor memory device of the present embodiment, for example, since the operation timing can be controlled at any timing after each power is turned on, the operation timing can be appropriately controlled according to the time change of the environment when the semiconductor memory device is used.

[0110] Furthermore, according to the semiconductor memory device of this embodiment, since the operation timing can be controlled after the power is turned on, for example, the process of presetting the operation timing can be omitted during the test process during manufacturing, thereby simplifying the test process during manufacturing of the semiconductor memory device.

[0111] [Example 2]

[0112] Hereinafter, description will be given regarding Embodiment 2 of the present invention. The semiconductor memory device of this embodiment is different from Embodiment 1 in that operation timing is controlled when a predefined command is input. Hereinafter, description will be given regarding a configuration different from Embodiment 1.

[0113] Figure 6 FIG. 2 is a diagram showing a configuration of a semiconductor memory device related to this embodiment. Figure 6 In the example of , a signal CMD indicating that a predefined command is input to the semiconductor memory device is input to the timing control unit 12 from a command decoder (not shown).

[0114] Here, the predefined command may be, for example, an instruction for executing only the timing of the control operation, or an instruction composed of a combination of the instruction for executing the timing of the control operation and the specified instruction. Furthermore, the specified instruction included in the predefined command may be, for example, a read instruction, a write instruction, or an instruction requiring relatively high timing accuracy (e.g., read leveling and write leveling, etc.).

[0115] In this embodiment, when the signal CMD is input from the command decoder (not shown), the timing control section 12 outputs the signal TRMEN for valid timing control processing to the first oscillator 13. Furthermore, the timing control section 12 outputs the signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18. Furthermore, the timing control section 12 outputs the signal CALC for requesting the operation timing corresponding to the temperature and power supply voltage of the semiconductor memory device to the lookup table 16.

[0116] Furthermore, the timing control section 12 outputs a signal CHG for setting the required operation timing to the timing setting section 17. Furthermore, when the signal CHG is output to the timing setting section 17, the timing control section 12 executes other instructions (e.g., read instructions, write instructions, read leveling, and write leveling, etc.) included in the predefined commands to control other devices or circuits in the control section 10.

[0117] Therefore, according to the semiconductor memory device of this embodiment, the same effects as those of the above-mentioned first embodiment can be achieved.

[0118] [Example 3]

[0119] Hereinafter, the third embodiment of the present invention will be described. The semiconductor memory device of this embodiment is different from the above-mentioned embodiments in that, when there is a memory requiring a refresh operation, the operation timing in the semiconductor memory device is controlled during the execution of the memory refresh operation. Hereinafter, the configuration different from the above-mentioned embodiments will be described.

[0120] Furthermore, the semiconductor memory device of this embodiment may be a semiconductor memory device (eg, DRAM, pSRAM, etc.) that requires a memory refresh operation.

[0121] Figure 7 1 is a configuration diagram of the control unit 10 of the semiconductor memory device related to the present embodiment. In the present embodiment, the control unit 10 further includes a second oscillator 19 in addition to the above-mentioned units 11 to 18. Furthermore, in the present embodiment, the timing control unit 12 and the temperature sensor 18 are configured to input a signal SREF indicating a request to execute a refresh operation from a command decoder (not shown).

[0122] When the wafer preparation signal CHRDY is input from the timing control section 12 , the second oscillator 19 generates a signal SRTRIG for triggering a refresh operation at a specific interval and outputs the signal to the timing control section 12 .

[0123] Furthermore, when there are no characteristics related to the temperature and the power supply voltage of the semiconductor memory device, the first oscillator 13 and the second oscillator 19 can set either one of the first oscillator 13 and the second oscillator 19 to perform the respective functions of the first oscillator 13 and the second oscillator 19 .

[0124] Next, the operation of the semiconductor memory device of this embodiment will be described with reference to Figure 8 illustrate. Figure 8 1 is a timing diagram of the signal voltage changes of each part in the control unit 10. Here, it is assumed that each time the signal SRTRIG switches four times, the operation timing is determined at the falling edge of the fourth signal SRTRIG, and each time the signal SRTRIG switches twice, the high potential quasi signal SREF is input to the timing control unit 12 at the rising edge of the second signal SRTRIG.

[0125] First, at time t21, when the operation timing is started to be determined, the timing control section 12 outputs a signal TRMEN of effective timing control processing to the first oscillator 13. Furthermore, the timing control section 12 outputs a signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18. Furthermore, the timing control section 12 outputs a signal CALC of the operation timing required according to the temperature and power supply voltage of the semiconductor memory device to the lookup table 16.

[0126] Next, at time t22, when the high-level signal SREF is input to the timing control section 12, the timing control section 12 sets the operation timing when the refresh operation starts.

[0127] Fig. 9 A timing diagram showing the voltage changes of various signals in the control unit 10 when the refresh operation is performed. At time t31, when the high potential signal SREF is input from the command decoder (not shown), the timing control unit 12 outputs the high potential signal CALC to the lookup table. The lookup table 16 determines the delay amount based on the signal CNT<4:0> input from the counter 15 and the signal TMP<4:0> indicating the temperature range input from the temperature sensor 18, and outputs the signal PTIM<4:0> indicating the determined delay amount to the timing setting unit 17.

[0128] Next, at time t32, the timing control section 12 outputs the high-level signal CHG to the timing control section 17. Then, the timing control section 17 outputs the signal TIM<4:0> to a device or circuit (e.g., a delay circuit, etc.) for controlling the operation timing of the device or circuit that is the control target of the operation timing. Furthermore, the timing control section 12 performs the refresh operation to control other devices or circuits in the control section 10.

[0129] Furthermore, the timing control unit 12 performs a refresh operation to control other devices or circuits within the control unit 10 .

[0130] Back to Figure 8 At time t23, when a signal indicating that a read or write command is input from a command decoder (not shown), the timing control unit 12 executes the read or write command to control other devices or circuits in the control unit 10. In the above case, during the period from time t22 to time t23, the read or write command is executed according to the controlled operation timing.

[0131] Next, at time t24, when the high potential signal SREF is input to the timing control section 12, the timing control section 12 sets the operation timing when starting to perform the refresh operation.

[0132] Then, at time t25, when the operation timing is started to be determined, the timing control section 12 outputs a signal TRMEN for valid timing control processing to the first oscillator 13. Furthermore, the timing control section 12 outputs a signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18. Furthermore, the timing control section 12 outputs a signal CALC for the operation timing required according to the temperature and power supply voltage of the semiconductor memory device to the lookup table 16.

[0133] Here, before inputting the high-level signal SREF to the timing control unit 12, when a signal indicating that a read or write command has been input is input from a command decoder (not shown), the timing control unit 12 keeps the signal SREF at a high level and executes the read or write command to control other devices or circuits in the control unit 10. Then, at time t26 after the execution of the read or write command is completed, the timing control unit 12 starts to execute the update operation (such as Fig. 9 as shown, including setting operation timing).

[0134] Then, at time t27, when the high potential signal SREF is input to the timing control unit 12, the timing control unit 12 starts to perform the refresh operation (eg, Fig. 9 Here, during the execution of the refresh operation, when a signal indicating that a read or write command has been inputted is inputted from a command decoder (not shown), at time t28 after the refresh operation is completed, the timing control unit 12 executes the read or write command to control other devices or circuits in the control unit 10.

[0135] As described above, according to the semiconductor memory device of the present embodiment, for example, since each time a memory update operation is performed, the operation timing can be appropriately controlled according to the temperature and power supply voltage of the semiconductor memory device in which the update operation is performed, the operation timing can be appropriately controlled in accordance with the time change of the environment when the semiconductor memory device is used. Furthermore, according to the semiconductor memory device of the present embodiment, since the operation timing can be controlled during the execution of the update operation (that is, when a specific instruction (for example, a valid instruction such as a read instruction and a write instruction, etc.) is not executed), the operation timing can be controlled without interfering with the specific instruction being executed.

[0136] The above-mentioned embodiments are used to simply understand the present invention and are not described to limit the present invention. Therefore, the various features shown in the above-mentioned embodiments are intended to include all design changes and equivalents belonging to the technical scope of the present invention.

[0137] For example, in the above-mentioned embodiments, the case where the setup time (tWLS) and the hold time (tWLH) of the clock signal are controlled when data writing is required is described as an example, but the present invention is not limited to this case. For example, the setup time and the hold time of the clock signal can be controlled when data reading is required, and other operation timings (for example, low word line activation timing, sense amplifier activation timing, field line activation timing, etc.) can also be controlled.

[0138] Furthermore, in each of the above-mentioned embodiments, the temperature of the semiconductor memory device is classified into any one of three temperature ranges, and the power supply voltage of the semiconductor memory device is classified into any one of three voltage ranges. However, the present invention is not limited to this case. For example, the temperature of the semiconductor memory device may be classified into any one of a plurality of temperature ranges other than three, and the power supply voltage of the semiconductor memory device may be classified into any one of a plurality of power supply ranges other than three.

[0139] Furthermore, in each of the above-mentioned embodiments, the configuration of the control unit 10 is an example, and it is possible to appropriately change or adopt various other configurations.

Claims

1. A semiconductor storage device, characterized in that: include: A temperature sensor for detecting the temperature of the semiconductor storage device; a voltage detection unit for detecting a power supply voltage of the semiconductor memory device; as well as a control unit that controls the operation timing in the semiconductor memory device to meet a specific condition based on the temperature detected by the temperature sensor after the power is turned on and the power voltage detected by the voltage detection unit after the power is turned on; When the semiconductor memory device has a memory that requires a refresh operation, the control unit controls the operation timing during the execution of the memory refresh operation; The control unit also includes an oscillator. The control unit and the temperature sensor are configured to input a signal indicating a requirement to execute the memory update operation from a command decoder. When a chip preparation signal is input from the control unit, the oscillator generates a signal for triggering the memory update operation at specific intervals and outputs the signal to the control unit.

2. The semiconductor memory device according to claim 1, wherein The control section controls the operation sequence in a power-on sequence executed when the power supply of the semiconductor memory device is turned on.

3. The semiconductor memory device according to claim 1, wherein: The control unit controls the operation timing when a specific command is input to the semiconductor memory device.

4. The semiconductor memory device according to claim 3, wherein: The control unit controls the operation sequence before the specific instruction is executed.

5. The semiconductor memory device according to claim 1, wherein: The control unit controls the operation timing by using the temperature detected by the temperature sensor, the power supply voltage detected by the voltage detection unit, and a lookup table corresponding to the delay amount of the operation timing in the semiconductor memory device.

6. The semiconductor memory device according to claim 1, wherein: The voltage detection unit detects the power supply voltage based on the number of switching times of a signal output by a specific ring oscillator operated by the power supply voltage.

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