Method for manufacturing a display device

Abstract

The present invention provides a method for manufacturing a display device, which reduces the source / drain resistance and realizes a TFT having stable Vd-Id characteristics in a display device having a TFT composed of an oxide semiconductor. A display device having a plurality of pixels each including a thin film transistor (TFT) composed of an oxide semiconductor (105), a channel is formed in the oxide semiconductor, a drain and a source are formed on both sides of the channel, an intermediate region is formed between the channel and the drain or between the channel and the source, a gate insulating film (106) is formed over the channel and the intermediate region of the oxide semiconductor, an alumina film (107) is formed over the gate insulating film, a gate electrode (109) is formed over the channel and over the alumina film, sidewall spacers (108) are formed on both sides of the gate electrode, and an interlayer insulating film (110) is formed so as to cover the gate electrode, the sidewall spacers, the source, and the drain.

Description

[0001] This application is a divisional application of a patent application for an invention titled "Display Device" with an application date of November 28, 2018, an international application number of PCT / JP2018 / 043661, and a national application number of 201880083528.6. Technical Field

[0002] The present invention relates to a display device, and more particularly to a display device having a TFT using an oxide semiconductor. Background Art

[0003] An organic EL display device includes a driving transistor and a switching transistor formed of a TFT (Thin Film Transistor) in each pixel. In addition, a liquid crystal display device includes a switching transistor formed of a TFT in each pixel. Therefore, the characteristics of the TFT are important.

[0004] An oxide semiconductor has a high OFF resistance, and when used in a TFT, it can reduce the OFF current. Therefore, it is possible to reduce the change in the pixel electrode potential. In addition, a TFT using an oxide semiconductor can be formed at a lower temperature compared to a TFT using polysilicon or the like, and thus a display device using a resin substrate can be realized.

[0005] In a TFT, electric field concentration occurs between the channel and the drain, and there is a risk of dielectric breakdown in this part. Therefore, in a TFT using polysilicon (poly-Si), an LDD (Lightly Doped Drain) region is formed between the channel and the drain to prevent dielectric breakdown in this part.

[0006] In a TFT using an oxide semiconductor, in order to form the drain and source, a process of imparting conductivity to a part of the oxide semiconductor by supplying hydrogen to the drain and source parts is performed. Patent Document 1 describes the following configuration: hydrogen supplied to the drain and source diffuses to form a region that plays the same role as the LDD region, that is, a region having a resistance smaller than that of the channel region and larger than that of the drain or source is formed between the channel and the drain or source.

[0007] Prior Art Documents

[0008] Patent Documents

[0009] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-85079 Summary of the Invention

[0010] Problems to be Solved by the Invention

[0011] As described in Patent Document 1, in the method of forming an intermediate resistance portion by annealing to diffuse hydrogen to the lower side of the gate electrode, it is difficult to control the diffusion region of hydrogen. In particular, if the channel length becomes smaller, there is a risk that the TFT will deplete. If more hydrogen is supplied to the drain and source in order to reduce the resistance of the drain and source, the risk of depletion further increases.

[0012] The subject of the present invention is to obtain the following configuration, that is, in a TFT using an oxide semiconductor, an intermediate region can be stably formed between the channel and the drain and source. In addition, the subject of the present invention is to realize a TFT using an oxide semiconductor having stable characteristics.

[0013] Means for Solving the Problem

[0014] The present invention can overcome the above problems, and the specific means are as follows.

[0015] (1) A display device having a plurality of pixels each including a thin film transistor (TFT) formed of an oxide semiconductor, characterized in that a channel is formed in the oxide semiconductor, a drain and a source are formed on both sides of the channel, an intermediate region is formed between the channel and the drain and between the channel and the source, a gate insulating film is formed over the channel and the intermediate region of the oxide semiconductor, an alumina film is formed over the gate insulating film, a gate electrode is formed over the channel and over the alumina film, sidewall spacers are formed on both sides of the gate electrode, and an interlayer insulating film is formed to cover the gate electrode, the sidewall spacers, the source, and the drain.

[0016] (2) The display device according to (1), characterized in that, when viewed from above, the channel is formed in a portion of the oxide semiconductor that overlaps a portion in contact with the gate electrode and the alumina film, and similarly, the intermediate region of the oxide semiconductor is formed in a portion corresponding to the sidewall spacer.

[0017] (3) The display device according to (1), characterized in that the interlayer insulating film is in direct contact with the drain and the source of the oxide semiconductor.

[0018] (4) The display device according to (1), characterized in that the drain and the source of the oxide semiconductor are covered by the gate insulating film, and the interlayer insulating film is in contact with the gate insulating film.

[0019] The present invention provides the following technical solutions:

[0020] A display device includes a plurality of pixels each having a thin film transistor (TFT) formed of an oxide semiconductor. A gate insulating film is formed over the oxide semiconductor, an alumina film is formed over the gate insulating film, a gate electrode is formed over the alumina film, sidewall spacers are formed on both sides of the gate electrode, and an interlayer insulating film is formed to cover the gate electrode, the sidewall spacers, and source and drain electrodes. When viewed from above, in a direction connecting the drain and the source, the width of the gate electrode is formed to be smaller than the width of the alumina film.

[0021] In the above display device, a channel is formed in the oxide semiconductor, the drain and the source are formed on both sides of the channel, intermediate regions are formed between the channel and the drain and between the channel and the source, a gate insulating film is formed over the channel and the intermediate regions of the oxide semiconductor, and a gate electrode is formed above the channel and over the alumina film.

[0022] In the above display device, when viewed from above, the channel is formed in a portion overlapping with a portion where the oxide semiconductor contacts the gate electrode and the alumina film, and similarly, the intermediate regions are formed in portions overlapping with portions where the oxide semiconductor contacts the sidewall spacers and the alumina film.

[0023] In the above display device, the interlayer insulating film is in direct contact with the drain and the source of the oxide semiconductor.

[0024] In the above display device, a portion of the interlayer insulating film that contacts the drain and the source is formed of SiN.

[0025] In the above display device, the hydrogen content of the interlayer insulating film is greater than the hydrogen content of the sidewall spacers.

[0026] In the above display device, the order of the hydrogen content in the oxide semiconductor is channel < intermediate region < drain and source.

[0027] In the above display device, the channel has a channel length and a channel width. When one side of the sidewall spacer that contacts the alumina film is defined as the bottom and the side opposite to the bottom of the sidewall spacer is defined as the top, the length of the bottom in the channel length direction is greater than the length of the top in the channel length direction.

[0028] In the above display device, the length of the bottom in the channel length direction is greater than the length of the top in the channel length direction by 0.3 μm or more.

[0029] In the above display device, the height of the sidewall spacer is 100 nm to 500 nm.

[0030] In the above display device, the metal forming the gate electrode covers the side surface of the sidewall spacer and extends to the upper surface of the sidewall spacer.

[0031] In the above display device, the amount by which the metal forming the gate electrode extends on the upper surface of the sidewall spacer is 0.1 μm or more.

[0032] In the above display device, the side surface of the sidewall spacer on the side in contact with the interlayer insulating film is an inclined surface.

[0033] In the above display device, the drain and the source of the oxide semiconductor are covered by the gate insulating film, and the interlayer insulating film is in contact with the gate insulating film.

[0034] In the above display device, the portion of the interlayer insulating film in contact with the gate insulating film is formed of SiN.

[0035] In the above display device, the hydrogen content of the interlayer insulating film is greater than the hydrogen content of the sidewall spacer.

[0036] In the above display device, the order of the hydrogen content in the oxide semiconductor is channel < intermediate region < drain and source.

[0037] In the above display device, the channel has a channel length and a channel width. When the side of the sidewall spacer in contact with the alumina film is set as the bottom and the side of the sidewall spacer opposite to the bottom is set as the upper part, the length of the bottom in the channel length direction is greater than the length of the upper part in the channel length direction.

[0038] In the above display device, the display device is an organic EL display device.

[0039] In the above display device, the display device is a liquid crystal display device Brief Description of the Drawings

[0040] Figure 1 is a top view of an organic EL display device.

[0041] Figure 2 is a cross-sectional view of a display area of an organic EL display device as a comparative example.

[0042] Figure 3 shows Figure 2 a cross-sectional view of the problems of the configuration of.

[0043] Figure 4It is a cross-sectional view of the display area of the organic EL display device of the present invention.

[0044] Figure 5 It is a cross-sectional view of the TFT part of Example 1.

[0045] Figure 6 It is a top view of the TFT part of Example 1.

[0046] Figure 7 It is a cross-sectional view showing an intermediate process for forming the TFT of the present invention.

[0047] Figure 8 It shows the continuation for forming the TFT of the present invention Figure 7 of the intermediate process cross-sectional view.

[0048] Figure 9 It shows the continuation for forming the TFT of the present invention Figure 8 of the intermediate process cross-sectional view.

[0049] Figure 10 It shows the continuation for forming the TFT of the present invention Figure 9 of the intermediate process cross-sectional view.

[0050] Figure 11 It shows the continuation for forming the TFT of the present invention Figure 10 of the intermediate process cross-sectional view.

[0051] Figure 12 It shows the continuation for forming the TFT of the present invention Figure 11 of the intermediate process cross-sectional view.

[0052] Figure 13 It is a cross-sectional view of the display area of the organic EL display device of Example 2.

[0053] Figure 14 It is a cross-sectional view showing an intermediate process for forming the TFT of Example 2.

[0054] Figure 15 It is a cross-sectional view showing the completed state of the TFT of Example 2.

[0055] Figure 16 It is a top view of the liquid crystal display device.

[0056] Figure 17 It is a cross-sectional view of the display area of the liquid crystal display device of the present invention. Detailed Description

[0057] Hereinafter, the content of the present invention will be described in detail by way of examples. As oxide semiconductors, there are IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), IGO (Indium Gallium Oxide), etc. Among oxide semiconductors, optically transparent and amorphous substances are called TAOS (Transparent Amorphous Oxide Semiconductor). In this specification, there are also cases where oxide semiconductors are referred to as TAOS. In Examples 1 and 2, the application of the present invention to an organic EL display device will be described, and in Example 3, the application of the present invention to a liquid crystal display device will be described.

[0058] Example 1

[0059] In Figure 1 it, a scan line driving circuit 80 is formed on both sides of the display area 10. In the display area 10, scan lines 91 extend in the horizontal direction (x direction) and are arranged in the vertical direction (y direction). Image signal lines 92 and power supply lines 93 extend in the vertical direction and are arranged in the horizontal direction. The area surrounded by the scan lines 91, image signal lines 92, and power supply lines 93 becomes a pixel 95, and a driving transistor, a switching transistor, a light-emitting organic EL layer, etc. formed by TFTs are formed in the pixel 95.

[0060] A terminal area 20 is formed on one side of the TFT substrate 100. In the terminal area 20, a flexible wiring substrate 600 is connected to supply power and signals to the organic EL display device. If the TFT substrate 100 is formed of glass with a thickness of 0.2 mm or less, the display can be bent and used. In addition, if the TFT substrate 100 is formed of a resin such as polyimide, a flexible display device can be formed. Polyimide has excellent characteristics as a substrate for a display device in terms of mechanical strength, heat resistance, etc.

[0061] Figure 2 It is a cross-sectional view of the display area 10 of an organic EL display device as a comparative example. A base film 101 is formed on the TFT substrate 100. The base film 101 prevents the oxide semiconductor 105 formed in the upper layer from being contaminated by impurities from the glass or resin, and improves the adhesion between the film formed on the display device and the resin substrate or glass substrate.

[0062] The base film 101 is, for example, a three-layer structure of a silicon oxide film (hereinafter represented as SiO), a silicon nitride film (hereinafter represented as SiN), and SiO. The lower SiO prevents the intrusion of impurities and ensures the adhesiveness to glass or polyimide as the TFT substrate. SiN has excellent barrier properties against, in particular, moisture and the like from the glass substrate or polyimide substrate. The upper SiO has the function of blocking impurities and improves the adhesion between the layer formed thereon and the substrate.

[0063] In Figure 2 this, a bottom gate electrode 102 is formed on the base film 101. The gate electrode is also formed on the upper side of the oxide semiconductor 105, Figure 2 and the TFT of Figure 2 is a so-called double-gate type. However, in the structure of

[0064] a bottom gate insulating film formed of a double-layer structure is formed between the bottom gate electrode 102 and the oxide semiconductor 105. The bottom gate insulating film is a double-layer structure of a first bottom gate insulating film 103 and a second bottom gate insulating film 104. The first bottom gate insulating film 103 is formed of, for example, a 50-nm silicon nitride film (SiN), and the second bottom gate insulating film 104 is formed of, for example, a 200-nm silicon oxide film (SiO).

[0065] An oxide semiconductor 105 is formed on the second bottom gate insulating film 104. A top gate insulating film 106 is formed on the portion of the oxide semiconductor 105 corresponding to the channel portion, and a top gate electrode 109 is formed thereon. Figure 2 The structure of the TFT in Figure 3 is described using

[0066] In Figure 2 this, an interlayer insulating film 110 is formed so as to cover the TFT. The interlayer insulating film 110 is a laminated structure of a SiN film, a SiO film, or SiN and SiO. Figure 2 The interlayer insulating film 110 of

[0067] has the function of supplying hydrogen to the oxide semiconductor 105. Therefore, it is preferable that the interlayer insulating film 110 is a film containing hydrogen. Through holes are formed in the interlayer insulating film 110 to connect the drain region of the oxide semiconductor 105 to the drain electrode 111 and connect the source region of the oxide semiconductor 105 to the source electrode 112. An organic planarization film 113 is formed of a resin such as acrylic acid so as to cover the interlayer insulating film 110, the drain electrode 111, the source electrode 112, etc. The organic planarization film 113 functions as a planarization film, and thus is formed relatively thick, about 1.5 μm to 4 μm.

[0068] A through-hole is formed in the organic planarization film 113 to connect the lower electrode 114 and the source electrode 112. The lower electrode 114 is a reflective electrode formed of a thin film of silver or the like in the lower layer, and acts as an anode for the organic EL layer on the upper side. The anode is formed of, for example, ITO (Indium Tin Oxide) which is a transparent conductive film.

[0069] A bank 115 is formed so as to cover the end portion of the lower electrode 114, the organic planarization film 113, etc. The bank 115 is formed of a resin such as acrylic acid. The function of the bank 115 is to prevent the organic EL layer 116 formed above the lower electrode 114 from being stepped and cut at the end portion of the lower electrode 114 and to divide between pixels. The bank 115 is initially formed on the entire surface, and then a hole is formed in the portion where the organic EL layer 116 is formed, that is, in the light-emitting portion.

[0070] In Figure 2 the organic EL layer 116 is formed above the lower electrode 114 in the hole of the bank 115. The organic EL layer 116 is formed of, for example, five layers including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer in this order from the bottom up.

[0071] Above the organic EL layer 116, an upper electrode 117 serving as a cathode is formed of a transparent electrode. The upper electrode 117 must be transparent. The upper electrode 117 is formed of, for example, a transparent conductive film such as ITO, IZO (Indium Zinc Oxide), AZO (Antimony Zinc Oxide), or a thin film of a metal such as silver. The metal also approaches transparency when thinned. The upper electrode 117 is commonly formed on the entire surface of the display region 10 in each pixel.

[0072] The organic EL layer 116 is intolerant to water and has low mechanical strength because it is thin. Therefore, a protective film 118 formed of a laminated film such as an organic film formed of SiN, SiO, acrylic acid, etc. is formed so as to cover the upper electrode 117. SiN becomes a barrier layer against moisture, the organic film constitutes a mechanical buffer layer, and SiO plays a role as a barrier layer and improves the adhesion to other films.

[0073] The organic EL display device has a reflective film and reflects external light. The reflection of external light deteriorates visual recognition. Thus, Figure 2 the organic EL display device shown is provided with a circularly polarized sheet 120 on the display surface by means of an adhesive material 119 to prevent the reflection of external light.

[0074] Figure 3 is Figure 2 an enlarged cross-sectional view of the TFT portion inFigure 3 In this case, a bottom gate electrode 102 is formed of metal on a base film 101. A first bottom gate insulating film 103 is formed of SiN to cover the bottom gate electrode 102 with a thickness of, for example, 50 nm. A second bottom gate insulating film 104 with a thickness of 200 nm is formed of SiO thereon. The first bottom gate insulating film 103 and the second bottom gate insulating film 104 can be continuously formed by CVD (Chemical Vapor Deposition).

[0075] An oxide semiconductor 105 is formed on the second bottom gate insulating film 104. The characteristics of the oxide semiconductor 105 change if it is hydrogen-reduced. In order to release hydrogen from SiN, the second bottom gate insulating film 104 in contact with the oxide semiconductor 105 is formed of SiO. The oxide semiconductor 105 is formed to a thickness of 10 nm to 100 nm by, for example, a sputtering method. The oxide semiconductor 105 is formed of, for example, IGZO.

[0076] In Figure 3 In this case, on the oxide semiconductor 105, a top gate insulating film 106 with a thickness of, for example, 100 nm is formed of SiO in a portion corresponding to the channel of the oxide semiconductor 105. The top gate insulating film 106 is formed of SiO over the entire surface and then only retained in the portion corresponding to the channel by photolithography, for example.

[0077] After that, a top gate electrode 109 is formed on the top gate insulating film 106. The thickness of the top gate electrode 109 is, for example, 200 nm. Since the thickness of the top gate insulating film 106 is 100 nm and the bottom gate insulating film is a laminated film of the 200-nm second bottom gate insulating film 104 formed of SiO and the 50-nm first gate insulating film 103 formed of SiN, in the Vg-Id characteristics of the TFT, the influence of the top gate electrode 109 is dominant. There are also cases where the top gate electrode 109 is simply referred to as the gate electrode and the top gate insulating film 106 is simply referred to as the gate insulating film hereinafter.

[0078] Thereafter, an interlayer insulating film 110 is formed so as to cover the gate electrode 109 and the oxide semiconductor 105. In many cases, the interlayer insulating film 110 is formed in a stacked structure with a SiN film as the lower layer and a SiO film as the upper layer. The reason for setting the lower layer as the SiN film is to supply hydrogen from the SiN film to the oxide semiconductor 105 to form a drain region and a source region on the oxide semiconductor 105. That is, in the annealing process, hydrogen diffuses to the portion of the oxide semiconductor 105 not covered by the gate electrode 109, imparting conductivity to the oxide semiconductor 105. Thus, a drain region and a source region are formed on the oxide semiconductor 105. Further, through holes are formed in the interlayer insulating film 110 to connect the drain of the oxide semiconductor 105 to the drain electrode 111 and connect the source of the oxide semiconductor 105 to the source electrode 112.

[0079] On the other hand, hydrogen does not diffuse to the portion of the oxide semiconductor 105 covered by the gate electrode 109, so it remains highly resistive. However, the hydrogen from the SiN absorbed by the drain and source of the oxide semiconductor 105 also diffuses laterally along the oxide semiconductor 105 in the annealing process. Thus, in the case of a short channel length, there will be a problem of channel conduction. Or although the channel is not conducting, there is a problem of deviation in the Vd-Id characteristics.

[0080] The present invention can address the above problems. Figure 4 It is a cross-sectional view of the display region 10 of the organic EL display device of the present invention. Figure 4 It is different from Figure 2 in the structure of the TFT having the oxide semiconductor 105 and the structure of the interlayer insulating film 110 covering the TFT. In Figure 4 , a second bottom gate insulating film 104 is formed of SiO, the oxide semiconductor 105 is formed thereon and patterned, and so far it is the same as Figure 2 .

[0081] In Figure 4 , a gate insulating film 106 formed of SiO is formed in a portion corresponding to the region of the oxide semiconductor 105 sandwiched by the drain region and the source region, and an aluminum oxide film (hereinafter referred to as AlO) 107 is formed thereon. Although the gate insulating film can also be formed of the SiO film 106 and the AlO film 107, in this specification, for convenience, the SiO film is referred to as the gate insulating film 106 and the aluminum oxide film is referred to as the AlO film 107.

[0082] A gate electrode 109 is formed of a metal or an alloy on the AlO film 107, and the feature of the present invention is that sidewall spacers 108 formed of an insulating film such as SiN are formed at both ends of the AlO film 107. As will be described later, the channel can be reliably separated from the drain or the source by the sidewall spacers 108.

[0083] The gate electrode 109 and the gate insulating film 106 are patterned, and the drain and source of the oxide semiconductor 105 are not covered by the gate insulating film 106 or the gate electrode 109 and are in direct contact with the interlayer insulating film 110. The interlayer insulating film 110 has a structure of a SiN film or a double layer structure of a SiN film and a SiO film. One of the features of the present invention is that the SiN film is in direct contact with the drain or source of the oxide semiconductor 105. Therefore, hydrogen can be supplied to the drain and source, and the resistance of the drain and source can be reduced.

[0084] When hydrogen is supplied to the drain and source, since hydrogen easily diffuses, in the structure of the comparative example Figure 3 , during the annealing process, hydrogen diffuses, and the characteristics of the TFT become unstable. In addition, if the channel length becomes shorter, there is also a risk of channel conduction. The present invention particularly prevents the characteristics of the TFT having an oxide semiconductor from becoming unstable by forming sidewall spacers 108 on both sides of the gate electrode 109. The structure above the interlayer insulating film 110 is the same as that described using Figure 2 .

[0085] Figure 5 is Figure 4 a cross-sectional view of the periphery of the TFT in. In Figure 5 , a gate insulating film 106, an AlO film 107, and a gate electrode 109 are formed on the oxide semiconductor 105. Sidewall spacers 108 are formed between the end of the gate electrode 109 and the AlO film 107. The portion of the gate electrode 109 that faces the oxide semiconductor 105 without sandwiching the sidewall spacers 108 becomes the channel 1051 of the oxide semiconductor 105. In other words, Figure 5 the portion of the oxide semiconductor 105 in corresponding to the portion that becomes the recess 1091 in the metal forming the gate electrode 109 becomes the channel 1051.

[0086] The gate insulating film 106 is formed only on the lower side of the gate electrode 109, and the portions of the oxide semiconductor 105 that become the drain and source are not covered. Then, the interlayer insulating film 110 is formed of SiN so as to cover the gate electrode 109, the oxide semiconductor 105, etc. Since the portion of the oxide semiconductor 105 in contact with the SiN film is supplied with hydrogen, the drain and source become low resistance, and the drain current can be increased.

[0087] In the past, the drain and source were formed by bringing SiO with relatively many defects into contact with the oxide semiconductor 105. However, in terms of hydrogen release, it is less than that of SiN. Therefore, it is impossible to sufficiently reduce the resistance of the drain and source, and it is impossible to increase the drain current. On the other hand, when the interlayer insulating film 110 is formed of SiN in the existing configuration, hydrogen is supplied to the oxide semiconductor 105, but this hydrogen also diffuses into the channel 1051 of the oxide semiconductor 105 to turn on the channel. In particular, in a TFT with a short channel length, this risk is great.

[0088] The present invention controls the diffusion of hydrogen into the channel 1051 by forming sidewall spacers 108 on both sides of the gate electrode 109, and at the same time realizes the low resistance of the drain and source in the oxide semiconductor 105 and prevents the influence of hydrogen on the channel 1051. The present invention also forms an AlO film 107 between the gate insulating film 106, the gate electrode 109 and the sidewall spacers 108, thereby further enhancing this effect.

[0089] In Figure 5 the thickness of the AlO film 107 located between the gate insulating film 106, the gate electrode 109 and the sidewall spacers 108 is 10 to 50 nm. In order to suppress the change in the characteristics of the channel of the oxide semiconductor 105, it is effective to supply oxygen. Therefore, oxygen is more stably supplied to the oxide semiconductor 105 by also supplying oxygen from the AlO film 107.

[0090] The shape of the sidewall spacer 108 formed on the AlO film 107 is a trapezoid with one sidewall inclined in cross section. An offset region 1052 is formed on the oxide semiconductor 105 by the sidewall spacer 108. The offset region 1052 reliably forms an intermediate region between the channel of the oxide semiconductor 105 and the drain and source (hereinafter represented by the drain). Even when a large amount of hydrogen is supplied to the drain or source, it is possible to prevent the hydrogen from affecting the channel and prevent the non-uniformity of the characteristics of the TFT. In particular, when the channel length becomes shorter, this effect is remarkable.

[0091] In Figure 5 the length d2 of the offset region 1052 is 0.5 μm to 2 μm. For example, when the channel length d1 is 2 μm, it is preferable that the length d2 of the offset region 1052 is about 1 μm. There is an AlO film 107 between the offset region 1052 and the sidewall spacer 108. This AlO film 107 becomes a good supply source of oxygen, so it offsets the hydrogen that wants to diffuse from the drain to the channel side, and effectively prevents the channel 1051 from being reduced by hydrogen.

[0092] In Figure 5In [description], the gate electrode 109 is placed on the upper surface of the sidewall spacer 108. This is to stably form the gate electrode 109. The amount d3 of the gate electrode 109 placed on the sidewall spacer 108 is preferably 0.1 μm or more. When viewed from above, the distance from the end of the gate electrode 109 to the end of the offset region 1052 is d4. d4 is preferably 0.3 μm or more. The width d2 of the offset region 1052 becomes d3 + d4.

[0093] In Figure 5 [description], one sidewall of the sidewall spacer 108 is an inclined surface. The reason for setting the sidewall of the sidewall spacer 108 as an inclined surface is to improve the step coverage of the interlayer insulating film 110 formed so as to cover the gate electrode 109 and the sidewall spacer 108. Therefore, the inclined surface is not an essential component of the present invention.

[0094] The thickness of the sidewall spacer 108 is, for example, 100 nm to 500 nm. If the thickness of the sidewall spacer 108 is too small, it will disappear when the sidewall spacer is processed by dry etching. On the other hand, when the thickness of the sidewall spacer 108 is too large, problems such as stepped cutting of the interlayer insulating film 110 covering the gate electrode 109 and the sidewall spacer 108 and an increase in the processing time of the sidewall spacer 108 will occur. In addition, when the thickness of the sidewall spacer 108 is too large, when the sidewall spacer 108 is formed of SiN, there will be a problem of an increase in the supply amount of hydrogen from the sidewall spacer 108 itself.

[0095] An interlayer insulating film 110 is formed so as to cover the gate electrode 109 and the sidewall spacer 108. The interlayer insulating film 110 is usually formed of two layers of SiN and SiO, but if possible, it is better that the lower layer in contact with the oxide semiconductor 105 is formed of a SiN film. The SiN film becomes a hydrogen supply source and can reduce the resistance of the drain region and the source electrode region of the oxide semiconductor 105.

[0096] In Figure 5 [description], as described later, the material of the sidewall spacer 108 is preferably formed of SiN according to the requirements of fine processing by dry etching, but depending on the processing conditions, it can also be formed of SiON (silicon oxynitride) or SiO. When the sidewall spacer 108 is formed of SiN, the SiN constituting the interlayer insulating film 110 and the SiN constituting the sidewall spacer 108 may have the same film quality. However, it is preferable that the hydrogen content of the SiN constituting the interlayer insulating film 110 is higher than the hydrogen content of the SiN constituting the sidewall spacer 108. That is, since the sidewall spacer 108 is close to the channel, it is better to suppress the supply of hydrogen from the sidewall spacer 108.

[0097] All SiN is formed by CVD. Even when the gas ratio, power, film formation pressure, etc. are the same, it is only necessary to set the film formation temperature during the formation of the film formation sidewall spacer 108 to a high temperature (for example, 300°C to 350°C). In the case of high-temperature film formation, since the film has better uniformity, there is also the advantage that air pits are not easily formed.

[0098] Figure 6 is a top view of the TFT. In Figure 6 an oxide semiconductor 105 is formed over the bottom gate electrode 102 with a bottom gate insulating film interposed therebetween. A gate insulating film is formed in an island shape over the oxide semiconductor 105, but in Figure 6 it is covered by the gate electrode 109 and the sidewall spacer 108 and is not visible. In Figure 6 the sidewall spacer 108 can be seen around the gate electrode 109, which is the Figure 5 inclined surface of the sidewall spacer 108 in

[0099] A recess 1091 is formed in the gate electrode 109. A channel of the oxide semiconductor 105 is formed in the portion of the gate electrode 109 where the recess 1091 is formed, and offset regions 1052 are formed on both sides of the recess 1091. In Figure 6 the SiN constituting the interlayer insulating film 110 contacts the oxide semiconductor 105 that does not overlap with the gate electrode 109 and the sidewall spacer 108, and the oxide semiconductor 105 is reduced by hydrogen supplied from the SiN to form a drain and a source. The drain is connected to the drain electrode 111 via a through hole, and the source is connected to the source electrode 112 via a through hole.

[0100] Figures 7 to 12 is a cross-sectional view showing the manufacturing process of the structure for realizing Figure 5 In Figure 7 a bottom gate electrode 102 is formed over the base film 101, and a first bottom gate insulating film 103 and a second bottom gate insulating film 104 are formed to cover the bottom gate electrode 102, and an oxide semiconductor 105 is formed thereon. The bottom gate electrode 102 is patterned after being formed by sputtering. The first bottom gate insulating film 103 is formed of SiN with a thickness of, for example, 50 nm, and the second bottom gate insulating film 104 is formed of SiO with a thickness of, for example, 200 nm. SiN and SiO can be continuously formed by CVD.

[0101] After that, an oxide semiconductor 105 is formed over the second bottom gate insulating film 104. The oxide semiconductor 105 is formed into an island shape after being formed with a thickness of 10 to 100 nm. Then, a top gate insulating film (gate insulating film) 106 is formed of SiO over the oxide semiconductor 105. The film thickness of SiO is, for example, 100 nm. The relationship between the film thicknesses of the bottom gate insulating film and the top gate insulating film is as shown in the use of Figure 2As described above. Then, an AlO film 107 with a thickness of 10 to 50 nm is formed by sputtering.

[0102] Figure 8 It is a cross-sectional view showing an intermediate process for forming the sidewall spacer 108. In Figure 8 , a SiN film for forming the sidewall spacer 108 is deposited by CVD with a thickness of 100 nm to 500 nm. The CVD for forming this SiN is carried out at a higher temperature (e.g., 300 °C to 350 °C) compared to the CVD for forming the subsequent interlayer insulating film 110. A denser film quality is adopted to suppress the release of hydrogen. In Figure 8 , a resist 400 for patterning the sidewall spacer is formed on the SiN film. Then, the SiN film is dry-etched using an SF6-based gas.

[0103] Figure 9 It is a cross-sectional view showing the state after dry-etching the SiN film for the sidewall spacer 108. SiN is prone to be side-etched by dry-etching using an SF6-based gas. The Figure 9 arrow shows the case of side-etching. By side-etching, the width of the sidewall spacer 108 becomes smaller than the width of the resist. The width of the sidewall spacer is very small at the bottom surface, being 0.5 μm to 2 μm, so it is difficult to form such a resist pattern. By using SiN, according to the effect of side-etching, the sidewall spacer 108 can be processed to a size below the patterning limit of the resist.

[0104] Comparing AlO with SiN that constitutes the sidewall spacer, it can be seen that in the dry-etching using an SF6-based gas, the selectivity of AlO is much larger than that of SiN. Therefore, in the Figure 9 shown dry-etching process, the AlO film is hardly etched.

[0105] After that, as shown in Figure 10 , a metal or alloy that becomes the gate electrode 109 is deposited, and a resist 400 is formed on the part that is desired to be retained as the gate electrode 109. As the gate electrode 109, for example, a stacked film such as Mo, MoW, or Ti-Al-Ti is used. And, the metal and the AlO film are etched by dry-etching using a Cl-based gas to pattern the AlO film 107 and the gate electrode 109. In the case of using a Cl-based gas, although SiO that constitutes the gate insulating film 106 is difficult to be etched, since it is not zero, the Cl-based dry-etching is stopped midway during the etching of SiO as needed.

[0106] Figure 11 It is shown by Figure 10A cross-sectional view of the state after patterning the gate electrode 109 and the AlO film 107 by dry etching using a Cl-based gas. In this state, the oxide semiconductor 105 is covered by the gate insulating film 106. Thus, as Figure 11 shown, the SiO which is the material of the gate insulating film is etched by F-based dry etching to pattern the gate insulating film 106. In the F-based dry etching, the oxide semiconductor 105 is hardly etched.

[0107] Figure 12 is a cross-sectional view showing the state after removing SiO by F-based dry etching to pattern the gate insulating film 106. The SiN constituting the sidewall spacer 108 is also etched somewhat by the F-based dry etching, and thus a tapered shape is formed on the outer wall of the sidewall spacer 108.

[0108] In Figure 12 , the gate electrode 109 remains on the upper base of the sidewall spacer 108 having a trapezoidal cross-section. This amount is d3. d3 is preferably 0.1 μm or more. Preferably, the difference between the lower base and the upper base of the sidewall spacer 108 is 0.3 μm or more.

[0109] After that, for Figure 12 the formation of the interlayer insulating film 110, it becomes Figure 5 the structure. The interlayer insulating film 110 is formed of SiN or a laminated film of SiN and SiO, and since the interlayer insulating film 110 supplies hydrogen to the oxide semiconductor 105, in the case of using a laminated film, it is preferably that the layer in contact with the oxide semiconductor 105 is formed of SiN. In addition, it is preferable that the hydrogen content of SiN in the interlayer insulating film 110 is more than that of the SiN constituting the sidewall spacer 108.

[0110] Example 2

[0111] Figure 13 is a cross-sectional view showing the display area of the organic EL display device according to Example 2 of the present invention. In Figure 13 , the top gate insulating film 106 is formed not only under the gate electrode 109 but also on the entire surface. In addition, the side surface of the sidewall spacer 108 is not inclined. Figure 13 The other structures of Figure 4 are the same. In Figure 13 , the drain region and the source region of the oxide semiconductor 105 do not contact the interlayer insulating film 110. Therefore, even if the interlayer insulating film 110 is formed of SiN, hydrogen cannot be received from the SiN. Therefore, in order to form the drain region and the source region of the oxide semiconductor 105, as Figure 14 shown, ion implantation (I / I) needs to be performed separately.

[0112] Figure 14The cross-sectional structure is the same as that of Embodiment 1. Figure 11 However, in Figure 14 , instead of dry etching, ion implantation (I / I) is performed, and boron (B), phosphorus (P), etc. are doped into the oxide semiconductor 105 to impart conductivity, and a drain and a source are formed on the oxide semiconductor. It should be noted that ion implantation (I / I) imparts conductivity by creating defects in the structure of the oxide semiconductor 105, so Ar, etc. can also be implanted. Ion implantation (I / I) is performed using the gate electrode 109 as a mask. In addition, the sidewall spacer 108 is also formed thicker, and there is also an AlO film 107 in this part, so an intermediate region is formed between the channel and the drain and source. It should be noted that in ion implantation (I / I), the sidewall spacer 108 is not etched, so it is not easy to form the Figure 12 shown inclination.

[0113] Figure 15 is a cross-sectional view showing a state in which an interlayer insulating film 110 is formed after ion implantation and a through hole is formed in the interlayer insulating film 110, and a drain electrode 111 and a source electrode 112 are connected. The structure of the interlayer insulating film 110 is the same as that described in the case of using Embodiment 1 Figure 5 and so on. In Embodiment 2, the drain region and the source region of the oxide semiconductor 105 are imparted conductivity by ion implantation.

[0114] The drain region and the source region of the oxide semiconductor 105 are covered by a gate insulating film 106 containing a large amount of oxygen. Thus, even if conductivity is imparted by ion implantation, there is a possibility that the resistance of the drain region and the source region gradually increases due to the influence of oxygen.

[0115] By forming the surface of the interlayer insulating film 110 in contact with the gate insulating film 106 from SiN, the influence of oxygen from the gate insulating film 106 on the drain and source of the oxide semiconductor 105 is alleviated by the supply of hydrogen from SiN. Therefore, the characteristics of the TFT can be stabilized. Other structures are the same as those described in Embodiment 1.

[0116] Embodiment 3

[0117] In Embodiments 1 and 2, the application of the present invention to an organic EL display device has been described. However, the present invention can also be applied to a liquid crystal display device. Figure 16 is a top view of a liquid crystal display device. In Figure 16 , the TFT substrate 100 and the counter substrate 200 are bonded by a sealing material 30, and liquid crystal is sandwiched between the TFT substrate 100 and the counter substrate 200 inside the sealing material 30.

[0118] A display region 10 is formed in a portion where the TFT substrate 100 and the counter substrate 200 overlap. In the display region 10, scan lines 91 extend in the lateral direction (x direction) and are arranged in the longitudinal direction (y direction). In addition, image signal lines 92 extend in the longitudinal direction and are arranged in the lateral direction. Pixels 95 are formed in regions surrounded by the scan lines 91 and the image signal lines 92. The TFT substrate 100 is formed larger than the counter substrate 200, and a portion of the TFT substrate 100 that does not overlap with the counter substrate 200 becomes a terminal region 20. A flexible wiring substrate 600 for supplying power and signals to the liquid crystal display device is connected in the terminal region 20.

[0119] Figure 17 is a cross-sectional view of a display region of a liquid crystal display device. In Figure 17 until the formation of the organic planarization film 113, it is the same as that of Embodiment 1. Figure 4 It should be noted that the TFT of Figure 4 in Embodiment 1 is a driving TFT for driving the organic EL layer, while the TFT in this embodiment is a switching TFT, but the basic configuration is the same.

[0120] That is, a double-layer bottom gate insulating film (103, 104) is formed on the bottom gate electrode 102 that also serves as a light-shielding film, and an oxide semiconductor 105 is formed thereon. A top gate insulating film 106 is formed in a portion of the oxide semiconductor 105 corresponding to the channel. An AlO film 107 is formed on the top gate insulating film 106. And sidewall spacers 108, which are a feature of the present invention, are formed at both upper ends of the AlO film 107. Then, a gate electrode 109 is formed.

[0121] An interlayer insulating film 110 is formed to cover the gate electrode 109, the sidewall spacers 108, the oxide semiconductor 105, etc. The configuration of the interlayer insulating film 110 is also the same as that described using Figure 5 The same content. And through holes are formed in the interlayer insulating film 110 to connect the drain of the oxide semiconductor 105 to the drain electrode 111 and connect the source of the oxide semiconductor 105 to the source electrode 112. An organic planarization film 113 is formed to cover the drain electrode 111, the source electrode 112, and the interlayer insulating film 110.

[0122] In Figure 17 the structure formed after the organic planarization film 113 is different from that of the organic EL display device shown in Figure 4 The same. Figure 17 is a cross-sectional view of an IPS (In Plane Switching) mode liquid crystal display device. In Figure 17 a through hole for connecting the source electrode 112 and the pixel electrode 152 is formed on the organic planarization film 113. In Figure 17In [the structure], a common electrode 150 formed of ITO is formed over the organic planarization film 113. A capacitive insulating film 151 is formed of SiN so as to cover the common electrode 150.

[0123] A pixel electrode 152 is formed over the capacitive insulating film 151. The pixel electrode 152 is connected to the source electrode 112 in a through hole formed in the organic planarization film 113. It should be noted that the capacitive insulating film 151 covers the sidewall of the through hole in the organic planarization film 113, but a through hole is formed in the lower part so that the pixel electrode 152 can be connected to the source electrode 112. An alignment film 153 for initial alignment of liquid crystal is formed over the pixel electrode 152.

[0124] A counter substrate 200 is formed so as to face the TFT substrate 100 with the liquid crystal layer 300 interposed therebetween. A black matrix 202 is formed inside the counter substrate 200, and a color filter 201 is formed in a portion corresponding to the pixel electrode 122. A top coat film 203 is formed so as to cover the black matrix 202 and the color filter 201. An alignment film 204 is formed over the top coat film 203 to align the liquid crystal initially.

[0125] In Figure 17 [the structure], when an image signal is applied to the pixel electrode 122, power lines as shown by the arrows are generated, causing the liquid crystal molecules 301 to rotate, controlling the transmittance of light from the backlight in the pixel, and forming an image.

[0126] As described above, in the liquid crystal display device, a TFT using an oxide semiconductor with stable characteristics can also be formed by applying the TFT having the configuration of Embodiment 1. The configuration described in Embodiment 2 can also be similarly applied to the liquid crystal display device.

[0127] In the above description, an IPS-mode liquid crystal display device has been described, but it can also be applied to other-mode liquid crystal display devices.

[0128] The oxide semiconductor can reduce the leakage current, but since the mobility is smaller than that of polysilicon, there is a case where it is difficult to form a peripheral drive circuit such as Figure 1 the scan line drive circuit 80 in [the structure] using a TFT with an oxide semiconductor. In this regard, since polysilicon has a high mobility, a TFT using polysilicon can be applied to the peripheral drive circuit.

[0129] On the other hand, the leakage current of a TFT using polysilicon is relatively large, so the potential change of the pixel electrode becomes a problem. Therefore, it is reasonable to apply a TFT using an oxide semiconductor to the pixels in the display area and a TFT using polysilicon to the peripheral drive circuit. Such a configuration is called a hybrid type, and the present invention can also be applied to such a hybrid display device.

[0130] Description of Reference Numerals

[0131] 10… Display area, 20… Terminal area, 30… Sealing material, 80… Scan line driving circuit, 91… Scan line, 92… Image signal line, 93… Power supply line, 95… Pixel, 100… TFT substrate, 101… Base film, 102… Bottom gate electrode, 103… First bottom gate insulating film, 104… Second bottom gate insulating film, 105… Oxide semiconductor, 106… Gate insulating film, 107… AlO film, 108… Sidewall spacer, 109… Gate electrode, 110… Interlayer insulating film, 111… Drain electrode, 112… Source electrode, 113… Organic planarization film, 114… Lower electrode, 115… Dam, 116… Organic EL layer, 117… Upper electrode, 118… Protective film, 119… Adhesive material, 120… Circular polarizer, 150… Common electrode, 151… Capacitive insulating film, 152… Pixel electrode, 153… Alignment film, 200… Counter substrate, 201… Color filter, 202… Black matrix, 203… Top coating film, 204… Alignment film, 300… Liquid crystal layer, 400… Resist, 301… Liquid crystal molecule, 1051… Channel, 1052… Offset area, 1091… Recess of gate electrode, I / I… Ion implantation.

Claims

1. A method of manufacturing a display device, the display device including a thin film transistor, wherein the method of manufacturing the display device is characterized by including the following steps: Forming a first insulating film on a substrate; Forming an oxide semiconductor on the first insulating film; Patterning the oxide semiconductor into an island shape; Forming a gate insulating film on the oxide semiconductor and the first insulating film; Forming an aluminum oxide film on the gate insulating film; Forming a SiN film for forming sidewall spacers on the aluminum oxide film; Forming a metal film as a gate electrode on the aluminum oxide film formed with the sidewall spacers; Forming a second insulating film on the gate electrode and the oxide semiconductor; Forming a through hole in the second insulating film; And Forming a drain electrode and a source electrode in the through hole in a manner connected to the oxide semiconductor, Before forming the second insulating film, patterning the aluminum oxide film and the gate electrode so that the sidewall spacers are formed on both sides of the gate electrode, and in a top view, in a direction connecting the drain electrode and the source electrode, the width of the gate electrode is smaller than the width of the aluminum oxide film.

2. The method of manufacturing a display device according to claim 1, wherein, The first insulating film is formed by CVD.

3. The method of manufacturing a display device according to claim 1, wherein, The aluminum oxide film is removed by dry etching using a Cl-based gas.

4. The method of manufacturing a display device according to claim 1, wherein, The through hole is formed to penetrate the gate insulating film at a position where the gate insulating film contacts the second insulating film.

5. The method of manufacturing a display device according to claim 3, wherein, The through hole is formed to penetrate the gate insulating film at a position where the gate insulating film contacts the second insulating film.

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