Semiconductor device, image sensor, and method of forming the same

Abstract

Image sensors and methods of forming image sensors are provided. A semiconductor device according to the present invention includes a semiconductor layer, a plurality of metal isolation components disposed in the semiconductor layer, a metal grid disposed directly above the plurality of metal isolation components, and a plurality of microlens components disposed above the metal grid. Embodiments of the present application also relate to semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices, image sensors, and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each with smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be manufactured using a process) has decreased. This scaling down generally benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Image sensors, such as complementary metal-oxide-semiconductor (CMOS) image sensors (CIS), are common in modern consumer electronics. As image sensor sizes shrink to keep up with the ever-increasing demands for pixel resolution, some existing image sensor structures may no longer provide sufficient quantum efficiency (QE). Therefore, while existing CMOS sensors are generally adequate for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device, including: a semiconductor layer; a plurality of metal isolation components disposed in the semiconductor layer; a metal grid disposed directly above and in contact with the plurality of metal isolation components; and a plurality of microlens components disposed above the metal grid.

[0005] Other embodiments of this application provide an image sensor, including: a first deep trench isolation (DTI) component and a second deep trench isolation component; a photodetector disposed between the first deep trench isolation component and the second deep trench isolation component; and a metal grid disposed on the first deep trench isolation component and the second deep trench isolation component and in direct contact with the first deep trench isolation component and the second deep trench isolation component, wherein the first deep trench isolation component, the second deep trench isolation component and the metal grid comprise aluminum.

[0006] Further embodiments of this application provide a method for forming an image sensor, comprising: receiving a substrate including a plurality of transistors adjacent to a front side of the substrate; forming a plurality of deep trenches from a back side of the substrate; depositing a first dielectric layer over the back side of the substrate after forming the plurality of deep trenches; forming a plurality of metal isolation components in the plurality of deep trenches after depositing the first dielectric layer; forming a top dielectric layer over the plurality of metal isolation components; forming a plurality of metal grid openings to expose the plurality of metal isolation components; and forming a metal grid in the plurality of metal grid openings. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the drawings illustrate only typical embodiments of the invention and should therefore not be considered as limiting the scope, as the invention can be equally applied to other embodiments.

[0008] Figure 1 This is a flowchart illustrating a method for manufacturing an image sensor device according to various aspects of the present invention.

[0009] Figures 2 to 11 The illustrations depict various aspects of the invention, according to Figure 1 The method is illustrated by partial cross-sectional views of workpieces that have undergone different manufacturing stages.

[0010] Figure 12 A partial top view of a metal grid according to various aspects of the present invention is illustrated.

[0011] Figures 13 to 18 The illustration shows alternative embodiments of an image sensor device according to various aspects of the present invention. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, this terminology takes into account the inherent deviations that arise during the manufacturing process, as assumed by those skilled in the art, and is intended to cover values ​​within this reasonable range. For example, a numerical value or range covers a reasonable range including the described value, such as within + / -10% of the described value, based on known manufacturing tolerances related to manufacturing parts having characteristics associated with that value. For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, and the manufacturing tolerances known to those skilled in the art related to depositing such a material layer are + / -15%. Furthermore, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) have become increasingly popular. Some existing CMOS image sensors include dielectric isolation components to isolate adjacent pixels. However, as pixel sizes continue to shrink, such pixel isolation structures may not provide sufficient isolation, and quantum efficiency (QE) may be affected as a result. This invention provides an image sensor comprising a photodetector (or photodiode) disposed in a semiconductor layer and a microlens disposed above the photodetector, such that light passes through the microlens and is guided to the photodetector. The photodetector is separated from each other by multiple metal isolation components or metal trench isolation components that extend partially or completely through the semiconductor layer. A network of metal grids or conductive components is disposed on and in direct contact with the multiple metal isolation components. A negative bias can be applied to the multiple metal isolation components to improve electrical isolation. The multiple metal isolation components can also serve as reflectors to further improve quantum efficiency (QE). In summary, the structure of this invention can help improve quantum efficiency (QE), reduce crosstalk, and improve performance. The process of this invention is robust and can be used to manufacture image sensors for future generations and even smaller ones.

[0016] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1This is a flowchart illustrating a method 100 for forming an image sensor on a workpiece according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 11 Description method 100, Figures 2 to 11 This is a partial cross-sectional view of the workpiece 200 at different manufacturing stages according to an embodiment of method 100. Because the workpiece 200 will be manufactured into a semiconductor device or image sensor at the end of the manufacturing process, it may also be referred to as semiconductor device 200 or image sensor 200, depending on the context. Furthermore, throughout this application, unless otherwise stated, the same reference numerals denote the same parts.

[0017] refer to Figure 1 and Figure 2 Method 100 includes a frame 102 for receiving workpiece 200. For example... Figure 2 As shown, workpiece 200 includes a front side 200F and a back side 200B. When workpiece 200 is received, processing of the front side 200F of workpiece 200 has already been performed. This front side process may include the formation of transistor 204 (described further below) and isolation component 206 (described further below). Workpiece 200 includes a substrate 202. Substrate 202 may be a bulk silicon (Si) substrate. Optionally, substrate 202 may include elemental semiconductors such as germanium (Ge); compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. In some embodiments, substrate 202 comprises one or more group III-V materials, one or more group II-VI materials, or combinations thereof. In other cases, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. In still other embodiments, substrate 202 may be a diamond substrate or a sapphire substrate.

[0018] To form an image sensing device 240 (described below) in substrate 202, substrate 202 may include various doped regions (not shown), such as p-type doped regions, n-type doped regions, or combinations thereof. Because substrate 202 includes the image sensing device 240, substrate 202 may also be referred to as sensor substrate 202. In one embodiment, substrate 202 may include p-type dopants such as boron (B), boron difluoride (BF2), or other p-type dopants, and n-type dopants such as phosphorus (P), arsenic (As), or other n-type dopants. In this embodiment, substrate 202 may be a commercially available silicon substrate having p-type dopants, and n-type dopants are introduced into certain regions of substrate 202 to form the image sensing device 240 (e.g., ...). Figure 4 (As shown). The image sensing device 240 may also be referred to as a photodetector 240 or a photodiode 240. In some embodiments, the thickness of the substrate 202 may be between about 15 μm and about 50 μm.

[0019] Workpiece 200 has undergone front-side processing and includes components formed using this processing. In the depicted embodiment, workpiece 200 includes a plurality of transistors 204 configured to process signals from image sensing device 240. Each of the transistors 204 includes a source, a drain, a channel region disposed between the source and drain, and a gate structure above the channel region. It should be noted that... Figure 2 The transistor 204 shown can represent transistors with different configurations. For example, transistor 204 can be a planar transistor, a fin field-effect transistor (finFET), a multi-bridge channel (MBC) transistor, a gate all-around (GAA) transistor, a nanowire transistor, a nanosheet transistor, a transistor with a nanostructure, or other multi-gate transistors in which the gate structure joins multiple surfaces of the channel region. The active region 2040 of transistor 204 can be isolated from each other by multiple isolation components 206. Depending on the configuration of transistor 204, the active region 2040 can have a sheet shape, a fin shape, or may include multiple channel members perpendicularly spaced from each other. The isolation components 206 can also be referred to as shallow trench isolation (STI) components 206 and can include silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In the depicted embodiment, workpiece 200 may also include a first interlayer dielectric (ILD) layer 205 disposed above transistor 204. The first ILD layer 205 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)) and / or other suitable dielectric materials.

[0020] refer to Figure 1 and Figure 3 Method 100 may optionally include block 104, wherein the workpiece 200 is flipped over so that the back side 200B faces upward. To flip the workpiece 200 over, a carrier substrate (not explicitly shown) is bonded to the front side 200F. In some embodiments, the carrier substrate may be bonded to the workpiece 200 by welding, by using an adhesive layer, or a combination thereof. In some cases, the carrier substrate may be formed of a semiconductor material (such as silicon), sapphire, glass, a polymeric material, or other suitable material. In embodiments using welding, the carrier substrate includes a bottom oxide layer, and the workpiece 200 includes a top oxide layer such as a first ILD layer 205. After both the bottom and top oxide layers are processed, they are placed in close contact with each other for direct bonding at room temperature or high temperature. Once the carrier substrate is bonded to the workpiece 200, the workpiece 200 is flipped over, as... Figure 3 As shown.

[0021] In some embodiments, the operation at box 104 is omitted, and the workpiece 200 is not flipped at this time. In these embodiments, the operations at boxes 104 to 114 are performed on the front side 200F of the workpiece 200, not the back side 200B. When the operation at box 104 is omitted, the metal IDT component 216 extends from the front side 200F into the substrate 202, as... Figures 17 to 18 As shown.

[0022] refer to Figure 1 and Figure 4 Method 100 includes block 106, wherein a deep trench 209 is formed in workpiece 200. To pattern workpiece 200 to form the deep trench 209, a hard mask 208 is formed over the back side 200B of an exposed substrate 202. In some embodiments, the hard mask 208 may be a single layer or multiple layers and may be deposited using chemical vapor deposition (CVD). In one embodiment, the hard mask 208 may include a silicon nitride layer and a silicon oxide layer above the silicon nitride layer. A photolithography process and an etching process are then performed to pattern the hard mask 208. For example, a photoresist layer (not shown) is formed over the hard mask, exposed to a suitable photolithography radiation source, and developed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etching mask to pattern the hard mask 208. The patterned hard mask 208 is then used as an etching mask to anisotropically etch the substrate 202 to form the deep trench 209. Figure 4 As shown, multiple deep trenches 209 can be formed. Anisotropic etching can be a dry etching process that uses sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), other fluorine-containing gases, oxygen (O2), or mixtures thereof. The deep trenches 209 can extend partially or completely through the substrate 202.

[0023] When the operation of frame 104 is performed, the deep trench 209 extends from the back side 200B of the workpiece 200 into the substrate 202. When the operation of frame 104 is not performed, the deep trench 209 extends from the front side 200F of the workpiece 200 into the substrate 202. Figure 4 In some embodiments shown, the deep trench 209 extends partially through the substrate 202 and partially into the STI component 206. Figure 15 In some embodiments shown, the deep trench 209 (now filled with other structures, such as the metal deep trench isolation member 216) partially extends through the substrate 202 but does not reach the STI member 206. Figure 16 In some embodiments shown, the deep trench 209 (now filled with other structures, such as the metal deep trench isolation member 216) extends completely through the substrate 202 and the STI member 206. Figure 17 In some embodiments shown, the deep trench 209 (now filled with other structures, such as the metal deep trench isolation member 216) extends entirely through the STI member 206, but extends through the substrate 202 from the front side 200F portion. Figure 18 In some of the embodiments shown, the deep trench 209 (now filled with other structures, such as the metal deep trench isolation member 216) extends completely from the front side 200F through the STI member 206 and the substrate 202.

[0024] refer to Figure 1 and Figure 5 Method 100 includes frame 108, wherein a dielectric layer 214 is deposited over a back surface 202B, including over a deep trench 209. (As...) Figure 5 As shown, dielectric layer 214 can be multilayered and includes a first dielectric layer 210, a second dielectric layer 211 above the first dielectric layer 210, and a third dielectric layer 212 above the second dielectric layer 211. The first dielectric layer 210 may include aluminum oxide, hafnium oxide, titanium oxide, barium titanate, zirconium oxide, lanthanum oxide, barium oxide, strontium oxide, yttrium oxide, or combinations thereof, and has a thickness between 2 nm and 20 nm. The second dielectric layer 211 may include metal oxides such as tantalum oxide (Ta₂O₅), titanium oxide, zirconium oxide, or combinations thereof, and has a thickness between 40 nm and 60 nm. The third dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof, and has a thickness between about 5 nm and 50 nm. In some embodiments, each layer of dielectric layer 214 may be conformally deposited such that each layer may line the bottom and sidewalls of the deep trench 209. For example, each layer in dielectric layer 214 can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). It should be noted that dielectric layer 214 does not completely fill deep trench 209.

[0025] refer to Figure 1 and Figure 6 Method 100 includes a frame 110 in which a metal deep trench isolation (DTI) component 216 is formed in a deep trench 209. At frame 110, metal is deposited over the workpiece 200, including over and into the deep trench 209 (e.g., ...). Figure 5 (As shown). Deposition can be performed using physical vapor deposition (PVD) or chemical vapor deposition (CVD). After metal deposition, a chemical mechanical polishing (CMP) process is performed to remove excess metal material above the third dielectric layer 212, thereby forming a metal DTI component 216. The metal DTI component 216 can be formed of aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). In one embodiment, the metal DTI component 216 is formed of aluminum (Al). When the metal DTI component 216 is formed of a highly optically reflective metal such as aluminum (Al), the metal DTI component 216 can be used as a reflector to reflect light toward the photodetector 240, thereby increasing quantum efficiency (QE). In other words, the metal DTI component 216 can allow incident light to bounce in the photodetector 240 before the incident light dissipates, is absorbed, or escapes. Figure 6 As shown, the metal DTI component 216 is spaced apart from the substrate 202 by a dielectric layer 214 comprising a first dielectric layer 210, a second dielectric layer 211, and a third dielectric layer 212. Still referring to... Figure 6 After the chemical mechanical polishing process, the surface of the substrate 202 adjacent to the back side 200B remains covered by the dielectric layer 214.

[0026] refer to Figure 1 and Figure 7 Method 100 includes a frame 112, wherein a top dielectric layer 218 is deposited over a back surface 202B. After forming a metal DTI component 216, method 100 deposits the top dielectric layer 218 over the metal DTI component 216 and the third dielectric layer 212. In some embodiments, the top dielectric layer 218 may be a silicon oxide layer and may be deposited using CVD. In some cases, the thickness of the top dielectric layer 218 may be between about 30 nm and about 50 nm. The composition of the top dielectric layer 218 may be similar to that of the first ILD layer 205.

[0027] refer to Figure 1 and Figure 8Method 100 includes block 114, in which an access opening 220 is formed in a top dielectric layer 218 to expose a metal DTI component 216. To form the access opening 220, a hard mask (not shown) may be formed over the top dielectric layer 218. Like hard mask 208, the hard mask in block 114 may be a single layer or multiple layers and may be deposited using chemical vapor deposition (CVD). A photolithography and etching process is then performed to pattern the hard mask. For example, a photoresist layer (not shown) is formed over the hard mask, exposed to a suitable photolithography radiation source, and developed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etching mask to pattern the hard mask over the top dielectric layer 218. The patterned hard mask is then used as an etching mask to anisotropically etch the top dielectric layer, thereby forming the access opening 220. Figure 8 As shown, a plurality of access openings 220 are formed, and each of the access openings 220 is positioned directly above the metal DTI component 216, thereby exposing the metal DTI component 216. Anisotropic etching can be a dry etching process that uses sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), other fluorine-containing gases, oxygen (O2), or mixtures thereof.

[0028] refer to Figure 1 and Figure 9 Method 100 includes a frame 116, wherein a metal grid 222 is formed over a back surface 202B, including formation in access openings 220. As the name suggests, the metal grid 222 is a grid-like structure or frame extending over several (if not all) access openings 220. Brief Reference Figure 12 The illustration shows a partial top view of the metal grid 222 as seen from the rear side 200B of the workpiece 200. From the top view, the metal grid 222 and the metal DTI component 216 directly below it define and isolate the photodetector 240. (As shown...) Figure 12As shown, the metal grid 222 defines the openings of the photodetector 240, and all openings have the same shape and size. In some embodiments, the metal grid 222 may comprise aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). In one embodiment, the metal grid 222 is formed of aluminum (Al). According to the invention, the metal grid 222 can have two functions. First, the metal grid 222 can physically block light reflection between adjacent photodetectors 240 and prevent crosstalk between adjacent photodetectors 240. Second, as will be further described below, the metal grid 222 can serve as a distribution network for the negative bias that is ultimately applied to the metal DTI component 216. In these embodiments, the metal grid 222 is in direct contact with the metal DTI component 216 to apply the negative bias. The negative bias applied at the metal DTI component 216 provides additional electrical isolation between adjacent photodetectors 240.

[0029] refer to Figure 1 and Figure 10 Method 100 includes a frame 118 in which a color filter 224 is formed over the back surface 202B of a workpiece 200. The color filter 224 may be formed of a polymeric material or resin comprising colored pigments. At frame 118, a plurality of color filters 224 are then formed over a metal grid 222 to fill openings in the metal grid 222. In some embodiments, the plurality of color filters 224 may be formed by forming a color filter layer to fill openings in the metal grid and then patterning the color filter layer. The color filter layer is formed of a material that allows radiation (e.g., light) with a specific wavelength range to pass through while blocking light of wavelengths outside the specific range.

[0030] refer to Figure 1 and Figure 11 Method 100 includes frame 120, wherein a planarization layer 226 is deposited over color filter 224. In some embodiments, planarization layer 226 may comprise an organic or polymeric material having high transmittance to visible light. This allows light to pass through planarization layer 226 with very little distortion, making the light detectable by photodetector 240. Planarization layer 226 may be formed by spin coating, which provides a uniform and flat layer.

[0031] refer to Figure 1 and Figure 11Method 100 includes a frame 122 in which a microlens component 228 is formed over a planarization layer 226. The microlens component 228 can be formed from any material that can be patterned and formed into a lens, such as a high-transmittance acrylic polymer. In embodiments, the microlens layer can be formed using liquid materials and spin-coating techniques. It has been found that this method produces a substantially flat surface and a microlens layer with a substantially uniform thickness, thereby providing greater uniformity in the microlens component 228. Other methods, such as CVD, PVD, etc., can also be used. The planar material for the microlens layer can be patterned using photolithography and etching techniques to pattern the planar material in an array corresponding to the photodiode array 240. The planar material is then reflowed to form a suitable curved surface for the microlens component 228. The microlens component 228 can be cured using ultraviolet (UV) treatment.

[0032] Although method 100 is a combination Figure 1 and Figure 11 The workpiece 200 is described using a partial cross-sectional view, but method 100 can be used to form... Figures 13 to 18 The optional semiconductor structure or image sensor shown.

[0033] Figure 13 An image sensor 200 is illustrated, which includes a metal DTI component 216 configured to be negatively biased. Although Figure 13 The image sensor 200 in the middle is similar to Figure 11 The image sensor 200 includes a negative bias source 250 electrically coupled to a metal grid 222. Because the metal grid 222 is in direct contact with the metal DTI component 216, the negative bias source 250 can apply a negative bias at the metal DTI component 216. Figure 13 As shown, when a negative bias is applied, positive charges or holes 252 can be attracted to the metal DTI component 216. The attracted positive charges or holes 252 can provide additional electrical isolation between adjacent photodiodes 240.

[0034] Figure 14 The image sensor 200 is illustrated, in which a portion of the metal grid 222 is omitted to increase the aperture of the incident light. Although Figure 14 The image sensor 200 in the middle is similar to Figure 11 The image sensor 200 is configured such that the metal grid 222 is not attached to each metal DTI component 216. In some embodiments, the metal grid 222 is attached only along the X direction and / or along the Y direction to every other metal DTI component 216. While the metal grid 222 serves to prevent crosstalk, it can reduce the overall aperture of the image sensor 200, resulting in less light penetrating into the photodiode 240. By removing a portion of the metal grid 222, Figure 14The image sensor 200 in the middle can have more than Figure 11 The image sensor in it has a larger overall aperture. Similar to Figure 13 Image sensor 200 in Figure 14 The image sensor 200 may include a negative bias source 250 configured to apply a negative bias at the metal DTI component 216.

[0035] Figure 15 The image sensor 200 is illustrated, in which the metal DTI component 216 does not reach the STI component 206. Although Figure 15 The image sensor 200 in the middle is similar to Figure 11 The image sensor 200 is shown, but the metal DTI component 216 (or the deep trench 209 where the metal DTI component 216 is located) does not have an STI component 206 adjacent to the front side 200F. This configuration can be called a partially isolated structure because the metal DTI component 216 does not completely isolate two adjacent photodiodes 240. This partially isolated structure can be achieved when the substrate 202 is thick and the metal DTI component 216 may not be able to be formed satisfactorily due to limitations in the etching or deposition process. Similar to... Figure 13 Image sensor 200 in Figure 15 The image sensor 200 may include a negative bias source 250 configured to apply a negative bias at the metal DTI component 216.

[0036] Figure 16 The image sensor 200 is illustrated, wherein a metal DTI component 216 extends from the rear side 200B and passes through an STI component 206 adjacent to the front side 200F. Although Figure 16 The image sensor 200 in the middle is similar to Figure 11 The image sensor 200 is used, but the metal DTI component 216 (or the deep trench 209 where the metal DTI component 216 is located) extends completely through the substrate 202 and the STI component 206. This configuration can be called a fully isolated structure because the metal DTI component 216 completely isolates two adjacent photodiodes 240 along the X direction. This fully isolated structure can be implemented to maximize the isolation between adjacent photodiodes 240. Similar to... Figure 13 Image sensor 200 in Figure 16 The image sensor 200 may include a negative bias source 250 configured to apply a negative bias at the metal DTI component 216.

[0037] Figure 11 and Figures 13 to 16 The metal DTI component 216 shown extends from the back side 200B of the workpiece 200 into the substrate 202 and may be referred to as the back side DTI. Figure 11 and Figures 13 to 16 The image sensor 200 is different. Figure 17 or Figure 18 The image sensor 200 includes a metal DTI component 216 extending from the front side 200F into the substrate 202. As a result, Figure 17 and Figure 18 The metal DTI component 216 shown can be referred to as the front DTI. As described above, a deep groove can be formed from the front side 200F of the workpiece 200 when optional block 104 of method 100 is not performed before block 106. Figure 17 or Figure 18 In some embodiments shown, a deep trench or metal DTI component 216 extends through the first ILD layer 205, the STI component 206, and the substrate 202. Figure 17 In some embodiments shown, the metal DTI component 216 does not extend completely through the substrate 202 and may terminate at the substrate 202. Figure 18 In some other embodiments shown, the metal DTI component 216 extends completely through the substrate 202.

[0038] First refer to Figure 17 .and Figure 11 The image sensor 200 is different. Figure 17 Dielectric layer 214 is deposited above the front side 200F. As a result, the first dielectric layer 210 is in direct contact with the substrate 202, the STI component 206, and the first ILD layer 205. A second dielectric layer 211 is disposed between the first dielectric layer 210 and the metal DTI component 216, and a third dielectric layer 212 is disposed between the second dielectric layer 211 and the metal DTI component 216. Due to the orientation of the workpiece 200, Figure 17 The image sensor 200 includes a bottom dielectric layer 2180. The composition and formation process of the bottom dielectric layer 2180 can be similar to that of the top dielectric layer 218. Each of the metal DTI components 216 is now disposed on a front contact component 2220, which extends through the bottom dielectric layer 2180 to directly contact the metal DTI component 216. In embodiments where the image sensor 200 includes a negative bias source 250, the negative bias source 250 passes through the front contact component 2220 instead of... Figure 11 and Figures 13 to 16 The metal grid 222 shown applies a negative bias to the metal DTI component. (This is related to the formation...) Figure 12 Unlike the checkerboard-like frame with its metal grid 222, the front contact component 2220 resembles a contact component in an interconnect structure and does not form a grid. Instead of the metal grid 222, Figure 17The image sensor 200 may include a composite grid 270 comprising a conductive grid 274 embedded in a low-refractive-index (low-n) layer 272. In some cases, the low-refractive-index (low-n) layer 272 may be formed of a porous silicon oxide material, and the conductive grid 274 may be formed of a metal such as aluminum. Unlike Figure 11 and Figures 13 to 16 The metal grid 222 and conductive grid 274 shown are insulated from the metal DTI component 216. (As shown) Figure 17 As shown, the conductive grid 274 is spaced apart from the metal DTI component 216 by the substrate 202 and the dielectric layer 214. Because the metal DTI component 216 does not extend completely through the substrate 202, the image sensor 200 includes a partially isolated structure. A second ILD layer 260 may be formed over the bottom dielectric layer 2180 and the front contact component 2220. The second ILD layer 260 may be similar to the first ILD layer 205 in composition and formation process.

[0039] Then refer to Figure 18 .and Figure 17 Unlike the image sensor 200, the dielectric layer 214 above the metal DTI component 216 is in contact with the composite grid 270. That is, Figure 18 The image sensor 200 includes a fully isolated structure in which a metal DTI component 216, together with a dielectric layer 214, completely isolates the adjacent photodiode 240. Similar to... Figure 17 In the image sensor 200, the first dielectric layer 210 is in direct contact with the substrate 202, the STI component 206, and the first ILD layer 205. A second dielectric layer 211 is disposed between the first dielectric layer 210 and the metal DTI component 216, and a third dielectric layer 212 is disposed between the second dielectric layer 211 and the metal DTI component 216. Due to the orientation of the workpiece 200, Figure 17 The image sensor 200 includes a bottom dielectric layer 2180. The composition and formation process of the bottom dielectric layer 2180 can be similar to that of the top dielectric layer 218. Each of the metal DTI components 216 is now disposed on a front contact component 2220, which extends through the bottom dielectric layer 2180 to directly contact the metal DTI component 216. In embodiments where the image sensor 200 includes a negative bias source 250, the negative bias source 250 passes through the front contact component 2220 instead of... Figure 11 and Figures 13 to 16 The metal grid 222 shown applies a negative bias to the metal DTI component. (This is related to the formation...) Figure 12 Unlike the checkerboard-like frame with its metal grid 222, the front contact component 2220 resembles a contact component in an interconnect structure and does not form a grid. Instead of the metal grid 222, Figure 18The image sensor 200 may include a composite grid 270 comprising a conductive grid 274 embedded in a low-refractive-index (low-n) layer 272. In some cases, the low-refractive-index (low-n) layer 272 may be formed of a porous silicon oxide material, and the conductive grid 274 may be formed of a metal such as aluminum. Unlike Figure 11 and Figures 13 to 16 The metal grid 222 and conductive grid 274 shown are insulated from the metal DTI component 216. (As shown) Figure 18 As shown, the conductive grid 274 is spaced apart from the metal DTI component 216 by a dielectric layer 214, which includes a first dielectric layer 210, a second dielectric layer 211, and a third dielectric layer 212. A second ILD layer 260 may be formed above the bottom dielectric layer 2180 and the front contact component 2220. The second ILD layer 260 may be similar to the first ILD layer 205 in composition and formation process.

[0040] The metal DTI component 216 of this invention is tapered. For example... Figure 11 and Figures 13 to 16 As shown, the back-side metal DTI component 216 has a back surface that contacts the metal grid 222 and a front surface that is away from the metal grid 222. For the back-side metal DTI component 216, the back surface is larger than the front surface. Figure 11 and Figures 13 to 16 In the middle, the dorsal surface includes a first dorsal width WB1 along the X direction, and the front surface includes a first front width WF1 along the X direction. The first dorsal width WB1 is greater than the first front width WF1. That is, Figure 11 and Figures 13 to 16 The metal DTI component 216 tapers gradually from the back surface toward the front surface. In some cases, the first back width WB1 can be between about 10 nm and about 5000 nm, and the first front width WF1 can be between about 15 nm and about 6000 nm. Figure 17 and Figure 18 As shown, the front metal DTI component 216 has a front surface that contacts the front contact component 2220 and a back surface that is away from the front contact component 2220. For the front metal DTI component 216, the front surface is larger than the back surface. Figure 17 and Figure 18 In the middle, the dorsal surface includes a second dorsal width WB2 along the X direction, and the front surface includes a second front width WF2 along the X direction. The second front width WF2 is greater than the second dorsal width WB2. That is, Figure 17 and Figure 18The metal DTI component 216 tapers gradually from the front surface toward the back surface. In some cases, the second back width WB2 can be between about 10 nm and about 5000 nm, and the second front width WF1 can be between about 15 nm and about 6000 nm.

[0041] Embodiments of the present invention offer advantages. For example, the present invention provides an image sensor comprising photodiodes in a sensor substrate. The photodiodes are separated by metallic DTI components that can extend partially or completely through the thickness of the sensor substrate. The metallic DTI components can be formed from the front or back of the sensor substrate. As the name suggests, the metallic DTI components are formed of metal and can be used as reflectors to improve the quantum efficiency (QE) of the image sensor. Additionally, the metallic DTI components can be electrically coupled to a metal grid or contact component configured to apply a negative bias at the metallic DTI component. The negative bias can improve the electrical isolation between adjacent photodiodes. Because the metallic DTI components are formed after the transistors are formed, the process for forming the metallic DTI components can be easily integrated with processes of different technology generations.

[0042] Therefore, in some embodiments, the present invention provides a semiconductor structure. The semiconductor structure includes a semiconductor layer, a plurality of metal isolation components disposed in the semiconductor layer, a metal grid disposed directly above and in contact with the plurality of metal isolation components, and a plurality of microlens components disposed above the metal grid.

[0043] In some embodiments, a plurality of metal isolation members extend partially into the semiconductor layer. In some embodiments, the plurality of metal isolation members extend completely through the semiconductor layer. In some embodiments, the plurality of metal isolation members and the metal grid comprise aluminum. In some embodiments, the plurality of metal isolation members are disposed above a plurality of dielectric isolation members disposed in the semiconductor layer. In some cases, the plurality of metal isolation members extend at least partially through the plurality of dielectric isolation members disposed in the semiconductor layer. In some embodiments, the semiconductor structure may further include a first dielectric layer disposed between the semiconductor layer and the plurality of metal isolation members, a second dielectric layer disposed between the first dielectric layer and the plurality of metal isolation members, and a third dielectric layer disposed between the second dielectric layer and the plurality of metal isolation members. The composition of the first dielectric layer differs from the composition of the second dielectric layer and the third dielectric layer. In some embodiments, the first dielectric layer comprises aluminum oxide, hafnium oxide, or a combination thereof, the second dielectric layer comprises tantalum oxide, and the third dielectric layer comprises silicon oxide. In some embodiments, the semiconductor device may further include a top dielectric layer disposed above the plurality of metal isolation members and the third dielectric layer, and the metal grid extends through the top dielectric layer to contact the plurality of metal isolation members. In some embodiments, the semiconductor device may further include a color filter disposed between the semiconductor layer and the plurality of microlens components, and a planarization layer disposed between the color filter and the plurality of microlens components.

[0044] Another aspect of the invention relates to an image sensor. The image sensor includes a first deep trench isolation (DTI) component and a second DTI component, a photodetector disposed between the first DTI component and the second DTI component, and a metal grid disposed on and in direct contact with the first DTI component and the second DTI component. The first DTI component, the second DTI component, and the metal grid are made of aluminum.

[0045] In some embodiments, the image sensor may further include a bias source electrically coupled to a metal grid, and the bias source and the metal grid are configured to apply a negative bias to a first DTI component and a second DTI component. In some embodiments, the image sensor may further include a semiconductor layer. The first and second DTI components partially extend into the semiconductor layer, and the thickness of the semiconductor layer is between about 1.5 μm and about 50 μm. In some embodiments, the image sensor may further include a semiconductor layer. The first and second DTI components extend completely into the semiconductor layer, and the thickness of the semiconductor layer is between about 1.5 μm and about 50 μm. In some cases, the image sensor may further include a first shallow trench isolation (STI) component, a second STI component, and a transistor disposed below the photodetector and between the first and second STI components. The first DTI component is located directly above the first STI component, and the second DTI component is located directly above the second STI component.

[0046] Another aspect of the present invention relates to a method. The method includes: receiving a substrate having a plurality of transistors adjacent to a front side of a substrate; forming a plurality of deep trenches from a back side of the substrate after forming a plurality of deep trenches; depositing a first dielectric layer on the back side of the substrate; forming a plurality of metal isolation members in the plurality of deep trenches after depositing the first dielectric layer; forming a top dielectric layer over the plurality of metal isolation members; forming a plurality of metal grid openings to expose the plurality of metal isolation members; and forming a metal grid in the plurality of metal grid openings.

[0047] In some embodiments, the substrate comprises silicon, and the thickness of the substrate is between about 1.5 μm and about 50 μm. In some embodiments, forming multiple deep trenches includes depositing aluminum over the back side of the substrate. In some cases, the method may also include depositing a second dielectric layer over a first dielectric layer and depositing a third dielectric layer on the second dielectric layer before forming multiple metal isolation components. In some embodiments, the first dielectric layer comprises aluminum oxide, hafnium oxide, or a combination thereof, the second dielectric layer comprises tantalum oxide, and the third dielectric layer comprises silicon oxide.

[0048] The features of several embodiments have been outlined above to enable those skilled in the art to better understand the following detailed description. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention. For example, different resistances of the conductors can be achieved by implementing different thicknesses for the bit line conductors and word line conductors. However, other techniques can also be used to change the resistance of the metallic conductors.

Claims

1. A semiconductor device, comprising: A semiconductor layer includes a first surface and a second surface opposite to the first surface; Multiple dielectric isolation components are disposed within the semiconductor layer and adjacent to a first surface of the semiconductor layer; Multiple metal isolation components extend from the second surface of the semiconductor layer; A metal grid is disposed directly above and in contact with the plurality of metal isolation components; Multiple microlens components are disposed above the metal grid; as well as The first dielectric layer extends continuously along the second surface of the semiconductor layer, between the semiconductor layer and the plurality of metal isolation components, and between each of the plurality of metal isolation components and a corresponding one of the plurality of dielectric isolation components.

2. The semiconductor device according to claim 1, wherein, The plurality of metal isolation components extend into the semiconductor layer.

3. The semiconductor device according to claim 1, wherein, The plurality of metal isolation components extend completely through the semiconductor layer.

4. The semiconductor device according to claim 1, wherein, The plurality of metal isolation components and the metal grid comprise aluminum.

5. The semiconductor device according to claim 1, wherein, The plurality of metal isolation components terminate within the semiconductor layer and do not extend into the plurality of dielectric isolation components.

6. The semiconductor device according to claim 1, wherein, The plurality of metal isolation components extend at least partially through the plurality of dielectric isolation components.

7. The semiconductor device according to claim 1, further comprising: A second dielectric layer is disposed between the first dielectric layer and the plurality of metal isolation components; as well as A third dielectric layer is disposed between the second dielectric layer and the plurality of metal isolation components. The composition of the first dielectric layer is different from the composition of the second dielectric layer and the composition of the third dielectric layer.

8. The semiconductor device according to claim 7, in, The first dielectric layer comprises aluminum oxide, hafnium oxide, or a combination thereof. The second dielectric layer includes tantalum oxide. The third dielectric layer comprises silicon oxide.

9. The semiconductor device according to claim 7, further comprising: A top dielectric layer is disposed above the plurality of metal isolation components and the third dielectric layer. The metal grid extends through the top dielectric layer to contact the plurality of metal isolation components.

10. The semiconductor device according to claim 7, further comprising: A color filter is disposed between the semiconductor layer and the plurality of microlens components; as well as A planarization layer is disposed between the color filter and the plurality of microlens components.

11. An image sensor, comprising: A semiconductor layer includes a first surface and a second surface opposite to the first surface; The first deep trench isolation component and the second deep trench isolation component extend from the second surface of the semiconductor layer; A first shallow trench isolation component and a second shallow trench isolation component are disposed within the semiconductor layer and adjacent to a first surface of the semiconductor layer, wherein the first deep trench isolation component is located directly above the first shallow trench isolation component, and the second deep trench isolation component is located directly above the second shallow trench isolation component. A photodetector is disposed between the first deep trench isolation component and the second deep trench isolation component; A metal grid is disposed on the first deep trench isolation component and the second deep trench isolation component and is in direct contact with the first deep trench isolation component and the second deep trench isolation component; and A first dielectric layer extends continuously along the second surface of the semiconductor layer, between the semiconductor layer and the first deep trench isolation member and the second deep trench isolation member, between the first deep trench isolation member and the first shallow trench isolation member, and between the second deep trench isolation member and the second shallow trench isolation member. The first deep trench isolation component, the second deep trench isolation component, and the metal grid are all made of aluminum.

12. The image sensor according to claim 11, further comprising: A bias source, electrically coupled to the metal grid, The bias source and the metal grid are configured to apply a negative bias to the first deep trench isolation component and the second deep trench isolation component.

13. The image sensor according to claim 11, wherein, The first deep trench isolation component and the second deep trench isolation component extend partially into the semiconductor layer. The thickness of the semiconductor layer is between about 1.5 μm and about 50 μm.

14. The image sensor according to claim 11, in, The first deep trench isolation component and the second deep trench isolation component extend completely into the semiconductor layer. The thickness of the semiconductor layer is between about 1.5 μm and about 50 μm.

15. The image sensor according to claim 11, further comprising: A transistor is disposed below the photodetector and between the first shallow trench isolation component and the second shallow trench isolation component.

16. A method for forming an image sensor, comprising: A substrate comprising a plurality of transistors is received, the plurality of transistors being adjacent to the front side of the substrate; Multiple deep trenches are formed from the back side of the substrate; After the formation of the plurality of deep trenches, a first dielectric layer is deposited over the back side of the substrate; After the first dielectric layer is deposited, a plurality of metal isolation components are formed in the plurality of deep trenches; A top dielectric layer is formed above the plurality of metal isolation components; Multiple metal grid openings are formed to expose the multiple metal isolation components; as well as Metal grids are formed in the plurality of metal grid openings. The plurality of dielectric isolation components are disposed within the substrate and adjacent to the front side of the substrate, and wherein the first dielectric layer extends continuously along the back side of the substrate, between the substrate and the plurality of metal isolation components, and between each of the plurality of metal isolation components and a corresponding one of the plurality of dielectric isolation components.

17. The method according to claim 16, in, The substrate comprises silicon. The thickness of the substrate is between about 1.5 µm and about 50 µm.

18. The method according to claim 16, wherein, The formation of the plurality of deep trenches includes depositing aluminum over the back side of the substrate.

19. The method of claim 16, further comprising: Before forming the plurality of metal isolation components, a second dielectric layer is deposited over the first dielectric layer; as well as A third dielectric layer is deposited on top of the second dielectric layer.

20. The method according to claim 19, in, The first dielectric layer comprises aluminum oxide, hafnium oxide, or a combination thereof. The second dielectric layer includes tantalum oxide. The third dielectric layer comprises silicon oxide.

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