Storage devices with improved durability

Abstract

This invention discloses a black box device for a vehicle, comprising a data storage system for recording event data fed to the black box from various vehicle sensors. The data storage system includes a memory having memory cells and a controller communicating with the memory. The controller is configured to receive data and determine one or more memory cells as destinations for writing the data. The controller is configured to determine wear levels of the memory cells and select a subset of programming states of the memory cells based on the wear levels; and to program the memory cells using a subset of the corresponding programming states for each respective memory cell.

Description

Technical Field

[0001] This disclosure relates to memory systems, and more particularly, to improving the durability of memory devices. Background Technology

[0002] Recent regulations require manufacturers of vehicles equipped with autonomous driving capabilities to install black boxes to help determine liability in the event of an accident. The use of black boxes helps ensure the safe deployment of autonomous driving technology. Black boxes may be needed to record data while the autonomous driving system is active, while the driver is driving the vehicle, and when the system requires the driver to take over. Furthermore, black boxes may need to remain operational and reliably retain the necessary data for many years. Therefore, highly durable storage devices may be required within the black box. Summary of the Invention

[0003] The specific embodiments described herein depict storage devices with improved durability. Various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, and no single one is solely responsible for the desired properties described herein. Some prominent features are described without limiting the scope of the appended claims. After considering this discussion, and specifically after reading the section entitled "Detailed Description," it should be understood how the features of the various embodiments can be used to reduce bit error rates in a first read scenario. Attached Figure Description

[0004] To gain a more detailed understanding of this disclosure, a more specific description can be obtained by referring to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, the drawings only illustrate more relevant features of this disclosure and are therefore not to be considered limiting, as the description may acknowledge other valid features.

[0005] Figure 1 This is a block diagram of a data storage system based on some implementation schemes.

[0006] Figure 2 This is a diagram of a memory cell array in the storage medium of a storage device according to some implementation schemes.

[0007] Figure 3 This is a diagram of memory cells based on some implementation schemes.

[0008] Figures 4A to 4C This is a graph showing the threshold voltage distribution of an exemplary memory cell according to some implementation schemes.

[0009] Figures 5A to 5D This is a graph showing the threshold voltage distribution of an exemplary memory cell according to some implementation schemes.

[0010] Figures 6A to 6B This is a graph showing the threshold voltage distribution of an exemplary memory cell according to some implementation schemes.

[0011] Figures 7A to 7C This is a graph showing the threshold voltage distribution of an exemplary memory cell according to some implementation schemes.

[0012] Figure 8 This is a flowchart illustrating a method for programming a memory cell according to some implementation schemes.

[0013] In accordance with common practice, various features shown in the accompanying drawings may not be drawn to scale. Therefore, for clarity, the dimensions of various features may be arbitrarily expanded or reduced. Furthermore, some drawings may not depict all components of a given system, method, or apparatus. Finally, similar reference numerals may be used throughout the specification and drawings to denote similar features. Detailed Implementation

[0014] The various specific implementations described herein include systems, methods, and / or apparatuses that have improved durability while minimizing the additional costs resulting from increased memory.

[0015] This document describes numerous details to provide a thorough understanding of the exemplary embodiments illustrated in the accompanying drawings. However, the invention can be practiced without these numerous details. Furthermore, known methods, components, and circuits are not described exhaustively to avoid unnecessarily obscuring more relevant aspects of the specific embodiments described herein. While the technology described herein is specifically related to vehicle black box recording equipment, those skilled in the art will understand that this technology can be applied to other equipment and devices, such as Internet of Things (IoT) devices.

[0016] Figure 1 This is a diagram illustrating a specific implementation of a data storage environment (i.e., data storage system 100). An exemplary storage system could be a black box event data logger (EDR) for vehicles such as cars, trucks, trains, airplanes, etc.

[0017] However, the concepts described herein can be applied to other data storage systems, including but not limited to storage systems for computing devices such as computers, laptops, tablets, netbooks, internet kiosks, personal digital assistants, mobile phones, smartphones, gaming devices, computer servers, Internet of Things (IoT) devices, smart home devices, or any other computing device. While certain specific features are shown, those skilled in the art will understand from this disclosure that various other features are not shown for brevity so as not to obscure more relevant aspects of the exemplary specific implementations disclosed herein. Therefore, as a non-limiting example, data storage system 100 includes a data processing system (alternatively referred to herein as a computer system or host) 110 and a storage device 120.

[0018] Host 110 is coupled to storage device 120 via data connector 101. In various embodiments, host 110 includes storage device 120 as a component. In some embodiments, host 110 includes one or more processors, one or more types of memory, a display and / or other user interface components, such as a keyboard, touchscreen display, mouse, touchpad, digital camera and / or any number of supplementary devices for adding functionality.

[0019] Storage device 120 includes one or more storage media 130 (sometimes referred to as non-volatile memory or NVM) coupled to storage controller 124 via data connection 103. In various embodiments, storage controller 124 and storage media 130 are included in the same device (e.g., storage device 120) as their constituent parts, while in other embodiments, storage controller 124 and storage media 130 are separate devices or in separate devices. Each data storage medium 130 includes any number (i.e., one or more) of memory devices, including but not limited to non-volatile semiconductor memory devices such as flash memory. For example, flash memory devices may be configured for enterprise storage suitable for applications such as cloud computing. Additionally and / or alternatively, flash memory devices may also be configured for relatively small-scale applications such as personal flash drives, or for hard drive replacements for personal computers, laptops, and tablets. In some embodiments, storage medium 130 includes one or more flash memory devices. In some embodiments, storage medium 130 includes at least one of NAND flash memory and / or NOR flash memory.

[0020] Storage media are typically divided into multiple addressable and individually selectable blocks, such as selectable portions 131. In some implementations, for flash memory, these individually selectable blocks are the smallest erasable units in the flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously. Each block is typically further divided into multiple pages, where each page is typically an instance of the smallest unit of the smallest individually accessible sub-block within the block. However, in some implementations (e.g., in some types of flash memory), the smallest unit of individually accessible data is a sector, which is a subset of a page. That is, each page contains multiple sectors, and each sector is the smallest unit of individually accessible data for writing data to or reading data from the flash memory device.

[0021] For illustrative purposes only, a data block comprises multiple pages, typically with a fixed number of pages per block, and each page comprises multiple sectors, typically with a fixed number of sectors per page. For example, in some implementations, a block may comprise 64 pages, 128 pages, 256 pages, or another suitable number of pages. The corresponding sizes of blocks, pages, and sectors typically depend on design choices or end-user choices and generally vary across a wide range of enterprise and consumer devices. However, by way of example and not limitation, in some enterprise applications, pages comprise 2K (i.e., 2048) bytes to 16K bytes, and sectors comprise any number of bytes from 256 bytes to 544 bytes. Depending on the specific application, those ranges may extend upwards or downwards, and / or shrink or expand. In some implementations, each page stores one or more codewords, where a codeword is the smallest unit of data that is individually encoded and decoded by the encoder and decoder mechanisms of the device-specific device.

[0022] Storage medium (NVM) 130 may include a number of growing physical bad blocks (also known as growing dead blocks). Growing dead blocks are blocks that become bad (i.e., fail to meet one or more data lifetime specifications) during the use of the storage device. Growing dead blocks are typically deactivated because they can no longer be reliably written to. Deactivated blocks become read-only. In some implementations, the number of growing physical bad blocks allowed is up to and exceeds approximately 5% of all physical blocks (or all addressable blocks), and up to approximately 95% of all physical blocks (or all addressable blocks), where “approximately” indicates ±10% of the value. It should be understood that an additional number of growing physical bad blocks may be allowed depending on the application. Therefore, the foregoing disclosure of a number of 5% of all blocks should not be construed as a necessary limitation.

[0023] In some implementations, the storage medium (NVM) 130 has a defined ratio of exported capacity to physical capacity that is greater than 0.02 and less than about 0.50 (where "about" indicates ±10% of the value). Exported capacity (also known as user capacity, host exported capacity, and host address range) is the size of the storage medium from the perspective of a user or host. More formally, exported capacity is defined by multiplying the range of addresses available for host writes by the number of bytes per address. For example, if a host writes data in 4KB units and there are 1,024 available addresses for writing those data units, the exported capacity is 4,096KB (approximately 4MB).

[0024] On the other hand, physical capacity refers to the physical size of the storage medium (the total number of memory cells). Derived capacity is allocated to data specified for writing by the host, while the remaining memory cells (physically present but not included in the address range) are typically used for error correction (e.g., ECC, parity bits, etc.). It should be understood that other ratios may be permitted depending on the application. Therefore, the aforementioned disclosure of ratios greater than 0.02 and less than approximately 0.50 should not be construed as a necessary limitation.

[0025] In some embodiments, the storage controller 124 includes a management module 121, an error control module 125, a storage media interface (I / O) 128, and a host interface 129. The host interface 129 couples the storage device 120 and its storage controller 124 to one or more hosts 110, while the storage media interface 128 couples the storage controller 124 to a storage medium 130. In some embodiments, the storage controller 124 includes various additional features, which are not shown for brevity so as not to obscure the more relevant features of the exemplary embodiments disclosed herein, and different arrangements of the features may be possible.

[0026] Host interface 129 typically includes a data buffer (not shown) to buffer data received and transmitted by storage device 120 via data connector 101. Similarly, storage medium I / O 128 provides an interface to storage medium 130 via data connector 103. In some embodiments, storage medium interface 128 includes read and write circuitry.

[0027] In some implementations, management module 121 includes one or more processors 122. However, in some implementations, processor 122 is shared by one or more components that are within the functionality of storage controller 124 and, in some cases, beyond its functionality.

[0028] The management module 121 is coupled to the host interface 129, the error control module 125, and the storage medium I / O 128 to coordinate the operation of these components.

[0029] Error control module 125 is coupled between storage medium I / O 128 and host interface 129. In some implementations, error control module 125 is provided to limit the number of uncorrectable errors unintentionally introduced into the data. For this purpose, error control module 125 includes encoder 126 and decoder 127. Encoder 126 encodes data to produce codewords, which are then stored in storage medium 130. When the encoded data is read from storage medium 130, decoder 127 applies a decoding process to recover the data and correct errors within the error correction capabilities of the error control codes. Various error control codes have different error detection and correction capabilities, and specific codes are selected for various applications.

[0030] In some implementations, the error control module 125 is configured to calculate the error correction code (ECC) for the data received from the host 110 and store the ECC along with the received data. In some implementations, the ECC code rate is less than about 0.60 (where "about" means ±10% of the value). It should be understood that different ECC code rates may be required depending on the application. Therefore, the foregoing disclosure regarding an ECC code rate of 0.60 should not be construed as a necessary limitation.

[0031] Management module 121 typically includes one or more processors 122 (sometimes referred to herein as CPU, processing unit, hardware processor, processor, microprocessor, or microcontroller) for executing modules, programs, and / or instructions stored in memory, and thereby performing processing operations. Management module 121 also includes memory 123 (sometimes referred to herein as controller memory) and one or more communication buses for interconnecting these components. The communication buses optionally include circuitry (sometimes referred to as chipsets) that interconnects system components and controls communication therebetween. Management module 121 is coupled to storage media interface 128, error control module 125, and host interface 129 via the communication buses. Controller memory 123 includes high-speed random access memory such as DRAM, SRAM, DDR RAM, or other random access solid-state memory devices, and may include non-volatile memory such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Controller memory 123 optionally includes one or more storage devices located remotely from one or more processors 122. In some embodiments, the controller memory 123 or alternatively, the non-volatile memory device within the controller memory 123 includes a non-transitory computer-readable storage medium. In some embodiments, the controller memory 123 or the non-transitory computer-readable storage medium of the controller memory 123 stores one or more programs, modules, and data structures, or subsets or supersets thereof, for performing the operations described herein.

[0032] Each of the elements identified above may be stored in one or more of the previously mentioned memory devices and corresponds to an instruction set for performing the functions described above. The modules or programs identified above (i.e., instruction sets) do not need to be implemented as separate software programs, processes, or modules, and therefore various subsets of these modules may be combined or otherwise rearranged in various embodiments. In some embodiments, memory 123 may store a subset of the modules and data structures identified above. Furthermore, memory 123 may store additional modules and data structures not described above. In some embodiments, programs, modules, and data structures stored in memory 123 or a non-transitory computer-readable storage medium of memory 123 provide instructions for implementing any of the methods described below. In other words, a program or module stored in memory 123, when executed by one or more processors 122, causes storage device 120 to perform any of the methods described below. Although Figure 1 Various modules are shown, but Figure 1 This is intended more as a functional description of the various features that can exist within a module, rather than as a structural diagram of the implementation described herein. During implementation, programs, modules, and data structures shown individually can be combined, and some programs, modules, and data structures can be separated.

[0033] Figure 2 The optional portion 131, including storage medium 130, is depicted. Figure 1 An exemplary block 200 of a memory cell array. In this example, the memory cell array is configured as a NAND array. The depicted configuration is one of many possible configurations, and various other configurations (e.g., NOR arrays, 3D NAND, etc.) are not shown for the sake of brevity so as not to obscure more relevant aspects of the exemplary specific implementation disclosed herein.

[0034] In the exemplary array, string 202 (column) is the smallest readable unit and may consist of 32 or 64 memory cells. Depending on the application, strings may include other numbers of memory cells (e.g., greater than 64, less than 32, or between 32 and 64). All strings in the array are connected at one end to a common source line 206 and at the other end to a bit line (e.g., BL3). Each string also includes two control transistors connected in series with the memory cells. String and ground select transistors are connected to the string select line (SGD) and the ground select line (SGS), respectively.

[0035] In the exemplary array, pages 204 (rows) share the same word line and are the smallest programmable units. They can consist of at least 32,768 (32K), 64K, or 128K memory units. Depending on the application, pages may include other numbers of memory units (e.g., greater than 128K, less than 32K, or between 32K and 128K). Typically, page sizes are referred to as 2K, 4K, 8K, and so on. This indicates that the page size is in bytes. So if the page size has 32,768 memory units (bits), that equals 4,096 (4K) bytes.

[0036] In the exemplary array, block 200 is a two-dimensional matrix consisting of strings (columns) and pages (rows). The total number of bits in a block can be calculated by multiplying the number of strings by the number of pages. Depending on the memory operation to be performed (e.g., read, program, erase), selectable portions 131 of storage medium 130 may include a single page, a single string, or a single block.

[0037] Memory cells in a memory array may have a threshold voltage Vth, which includes... Figures 4A to 4C One of the distributions. Figure 4A The cell distribution in a single-cell (SLC) memory is shown, where each cell is programmed with one bit. Figure 4B The cell distribution in a 2-bit multi-level cell (MLC) memory is shown, where each cell is programmed with two bits. Figure 4C The cell distribution in a 3-bit multi-level cell (TLC) memory is shown, where each cell is programmed with three bits. For SLC flash memory, Figure 2 Each cell in the array has a threshold voltage, which is included in either erase state E or programming state A depending on the value of the programmed data, such as... Figure 4A As shown. For a 2-bit MLC flash memory, Figure 2 Each cell of the array has a threshold voltage, which includes any one of the erase state E or the first programming state A through the third programming state C, such as Figure 4B As shown. For a 3-bit MLC flash memory, Figure 2 Each cell of the array has a threshold voltage, which includes any one of the erase state E or the first programming state A through the seventh programming state G, such as Figure 4C As shown. However, the implementation described herein is not limited to these three configurations. For example, each unit can be programmed with four bits (QLC unit), five bits (PLC unit), or more than five bits. Furthermore, depending on the application, the various units in the array can be programmed with different numbers of bits.

[0038] Return to reference Figure 2Reading the state of a memory cell (e.g., 208) requires distinguishing the cell's voltage threshold level, regardless of the voltage threshold levels of all other cells in the string. To achieve this, the string (e.g., 202) is connected to a sensing circuit (e.g., selecting lines SGD and SGS high), and a specific line (e.g., BL3) is biased; thus, current can flow to (e.g., through string 202) the (grounded) source line. Unselected cells (e.g., cells coupled to WL0 and WL2 through WL7) are placed in transfer transistor mode, thereby biasing their word lines with a transfer voltage greater than the maximum threshold voltage Vth. The actual read operation is then performed by applying a read voltage (e.g., to WL1), sensing the cell current through the cell string (BL3), and comparing the sensed current with a fixed reference value to evaluate the corresponding binary code. More than one operation is performed for MLC, TLC, and QLC cells.

[0039] Figure 3 A memory cell according to some embodiments is shown (e.g., Figure 2 The memory cell (cell 208) is in its programming state. This memory cell includes a control gate 302, a floating gate 306, and a conductive channel 310. In some embodiments (e.g., 3D NAND), the floating gate 306 is referred to as a charge trapping layer, and the conductive channel is referred to as a memory via. The memory cell also includes a tunnel oxide layer 308 disposed between the floating gate 306 and the conductive channel 310, and a gate oxide layer 304 disposed between the control gate 302 and the floating gate 306.

[0040] During a read operation, a read voltage is applied to control gate 302. If the floating gate 306 is programmed (i.e., electrons are present in the floating gate), current will not flow in the conductive channel 310, which is interpreted as logic 0. If the floating gate 306 is erased (i.e., most electrons are no longer present in the floating gate), current will flow in the conductive channel 310, which is interpreted as logic 1. For MLC, TLC, and QLC memories, the amount of current for each consecutively applied read voltage is measured to determine which logic it represents (e.g., 11, 10, 01, 00 for MLC).

[0041] During a write operation, a high voltage (e.g., 12V) is applied to the control gate 302, which pulls electrons from the conductive channel 310 into the floating gate 306. Electrons then escape the conductive channel 310 and tunnel through the oxide 308 into the floating gate 306. For MLC, TLC, and QLC memories, multiple voltages are required to pull varying amounts of electrons into the floating gate. For example, in a TLC memory cell (… Figure 4CIn this configuration, each state AG is associated with a different amount of charge on the floating gate, and the amount of these charges affects how much read current can pass through the conductive path. In some implementations, the programming operation includes one or more programming pulses during which a progressively increasing voltage is applied to the control gate to draw progressively increasing amounts of electrons onto the floating gate.

[0042] Figures 4A to 4C The cell voltage threshold and the corresponding read voltage level (sometimes referred to as the reference voltage level) for the read operation are shown.

[0043] For example, in SLC memory cells ( Figure 4A In the memory, there are two threshold voltages: E (for the erase state: 1) and A (for the programmable state: 0). When the read voltage signal 402 is applied, if current flows through the memory cell, the cell is erased (e.g., logic 1). If no current flows through the memory cell, the cell is programmed (e.g., logic 0).

[0044] In two MLC memory cells ( Figure 4B In the memory, there are four threshold voltages: E (for the erase state: 1) and A through C (for the three programming states: 01, 00, 10). When a read voltage signal 412 is applied, if current flows through the memory cell above the first threshold, the cell is erased (e.g., logic 11). When voltage 414 is applied, if current flows below the first threshold but above the second threshold, the cell is in a first programming state (e.g., logic 01). When voltage 416 is applied, if current flows below the second threshold but above the third threshold, the cell is in a second programming state (e.g., logic 00), and if current flows below the third threshold, the cell is in a third programming state (e.g., logic 10).

[0045] In three-dimensional TLC memory cells ( Figure 4C In the memory, there are eight threshold voltages: E (for the erase state: 1) and A through G (for the seven programming states: 011, 001, 000, 010, 110, 100, 101). When a read voltage 418 is applied, if current flows through the memory cell above the first threshold, the cell is erased (e.g., logic 111). The remaining portions of the read voltage are selected such that they fall between the voltage thresholds for the remaining programming states, as described above regarding... Figure 4B As stated above.

[0046] Specific implementations requiring high durability

[0047] In some applications of the aforementioned data storage system 100, read and write performance requirements are relatively low, while durability requirements are relatively high. For example, in some implementations, the host 110 is a processing system on a vehicle, sometimes referred to as an engine control unit (ECU). In some implementations, the ECU includes one or more controllers and a memory operatively coupled to one or more sensors embedded in the vehicle, and the data transmitted by the ECU for storage in the storage device 120 includes sensor data from one or more of these sensors. In these applications, the storage device 120 is implemented as a black box event data logger (EDR).

[0048] In some EDR implementations, sensor data (provided by host 110 via data connection 101) describes the continuous state of the vehicle, the driver, and / or the environment surrounding the vehicle. Exemplary sensor data may include driver operation data describing interactions between the driver and various control systems of the vehicle, such as accelerator pedal operation data, brake pedal operation data, and / or steering wheel operation data. Exemplary sensor data may include environmental data describing the continuous state of the environment surrounding the vehicle, such as the distance between the vehicle and other vehicles or objects nearby, characteristics of other vehicles or objects nearby, road condition data, speed limit or traffic signal data, road signs, etc. Exemplary sensor data may include driver awareness data (e.g., whether the driver's hands are on the steering wheel, whether the driver's eyes are looking forward, whether a phone call or other communication is being made), event logs (e.g., including warnings for driver control of the vehicle), vehicle health data (e.g., fuel levels, error codes, etc.), and / or any other sensor data indicating the state of the driver, vehicle, and / or environment at any given moment.

[0049] Regarding the read performance in the specific implementation of EDR described herein, reads are very infrequent. Different host units 110 read from storage device 120 (relative to hosts writing to storage device 120). For example, while the ECU in the vehicle writes sensor data and other vehicle-related data as described above to storage device 120, in a collision event, storage device 120 is removed from the vehicle and read in another environment (such as a laboratory) via a computer system optimized for reading accident-recovered data from the EDR storage device (also known as reading "offline"). Because storage device 120 is only read in the event of an accident, this storage device can be configured as a repetitive "write-only" device with relatively low read performance requirements. Therefore, for EDR storage devices, read performance (often a storage bottleneck) can be significantly compromised.

[0050] Regarding the write performance in the specific EDR implementation described herein, the write rate is relatively moderate. In some implementations, the programming rate for storage device 120 is 60 MB per second. However, this rate can be higher or lower depending on the EDR and vehicle-specific specifications. While higher write rates are possible, many vehicle sensor data transfers cannot be performed as quickly as the programming capacity of storage device 120. Therefore, write performance may be compromised for EDR storage devices.

[0051] Regarding the durability of the specific EDR implementations described herein, some jurisdictions require the black box EDR storage device to reliably store sensor data and other information over a lifespan equivalent to 15 years of driving at 8 hours per day. This roughly translates to a total EDR durability capacity requirement of 1,400 terabytes of writes (TBW). On the other hand, not all of this data needs to be stored permanently. For example, a requirement might be to have data from 30 seconds before and 30 seconds after an accident. Data collected during these time windows is sometimes referred to herein as “user data.” This user data could be as little as 4 GB. However, the amount of user data may be higher or lower depending on vehicle specifications, EDR specifications, and time window requirements. While this disclosure relates to exemplary requirements of 1,400 TBW and 4 GB of user data, it should be understood that these figures are merely examples and are not intended to limit the concepts described herein.

[0052] Cost-optimized conventional storage devices may include just enough memory to capture the required user data, but such devices do not meet endurance requirements. On the other hand, conventional storage devices can be designed to meet endurance requirements, but such devices will include far more memory than is needed to capture user data, and will therefore be more expensive. Therefore, there is a need for a storage device that is cost-optimized (i.e., with a relatively low memory footprint) but also meets the endurance requirements of black-box EDR.

[0053] Durability improvement

[0054] The specific implementations described herein increase the durability of the storage device without incurring additional cost in the form of increased memory. For example, while a conventional SLC storage device may perform 100K program / erase cycles (PECs) over its lifetime, the specific implementations described herein allow the storage device to perform 500K to 1M PEC cycles. These figures are sufficient to meet durability requirements of 1,400 TBW.

[0055] Return to reference Figures 4A to 4CThe more bits a storage cell can store, the slower the performance, but the lower the cost (because the memory footprint is smaller). Therefore, multi-layered cell architectures are useful in cost-optimized black-box EDRs. Figure 4C The TLC implementation shown will be more... Figure 4A The SLC shown has a lower implementation cost.

[0056] As another consideration, the higher the programming voltage, the lower the endurance (the number of times a cell can be programmed while data can be reliably stored and read from the cell). Regardless of the type of programming operation or the type of memory cell, the endurance of a memory cell is related to the number of times it passes through tunneling oxide (308) during the cell's lifetime. Figure 3 The amount of electrons tunneling through oxide 308 is inversely proportional to the number of electrons. In other words, the more electrons tunnel through oxide 308, the greater the negative impact on the durability of the memory cell. This is partly attributed to the fact that oxide 308 becomes less resistant to tunneling electrons with successive programming operations, causing a specific control gate voltage to cause the floating gate to acquire more and more charge, thus affecting the read distribution of each state. In other words, when oxide 308 becomes less resistant to tunneling electrons, the programming voltage applied to control gate 302 will result in... Figures 4A to 4C The state distribution shown widens and eventually overlaps, leading to an increase in read errors.

[0057] Therefore, a multi-layer scheme is chosen, but the programming state is restricted to the lower end of the voltage spectrum. Figures 4A to 4C The programming states on the left side of the Vth axis will optimize the memory cells to achieve (i) cost optimization, because using multi-layer cells can achieve a smaller memory footprint, and (ii) durability optimization, because the programming cells require lower voltage.

[0058] Using a two-layer pseudo-TLC programming scheme, such as states A and C (and progressively other states), can be based on a TLC programming scheme with lower, middle, and higher pages, allowing for appropriately finer programming fine-tuning and rates. However, for this pseudo-TLC scheme, all data is only programmed to two states (A and C, or other TLC layers discussed below). Since write time is not limiting, MLC, QLC, and any other programming scheme involving more than two states (not just TLC) can be used, and even finer programming step sizes can be used to relax the requirements for improved durability. The spacing requirement between the two states can also be more relaxed, as more guard bits can be used in decoders less constrained by read latency.

[0059] Figures 5A to 5DA pseudo-TLC scheme is shown for encoding memory cells using a subset (less than all) of the available programmable states. While TLC is used in this example, the basic concepts also apply to MLC, QLC, and any other programming scheme involving more than two states. Figure 5A The available programming states AG and erase state E for a TLC memory cell are shown. In a pseudo-TLC programming scheme, a TLC memory cell can be programmed to represent only two states, similar to the SLC programming scheme. However, in the pseudo-TLC scheme, these two states are determined by two states in the TLC state (e.g., ...). Figure 5B (states A and B in the SLC) instead of two SLC states ( Figure 4A E and A in the text are used to represent this. For example, in pseudo-TLC scheme 510-1 ( Figure 5B The voltages required for programming states A and B in SLC scheme 410 are lower than those required in SLC scheme 410. Figure 4A The voltage required for programming state A in the program is reduced, thus improving durability.

[0060] Due to the proximity of the programming states (e.g., states A and B in scheme 500-1), memory cells programmed using a pseudo-TLC scheme will eventually result in read errors. This is known as device loss and is caused by the oxide layer between the floating gate and the control gate, as described above, becoming less resistant to tunneling electrons. Therefore, the memory controller 124 can switch states such that they are further apart while still maintaining the state at the lower end of the voltage spectrum (closer). Figures 5A to 5D Instead of marking the cell as unavailable, the left side of the Vth axis in the memory controller (the left side of the Vth axis). For example, when the memory controller determines that the loss level of a particular cell or multiple cells is higher than a threshold, the memory controller can transition from the second programming state form B to C, such as... Figure 5C As shown in pseudo-TLC scheme 500-2, the voltage distribution can be widened without causing excessive errors (too high for the error control module 125 to be corrected by various ECC processes) because there is more space between states A and C. However, eventually, the distribution of states A and C may lead to excessive errors, so the memory controller may switch states again, as... Figure 5D The pseudo-TLC scheme is shown in 500-3.

[0061] In some specific implementations, refer to Figures 5B to 5DThe described programming state transitions can be triggered based on wear levels. The wear detection module of the memory controller can detect or estimate wear on one or more memory cells by tracking the number of program-erase cycles (PECs) for each cell. After various PEC thresholds, the programming state can transition to prevent excessive wear-related errors. Alternatively or additionally, the wear detection module can detect or estimate wear by tracking the lifetime of the device. After various time or usage thresholds (e.g., after 1 year of use, 2 years of use, etc.), the programming state can transition to prevent excessive wear-related errors. Alternatively or additionally, the wear detection module can cause diagnostic reads to be performed on one or more memory cells for the purpose of determining the amount of errors or the width and / or location of various state distributions. Based on the number, width, and / or location of detected errors, the programming state can transition to prevent excessive wear-related errors.

[0062] In some implementations, the programming state distribution (also known as the window) can be configured to be relatively narrow. This narrowing of the voltage distribution for each programming state can be achieved by using smaller step sizes between consecutive programming pulses. Smaller step sizes result in longer programming times. However, for EDR implementations, a trade-off can be made for program performance to capture sensor data and other vehicle data provided by ECU 110 for storage, as described above, provided minimum throughput requirements are met. In addition to, or as an alternative to, programming state modification, the storage controller can adjust one or more programming fine-tuning parameters to optimize durability. Programming fine-tuning parameters include window size, starting voltage, step size, verification level, read level on the word line, etc.

[0063] In some specific implementations, the distance between programmed states can be reduced compared to conventional TLC schemes. For example, the distance between programmed states can be reduced from 800mV to 400mV, or even less than 400mV. Figure 6A and Figure 6B A pseudo-TLC scheme 600 is shown for encoding memory cells using only a subset of available programmable states, in which the distance between programmable states is reduced. For example, in pseudo-TLC scheme 600-1 ( Figure 6A States A and C are closer to the corresponding states in scheme 500-2. Figure 5C Similarly, in pseudo-TLC scheme 600-2 ( Figure 6B States B and D are closer to the corresponding states in scheme 500-3. Figure 5D ).

[0064] Figures 7A to 7C This illustrates the programming state transition caused by the broadening of the voltage threshold distribution corresponding to the programming state. At the first time (t1), using... Figure 7AThe pseudo-TLC scheme 500-1 shown has programming states A (011) and B (001), as referenced above. Figure 5B As stated above. After a certain number of programming operations have occurred, the voltage distribution widens in the subsequent time (t2), as... Figure 7B As shown. The voltage distribution widens due to losses, and the overlap between distributions can increasingly lead to errors as it grows. When the overlap reaches a threshold associated with excessive errors, the memory controller transitions the second programming state (B) to the right, as shown. Figure 7C The pseudo-TLC scheme 500-2 shown (corresponding to Figure 5C As shown in the diagram. The second programming state of the transition (now C) no longer overlaps with programming state A, thereby minimizing loss-related errors. Even though programming state C requires more voltage for the floating gate to be programmed, that voltage can still be less than... Figure 4A The distribution A in the SLC scheme 410 shown improves durability by allowing for lower programming voltages.

[0065] The pseudo-TLC scheme described above implements the SLC scheme (using only two states per cell) using a TLC programming distribution (seven possible programming states). Therefore, when data X is written to a specific cell using states A (011) and C (000), the memory controller will cause the following to be programmed into the lower, middle, and upper pages of that cell, respectively: 0 XX. This corresponds to the 011 and 000 values ​​of states A and C (where the data to be written is 1 or 0, representing X).

[0066] In addition to, or as an alternative to, the aforementioned pseudo-MLC / TLC / QLC two-layer programming features, memory cell endurance can be improved by increasing the number of parity bits used with the codeword during programming operations. Since the error control module 125 can more effectively use the ECC process to recover from errors, the increased parity means that more errors can be absorbed. In some implementations, the number of parity bits is increased such that the code rate (the ratio of the number of bits in the codeword of data to the total number of bits in the codeword including the ECC parity bits) is 0.6 or less. The additional parity bits result in slower programming speeds, but in EDR applications, programming performance may be traded off for the aforementioned reasons to optimize endurance. Because the error recovery capability is increased by adding parity bits, the state (e.g., Figure 5C and Figure 6AThe spacing between states A and C in the program can be more relaxed because it allows for a greater overlap area between the two states. For the same reason (increased resilience allows for more overlap between states), the amount of time between state transitions can be increased. By allowing shorter distances between programmed states and longer times between transitions, programming operations can use lower voltages over a longer period of time, thereby further improving durability.

[0067] Additional parity bits can also be implemented by increasing the memory footprint. The size of the memory can be increased by increasing the ratio of physical capacity (e.g., all physically existing memory cells) to derived capacity (e.g., addressable memory cells). Physically existing but not addressable memory cells can be used for error correction operations (e.g., parity bits). By increasing the ratio of physical capacity to derived capacity to 50:1 (0.02 of derived capacity to physical capacity), the number of physical memory cells available for error correction operations increases, thereby increasing the error recovery capability as described above. For example, instead of choosing between a 512GB storage device (optimizing durability at the cost of cost) and a 16GB storage device (optimizing cost at the cost of durability), a 32GB or 64GB storage device can be selected, thus maintaining a relatively low memory footprint (and therefore, low cost) compared to the 512GB storage device, but at the same time, doubling or quadrupling the amount of available storage required to store 4GB of user data (referred to as "overprovision"). The greater the overprovision, the more storage space can be used for parity bits. In some implementations, the ratio of physical capacity to exported capacity may be as low as 2:1 (0.50 of exported capacity to physical capacity).

[0068] In addition to or as an alternative to the aforementioned pseudo-MLC / TLC / QLC two-layer programming features, increasing the codeword length (e.g., convolutional low-density parity-check (CLDPC) codewords) also improves durability. Long codewords can be implemented at different code rates. For example, for a codeword length of 4.5KB, the codeword length can be set to 4KB with 512 bytes of parity, resulting in a code rate of 0.9. Alternatively, the codeword length can be set to 2.25KB with 2.25KB of parity, resulting in a code rate of 0.5. Increasing the codeword length means increasing read time, as the entire codeword needs to be decoded to read the data within it. However, due to the reasons described above, read performance in a practical EDR implementation may be sacrificed, so the better correction capability (and therefore, higher durability) associated with longer codewords may outweigh the reduced read performance. For example, after an accident, data can be read from a black box EDR at a reduced speed in a laboratory setting. The additional time that might be spent reading the data (hours instead of minutes) is likely not a major factor in the design of an EDR because the data only needs to be read once and the dataset is finite (e.g., 30 seconds before and after an incident). The use of CLDPC is described in U.S. Patent Application No. 15 / 817,442, which is incorporated herein by reference in its entirety.

[0069] By implementing the aforementioned features regarding the increased physical capacity to derived capacity ratio, additional parity bits, and / or increased codeword length, the amount of increased physical bad blocks can be allowed to be up to and exceed 5% of all physical blocks (or all addressable blocks), and up to 95% of all physical blocks (or all addressable blocks).

[0070] In addition to or as an alternative to the aforementioned pseudo-MLC / TLC / QLC two-layer programming features, other durability enhancement techniques can be used to improve durability.

[0071] For example, storage controllers can use adjustable ECC (TECC) technology to enhance endurance. Since not all data blocks have the same error rate, the storage controller can use more parity to program cells with more errors and less parity to program cells with fewer errors, saving storage capacity. The additional storage capacity available for programming improves endurance because programming operations can be distributed across the available memory cells. For example, instead of using 50% of the parity bits for each memory cell, the storage controller can use 50% parity for only 1% of the cells, 40% parity for 20% of the cells, and so on.

[0072] For example, storage controllers can use durability coding and / or shaping, which adds more parity bits to reduce the number of programmed cells, thus reducing wear and tear and thereby improving durability.

[0073] For example, the storage controller (e.g., encoder 126) can use one or more compression processes to compress the data to be programmed. This results in less data being written, thus improving durability.

[0074] For example, storage controllers can use Partially Good Blocks (PGB) technology to improve durability. For instance, if a block is not completely unusable (e.g., a subset of word lines is causing an error), the storage controller can continue using portions of the block that are still usable (e.g., word lines that are not causing an error) instead of stopping the entire block. This results in fewer blocks being retired, thus improving durability.

[0075] For example, the storage controller can reduce noise by using extended read times and / or multiple read operations. The storage controller can read soft information, which allows the ECC process to correct more errors, thereby improving durability.

[0076] For example, storage controllers can use Direct Lookahead (DLA) technology, which involves using the next word line to reduce cross-coupling. This increases read time, but for the reasons mentioned above, the improved endurance outweighs the reduced read performance.

[0077] For example, storage controllers can use combined ECC and RAID (JLR) technology, which improves upon high-end ECC events. Assuming no critical failures but a high number of errors, JLR can improve ECC by using additional parity checks for critical failures. Since the storage controller can use parity checks from RAID to bring states closer together, this reduces overhead and thus improves durability.

[0078] Figure 8 A flowchart depicts a method 800 for programming memory cells using a pseudo-MLC / TLC / QLC two-layer programming scheme. Method 800 is typically executed by a memory controller 124, a memory device 120, or a management module 121 of the memory system, but alternatively may be executed by a computer system (e.g., host 110) in which the memory device is embedded. In some implementations, various operations in method 800 may be reordered or omitted.

[0079] The storage controller receives (802) data to be written (e.g., vehicle sensor data as described above) and determines (804) one or more memory cells from the plurality of memory cells as the destination for the data to be written, wherein the one or more memory cells are configured to be programmed using at least three programming states (e.g., MLC, TLC, or QLC programming states as described above). The storage controller determines (806) the wear level of the one or more memory cells (e.g., using any of the wear level detection or estimation techniques described above). Based on the wear level of the one or more memory cells, the storage controller selects (808) a first programming state and a second programming state (e.g., TLC states A and B) from the at least three programming states for each of the one or more memory cells. Figure 7A In some specific implementations, the memory controller transitions (810) the previously selected programming state based on a determined wear level (and / or other error metric) associated with the memory cell and / or a particular programming state (e.g., from state B to state C). Figure 7C When selecting a programming state, the storage controller programs the target cell using the selected programming state (812).

[0080] The aforementioned pseudo-MLC / TLC / QLC two-layer programming scheme, combined with a high number of parity bits and a low coding rate (e.g., 50%), provides high endurance of 500,000 cycles and more for 32GB or 64GB NAND storage devices. These concepts can be used in any application with similar low read / write rates and high endurance requirements, such as IoT devices.

[0081] Furthermore, it should be noted that the specific implementation described above does not require conventional wear leveling protection because writes are always on, continuously overwriting the memory address space of the storage device; therefore, the flash management firmware can be much simpler. This significantly reduces write amplification (e.g., because compaction for data lifetime management operations such as garbage collection is not required). It should also be noted that using different MLC / TLC / QLC states instead of the erase (E) state is also beneficial in avoiding over-erasing cells. Over-erased cells become outliers that can lead to complete device failure; using higher programming states as proposed herein prevents this over-erasing failure.

[0082] It should be understood that although the terms "first," "second," etc., may be used herein to describe various components, these components should not be limited by these terms. Apart from the phrases "first read condition" and "second read condition," the terms "first," "second," etc., are used only to distinguish one component from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without changing the meaning of the description, provided that all occurrences of "first contact" are consistently renamed and all occurrences of "second contact" are consistently renamed. First contact and second contact are both contacts, but they are not the same contact.

[0083] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the claims. As used in the description of the embodiments and appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the term “comprising” specifies the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0084] As used herein, the term "if" can be interpreted as meaning "when the stated prerequisite is true" or "when the stated prerequisite is true" or "in response to determining that the stated prerequisite is true" or "based on determining that the stated prerequisite is true" or "in response to detecting that the stated prerequisite is true," depending on the context. Similarly, the phrases "if it is determined that [the stated prerequisite is true]" or "if [the stated prerequisite is true]" or "when [the stated prerequisite is true]" can be interpreted as meaning "when the stated prerequisite is determined to be true" or "in response to determining that the stated prerequisite is true" or "based on determining that the stated prerequisite is true" or "in response to detecting that the stated prerequisite is true," depending on the context.

[0085] For purposes of explanation, the foregoing description has been illustrated with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the invention to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. These embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention and its various embodiments with various modifications suitable for the contemplated particular purpose.

Claims

1. A data storage system comprising: a non-volatile memory (NVM) comprising a plurality of memory cells, wherein the NVM has a defined ratio of derived capacity to physical capacity greater than 0.02 and less than 0.50; and a controller coupled with the NVM, wherein the controller receives data from a host and writes the data into the NVM, wherein the controller is configured to: calculate an error correction code (ECC) for the received data and save the ECC with the received data, wherein an ECC code rate is less than 0.60; determine a first memory cell of the plurality of memory cells as a destination for the data to be written, wherein the first memory cell is configured to be programmed using at least three program states; determine a wear level of the first memory cell; based on the wear level of the first memory cell, select, for the first memory cell, a subset of the at least three program states to render at least one program state not included in the subset as unavailable for programming, the subset comprising a first program state and a second program state; and program the first memory cell using one of the first program state and the second program state; and wherein determining which of the at least three program states are available for programming comprises: determining a distribution width or error rate of the at least three program states; and classifying a particular program state of the at least three program states as available for programming based on the distribution width or the error rate of the particular program state; and wherein selecting the first program state and the second program state comprises: determining which of the at least three program states are available for programming; and selecting as the first program state and the second program state two available states associated with the lowest program voltage.

2. The data storage system of claim 1, wherein the NVM comprises a plurality of blocks, and an allowed number of growing physical bad blocks is greater than 5% and less than 95% of the plurality of blocks.

3. The data storage system of claim 1, wherein the system is used as a black box recording device in a vehicle, and the data from the host comprises event data generated by a plurality of vehicle sensors.

4. The data storage system of claim 1, wherein selecting the first program state and the second program state comprises: determining the wear level of the first memory cell relative to one or more program states based on program state distribution widths of the one or more program states; based on the determined wear level of the first memory cell relative to the one or more program states, transitioning one of a previously selected first program state or a previously selected second program state to a new program state.

5. The data storage system of claim 4, wherein transitioning one of the previously selected first program state or the previously selected second program state to the new program state comprises selecting a program state corresponding to a program voltage higher than the program voltage of the one of the previously selected first program state or the previously selected second program state as the new program state.

6. The data storage system of claim 1, wherein determining a level of wear of the first memory cell comprises: counting program-erase cycles (PECs) of the first memory cell; and determining the level of wear based on whether the number of PECs of the first memory cell is above a threshold.

7. The data storage system of claim 1, wherein determining a level of wear of the first memory cell comprises: performing a diagnostic read operation on the first memory cell; and determining an amount of errors or a program state distribution width based on the diagnostic read operation; and determining the level of wear based on whether the amount of errors or the program state distribution width is above a respective threshold.

8. A method of storing data in a black box recorder system for a vehicle, the black box recorder system comprising a data storage system according to claim 1, the data storage system comprising a memory comprising a plurality of memory cells and a controller in communication with the memory, the method comprising: determining a first memory cell of the plurality of memory cells as a destination for the data to be written to, wherein the first memory cell is configured to be programmed using at least three program states; determining a level of wear of the first memory cell; based on the level of wear of the first memory cell, for the first memory cell, selecting a subset of the at least three program states to render at least one program state not included in the subset as unavailable for programming, the subset comprising a first program state and a second program state; and programming the first memory cell using one of the first program state and the second program state; and wherein determining which of the at least three program states are available for programming comprises: determining a distribution width or an error rate of the at least three program states; and classifying a particular program state of the at least three program states as available for programming based on the distribution width or the error rate of the particular program state; and wherein selecting the first program state and the second program state comprises: determining which of the at least three program states are available for programming; and selecting the two available states associated with the lowest program voltage as the first program state and the second program state.

9. The method of claim 8, wherein selecting the first program state and the second program state comprises: determining the level of wear of the first memory cell relative to one or more program states based on program state distribution widths of the one or more program states; based on the determined level of wear of the first memory cell relative to the one or more program states, transitioning one of the previously selected first program state or the previously selected second program state to a new program state.

10. A data storage system comprising a memory, the memory comprising a plurality of memory cells; and a controller in communication with the memory, the controller configured to: receive data to be written; determine a first memory cell of the plurality of memory cells as a destination for the data to be written, wherein the first memory cell is configured to be programmed using at least three program states; determine a level of wear of the first memory cell; based on the level of wear of the first memory cell, select, for the first memory cell, a subset of the at least three program states to render at least one program state not included in the subset as unavailable for programming, the subset comprising a first program state and a second program state; and program the first memory cell using one of the first program state and the second program state; and wherein determining which of the at least three program states are available for programming comprises: determining a distribution width or error rate of the at least three program states; and based on the distribution width or the error rate of a particular program state of the at least three program states, classifying the particular program state as available for programming; and wherein selecting the first program state and the second program state comprises: determining which of the at least three program states are available for programming; and selecting as the first program state and the second program state, the two available states associated with the lowest program voltage.

11. The data storage system of claim 10, wherein selecting the first program state and the second program state comprises: determining the level of wear of the first memory cell relative to one or more program states based on a program state distribution width of the one or more program states; based on the determined level of wear of the first memory cell relative to the one or more program states, transitioning one of the previously selected first program state or the previously selected second program state to a new program state.

12. The data storage system of claim 11, wherein transitioning one of the previously selected first program state or the previously selected second program state to the new program state comprises selecting as the new program state, a program state corresponding to a higher program voltage than a program voltage of the one of the previously selected first program state or the previously selected second program state.

13. A black box recorder system for a vehicle, the black box recorder system comprising: a data storage system comprising a plurality of memory cells; and a controller in communication with the plurality of memory cells, the controller comprising: means for determining a first memory cell of the plurality of memory cells as a destination for the data to be written, wherein the first memory cell is configured to be programmed using at least three program states; means for determining a wear level of the first memory cell; means for selecting, for the first memory cell, a subset of the at least three program states to render at least one program state not included in the subset as unavailable for programming based on the wear level of the first memory cell, the subset including a first program state and a second program state; and means for programming the first memory cell using one of the first program state and the second program state; and wherein determining which of the at least three program states are available for programming comprises: determining a distribution width or an error rate of the at least three program states; and classifying a particular program state of the at least three program states as available for programming based on the distribution width or the error rate of the particular program state; and wherein selecting the first program state and the second program state comprises: determining which of the at least three program states are available for programming; and selecting as the first program state and the second program state two available states associated with the lowest program voltage.

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