Generating programming parameters for non-volatile memory devices based on physical device parameters

Abstract

The present disclosure generally relates to generating programming parameters for non-volatile memory devices based on physical device parameters. Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command, and setting a row-based programming parameter for the target row using a target physical device parameter for the target row and an optimized programming parameter corresponding to the physical device parameter.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to systems and methods for generating programming parameters for programming data on a non-volatile memory device. BACKGROUND

[0002] A program digital signal processing (DSP) is a process by which a controller (e.g., firmware implemented thereon) controls NAND programming parameters for programming data on a NAND flash device. In one example, a conventional program DSP can be used to obtain high reliability (at the expense of write performance), e.g., by modifying NAND parameters to reduce bit error rate (BER) after programming, by using more accurate programming (e.g., by using smaller voltage steps, such as (but not limited to) incremental step pulse programming (ISPP)), etc. Such reliability improvement is obtained at the expense of programming speed and write performance. Program DSP is typically implemented on the controller due to high cycle count for. SUMMARY

[0003] In some arrangements, a method for programming data on a storage device having non-volatile memory includes determining a target row corresponding to a program command; and setting row-based programming parameters for the target row using target physical device parameters for the target row and optimized programming parameters corresponding to the physical device parameters.

[0004] In some arrangements, a training method for determining row-based or WL-based optimized programming parameters includes programming using programming parameters for a plurality of blocks of a plurality of NAND flash devices to determine at least one result parameter for each row of a plurality of block rows of the plurality of NAND flash devices; and modifying the programming parameters for one or more rows of the plurality of rows based on the at least one result parameter. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A block diagram of a system including a non-volatile storage device coupled to a host in accordance with some embodiments is shown.

[0006] Figure 2 is a flow diagram illustrating an example training method in accordance with some arrangements.

[0007] Figure 3 is a flow diagram illustrating an example training method in accordance with some arrangements.

[0008] Figure 4 is a flow diagram illustrating an example training method in accordance with some arrangements.

[0009] Figure 5 is a flow diagram illustrating an example training method in accordance with some arrangements.

[0010] Figure 6 is a flowchart illustrating an example training method according to some arrangements.

[0011] Figure 7 is a process flowchart illustrating an example method for programming data using trained programming parameters according to some arrangements. DETAILED DESCRIPTION

[0012] The arrangements disclosed herein relate to systems, methods, and non-transitory computer readable media for providing improved endurance, average write performance, reliability (under all stress conditions), and device lifetime for a non-volatile memory device (e.g., a NAND flash device) by allowing a controller of the non-volatile memory device (e.g., a NAND flash device) to control the programming flow of the non-volatile memory storage device (e.g., a NAND flash device). In some arrangements, an adaptation of specific trim parameters that vary depending on a target memory row or word line (WL) is applied, where this adaptation is based on training a plurality of non-volatile memory devices. In some arrangements, the program DSP algorithm is implemented on controller (e.g., NAND memory controller) hardware and / or firmware. In some arrangements, the program DSP algorithm is implemented on host software. The program DSP algorithm itself is suitable for low-complexity processing.

[0013] To assist in the explanation of the present embodiments, Figure 1 A block diagram of a system including a non-volatile storage device 100 coupled to a host 101 according to some embodiments is shown. In some examples, the host 101 can be a user device operated by a user. The host 101 can include an operating system (OS) configured to provide a file system and applications that use the file system. The file system communicates with the non-volatile storage device 100 (e.g., a controller 110 of the non-volatile storage device 100) over a suitable wired or wireless communication link or network to manage data storage in the non-volatile storage device 100. In this regard, the file system of the host 101 sends and receives data to and from the non-volatile storage device 100 using a suitable interface to the communication link or network.

[0014] In some examples, the non-volatile storage device 100 is located in a data center (not shown for brevity). The data center can include one or more platforms, where each supports one or more storage devices, such as (but not limited to) the non-volatile storage device 100. In some implementations, the storage devices within a platform are connected to a top-of-rack (TOR) switch and can communicate with each other via the TOR switch or another suitable intra-platform communication mechanism. In some implementations, at least one router can facilitate communication between non-volatile storage devices in different platforms, racks, or cabinets via a suitable network fabric. Examples of the non-volatile storage device 100 include (but are not limited to) solid state drives (SSDs), non-volatile dual in-line memory modules (NVDIMMs), universal flash storage (UFS), secure digital (SD) devices, etc. In other examples, the non-volatile storage device 100 can be operably coupled to the host 101 in environments other than a data center.

[0015] The non-volatile storage device 100 includes at least a controller 110 and a memory array 120. Other components of the non-volatile storage device 100 are not shown for brevity. The memory array 120 includes NAND flash devices 130a-130n. Each of the NAND flash devices 130a-130n includes one or more individual NAND flash dies, which are non-volatile memories (NVMs) capable of saving data without power. Thus, the NAND flash devices 130a-130n refer to multiple NAND flash devices or dies within the flash device 100. Each of the NAND flash devices 130a-130n includes one or more dies, where each has one or more planes. Each plane has multiple blocks, and each block has multiple pages.

[0016] In some arrangements, each of the NAND flash devices 130a-130n is a three-dimensional NAND flash device that includes one or more blocks each having multiple tiers. Each tier includes multiple physical rows. Applicant recognizes that there are correlations and similarities in behavior between rows on the same tier. The behavior between rows of different tiers of a three-dimensional NAND flash device varies more significantly than the behavior between rows of the same tier of a three-dimensional NAND flash device.

[0017] As used herein, in some examples, a WL is a set of physical rows that belong to the same physical tier of a three-dimensional NAND flash device having multiple physical tiers. The rows of a WL can be adjacent to each other. In some examples, a WL is used to refer to a set of rows of a NAND flash device where the rows can not be adjacent to each other and / or can not be in the same physical tier. Optimizing programming parameters per WL means that all rows belonging to a given WL will use the same parameters.

[0018] Although the NAND flash devices 130a-130n are shown as examples of the memory array 120, other examples of non-volatile memory technologies used to implement the memory array 120 include, but are not limited to, (battery-backed) dynamic random access memory (DRAM), magnetic random access memory (MRAM), phase change memory (PCM), ferroelectric RAM (FeRAM), etc. The ECC structures described herein can likewise be implemented on memory systems using such memory technologies and other suitable memory technologies.

[0019] Examples of the controller 110 include, but are not limited to, an SSD controller (e.g., a client SSD controller, a data center SSD controller, an enterprise SSD controller, etc.), a UFS controller, or an SD controller, etc.

[0020] The controller 110 can combine raw data storage in the plurality of NAND flash devices 130a-130n such that the NAND flash devices 130a-130n are logically used as a single storage unit. The controller 110 can include a processor, a microcontroller, a buffer, an error correction system, a data encryption system, a flash translation layer (FTL), and a flash interface module. Such functionality can be implemented in hardware, software, and firmware, or any combination thereof. In some arrangements, the software / firmware of the controller 110 can be stored in the memory array 120 or any other suitable computer-readable storage medium.

[0021] The controller 110 includes suitable processing and memory capabilities for performing the functions described herein, as well as other functions. As described, the controller 110 manages various features of the NAND flash devices 130a-130n, including, but not limited to, I / O handling, read, write / program, erase, monitoring, logging, error handling, garbage collection, wear leveling, logical to physical address mapping, data protection (encryption / decryption, cyclic redundancy check (CRC)), error correction coding (ECC), data scrambling, etc. Thus, the controller 110 provides visibility into the NAND flash devices 130a-130n.

[0022] The controller 110 further includes a controller memory 112. The controller memory 112 is a memory device that is local to or operably coupled to the controller 110. For example, the controller memory 112 can be on-chip non-volatile memory or volatile memory that is on the chip of the controller 110. In some implementations, the controller memory 112 can be implemented using a memory device that is external to the controller 110. For example, the controller memory 112 can be non-volatile memory or volatile memory that is on a chip other than the chip of the controller 110. In some implementations, the controller memory 112 can be implemented using memory devices that are internal and external to the controller 110, such as on and off the chip of the controller 110.

[0023] In some arrangements, after the NAND flash devices 130a-130n are manufactured and before the NAND flash devices 130a-130n are installed within the non-volatile memory device 100 (e.g., before the NAND flash devices 130a-130n are connected to other components of the non-volatile memory device 100, such as the controller 110), the NAND flash devices 130a-130n are operably coupled to the test circuit 102, which is configured to perform training on the program DSP parameters, as disclosed herein. Performing the training using a third-party test circuit 102 before the non-volatile memory device 100 (with the memory array 120) is first powered on is referred to as offline training. The training methods described herein are performed with respect to a small number of blocks of the NAND flash devices 130a-130n, such that running P / E cycles on these blocks does not significantly shorten the lifetime of all of the blocks of the NAND flash devices 130a-130n. In other examples, this training is performed with respect to sacrificial NAND flash devices that represent the NAND flash devices 130a-130n, such as NAND flash devices that are cut from the same wafer as the NAND flash devices 130a-130n. In such examples, the tables determined using the sacrificial NAND flash devices are equally applicable to the NAND flash devices 130a-130n due to similar behavior. It is assumed that P / E cycles are run on devices other than the NAND flash devices 130a-130n included in the non-volatile memory device 100. Thus, performing offline training allows the memory array 120 to be optimized before the non-volatile memory device 100 is powered on for use, thus saving power-up time and lifetime of the NAND flash devices 130a-130n.

[0024] The test circuit 102 can include suitable processing capability (e.g., processor, memory, etc.) for performing the functions described herein. Additionally, the test circuit 102 includes a test data memory 104 configured to store data generated during the training methods described herein as well as the output of the training methods (e.g., a table of programming parameters mapped to physical device parameters such as, but not limited to, row address, block address, cycle count, etc.). The test circuit 102 can use any suitable mechanism to transfer the table to the controller memory 112.

[0025] In other arrangements, the training methods described herein can be performed by the test circuit 102 or the controller 110 online, during or after the first power-up of the non-volatile storage device 100. In examples where the training methods are performed by the controller 110, the data generated during the training methods and the table of programming parameters mapped to physical device parameters can be stored directly in the controller memory 112.

[0026] In some examples, in a triple BPC non-volatile storage device (e.g., a flash device, a NAND device, etc.), the threshold voltage distribution includes a superposition of 8 (e.g., 0 to 7) viable voltage threshold distributions of a triple BPC flash device or NAND device, also known as a triple level cell (TLC). The viable voltage threshold (VT) distribution of a cell has 8 lobes that correspond to 8 different bit combinations of 3 bits represented by the state of charge of the cell. A most significant bit (MSB) page read uses a first reference voltage (or read threshold) to separate the lobes into lobes with MSB 0 and lobes with MSB 1. A center significant bit (CSB) page read uses a second reference voltage. A least significant bit (LSB) page read uses a third reference voltage.

[0027] In some examples, programming of four BPC in a quad level cell (QLC) uses 16 charge levels to store information per cell. QLC uses more accurate programming circuitry than the programming circuitry of TLC. In this regard, QLC devices with more accurate programming circuitry have longer programming times than the programming times of TLC devices or single level cell (SLC) devices. The programming time is denoted by tProg and represents the time that a NAND device is busy due to its internal programming circuitry being activated to program new data. The average tProg measured over multiple blocks and rows determines the write performance of a NAND device. The arrangements disclosed herein provide a program DSP solution to improve the programming performance of QLC (e.g., by improving the QLC tProg) without degrading the reliability that can be achieved.

[0028] The program DSP is the process by which the controller 110 (e.g., firmware implemented thereon) controls the NAND programming parameters. In one example, a traditional program DSP can be used to obtain high reliability (at the expense of write performance), e.g., by modifying the NAND parameters to reduce the bit error rate (BER) after programming, by using more accurate programming (e.g., by using smaller voltage steps, such as (but not limited to) incremental step pulse programming (ISPP)), etc. Such reliability improvements come at the expense of programming speed and write performance. Because of the high cycle count, the program DSP is typically implemented on the controller 110.

[0029] In another example, a traditional program DSP can be used to obtain high write performance (fast programming) by individually tuning the NAND parameters of each of the NAND flash devices 130a-130n. The controller 110 can set the NAND parameters of each of the NAND flash devices 130a-130n during programming. This program DSP includes a training process at the beginning of life (before the device is first used) and / or on a cycle-by-cycle basis for each of the NAND flash devices 130a-130n. This training process is an overhead during production and in some cases affects the initial power-up performance of a new NAND flash device.

[0030] In one traditional program DSP, the controller 110 estimates new parameters for the NAND flash devices every cycle range. Each cycle range can include, for example, 200 program / erase (P / E) cycles. Within each cycle range, a test block is used to check different candidates for the programming parameters. The parameters are estimated using a program time improvement estimator, and evaluated by measuring the BER after programming. The BER is measured by performing a read of the previously programmed data, which means that both a program and read process are needed for evaluating the parameters. Assuming that such processes are performed for each NAND flash device, the controller 110 is best suited to perform these processes. Additionally, the criteria for accepting a new parameter is based on the measured tProg and the maximum page BER value. Such criteria limit the robustness of the program DSP.

[0031] The arrangements described herein involve performing training on a sufficiently large group of NAND flash devices 130a-130n to determine a most suitable common set of programming parameters, which can vary as a function of the physical device parameters of the NAND flash devices 130a-130n. Examples of physical device parameters include, but are not limited to, number of rows, number of blocks, loop counts, etc. In some implementations, the output of the training includes a table of programming parameters mapped to the physical device parameters of all of the NAND flash devices 130a-130n of the memory array 120. Using the table, the controller 110 can determine the values of the program parameters using the physical device parameters. In some examples, the table is stored in the controller memory 112. Thus, the controller 110 can use the table to set the programming parameters for all of the NAND flash devices 130a-130n managed by the controller 110, and need not tune any of the programming parameters of each of the NAND flash devices 130a-130n other than determining the programming parameters that vary as a function of the common physical device parameters.

[0032] In some implementations, the training of the program DSP can be performed on a sufficiently number of NAND flash devices 130a-130n to determine a most suitable common set of programming parameters, which varies as a function of the physical device parameters of the NAND flash devices 130a-130n. This allows the controller 110 to set the sufficient programming parameters and without the overhead of tuning each of the NAND flash devices 130a-130n attached to the controller 110.

[0033] Figure 2 is a flowchart illustrating an example training method 200 according to some arrangements. Referring to Figures 1 to 2 , the training method 200 allows the test circuit 102 to generate a table of parameters. The training method 200 can be an offline training method or an online training method. While the test circuit 102 is described as performing the training method 200 (online or offline), the controller 110 can also perform the training method 200 (online). The table of parameters maps the correspondence between programming parameters and physical device parameters, such as (but not limited to) rows (defined by row address / ID / number), WLs (defined by WL address / ID / number or a series of row address / ID / numbers), etc. Generally, the method 200 optimizes the write performance of N NAND flash devices to a target average program time (tProg DSP ) for a given set of physical device parameters. In some examples where higher write performance is desired, tProg DSPshorter than the default tProg. The N NAND flash devices can be all of the NAND flash devices 130a-130n, some but not all of the NAND flash devices 130a-130n, or a sacrificial NAND flash device having behavior similar to the NAND flash devices 130a-130n. In examples where the N NAND flash devices correspond to some but not all of the NAND flash devices 130a-130n or a sacrificial NAND flash device, the N NAND flash devices constitute a large enough group of NAND flash devices for which a most suitable common set of programming parameters can be determined, where such programming parameters can be applied to all of the NAND flash devices 130a-130n.

[0034] At 210, the test circuit 102 preconditions M blocks of each of the N NAND flash devices to different cycle counts. In some examples, M is less than the total number of blocks of each NAND flash device. Each of the M blocks is identified by a block address. In some examples, the M blocks (also referred to as M test blocks) can be arbitrarily selected within a set of all blocks of each NAND flash device. In other examples, the M blocks can be selected according to other suitable methods, such as the method described in U.S. Patent Application No. 62 / 729, 1 10, filed September 10, 2018, entitled "METHOD FOR DETERMINING PROGRAMMING PARAMETERS FOR NAND FLASH DEVICES," which is incorporated by reference in its entirety. Thus, each of the N NAND flash devices can have a different M blocks (a different M block address list including addresses of the M blocks) for write performance optimization. All of the M blocks are within a common block set. Figure 4

[0035] The different cycle counts can be determined based on a maximum number of P / E cycles (maximum cycle count) that a NAND flash device can sustain before the NAND flash device is unable to be written or programmed with any new data. Writing data on a block (by writing on pages thereon) and erasing data on a block constitute one P / E cycle. The maximum cycle count can depend on the specification (designating device endurance) and can vary for different applications of the non-volatile storage device 100. In some implementations, the number of different cycle counts is also M.

[0036] In one example application where the non-volatile storage device 100 is an SSD, the maximum cycle count supported by the NAND flash devices is 10,000 P / E cycles. For example, in this application, a sample set of 50 blocks (M = 50) can be preconditioned to different cycle counts 200, 400, 600,..., 10,000 P / E cycles for each NAND flash device to obtain a representative set of program disturb stress conditions. Program disturb stress conditions are achieved via different cycle counts, where high program disturb corresponds to a large number of P / E cycles. The cycle counts are applied in an "up-ladder" fashion to determine the maximum cycle count point for a particular device in a particular application.

[0037] ​In one example application in which the non-volatile storage devices 100 are UFS, the maximum cycle count supported by the NAND flash devices is 3,000 P / E cycles. For example, in this application, 50 blocks (M = 50) can be pre-conditioned for each NAND flash device to different cycle counts 60, 120, 180,..., 3,000 P / E cycles to obtain a representative set of program disturb stress conditions.

[0038] Pre-conditioning M blocks of each of N NAND flash devices refers to cycling each of the M blocks to one of the different cycle counts.

[0039] At 220, the test circuit 102 determines result parameters for the M blocks of the N NAND flash devices based on the default programming parameters, where the result parameters include WL-based result parameters. For example, the controller 110 programs all rows and WLs of all M blocks of all N NAND flash devices with random reference data using the default programming parameters. Examples of the default programming parameters include, but are not limited to, a default initial voltage level V start , a default pulse voltage step V step , a default bias voltage V bias , a default maximum number of pulses (NPP), and other default parameters used in ISPP, etc. The random reference data is then read using default voltage thresholds.

[0040] Generally, a program operation includes a process of multiple small charge injection steps. Charge can be injected to a memory cell by applying a voltage pulse V pulse starting at V start to the programmed row and setting the gate voltage of all other transistors in the string to V bias . After applying V pulse , the programmed cell is read and compared to a desired program voltage. In response to determining that the desired program voltage is reached, the programming ends. On the other hand, in response to determining that the desired program voltage is not reached, additional pulses are provided until the desired program voltage is reached or until NPP is reached. In cases where there are still cells that fail the verify test (e.g., the cells are not programmed to the desired program voltage) after using NPP, a program error (or failure) can be declared. ISPP includes increasing the level of V pulse by V step for each increment.

[0041] Based on the programming and reading, result parameters are measured and stored. For example, the test circuit 102 determines and stores the average tProg across all M blocks of all N NAND flash devices and the average page BER across all M blocks of all N NAND flash devices in the test data storage 104.

[0042] Furthermore, the test circuit 102 determines a standard deviation (STD) of the page BER for each WL with respect to the average page BER across all M blocks and N NAND flash devices and stores it in the controller memory 112, where this STD is referred to as STD(WL). In other words, STD(WL) refers to the standard deviation of the page BER as a function of the WL, which is measured with respect to the average page BER across all M blocks and N NAND flash devices. For example, the test circuit 102 can measure the page BER for each WL and compute the STD of the page BER as a function of the individual row or WL (multiple rows) and with respect to the average (mean) page BER across all M blocks of all N NAND flash devices to determine STD(WL).

[0043] Furthermore, the test circuit 102 determines a maximum BER (referred to as BER MAX (WL)) for each WL of all M blocks of all N NAND flash devices and a mean BER (referred to as BER AVG (WL)) for each WL of all M blocks of all N NAND flash devices and stores them in the controller memory 112.

[0044] Thus, the result parameters include, but are not limited to, the average tProg, the average page BER, STD(WL), BER MAX (WL), and BER AVG (WL). The WL-based result parameters include STD(WL), BER MAX (WL), and BER AVG (WL) for each WL.

[0045] In some arrangements, the test circuit 102 determines higher order moments of the page BER distribution as a function of the physical device parameters (e.g., row, WL, etc.) of the NAND flash devices and stores them in the controller memory 112. For example, the n-th moment μ n of a random variable x is defined as:

[0046] μ n (x) = E[(x - E[x]) n ] (1);

[0047] where E[x] is the expected value of the random variable x. The STD(WL) of a random variable with moment 2 can be determined using:

[0048]

[0049] WL refers to the BER distribution as a function of the WL. Higher moments (e.g., μ3(WL) in equation (3) below and μ4(WL) in equation (4) below) can also be used to determine STD(WL):

[0050] and

[0051]

[0052] The initial characteristic condition corresponding to 220 is a baseline of default conditions used as a starting point for an optimization process of a target average program time (tProg DSP ).

[0053] At 230, the test circuit 102 modifies the default program parameters so that the average tProg DSP becomes (becomes closer to) tProg TH and sets a STD threshold target (STD start ). As shown, 230 includes blocks 240-270 that are performed iteratively.

[0054] At 240, the current program parameters are set. The previous program parameters (the current program parameters in the previous iteration) are modified to become the current program parameters.

[0055] At 250, the test circuit 102 determines result parameters for the M blocks of the N NAND flash devices based on the current program parameters, where the result parameters include updated WL-based result parameters. For example, the controller 110 programs all rows and WLs of all M blocks of all N NAND flash devices with random reference data using the current program parameters. Examples of the current program parameters include, but are not limited to, V step , V bias , NPP, and other parameters used in ISPP or other program trim parameters, etc. The random reference data is then read using default voltage thresholds. Based on the programming and reading, the updated result parameters are measured by the test circuit 102 and stored in the controller memory 112. Such updated result parameters include, but are not limited to, average tProg, average page BER, STD(WL), BER MAX (WL), and BER AVG (WL). The updated WL-based result parameters include STD(WL), BER MAX (WL), and BER AVG (WL) for each WL.

[0056] At 260, the test circuit 102 determines whether one or more of the updated WL-based result parameters cross a threshold.

[0057] In some examples, the test circuit 102 determines whether the STD(WL) for any WL of all M blocks of all N NAND flash devices is greater than a predetermined threshold STD TH :

[0058] STD(WL) > STD TH (5).

[0059] in response to determining that the STD(WL) of at least one WL of all M blocks of all N NAND flash devices is greater than STD TH (260: YES), the method 200 proceeds to 270. On the other hand, in response to determining that there is no WL with a STD(WL) greater than STD TH (260: NO), the process 200 ends, assuming that the current programming parameters are optimized.

[0060] In some instances, the test circuit 102 determines whether the BER MAX (WL) of any WL of all M blocks of all N NAND flash devices is greater than a predetermined threshold MAX TH :

[0061] BER MAX (WL) > MAX TH (6).

[0062] in response to determining that the BER MAX (WL) of at least one WL of all M blocks of all N NAND flash devices is greater than MAX TH (260: YES), the method 200 proceeds to 270. On the other hand, in response to determining that there is no WL with a BER TH (WL) greater than MAX MAX (260: NO), the process 200 ends, assuming that the current programming parameters are optimized.

[0063] In some instances, the test circuit 102 determines whether the BER AVG (WL) of any WL of all M blocks of all N NAND flash devices is greater than a predetermined threshold AVG TH :

[0064] BER AVG (WL) > AVG TH (7).

[0065] in response to determining that the BER AVG (WL) of at least one WL of all M blocks of all N NAND flash devices is greater than AVG TH (260: YES), the method 200 proceeds to 270. On the other hand, in response to determining that there is no WL with a BER TH (WL) greater than AVG AVG (260: NO), the process 200 ends, assuming that the current programming parameters are optimized.

[0066] In some examples, one of STD(WL), BER MAX (WL), or BER AVG (WL) is used as the WL-based result parameter evaluated at 260. In other examples, two or more of STD(WL), BER MAX (WL), and BER AVG (WL) are used as the WL-based result parameter evaluated at 260.

[0067] At 270, the test circuit 102 modifies the current program parameter. The modified current program parameter in the current iteration is set as the current program parameter in the next iteration, e.g., at 240.

[0068] In examples where STD(WL) is used as the updated WL-based result parameter at 260, the test circuit 102 can modify the current program parameter to: increase tProg (e.g., by decreasing V TH or changing other program DSP trim parameters) on each WL having a STD(WL) greater than STD start ; and decrease tProg (e.g., by increasing V TH or changing other program DSP trim parameters) on each WL having a STD(WL) less than or equal to STD start In some implementations, the trim parameters can be accessed using NAND internal configurable registers that control the program / read logic. In some implementations, these registers are set using a specific feature set command issued to the controller 110. For example, in a program process that includes generating pulses at progressively increasing voltage levels, the voltage level of the first pulse is referred to as V start , and the incremental step of the next pulse is referred to as V step . Increasing the value of the V start parameter results in more cells responding to the first pulse and the program process can succeed faster, but at the expense of program accuracy (as assessed by BER in a memory read taken after programming). Similarly, increasing / decreasing the value of the V step parameter makes the program accuracy coarser / finer, while making the program process proceed faster / slower. Examples of other DSP trim parameters include, but are not limited to, program voltage pulse width, pulse shape, pulse rise time, pulse fall time, and inter-pulse delay time. Decreasing V start allows higher accuracy programming, which in turn reduces STD(WL). On the other hand, increasing V start allows lower accuracy programming, which in turn increases STD(WL). Increasing tProg on some WLs and decreasing tProg on other WLs equalizes the STD(WL) of the WLs while maintaining the same average tProg DSP across the M program blocks.

[0069] In an example where BER MAX (WL) is used as the updated WL-based result parameter at 260, test circuit 102 can modify the current programming parameters to: increase tProg (e.g., by decreasing V TH or changing other program DSP trim parameters) on each WL having a BER MAX (WL) greater than MAX start ; and decrease tProg (e.g., by increasing V TH or changing other program DSP trim parameters) on each WL having a BER MAX (WL) less than or equal to MAX start . Decreasing V start allows for higher precision programming, which in turn decreases BER MAX (WL). On the other hand, increasing V start allows for lower precision programming, which in turn increases BER MAX (WL). Increasing tProg on some WLs and decreasing tProg on other WLs equalizes the BER MAX (WL) across the WLs while maintaining the same average tProg DSP across the M program blocks.

[0070] In an example where BER AVG (WL) is used as the updated WL-based result parameter at 260, test circuit 102 can modify the current programming parameters to: increase tProg (e.g., by decreasing V TH or changing other program DSP trim parameters) on each WL having a BER AVG greater than AVG start ; and decrease tProg (e.g., by increasing V TH or changing other program DSP trim parameters) on each WL having a BER AVG less than or equal to AVG start . Decreasing V start allows for higher precision programming, which in turn decreases BER AVG . On the other hand, increasing V start allows for lower precision programming, which in turn increases BER AVG . Increasing tProg on some WLs and decreasing tProg on other WLs equalizes the BER AVG (WL) across the WLs while maintaining the same average tProg DSP across the M program blocks.

[0071] The output at the end of method 200 (e.g., at 260:NO) is a set of current programming parameters (e.g., Vstart , V step , V bias , NPP and other parameters for ISPP or other program trim parameters). Each row or WL has a set of programming parameters determined using the method 200. This output can be in the form of a table of parameters as described. In some implementations, the controller 110 selects the programming parameters for a row or WL from a row-dependent programming parameter table indexed using row or WL numbers. For each row or WL, the physical device parameters include the row or WL address / ID / number or a series of row addresses / IDs / numbers for each row or WL. For each row or WL, the physical device parameters can further include the block address / ID / number of the block in which the row or WL resides and the cycle count to which the block of the row or WL cycles (during pre-conditioning). The programming parameters for each row or WL are the current programming parameters during the iteration in which 260: NO is detected, which are mapped to the physical device parameters for each row or WL.

[0072] The method 200 allows for using a pre-conditioning program to only disturb the iteration calculation of a set of rows (WLs) of a block and can run in parallel on multiple NAND flash devices. The output of the method 200 is used by the controller 110 to program the NAND flash devices at tProg DSP to provide high performance programming at the target while guaranteeing reliability due to the training algorithm verifying the BER distribution conditions.

[0073] While the method 200 is described with respect to WLs as a set of rows, the method 200 can equally be performed as a unit of a row, e.g., a WL includes only one row instead of multiple rows. For example, instead of determining WL-based result parameters at 220, row-based result parameters can be determined. In this regard, the resulting set of programming parameters of the method 200 is specific to a WL (multiple rows) or to a single row.

[0074] Figure 3 is a flowchart illustrating an example training method 300 according to some arrangements. Reference is made to Figures 1 to 3 The training method 300 allows the test circuit 102 to generate a table of parameters. The training method 300 can be an offline training method or an online training method. While the test circuit 102 is described as performing the training method 300 (online or offline), the controller 110 can also perform the training method 300 (online). Generally, the method 300 optimizes the write performance of N NAND flash devices to tProg DSPThe N NAND flash devices can be all of the NAND flash devices 130a-130n, some but not all of the NAND flash devices 130a-130n, or sacrificial NAND flash devices having behavior similar to the NAND flash devices 130a-130n. In examples where the N NAND flash devices correspond to some but not all of the NAND flash devices 130a-130n or sacrificial NAND flash devices, the N NAND flash devices constitute a large enough group of NAND flash devices for which a most suitable set of programming parameters can be determined based on which such programming parameters can be applied to all of the NAND flash devices 130a-130n. The method 300 can be applied to the particular NAND distribution described.

[0075] At 310, the test circuit 102 determines WL-based result parameters based on the programming of the M blocks of each of the N NAND flash devices using the current programming parameters. For example, the controller 110 programs all of the M blocks of all of the N NAND flash devices with random reference data using the current programming parameters for all of the WLs. Examples of the current programming parameters include, but are not limited to, V start , V step , V bias , NPP, and other parameters used in ISPP or other program trim parameters, etc. The random reference data is then read using default voltage thresholds.

[0076] Based on the programming and reading, result parameters are measured and stored. For example, the test circuit 102 determines and stores in the test data memory 104 the average tProg across all of the M blocks of all of the N NAND flash devices and the average page BER across all of the M blocks of all of the N NAND flash devices.

[0077] In addition, the test circuit 102 determines and stores in the controller memory 112 the maximum BER (referred to as BER MAX (WL)) for each WL of all of the M blocks of all of the N NAND flash devices.

[0078] Further, the test circuit 102 determines and stores in the controller memory 112 a plurality of moments (from order 1 to K) of the BER distribution as a function of WL (referred to as WL) and referred to as:

[0079]

[0080] The test circuit 102 can determine an optimization score using an optimization scoring function incorporating the plurality of moments, for example:

[0081]

[0082] where w iLet S be the weight of the i-th moment in the optimization scoring function, and let S be the optimization score. Therefore, the optimization scoring function is the sum of the weights of the moment functions.

[0083] Therefore, the result parameters based on WL include BER. MAX (WL) or at least one of S.

[0084] At 320, test circuit 102 determines whether one or more of the result parameters based on WL cross the threshold.

[0085] In some instances, test circuit 102 determines whether the optimized score S (e.g., the weighted sum of moments) of any WL for all M blocks of all N NAND flash memory devices is greater than a score threshold UTH:

[0086] S>UTH (10).

[0087] In response to determining that at least one WL of all M blocks of all N NAND flash memory devices has a S greater than UTH (320: Yes), method 300 proceeds to 330. On the other hand, in response to determining that there is no WL with a S greater than MAX... TH S's WL(320: No), process 300 ends, assuming the current programming parameters have been optimized.

[0088] In some instances, test circuit 102 (for example) determines the BER of any WL for all M blocks of all N NAND flash memory devices according to formula (6). MAX Is (WL) greater than the predetermined threshold MAX? TH In response to determining the BER of at least one WL for all M blocks of all N NAND flash memory devices. MAX (WL) is greater than MAX TH (320: Yes), method 300 proceeds to 330. On the other hand, in response to determining that there is no value greater than MAX... TH BER MAX (WL) of WL(320: No), process 200 ends, assuming the current programming parameters have been optimized.

[0089] At 330, test circuit 102 modifies the current programming parameters. The modified current programming parameters in the current iteration are set as the current programming parameters in the next iteration, for example, as used in 310.

[0090] In an instance where S is used as a WL-based result parameter at 320, test circuit 102 can modify the current programming parameters to: increase tProg on each WL with S greater than UTH (e.g., by decreasing V). start Or change other program DSP trimming parameters); and reduce tProg on each WL with an S less than or equal to UTH (e.g., by increasing V).start or changing other program DSP trim parameters). Decreasing V start allows for higher precision programming, which in turn decreases S. On the other hand, increasing V start allows for lower precision programming, which in turn increases S. Increasing tProg on some WLs and decreasing tProg on other WLs equalizes S across the WLs while maintaining the same average tProg across the M program blocks DSP .

[0091] In which BER MAX (WL) is used as the WL-based outcome parameter at 320, the test circuit 102 can modify the current programming parameters to: increase tProg on each WL having a BER TH (WL) greater than MAX MAX (WL) (e.g., by decreasing V start or changing other program DSP trim parameters); and decrease tProg on each WL having a BER TH (WL) less than or equal to MAX MAX (WL) (e.g., by increasing V start or changing other program DSP trim parameters). As described, decreasing V start allows for higher precision programming, which in turn decreases BER MAX (WL). On the other hand, increasing V start allows for lower precision programming, which in turn increases BER MAX (WL). Increasing tProg on some WLs and decreasing tProg on other WLs equalizes BER MAX (WL) across the WLs while maintaining the same average tProg across the M program blocks DSP .

[0092] The output at the end of the method 300 (e.g., at 320:NO) is a set of current programming parameters (e.g., V start , V step , V bias , NPP, and other parameters used in ISPP or other program trim parameters) that vary by WL. Each WL itself has a set of programming parameters determined using the method 300. This output can be in the form of a table of parameters as described. For each WL, the physical device parameters include the WL address / ID / number or a range of row addresses / IDs / numbers of each WL. For each WL, the physical device parameters can further include the block address / ID / number of the block in which the WL resides. The programming parameters for each WL are the current programming parameters during the iteration in which 320:NO is detected, which are mapped to the WL address / ID / number or a range of row addresses / IDs / numbers of each WL.

[0093] Figure 4 is a flowchart illustrating an example training method 400 according to some arrangements. Referring to Figures 1 to 4 , the training method 400 allows the test circuit 102 to generate a parameter table and incorporate the method 200. In the method 400, all blocks of the N NAND flash devices are divided into a plurality of block sets, each block set including a plurality of blocks. Each block set includes blocks having similar tProg and BER distributions, while blocks from different block sets have more different tProg and BER distributions. In this regard, the values of the programming parameters of the blocks within the same block set are more similar than the programming parameters of the blocks in different block sets. The method 200 is performed on each block set such that the plurality of blocks in each block set corresponds to the M blocks in the method 200.

[0094] At 410, the test circuit 102 determines the tProg and BER characteristics of all blocks of the N NAND flash devices. For example, the controller 110 programs all rows and WLs of all blocks of all N NAND flash devices with random reference data using default programming parameters. Examples of the default programming parameters include, but are not limited to, default V start , default V step , default V bias , default NPP, and other default parameters used in ISPP, etc. The random reference data is then read using default voltage thresholds. Based on the programming and reading, the tProg and BER characteristics of each of all blocks of the N NAND flash devices are determined. For example, the tProg and BER of each of all blocks of the N NAND flash devices are measured based on the programming and reading.

[0095] At 420, the test circuit 102 determines block sets, each block set including blocks having common tProg and BER characteristics. For example, the test circuit 102 divides all blocks of all N NAND flash devices into a plurality of different block sets or groups. The number of block sets is referred to as Sb.

[0096] In some examples, all blocks are sorted according to their tProg and divided into Sb block sets according to different tProg ranges, such that a first block set includes blocks having tProg within a lowest tProg range, a second block set includes blocks having tProg within a second lowest tProg range (and higher than the lowest tProg range), a third block set includes blocks having tProg within a third lowest tProg range (and higher than the lowest and second lowest tProg ranges), and so on, and an Sb block set includes blocks having tProg within a highest tProg range.

[0097] In some examples, all the blocks are sorted according to their BERs and divided into Sb block sets according to different BER ranges, such that the first block set contains blocks with BERs in the lowest BER range, the second block set contains blocks with BERs in the second-lowest BER range (and higher than the lowest BER range), the third block set contains blocks with BERs in the third-lowest BER range (and higher than the lowest and second-lowest BER ranges), and so on, and the Sb block set contains blocks with tProg in the highest BER range.

[0098] In some examples, a score is computed for each of all the blocks of the N NAND flash devices based on a combination of the per-block BER and the per-block tProg. For example, the score can be a weighted sum of the per-block BER and the per-block tProg, or a result of another suitable function with the per-block BER and the per-block tProg as inputs. All the blocks are sorted according to their scores and divided into Sb block sets according to different score ranges, such that the first block set contains blocks with scores in the lowest score range, the second block set contains blocks with scores in the second-lowest score range (and higher than the lowest score range), the third block set contains blocks with scores in the third-lowest score range (and higher than the lowest and second-lowest score ranges), and so on, and the Sb block set contains blocks with tProg in the highest score range.

[0099] Each of the Sb block sets is processed 430-450. For example, at 430, the test circuit 102 performs the method 200 on the current block set, where the blocks in the current block set are the M blocks of the method 200. The method 200 ends at 260:NO, where the tuned programming parameters (e.g., as a table) as a function of WL are generated. At 440, the test circuit 102 determines whether the current block set is the last block set. In response to determining that the current block set is the last block set (440:YES), the method 400 ends, and the tuned programming parameters for each of the Sb block sets have been generated. On the other hand, in response to determining that the current block set is not the last block set (440:NO), the next block set is set as the current block set at 450, and the method 400 returns to 430.

[0100] Dividing the blocks into different block sets allows more accurate characterization of the programming parameters to be determined more efficiently for all the N NAND flash devices. Instead of the tProg and BER characterization of each block described herein, the block sets can also be generated based on physical locations within a die of the NAND flash devices that are related to the BER and tProg distributions.

[0101] Figure 5 is a flowchart illustrating an example training method 500 according to some arrangements. Reference is made to Figures 1 to 5The training method 500 allows the test circuit 102 to generate parameter tables and incorporate the method 300. In the method 500, all blocks of the N NAND flash devices are divided into a plurality of block sets, as described with respect to Figure 4 The method 300 is performed on each block set, such that the plurality of blocks in each block set correspond to the M blocks in the method 300.

[0102] At 410, the test circuit 102 determines the tProg and BER characteristics of all blocks of the N NAND flash devices, as described with respect to Figure 4 At 420, the test circuit 102 determines block sets, each block set including blocks having common tProg and BER characteristics, as described with respect to Figure 4

[0103] 510, 440, and 450 are performed on each of the Sb block sets. For example, at 510, the test circuit 102 performs the method 300 on a current block set, where the blocks in the current block set are the M blocks of the method 300. The method 300 ends at 320:NO, where the tuned programming parameters (e.g., as a table) are generated as a function of WL. At 440, the test circuit 102 determines whether the current block set is the last block set. In response to determining that the current block set is the last block set (440:YES), the method 500 ends, and the tuned programming parameters for each of the Sb block sets have been generated. On the other hand, in response to determining that the current block set is not the last block set (440:NO), the next block set is set as the current block set at 450, and the method 500 returns to 510.

[0104] In some implementations, the voltage thresholds for read operations can be acquired (rather than using default voltage read thresholds) for minimizing NAND read errors. In this regard, a threshold tracking estimator that knows the physical parameters (e.g., row, word line, block address, P / E cycle count, etc.) can be used for the program DSP. Thus, the methods described herein for determining programming parameters for a WL or row can be combined with a threshold tracking estimator. In some examples, the read DSP with threshold tracking algorithm for each row set can be trained separately from the methods described herein, thus improving the accuracy of the threshold estimates.

[0105] In other examples, the read DSP with threshold tracking algorithm for each row set can be co-trained with the program DSP selection for the row set or other parameters. That is, for each iteration where the programming parameters are updated for a given WL, the updated programming parameters in that iteration are also used to calculate the read DSP estimate accuracy.

[0106] Figure 6 is a flowchart illustrating an example training method 600 according to some arrangements. Reference is made to Figures 1 to 6 ​Methods 200, 300, 400, and 500 are particular embodiments of method 600. Method 600 can be performed by test circuit 102 to generate optimized programming parameters for each WL or each row of a plurality of NAND flash devices (e.g., N NAND flash devices). In some examples, each WL includes a set of physical rows in the same physical layer of one of the plurality of NAND flash devices. In other examples, each WL refers to a group of rows only.

[0107] At 610, test circuit 102 determines at least one result parameter for each row or each WL in the plurality of WLs on the plurality of blocks of the plurality of NAND flash devices based on programming using the programming parameters. The at least one result parameter includes a STD of page BER for each WL or each row. The STD of page BER for each WL or row is determined using a moment of a BER distribution for each WL or row. In some examples, the moment can be greater than 2. The at least one result parameter includes an average BER for each WL or each row. The at least one result parameter includes a maximum BER for each WL or each row. The at least one result parameter includes a fraction for each WL or each row, the fraction determined using a plurality of moments of a page BER distribution for each WL or each row.

[0108] At 620, test circuit 102 modifies the programming parameters for one or more WLs or one or more rows in the plurality of WLs based on the at least one result parameter. In some examples, the programming parameters include at least one of V start , V step , V bias , or NPP. In some examples, modifying the programming parameters for one or more WLs or one or more rows in the plurality of WLs based on the at least one result parameter includes determining that one of the at least one result parameter for each of the one or more WLs or each of the one or more rows crosses a threshold, and responsively modifying the programming parameters for each of the one or more WLs or the one or more rows.

[0109] In some examples, method 600 further includes determining at least one result parameter for each WL in the plurality of WLs or each row on the plurality of blocks of the plurality of NAND flash devices based on programming using the modified programming parameters. In some examples, method 600 further includes determining that one of the at least one result parameter for any of the plurality of WLs or any of the rows does not cross a threshold, and responsively determining that the programming parameters for each of the plurality of WLs or each of the rows is an optimized programming parameter. In some examples, modifying the programming parameters for each of the one or more WLs or each of the one or more rows includes adjusting tProg for each of the one or more WLs or each of the one or more rows by modifying the programming parameters for each of the one or more WLs or each of the one or more rows.

[0110] At 630, the test circuit 102 generates optimized programming parameters corresponding to the physical device parameters by modifying the programming parameters for one or more of the plurality of WLs or one or more of the rows based on the at least one result parameter. The physical device parameters include at least an address of each of the plurality of WLs or an address of each of the one or more rows.

[0111] In some examples, the method 600 further includes pre-conditioning a plurality of blocks to different cycle counts. The at least one result parameter is determined after pre-conditioning the plurality of blocks.

[0112] In some examples, the number of the plurality of blocks is less than a total number of blocks on the plurality of NAND flash devices. In some examples, the plurality of blocks is randomly selected from all blocks on the plurality of NAND flash devices. In some examples, all blocks on the plurality of NAND flash devices are divided into a plurality of block sets based on one or more of a program time or an error characteristic such that blocks within each of the plurality of block sets correspond to the plurality of blocks involved at 610.

[0113] Accordingly, the methods described herein involve a training process for obtaining adaptive trim parameters (optimized programming parameters) for different row sets. The training process includes testing a plurality of NAND flash devices under different endurance and stress conditions (e.g., different cycle counts) to: measure a defined row set (WL) from tProg and BER per page on the plurality of devices; calculate a score for each row set to indicate feasible parameter modifications; update program DSP trim parameters for each row set; and repeat the above process until a performance target is met and similar scores are obtained on all row sets.

[0114] In some examples, the score for optimization is a STD of page BER measured on the plurality of NAND flash devices as a function of WL. In some examples, the score optimization can be performed using any higher order moment of the page BER distribution as a function of physical device parameters (e.g., row, WL, etc.) of the NAND flash device.

[0115] As described, the methods described herein reduce the standard deviation of BER per row or WL to enable reliability and allow high average BER operation while controlling low peak to average BER distribution. High write performance can be achieved by improving reliability under the same stress conditions.

[0116] The methods include optimizing programming parameters as a function of other physical device parameters (e.g., block address, P / E cycle count, etc.). This means that the methods described herein can be implemented for a block set with common physical device characteristics, and a set of programming parameters for each block set with different row sets can be obtained. In addition, the methods described herein can be applied separately for different cycle ranges.

[0117] Figure 7is a process flow diagram illustrating an example method 700 for programming data using trained programming parameters according to some arrangements. Reference is made to Figures 1 to 7 Method 700 is performed by controller 110. As described, after test circuit 102 determines optimized programming parameters using one or more of methods 200, 300, 400, 500, or 600, test circuit 102 can use any suitable mechanism to communicate the programming parameters that vary as a function of WL or row (e.g., in the form of a table) to controller memory 112. Controller 110 can use such programming parameters to program data. Method 700 is simpler and brings insignificant overhead in tuning each NAND flash device.

[0118] At 710, controller 110 determines a target row corresponding to a program command. Controller 110 can receive a program command from host 101 and translate (via FTL) a logical address corresponding to the command to a physical address including a row address / ID / number and a block address / ID / number.

[0119] At 720, controller 110 sets the programming parameters for the target row using the physical device parameters of the target row and the optimized programming parameters corresponding to the physical device parameters. For example, controller 110 looks up the physical device parameters (e.g., row address / ID / number, block address / ID / number, and cycle count (if available)) in the parameter table stored in controller memory 112 and determines the optimized programming parameter set (e.g., V start step bias , NPP, and other parameters used in ISPP, or other program trim parameters) mapped to the physical device parameters.

[0120] At 730, controller 110 activates the program command. In response to the programming parameters being set for the row / block identified by the row address / ID / number and the block address / ID / number, controller 110 activates the program command and programs data corresponding to the program command on the row / block identified by the row address / ID / number and the block address / ID / number.

[0121] ​​The above description is presented to enable a person of ordinary skill in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those of ordinary skill in the art, and the general principles defined herein can be applied to other aspects as well. Thus, the claims are not intended to be limited to the aspects presented herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more." Unless otherwise noted, the terms "some" and "another" refer to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether these disclosure are explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase "means for."

[0122] It is to be understood that the specific order or hierarchy of steps in the processes disclosed is an example of illustrative approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes can be rearranged while remaining within the scope of the above description. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0123] The above description of disclosed implementations is provided to enable any person skilled in the art to make or use the disclosed subject matter. Various modifications to these implementations will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of the description. Thus, the description is not intended to be limited to the implementations shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0124] The various examples illustrated and described above are provided merely as examples to illustrate various features of the claims. However, features shown and described with respect to any given example are not necessarily limited to the associated example, but can be used with or combined with other examples shown and described. Moreover, the claims are not intended to be limited by any one example.

[0125] The above method descriptions and the process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by one of ordinary skill in the art, the order of steps in the foregoing examples can be performed in any order. Words such as "thereafter," "then," "next," etc. are used merely to guide the reader through the description of processes. Additionally, any reference to claim elements in the singular, for example, using the articles "a," "an" or "the" is not nevertheless a limitation of the implementations to a single element, but encompasses a full range of zero or more elements. Additionally, the words "comprises," "comprising," "includes," "including," and the like can have the meaning ascribed to them under

[0126] The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the examples disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0127] The hardware used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the examples disclosed herein can be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some steps or methods can be performed by circuitry that is specific to a given function.

[0128] In some demonstrative examples, the described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. The steps of a method or algorithm disclosed herein can be embodied in a processor-executable software module which can reside on a non-transitory computer- or processor- readable storage medium. Non-transitory computer- or processor-readable storage media can be any storage media that can be accessed by a computer or a processor. By way of example, and not limitation, such non-transitory computer- or processor-readable storage media can include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks and Blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of non-transitory computer- and processor-readable media. Additionally, the operations of a method or algorithm can reside in one or any combination of the above memory hardware, as one or any combination of the code and / or instructions for the operating method or algorithm can be stored in the non-transitory processor-readable storage media and / or the computer-readable storage media.

[0129] The above description of the disclosed examples is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these examples will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to some examples. Thus, the disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for programming data on a storage device, comprising: determining a target row corresponding to a program command; setting row-based programming parameters for the target row using a target physical device parameter for the target row and optimized programming parameters corresponding to the physical device parameter; and activating a data programming operation for the target row by setting trim parameters of a program DSP using the row-based programming parameters.

2. The method of claim 1, further comprising: determining at least one result parameter for each row of a plurality of rows of a block of a plurality of NAND flash devices based on programming parameter programming of the plurality of blocks of the plurality of NAND flash devices; and modifying the programming parameters for one or more rows of the plurality of rows based on the at least one result parameter.

3. The method of claim 2, further comprising generating the optimized programming parameters mapped to physical device parameters via modifying the programming parameters for the one or more rows of the plurality of rows based on the at least one result parameter.

4. The method of claim 3, wherein the physical device parameters comprise an address for each of the plurality of rows.

5. The method of claim 2, wherein the programming parameters include at least one of: an initial voltage level V start , a pulse voltage step V step , a bias voltage V bias , a maximum number of pulses NPP, a program voltage pulse width, a pulse shape, a pulse rise time, a pulse fall time, or a pulse to pulse delay time.

6. The method of claim 2, wherein the at least one result parameter comprises a standard deviation of a page error rate for each row.

7. The method of claim 6, wherein the standard deviation of the page error rate for each row is determined using a moment of an error rate distribution for each row, the moment being greater than 2.

8. The method of claim 2, wherein the at least one result parameter comprises an average error rate for each row.

9. The method of claim 2, wherein the at least one result parameter comprises a maximum error rate for each row.

10. The method of claim 2, wherein the at least one result parameter comprises a score for each row, the score determined using a plurality of moments of a page error rate distribution for each row.

11. The method of claim 2, wherein modifying the programming parameters for the one or more rows of the plurality of rows based on the at least one result parameter comprises: determining that one of the at least one result parameter for each of the one or more rows crosses a threshold; and responsively modifying the programming parameters for each of the one or more rows.

12. The method of claim 11, further comprising determining the at least one result parameter for each row of the plurality of rows on the plurality of blocks of the plurality of NAND flash devices based on programming parameter programming of the plurality of blocks of the plurality of NAND flash devices using the modified programming parameters.

13. The method of claim 11, further comprising: determining that one of the at least one result parameter for any of the plurality of rows does not cross a threshold; and responsively determining that the programming parameters for each of the plurality of rows are optimized programming parameters.

14. The method of claim 11, wherein modifying the program parameters of each of the one or more rows comprises adjusting a program time, tProg, of each of the one or more rows by modifying the program parameters of each of the one or more rows.

15. The method of claim 2, further comprising pre-conditioning the plurality of blocks to different cycle counts, wherein the at least one result parameter is determined after pre-conditioning the plurality of blocks.

16. The method of claim 2, wherein a number of the plurality of blocks is less than a total number of blocks on the plurality of NAND flash devices.

17. The method of claim 16, wherein the plurality of blocks are randomly selected from all blocks on the plurality of NAND flash devices.

18. The method of claim 16, wherein all blocks on the plurality of NAND flash devices are divided into a plurality of block sets based on one or more of program time or error characteristics, and blocks within each of the plurality of block sets correspond to the plurality of blocks.

19. A storage device comprising: a non-volatile memory; and a controller configured to: determine a target row corresponding to a program command; set row-based program parameters for the target row using a target physical device parameter of the target row and optimized program parameters corresponding to the physical device parameter; and activate a data program operation for the target row by setting trim parameters of a program DSP using the row-based program parameters.

20. A non-transitory processor-readable medium comprising processor-readable instructions such that, when executed by a processor, cause the processor to: determine a target row corresponding to a program command; set row-based program parameters for the target row using a target physical device parameter of the target row and optimized program parameters corresponding to the physical device parameter; and activate a data program operation for the target row by setting trim parameters of a program DSP using the row-based program parameters. ​

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