Semiconductor packaging method

Abstract

The present application provides a semiconductor packaging method. The semiconductor packaging method includes: mounting a chip on a carrier, the chip having a front side, the front side of the chip facing away from the carrier, and a plurality of pads being provided on the front side of the chip; forming a support layer on the carrier, the support layer encapsulating the side surface of the chip, and the front side of the chip being exposed; forming a first redistribution structure on a side of the support layer facing away from the carrier, the first redistribution structure being electrically connected to the pads of the chip; removing the support layer; and forming a molding layer, the molding layer encapsulating the chip and the first redistribution structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technology, mainly include the following process: first, the front side of the chip is bonded to the carrier with tape, and hot pressing is performed to form a plastic layer. Then, the carrier is peeled off, the surface of the plastic layer is processed, and then a rewiring layer is formed on the surface of the plastic layer to lead out the solder pads on the front side of the chip.

[0003] Generally, the plastic encapsulation layer needs to be pre-processed before forming the rewiring layer, such as grinding, cleaning, plasma and other processing steps, to ensure that the surface flatness of the plastic encapsulation layer is good, the adhesion between the plastic encapsulation layer and the rewiring layer is good, and it is not easy to peel off. The pre-processing process of the plastic encapsulation layer is relatively complicated, resulting in a complicated semiconductor packaging process and a long time. Summary of the invention

[0004] The present application provides a semiconductor packaging method. The semiconductor packaging method includes:

[0005] Mounting a chip on a carrier, the chip having a front side, the front side of the chip facing away from the carrier, and a plurality of pads being arranged on the front side of the chip;

[0006] forming a support layer on the carrier, wherein the support layer encapsulates the side surface of the chip and the front surface of the chip is exposed;

[0007] forming a first rewiring structure on a side of the support layer away from the carrier, wherein the first rewiring structure is electrically connected to a pad of the chip;

[0008] removing the support layer;

[0009] A plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the chip and the first rewiring structure.

[0010] In one embodiment, the support layer is made of metal or insulating material.

[0011] In one embodiment, the material of the support layer is metal tin;

[0012] The forming of the support layer on the carrier plate comprises:

[0013] Tin powder is laid on the carrier plate, and the tin powder is heated. After the tin powder is melted, it is bonded together to obtain the support layer.

[0014] In one embodiment, the material of the support layer is metallic tin; and removing the support layer comprises:

[0015] Heat the support layer to melt it, and separate the melted support layer from the chip and the first redistribution structure; or, rapidly cool the support layer to transform it into tin powder, and separate the tin powder from the chip and the first redistribution structure.

[0016] In one embodiment, before removing the support layer, the semiconductor packaging method further includes:

[0017] Peel off the carrier plate, and mount the obtained structure on a support plate.

[0018] In one embodiment, the molding compound layer is exposed on the side of the first redistribution structure facing away from the chip.

[0019] In one embodiment, before forming the support layer on the carrier plate, the semiconductor packaging method further includes: providing a conductive structure on the carrier plate; the surface of the conductive structure facing away from the carrier plate exposes the support layer, and the conductive structure is electrically connected to the first redistribution structure;

[0020] After forming the first redistribution structure on the side of the support layer facing away from the carrier plate and before removing the support layer, the semiconductor packaging method further includes: peeling off the carrier plate to expose the back surface of the chip; forming a second redistribution structure on the back surface of the chip, and the second redistribution structure is electrically connected to the conductive structure;

[0021] After forming the molding compound layer, the surface of the second redistribution structure facing away from the chip exposes the molding compound layer.

[0022] In one embodiment, the conductive structure is pre-prepared, and providing the conductive structure on the carrier plate includes:

[0023] Mount the conductive structure on the carrier plate.

[0024] In one embodiment, before removing the support layer, the semiconductor packaging method further includes: performing at least once the following steps:

[0025] Form a third redistribution structure on the side of the exposed redistribution structure facing away from the chip, and the third redistribution structure is electrically connected to the first redistribution structure;

[0026] Form a support material layer that encapsulates the third redistribution structure, and the side of the third redistribution structure facing away from the chip exposes the support material layer;

[0027] Before forming the molding compound layer, the semiconductor packaging method further includes: removing the support material layer;

[0028] After the plastic encapsulation layer is formed, the plastic encapsulation layer is exposed on a side of the third rewiring structure that is the largest distance from the chip and is away from the chip.

[0029] In one embodiment, the support material layer is made of the same material as the support layer;

[0030] The step of removing the support layer is performed simultaneously with the step of removing the support material layer.

[0031] The main technical effects achieved by the embodiments of the present application are:

[0032] The semiconductor packaging method provided in the embodiment of the present application can form a first rewiring structure on the side of the supporting layer away from the carrier by forming a supporting layer. Therefore, there is no need to form a plastic encapsulation layer before forming the first rewiring structure, and the plastic encapsulation layer formed after the first rewiring structure is formed is tightly combined with the first rewiring structure. Since the plastic encapsulation layer is formed after the first rewiring structure, there is no need to pre-treat the plastic encapsulation layer, which can simplify the semiconductor packaging process and shorten the packaging time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

[0034] Figure 2 is a schematic structural diagram of a protective film formed on the active surface of a silicon wafer provided by an exemplary embodiment of the present application;

[0035] Figure 3 Yes Figure 2 A schematic diagram of the structure obtained by cutting a hole in the protective film on the silicon wafer shown;

[0036] Figure 4 is Figure 3 A schematic diagram of a structure obtained by forming a metal layer on a protective film of a silicon wafer as shown;

[0037] Figure 5 is a schematic diagram of the structure of a chip provided by an exemplary embodiment of the present application;

[0038] Figure 6 is a structural schematic diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0039] Figure 7 is a structural schematic diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0040] Figure 8 is a structural schematic diagram of a third intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0041] Figure 9 It is a schematic structural diagram of the fourth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0042] Figure 10 It is a schematic structural diagram of the fifth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0043] Figure 11 It is a schematic structural diagram of the sixth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0044] Figure 12 It is a schematic structural diagram of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0045] Figure 13 It is a schematic structural diagram of the structure obtained by forming metal layers on both sides of a silicon wafer provided by an exemplary embodiment of the present application;

[0046] Figure 14 It is a schematic structural diagram of the seventh intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0047] Figure 15 It is a schematic structural diagram of the eighth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0048] Figure 16 It is a schematic structural diagram of the ninth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0049] Figure 17 It is a schematic structural diagram of the tenth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0050] Figure 18 It is a schematic structural diagram of the eleventh intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0051] Figure 19 It is a schematic structural diagram of the twelfth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0052] Figure 20 It is a schematic structural diagram of the thirteenth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0053] Figure 21 It is a schematic structural diagram of the fourteenth intermediate structure of the semiconductor package structure provided by an exemplary embodiment of the present application;

[0054] Figure 22It is a schematic structural diagram of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0055] Figure 23 It is a schematic structural diagram of the fifteenth intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0056] Figure 24 It is a schematic structural diagram of the sixteenth intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0057] Figure 25 It is a schematic structural diagram of the seventeenth intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0058] Figure 26 It is a schematic structural diagram of the eighteenth intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0059] Figure 27 It is a schematic structural diagram of the nineteenth intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0060] Figure 28 It is a schematic structural diagram of the twentieth intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0061] Figure 29 It is a schematic structural diagram of the twenty - first intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0062] Figure 30 It is a schematic structural diagram of the twenty - second intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0063] Figure 31 It is a schematic structural diagram of a semiconductor packaging structure provided by an exemplary embodiment of the present application. Specific Embodiments

[0064] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0065] The terms used in this application are for the purpose of describing particular embodiments only and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0066] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0067] The following will, with reference to the accompanying drawings, elaborate on some embodiments of this application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0068] Embodiments of this application provide a semiconductor packaging method. Refer to Figure 1 , the semiconductor packaging method includes the following steps 110 to 150.

[0069] In step 110, a chip is mounted on a carrier, the chip has a front side, the front side of the chip faces away from the carrier, and a plurality of pads are provided on the front side of the chip.

[0070] In step 120, a support layer is formed on the carrier, the support layer encapsulates the side of the chip, and the front side of the chip is exposed.

[0071] In step 130, a first redistribution structure is formed on a side of the support layer facing away from the carrier, and the first redistribution structure is electrically connected to the pads of the chip.

[0072] In step 140, the support layer is removed.

[0073] In step 150, a molding layer is formed, and the molding layer encapsulates the chip and the first redistribution structure.

[0074] The semiconductor packaging method provided by the embodiments of the present application forms a support layer, and a first redistribution structure can be formed on the side of the support layer facing away from the carrier board. Therefore, there is no need to form a molding compound layer before forming the first redistribution structure, and the molding compound layer formed after forming the first redistribution structure is tightly combined with the first redistribution structure. Since the molding compound layer is formed after the first redistribution structure, there is no need to perform pretreatment on the molding compound layer, which can simplify the semiconductor packaging process and shorten the packaging duration.

[0075] The steps of a semiconductor packaging method provided by the embodiments of the present application will be introduced in detail below.

[0076] In step 110, a chip is mounted on a carrier board. The chip has a front side, and the front side of the chip faces away from the carrier board. A plurality of pads are provided on the front side of the chip.

[0077] In one embodiment, the first chip can be prepared through the following process:

[0078] First, a silicon wafer is provided, and the silicon wafer has a specific function. The silicon wafer has an active surface, and pads are provided on the active surface of the silicon wafer. The pads are used for electrical connection with external components.

[0079] Subsequently, the active surface of the silicon wafer is subjected to plasma treatment. By subjecting the active surface of the silicon wafer to plasma treatment, the surface energy of the active surface of the silicon wafer can be increased, so that the active surface of the silicon wafer is more firmly bonded to the subsequent formed protective layer.

[0080] Subsequently, an insulating material is coated on the active surface of the silicon wafer.

[0081] Subsequently, the insulating material is cured to form a protective layer. Through this step, the structure as shown in Figure 2 can be obtained. As shown in Figure 2 , the protective layer 12 covers the active surface of the silicon wafer 11. The protective layer 12 is one or more layers of insulating materials, and the material of the protective layer 12 can be a molding film, PI (polyimide), PBO (polyphenylene benzoxazole), organic polymer film, organic polymer composite material, or other materials with similar properties. The protective layer 12 can be formed on the active surface of the silicon wafer 11 by lamination, spin coating, printing, molding, or other suitable methods.

[0082] Subsequently, an opening exposing the pads is formed in the protective layer. Through this step, the structure as shown in Figure 3 can be obtained. The opening 121 can be formed by laser drilling.

[0083] Subsequently, the protective layer is subjected to plasma treatment. Through this step, the residual insulating material in the opening 121 can be removed, and the surface energy on the side of the protective layer 12 facing away from the silicon wafer 11 can be increased, so that the adhesion between the protective layer 12 and the subsequent formed metal layer stack can be increased.

[0084] Subsequently, a metal layer is formed on the side of the protective layer 12 facing away from the silicon wafer 11. Through this step, the structure as shown in Figure 4 can be obtained. Refer to Figure 4 . The metal layer 13 covers the side surface and the bottom surface of the opening 121. The metal layer 13 can be formed by a sputtering process.

[0085] Subsequently, the silicon wafer 11 is cut. The silicon wafer 11 can be cut along the position of the dashed line shown in Figure 4 . The silicon wafer 11 can be cut by mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer 11, a grinding device can be used to grind the back surface of the silicon wafer opposite to the active surface so that the thickness of the silicon wafer 11 is a specified thickness. Through this step, the chip 10 as shown in Figure 5 can be obtained.

[0086] In some embodiments, the chip 10 may not include the metal layer 13, and the metal layer 13 may also be formed in subsequent process steps.

[0087] Through step 110, the first intermediate structure as shown in Figure 6 can be obtained. Figure 6 In the embodiment shown in , a plurality of chips 10 are mounted on the carrier 20. In other embodiments, the number of chips 10 mounted on the carrier 20 can be one. The back surface of the chip 10 can be adhered to the carrier 20 through the adhesive layer 21.

[0088] In one embodiment, the shape of the carrier 20 can be circular, rectangular or other shapes. The carrier 20 can be a small-sized wafer substrate or a larger-sized carrier, such as a stainless steel plate substrate, a polymer substrate, etc.

[0089] In step 120, a support layer is formed on the carrier, and the support layer encapsulates the side surfaces of the chips, and the front surfaces of the chips are exposed.

[0090] Through step 120, the second intermediate structure as shown in Figure 7 can be obtained. Refer to Figure 7 . The surface of the support layer 30 facing away from the carrier 20 can be flush with the surface of the metal layer 13 facing away from the carrier 20. The gaps between adjacent chips 10 are filled with the support layer 30.

[0091] In one embodiment, the material of the support layer 30 is a metal or an insulating material. In this way, the material of the support layer 30 is easy to obtain.

[0092] In one embodiment, the material of the support layer 30 is metallic tin. The step 120 of forming the support layer on the carrier may include the following process:

[0093] Lay solder powder on the carrier board, heat the solder powder, and after the solder powder melts, it adheres together to obtain the support layer.

[0094] In this step, solder powder can be laid on the periphery of the chip 10, and the amount of solder powder laid can be determined according to the volume of the support layer 30 to be formed subsequently. By heating the solder powder, the solder powder melts, and after cooling, the support layer 30 can be obtained, which is relatively easy to operate.

[0095] In one embodiment, after step 120, the semiconductor packaging method further includes: cleaning the surface of the second intermediate structure to remove impurities on the surface of the second intermediate structure. The impurities on the surface of the second intermediate structure can be removed by water washing or acid washing.

[0096] In step 130, a first redistribution structure is formed on the side of the support layer facing away from the carrier board, and the first redistribution structure is electrically connected to the solder pads of the chip.

[0097] Through step 130, the third intermediate structure as shown in Figure 8 can be obtained. Refer to Figure 8 , the first redistribution structure includes a first redistribution layer 40, the first redistribution layer 40 includes a plurality of first conductive traces 41, and the first conductive traces 41 are electrically connected to the solder pads of the chip 10.

[0098] In one embodiment, the step 130 of forming a first redistribution structure on the side of the support layer facing away from the carrier board includes the following process:

[0099] First, a photosensitive material is coated on the side of the third intermediate structure facing away from the carrier board, and the photosensitive material can cover the side of the third intermediate structure facing away from the carrier board.

[0100] In some embodiments, when the chip 10 does not include the metal layer 13, the metal layer 13 can be formed first before coating the photosensitive material.

[0101] Subsequently, the photosensitive material is baked to cure the photosensitive material to form a photosensitive layer.

[0102] Subsequently, the photosensitive layer is patterned to remove the photosensitive layer at the position where the first redistribution structure needs to be formed. The photosensitive layer can be patterned by an exposure and development process.

[0103] Subsequently, the photosensitive layer is subjected to plasma treatment. Through this step, the remaining photosensitive material at the position where the first redistribution structure needs to be formed can be removed.

[0104] Subsequently, a conductive layer is formed in the area where the metal layer is not covered by the photosensitive layer. The conductive layer can be formed by an electroplating process. When electroplating, the metal layer 13 serves as a seed layer, and the support layer electrically connects the metal layers 13 on adjacent chips 10.

[0105] Subsequently, the photosensitive layer is peeled off.

[0106] Subsequently, the metal layer is etched to remove the area of the metal layer not covered by the conductive layer, forming the first conductive trace 41. The first conductive trace 41 includes the conductive layer and the metal layer.

[0107] In step 140, the support layer is removed.

[0108] In one embodiment, before step 140, the semiconductor packaging method further includes: peeling off the carrier plate and mounting the obtained structure on a support plate.

[0109] Through this step, the fourth intermediate structure as shown in Figure 9 can be obtained. As shown in Figure 9 , the first conductive trace 41 of the first redistribution structure faces the support plate 22, and the first conductive trace 41 is mounted on the support plate 22 through the bonding layer 23.

[0110] Removing the carrier plate before removing the support layer and mounting the obtained structure on the support plate 22 can avoid the relative movement of different structures after removing the support layer, which may affect the product yield, compared with the solution of mounting the obtained structure on the support plate 22 after removing the support layer.

[0111] In one embodiment, the material of the support layer is metallic tin. The step 140 of removing the support layer may include the following process:

[0112] Heating the support layer to melt the support layer, and separating the melted support layer from the chip and the first redistribution structure. By heating the fourth intermediate structure as shown in Figure 9 , after the temperature of the fourth intermediate structure reaches the melting point of tin, 232 °C, the support layer 30 melts and separates from other structures including the chip and the first redistribution structure.

[0113] In another embodiment, the material of the support layer is metallic tin. The step 140 of removing the support layer may include the following process:

[0114] Rapidly cooling the support layer to transform the support layer into tin powder, and separating the tin powder from the support layer, the chip and the first redistribution structure. By performing rapid cooling treatment on the fourth intermediate structure as shown in Figure 9 , when the temperature drops below -33 °C, the support layer 30 transforms into powdered gray tin, and the tin powder is easily separated from the chip and the first redistribution structure, so that the support layer 30 can be separated from the chip and the first redistribution structure.

[0115] Through step 140, the structure as shown inFigure 10 The fifth intermediate structure shown. Refer to Figure 10 , the entire support layer 30 is removed.

[0116] In step 150, a molding compound layer is formed, and the molding compound layer encapsulates the chip and the first redistribution structure.

[0117] Through step 150, the sixth intermediate structure as shown in Figure 11 can be obtained. Refer to Figure 11 , the back surface and side surfaces of the chip 10 are covered by the molding compound layer 50, the gap between the front surface of the chip and the support plate 22 is filled with the molding compound layer, and the surface of the first conductive trace 41 of the first redistribution structure facing away from the chip 10 is not covered by the molding compound layer 50.

[0118] In one embodiment, the molding compound layer 50 can be a polymer, resin, resin composite material, or polymer composite material. For example, the molding compound layer 50 can be a resin with fillers, where the fillers are inorganic particles. The molding compound layer 50 can be formed by laminating an epoxy resin film, or can also be formed by injection molding, compression molding, or transfer molding of an epoxy resin compound, etc.

[0119] After step 150, the semiconductor packaging method further includes: removing the support plate. By removing the support plate 22, the semiconductor packaging structure as shown in Figure 12 can be obtained. Refer to Figure 12 , the side of the first redistribution structure facing away from the chip exposes the molding compound layer, that is, the surface of the first conductive trace 41 of the first redistribution structure facing away from the chip 10 exposes the molding compound layer 50.

[0120] Next, the steps of another semiconductor packaging method provided by the embodiments of the present application will be introduced in detail.

[0121] In step 110, the chip is mounted on a carrier, the chip has a front surface, the front surface of the chip faces away from the carrier, and a plurality of pads are provided on the front surface of the chip.

[0122] In one embodiment, the first chip can be prepared through the following process:

[0123] First, a silicon wafer is provided, and the silicon wafer has a specific function. The silicon wafer has an active surface, and pads are provided on the active surface of the silicon wafer. The pads are used for electrical connection with external components.

[0124] Subsequently, the active surface of the silicon wafer is subjected to plasma treatment. By subjecting the active surface of the silicon wafer to plasma treatment, the surface energy of the active surface of the silicon wafer can be increased, so that the active surface of the silicon wafer is more firmly bonded to the subsequent formed protective layer.

[0125] Subsequently, an insulating material is coated on the active surface of the silicon wafer.

[0126] Subsequently, the insulating material is cured to form a protective layer. Through this step, a structure as shown in Figure 2 can be obtained. Refer to Figure 2 . The protective layer 12 covers the active surface of the silicon wafer 11. The protective layer 12 is one or more layers of insulating material, and the material of the protective layer 12 can be a plastic film, PI (polyimide), PBO (polyphenylene benzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties. The protective layer 12 can be formed on the active surface of the silicon wafer 11 by means of lamination, spin coating, printing, molding, or other suitable methods.

[0127] Subsequently, an opening for exposing the bonding pad is formed in the protective layer. Through this step, a structure as shown in Figure 3 can be obtained. The opening 121 can be formed by means of laser drilling.

[0128] Subsequently, the protective layer is subjected to plasma treatment. Through this step, the residual insulating material in the opening 121 can be removed, and the surface energy of the side of the protective layer 12 facing away from the silicon wafer 11 can be increased, thereby increasing the lamination adhesion between the protective layer 12 and the subsequently formed metal layer.

[0129] Subsequently, a metal layer 13 is formed on the side of the protective layer 12 facing away from the silicon wafer 11, and a metal layer is formed on the side of the silicon wafer 11 facing away from the protective layer 12. Through this step, a structure as shown in Figure 13 can be obtained. Refer to Figure 13 . The metal layer 13 covers the side surface and the bottom surface of the opening 121, and the metal layer 14 covers the back surface of the silicon wafer 11. The metal layer 13 and the metal layer 14 can be formed by a sputtering process.

[0130] Subsequently, the silicon wafer 11 is cut. The silicon wafer 11 can be cut along the position of the dotted line shown in Figure 13 . The silicon wafer 11 can be cut by means of mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer 11, a grinding device can be used to grind the back surface of the silicon wafer opposite to the active surface so that the thickness of the silicon wafer 11 is a specified thickness. Through this step, the chip 10 can be obtained.

[0131] In some embodiments, the chip 10 may not include the metal layer 13 and the metal layer 14, and the metal layer 13 and the metal layer 14 may also be formed in subsequent process steps.

[0132] In one embodiment, before the step 120 of forming the support layer on the carrier, the semiconductor packaging method further includes: disposing a conductive structure on the carrier.

[0133] In some embodiments, the conductive structure is pre-prepared. The step of disposing the conductive structure on the carrier includes: mounting the conductive structure on the carrier. Since the conductive structure is pre-prepared, the time for forming the conductive structure can be saved, and the process duration of the semiconductor packaging method can be shortened.

[0134] In one embodiment, the chip 10 can be mounted on the carrier first, and then the conductive structure can be mounted on the carrier; or the conductive structure can be mounted on the carrier first, and then the chip 10 can be mounted on the carrier; or the chip 10 and the conductive structure can be mounted on the carrier simultaneously.

[0135] After mounting the chip 10 and the conductive structure on the carrier, the seventh intermediate structure as shown in Figure 14 can be obtained. Refer to Figure 14 , the number of the conductive structures 61 can be multiple, and the conductive structure 61 can be disposed on the peripheral side of each chip. The multiple conductive structures 61 can belong to the same lead frame, and the lead frame can further include a frame body, and the multiple conductive structures 61 are respectively connected to the frame body. Thus, the multiple conductive structures 61 are of an integral structure, which can avoid relative movement of the multiple conductive structures 61 during mounting and is more convenient for mounting.

[0136] Figure 14 In the embodiment shown in

[0137] , multiple chips 10 are mounted on the carrier 20. In other embodiments, the number of the chips 10 mounted on the carrier 20 can be one. The back surface of the chip 10 can be adhered to the carrier 20 through the bonding layer 21.

[0138] In step 120, a support layer is formed on the carrier, and the support layer encapsulates the side surface of the chip, and the front surface of the chip is exposed.

[0139] Through step 120, the eighth intermediate structure as shown in Figure 15 can be obtained. Refer to Figure 15 , the surface of the support layer 30 facing away from the carrier 20 and the surface of the metal layer 13 facing away from the carrier 20 can be flush. The gaps between the chip 10 and the conductive structure 61 and the gaps between adjacent conductive structures 61 are filled with the support layer 30.

[0140] In one embodiment, the material of the support layer 30 is a metal or an insulating material. Thus, the material of the support layer 30 is easy to obtain.

[0141] In one embodiment, the material of the support layer 30 is metallic tin. The step 120 of forming the support layer on the carrier may include the process:

[0142] Tin powder is laid on the carrier plate, and the tin powder is heated. After the tin powder is melted, it is bonded together to obtain the support layer.

[0143] In this step, tin powder can be laid on the peripheral side of the chip 10, and the amount of tin powder laid can be determined according to the volume of the support layer 30 to be formed later. The support layer 30 can be obtained by heating the tin powder to melt it and cooling it. The formation of the support layer 30 is relatively easy to operate.

[0144] In one embodiment, after step 120, the semiconductor packaging method further includes: cleaning the surface of the seventh intermediate structure to remove impurities on the surface of the seventh intermediate structure. The impurities on the surface of the seventh intermediate structure can be removed by water washing or acid washing.

[0145] In step 130, a first rewiring structure is formed on a side of the support layer facing away from the carrier, and the first rewiring structure is electrically connected to the bonding pad of the chip.

[0146] Through step 130, the following can be obtained: Figure 16 The ninth intermediate structure shown. Figure 16 The first redistribution structure includes a first redistribution layer 40 , the first redistribution layer 40 includes a plurality of first conductive traces 41 , and the first conductive traces 41 are electrically connected to the pads of the chip 10 .

[0147] In one embodiment, the step 130 of forming a first rewiring structure on a side of the support layer facing away from the carrier includes the following process:

[0148] First, a photosensitive material is coated on a side of the third intermediate structure that is away from the carrier. The photosensitive material may cover the side of the third intermediate structure that is away from the carrier.

[0149] In some embodiments, when the chip 10 does not include the metal layer 13 , the metal layer 13 may be formed first before coating the photosensitive material.

[0150] Then, the photosensitive material is baked to solidify the photosensitive material to form a photosensitive layer.

[0151] Then, the photosensitive layer is patterned to remove the photosensitive layer at the position where the first rewiring structure is to be formed. The photosensitive layer can be patterned by using an exposure and development process.

[0152] Then, the photosensitive layer is subjected to plasma treatment, through which the residual photosensitive material at the position where the first redistribution structure is to be formed can be removed.

[0153] Subsequently, a conductive layer is formed in the area where the metal layer is not blocked by the photosensitive layer. The conductive layer can be formed by electroplating. During electroplating, the metal layer 13 serves as a seed layer. When the material of the support layer 30 is metal, the support layer 30 electrically connects the metal layers 13 on adjacent chips 10.

[0154] Subsequently, the photosensitive layer is peeled off.

[0155] Subsequently, the metal layer is etched to etch away the area where the metal layer is not blocked by the conductive layer, forming a first conductive trace 41. The first conductive trace 41 includes the conductive layer and the metal layer.

[0156] In step 160, the carrier plate is peeled off, and the back surface of the chip is exposed; a second redistribution structure is formed on the back surface of the chip, and the second redistribution structure is electrically connected to the conductive structure.

[0157] In one embodiment, step 161 can be completed through the following process:

[0158] First, after the carrier plate is peeled off, the obtained structure is mounted on the carrier plate 20.

[0159] Through this step, the tenth intermediate structure as shown in Figure 17 can be obtained. Refer to Figure 17 . The first conductive trace 41 of the first redistribution structure faces the carrier plate 20, and the metal layer 14 faces away from the carrier plate 20.

[0160] Subsequently, a second redistribution structure is formed on the back surface of the chip, and the second redistribution structure is electrically connected to the conductive structure.

[0161] Through this step, the eleventh intermediate structure as shown in Figure 18 can be obtained. Refer to Figure 18 . The second redistribution structure includes a second conductive trace 62, and the second conductive trace 62 is electrically connected to the pad on the front surface of the chip through the conductive structure 61 and the first conductive trace 41, leading out the pad on the front surface of the chip.

[0162] In some embodiments, the step of forming the second redistribution structure on the back surface of the chip can be completed through the following process:

[0163] First, a photosensitive material is coated on the side of the tenth intermediate structure facing away from the carrier plate, and the photosensitive material can cover the side of the third intermediate structure facing away from the carrier plate.

[0164] In some embodiments, when the chip 10 does not include the metal layer 14, the metal layer 14 can be first formed before coating the photosensitive material, and the photosensitive material is formed on the side of the metal layer 14 facing away from the chip.

[0165] Subsequently, the photosensitive material is baked to cure the photosensitive material to form a photosensitive layer.

[0166] Subsequently, the photosensitive layer is patterned to remove the photosensitive layer at the positions where the second redistribution structure needs to be formed. The photosensitive layer can be patterned by an exposure and development process.

[0167] Subsequently, the photosensitive layer is subjected to plasma treatment. Through this step, the remaining photosensitive layer at the positions where the second redistribution structure needs to be formed can be removed.

[0168] Subsequently, a conductive layer is formed in the regions where the metal layer 14 is not blocked by the photosensitive layer. The conductive layer can be formed by an electroplating process. During electroplating, the metal layer 14 serves as a seed layer, and the support layer electrically connects the metal layers 14 on adjacent chips 10.

[0169] Subsequently, the photosensitive layer is peeled off.

[0170] Subsequently, the metal layer 14 is etched to etch away the regions of the metal layer 14 that are not blocked by the conductive layer, forming the second conductive traces 62. The second conductive traces 62 include the conductive layer and the metal layer.

[0171] In step 140, the support layer is removed.

[0172] In one embodiment, before step 140, the semiconductor packaging method further includes: peeling off the carrier plate and mounting the obtained structure on a support plate.

[0173] Through this step, the twelfth intermediate structure as shown in Figure 19 can be obtained. As shown in Figure 19 , the second conductive traces 62 of the second redistribution structure face the support plate 24, and the second conductive traces 62 are mounted on the support plate 24 through the bonding layer 25.

[0174] Removing the carrier plate before removing the support layer and mounting the obtained structure on the support plate 24 can avoid relative movement of different structures after removing the support layer, which may affect the yield of the product, compared with the solution of mounting the obtained structure on the support plate 24 after removing the support layer.

[0175] In one embodiment, the material of the support layer is metallic tin. The step 140 of removing the support layer may include the following process:

[0176] Heating the support layer to melt the support layer and separating the melted support layer from the chip and the first redistribution structure. By heating the twelfth intermediate structure as shown in Figure 19 , after the temperature of the fourth intermediate structure reaches the melting point of tin, 232 °C, the support layer 30 melts and separates from other structures including the chip and the first redistribution structure.

[0177] In another embodiment, the material of the support layer is metallic tin. The step 140 of removing the support layer may include the following process:

[0178] Rapidly cool the support layer to transform the support layer into tin powder, and separate the tin powder from the support layer, the chip and the first redistribution structure. By Figure 19 performing a rapid cooling process on the twelfth intermediate structure shown, when the temperature drops below -33 °C, the support layer 30 transforms into powdery gray tin, and the tin powder is easily separated from the chip and the first redistribution structure.

[0179] Through step 140, the thirteenth intermediate structure shown in Figure 20 can be obtained. Refer to Figure 20 . The support layer 30 is completely removed.

[0180] In step 150, a molding compound layer is formed, and the molding compound layer encapsulates the chip and the first redistribution structure.

[0181] Through step 150, the fourteenth intermediate structure shown in Figure 21 can be obtained. Refer to Figure 21 . The side surfaces of the chip 10 and the first redistribution structure 40 are coated with the molding compound layer 50, the side surface of the conductive structure 61 is encapsulated by the molding compound layer 50, and the surface of the second conductive trace 62 of the second redistribution structure facing away from the chip 10 is not covered by the molding compound layer 50.

[0182] In one embodiment, the molding compound layer 50 can be a polymer, a resin, a resin composite material, or a polymer composite material. For example, the molding compound layer 50 can be a resin with fillers, where the fillers are inorganic particles. The molding compound layer 50 can be formed by laminating an epoxy resin film, or can also be formed by injection molding, compression molding, or transfer molding of an epoxy resin compound, etc.

[0183] After step 150, the semiconductor packaging method further includes: removing the support plate. By removing the support plate 24, the semiconductor packaging structure shown in Figure 22 can be obtained. Refer to Figure 22 . The side of the second redistribution structure facing away from the chip exposes the molding compound layer, that is, the surface of the second conductive trace 62 of the second redistribution structure facing away from the chip 10 exposes the molding compound layer 50. The second conductive trace 62 can be used to connect to external components such as a circuit board.

[0184] Next, the steps of another semiconductor packaging method provided by the embodiments of the present application will be introduced in detail.

[0185] In step 110, the chip is mounted on a carrier plate. The chip has a front side, the front side of the chip faces away from the carrier plate, and a plurality of pads are provided on the front side of the chip.

[0186] In one embodiment, the first chip can be prepared through the following process:

[0187] First, a silicon wafer is provided, and the silicon wafer has a specific function. The silicon wafer has an active surface, and bonding pads are provided on the active surface of the silicon wafer. The bonding pads are used for electrical connection with external components.

[0188] Subsequently, the active surface of the silicon wafer is subjected to plasma treatment. By subjecting the active surface of the silicon wafer to plasma treatment, the surface energy of the active surface of the silicon wafer can be increased, so that the active surface of the silicon wafer is more firmly bonded to the subsequently formed protective layer.

[0189] Subsequently, an insulating material is coated on the active surface of the silicon wafer.

[0190] Subsequently, the insulating material is cured to form a protective layer. Through this step, the structure as shown in Figure 2 can be obtained. As shown in Figure 2 , the protective layer 12 covers the active surface of the silicon wafer 11. The protective layer 12 is one or more layers of insulating material, and the material of the protective layer 12 can be a plastic film, PI (polyimide), PBO (polyphenylene benzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties. The protective layer 12 can be formed on the active surface of the silicon wafer 11 by means of lamination, spin coating, printing, molding, or other suitable methods.

[0191] Subsequently, an opening exposing the bonding pads is formed in the protective layer. Through this step, the structure as shown in Figure 3 can be obtained. The opening 121 can be formed by means of laser drilling.

[0192] Subsequently, the protective layer is subjected to plasma treatment. Through this step, the residual insulating material in the opening 121 can be removed, and the surface energy on the side of the protective layer 12 facing away from the silicon wafer 11 can be increased, thereby increasing the bonding property between the protective layer 12 and the subsequently formed metal layer stack.

[0193] Subsequently, a metal layer is formed on the side of the protective layer 12 facing away from the silicon wafer 11. Through this step, the structure as shown in Figure 4 can be obtained. Referring to Figure 4 , the metal layer 13 covers the side surface and the bottom surface of the opening 121. The metal layer 13 can be formed by a sputtering process.

[0194] Subsequently, the silicon wafer 11 is cut. The silicon wafer 11 can be cut along the position of the dashed line shown in Figure 4 . The silicon wafer 11 can be cut by means of mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer 11, the back surface of the silicon wafer opposite to the active surface can be ground by means of a grinding device so that the thickness of the silicon wafer 11 is a specified thickness. Through this step, the structure as shown inFigure 5 The chip 10 shown

[0195] In some embodiments, the chip 10 may not include the metal layer 13, and the metal layer 13 may also be formed in subsequent process steps.

[0196] Through step 110, the first intermediate structure as shown Figure 6 can be obtained. Figure 6 In the embodiment shown, a plurality of chips 10 are mounted on the carrier 20. In other embodiments, the number of chips 10 mounted on the carrier 20 may be one. The back surface of the chip 10 may be adhered to the carrier 20 through the adhesive layer 21.

[0197] In one embodiment, the shape of the carrier 20 may be circular, rectangular or other shapes. The carrier 20 may be a small-sized wafer substrate, or a larger-sized carrier, such as a stainless steel substrate, a polymer substrate, etc.

[0198] In step 120, a support layer is formed on the carrier, and the support layer encapsulates the side surfaces of the chips, and the front surfaces of the chips are exposed.

[0199] Through step 120, the second intermediate structure as shown Figure 7 can be obtained. Refer to Figure 7 , the surface of the support layer 30 facing away from the carrier 20 may be flush with the surface of the metal layer 13 facing away from the carrier 20. The gaps between adjacent chips 10 are filled with the support layer 30.

[0200] In one embodiment, the material of the support layer 30 is a metal or an insulating material. In this way, the material of the support layer 30 is easy to obtain.

[0201] In one embodiment, the material of the support layer 30 is metallic tin. The step 120 of forming the support layer on the carrier may include the process of

[0202] laying tin powder on the carrier, heating the tin powder, and the tin powder is bonded together after melting to obtain the support layer.

[0203] In this step, tin powder may be laid on the peripheral side of the chip 10, and the amount of tin powder laid can be determined according to the volume of the support layer 30 to be formed subsequently. By heating the tin powder to melt it, the support layer 30 can be obtained after cooling, and the formation of the support layer 30 is relatively easy to operate.

[0204] In one embodiment, after step 120, the semiconductor packaging method further includes: cleaning the surface of the second intermediate structure to remove impurities on the surface of the second intermediate structure. The impurities on the surface of the second intermediate structure can be removed by water washing or acid washing.

[0205] In step 130, a first redistribution structure is formed on the side of the support layer facing away from the carrier substrate, and the first redistribution structure is electrically connected to the pads of the chip.

[0206] Through step 130, the fifteenth intermediate structure as shown in Figure 23 can be obtained. Refer to Figure 23 . The first redistribution structure includes a first redistribution layer. The first redistribution layer includes a plurality of first conductive traces 41 and conductive bumps 71 located on the side of each first conductive trace 41 facing away from the chip. The first conductive traces 41 are electrically connected to the pads of the chip 10.

[0207] In one embodiment, step 130 of forming the first redistribution structure on the side of the support layer facing away from the carrier substrate includes the following process:

[0208] First, a photosensitive material is coated on the side of the third intermediate structure facing away from the carrier substrate, and the photosensitive material can cover the side of the third intermediate structure facing away from the carrier substrate.

[0209] In some embodiments, when the chip 10 does not include the metal layer 13, the metal layer 13 can be first formed before coating the photosensitive material.

[0210] Subsequently, the photosensitive material is baked to cure the photosensitive material to form a photosensitive layer.

[0211] Subsequently, the photosensitive layer is patterned to remove the photosensitive layer at the position where the first redistribution structure needs to be formed. The photosensitive layer can be patterned by an exposure and development process.

[0212] Subsequently, the photosensitive layer is subjected to plasma treatment. Through this step, the residual photosensitive material at the position where the first redistribution structure needs to be formed can be removed.

[0213] Subsequently, a conductive layer is formed in the area where the metal layer is not blocked by the photosensitive layer. The conductive layer can be formed by an electroplating process. When electroplating, the metal layer 13 serves as a seed layer, and the support layer electrically connects the metal layers 13 on adjacent chips 10.

[0214] Subsequently, the photosensitive layer is peeled off.

[0215] Subsequently, the metal layer is etched to etch away the area of the metal layer that is not blocked by the conductive layer, forming the first conductive traces 41. The first conductive traces 41 include the conductive layer and the metal layer.

[0216] Subsequently, conductive bumps 71 are formed on the side of the first conductive traces 41 facing away from the chip.

[0217] In one embodiment, after step 130, the semiconductor packaging method further includes: forming a support material layer 81, the support material layer 81 encapsulating the first redistribution structure, and a surface of the first redistribution structure facing away from the chip exposing the support material layer 81. That is, a surface of the conductive bump 71 facing away from the chip 10 exposes the support material layer 81.

[0218] In step 171, at least one of the following steps is performed:

[0219] Forming a third redistribution structure on a side of the exposed redistribution structure facing away from the chip, the third redistribution structure being electrically connected to the first redistribution structure;

[0220] Forming a support material layer, the support material layer encapsulating the third redistribution structure, and a side of the third redistribution structure facing away from the chip exposing the support material layer;

[0221] Before forming the encapsulation layer, the semiconductor packaging method further includes: removing the support material layer;

[0222] After forming the encapsulation layer, a side of the third redistribution structure that is farthest from the chip exposes the encapsulation layer.

[0223] Wherein, the exposed redistribution structure may refer to partial exposure or complete exposure of the redistribution structure. For example, it may be that a surface of the redistribution structure facing away from the chip is exposed.

[0224] In one embodiment, the third redistribution structure includes a third conductive trace and conductive pillars located on a side of the third conductive trace facing away from the chip.

[0225] In one embodiment, the above steps may be repeatedly executed twice in step 171. In other embodiments, the above steps may be executed once or more than twice in step 171. When the above steps are repeatedly executed twice in step 171, step 171 specifically includes the following process:

[0226] First, forming a third redistribution structure on a side of the first redistribution structure facing away from the chip.

[0227] Through this step, the sixteenth intermediate structure as shown in Figure 24 can be obtained. As shown in Figure 24 , the third redistribution structure includes a third conductive trace 72 and conductive bumps 73 located on a side of the third conductive trace 72 facing away from the chip.

[0228] Subsequently, forming a support material layer, the support material layer encapsulating the third redistribution structure, and a side of the third redistribution structure facing away from the chip exposing the support material layer.

[0229] Through this step, the seventeenth intermediate structure as shown in Figure 25 can be obtained. As shown in Figure 25 , the support material layer 82 encapsulates the third conductive trace 72 and the conductive bump 73, and one side of the conductive bump 73 facing away from the chip exposes the support material layer 82.

[0230] Subsequently, a third redistribution structure is formed on the side of the third redistribution structure facing away from the chip.

[0231] Through this step, the eighteenth intermediate structure as shown in Figure 26 can be obtained. As shown in Figure 26 , the third redistribution structure formed in this step includes a fourth conductive trace 74 and a conductive bump 75 located on the side of the fourth conductive trace 74 facing away from the chip.

[0232] Subsequently, a support material layer is formed, and the support material layer encapsulates the exposed third redistribution structure, and one side of the third redistribution structure facing away from the chip exposes the support material layer.

[0233] Through this step, the nineteenth intermediate structure as shown in Figure 27 can be obtained. As shown in Figure 27 , the support material layer 83 encapsulates the fourth conductive trace 74 and the conductive bump 75, and one side of the conductive bump 75 facing away from the chip exposes the support material layer 83.

[0234] In step 140, the support layer is removed.

[0235] In one embodiment, before step 140, the semiconductor packaging method further includes: peeling the carrier plate and mounting the obtained structure on a support plate.

[0236] Through this step, the twentieth intermediate structure as shown in Figure 28 can be obtained. As shown in Figure 28 , the conductive bump 75 faces the carrier plate, and the conductive bump 75 is mounted on the support plate 26 through the bonding layer 27.

[0237] Removing the carrier plate before removing the support layer and mounting the obtained structure on the support plate 26 can avoid relative movement of different structures after removing the support layer, which may affect the yield of the product, compared with the solution of mounting the obtained structure on the support plate 26 after removing the support layer.

[0238] In one embodiment, the material of the support layer is metallic tin. The step 140 of removing the support layer may include the following process:

[0239] Heating the support layer to melt the support layer and separating the melted support layer from the chip and the first redistribution structure. By Figure 28Heat the twentieth intermediate structure shown. After the temperature of the twentieth intermediate structure reaches the melting point of tin, 232 °C, the support layer 30 melts and separates from other structures including the chip and the first redistribution structure.

[0240] In another embodiment, the material of the support layer is metallic tin. The step 140 of removing the support layer may include the following process:

[0241] Rapidly cool the support layer so that the support layer turns into tin powder, and separate the tin powder from the chip and the first redistribution structure. By Figure 28 performing a rapid cooling process on the twentieth intermediate structure shown, when the temperature drops below -33 °C, the support layer 30 turns into powdery gray tin, and the tin powder is easy to separate from the chip and the first redistribution structure.

[0242] In one embodiment, the material of the support material layer is the same as that of the support layer; the semiconductor packaging method further includes: removing the support material layer, and the step of removing the support layer is performed simultaneously with the step of removing the support material layer.

[0243] By setting the material of the support material layer to be the same as that of the support layer, the support material layer and the support layer can be removed simultaneously through one process step, which helps to simplify the semiconductor packaging process.

[0244] After removing the support layer and the support material layer, the twenty-first intermediate structure as shown in Figure 29 can be obtained. Refer to Figure 29 . The support layer 30, the support material layer 81, the support material layer 82, and the support material layer 83 are all removed.

[0245] In step 150, a molding compound layer is formed, and the molding compound layer encapsulates the chip, the first redistribution structure, and the third redistribution structure.

[0246] Through step 150, the twenty-second intermediate structure as shown in Figure 30 can be obtained. Refer to Figure 30 . The chip 10, the first redistribution structure, and the third redistribution structure are encapsulated by the molding compound layer 50, and the surface of the third redistribution structure that is farthest from the chip and faces away from the chip exposes the molding compound layer 50, that is, the surface of the conductive bump 75 that faces away from the chip exposes. The gap between the front surface of the chip and the support plate 22 is filled with the molding compound.

[0247] In one embodiment, the molding compound layer 50 can be a polymer, a resin, a resin composite material, or a polymer composite material. For example, the molding compound layer 50 can be a resin with fillers, where the fillers are inorganic particles. The molding compound layer 50 can be formed by laminating an epoxy resin film, or can also be formed by injection molding, compression molding, or transfer molding of an epoxy resin compound, etc.

[0248] After step 150, the semiconductor packaging method further includes: removing the support plate. By removing the support plate 22, the semiconductor packaging structure as shown in Figure 31 can be obtained. Refer to Figure 31 . On the side of the redistribution structure with the largest distance from the chip, the molding compound layer is exposed on the side facing away from the chip, that is, the surface of the conductive bump 75 facing away from the chip 10 is exposed on the molding compound layer 50. The side of the redistribution structure with the largest distance from the chip facing away from the chip is used to connect to other structures such as a circuit board.

[0249] In one embodiment, after obtaining the semiconductor packaging structure as shown in Figure 12 , Figure 22 and Figure 31 , the semiconductor packaging method further includes:

[0250] Cutting the semiconductor packaging structure to obtain a plurality of sub-packaging structures, and each sub-packaging structure includes one or more chips.

[0251] In this application, the device embodiments and the method embodiments can complement each other without conflict. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this application. Those of ordinary skill in the art can understand and implement it without creative work.

[0252] The above are only the preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the scope of protection of this application.

Claims

1. A semiconductor packaging method, characterized in that, The semiconductor packaging method includes: Mounting a chip on a carrier substrate, the chip having a front side, the front side of the chip facing away from the carrier substrate, and a plurality of pads being provided on the front side of the chip; Forming a support layer on the carrier substrate, the support layer encapsulating the side surfaces of the chip, and the front side of the chip being exposed; Forming a first redistribution structure on a side of the support layer facing away from the carrier substrate, the first redistribution structure being electrically connected to the pads of the chip; Removing the support layer; Forming a molding layer, the molding layer encapsulating the chip and the first redistribution structure.

2. The semiconductor packaging method according to claim 1, wherein The material of the support layer is a metal or an insulating material.

3. The semiconductor packaging method according to claim 1, wherein The material of the support layer is metallic tin; The forming the support layer on the carrier substrate includes: Laying tin powder on the carrier substrate, heating the tin powder, and the tin powder bonding together after melting to obtain the support layer.

4. The semiconductor packaging method according to claim 1, wherein The material of the support layer is metallic tin; The removing the support layer includes: Heating the support layer to melt the support layer, and separating the melted support layer from the chip and the first redistribution structure; Alternatively, rapidly cooling the support layer to transform the support layer into tin powder, and separating the tin powder from the chip and the first redistribution structure.

5. The semiconductor packaging method according to claim 1, wherein Before removing the support layer, the semiconductor packaging method further includes: Peeling off the carrier substrate and mounting the obtained structure on a support board.

6. The semiconductor packaging method according to claim 1, wherein, A side of the first redistribution structure facing away from the chip exposes the molding layer.

7. The semiconductor packaging method according to claim 1, wherein, Before forming the support layer on the carrier substrate, the semiconductor packaging method further includes: disposing a conductive structure on the carrier substrate; a surface of the conductive structure facing away from the carrier substrate exposes the support layer, and the conductive structure is electrically connected to the first redistribution structure; After forming the first redistribution structure on a side of the support layer facing away from the carrier substrate and before removing the support layer, the semiconductor packaging method further includes: peeling off the carrier substrate, and the back side of the chip is exposed; forming a second redistribution structure on the back side of the chip, the second redistribution structure being electrically connected to the conductive structure; After forming the molding layer, a surface of the second redistribution structure facing away from the chip exposes the molding layer.

8. The semiconductor packaging method according to claim 7, wherein The conductive structure is pre-prepared, and the disposing the conductive structure on the carrier substrate includes: Mounting the conductive structure on the carrier substrate.

9. The semiconductor packaging method according to claim 1, wherein Before removing the support layer, the semiconductor packaging method further includes: performing at least once the following steps: Forming a third redistribution structure on a side of the exposed redistribution structure facing away from the chip, the third redistribution structure being electrically connected to the first redistribution structure; Forming a support material layer, the support material layer encapsulating the third redistribution structure, and a side of the third redistribution structure facing away from the chip exposes the support material layer; Before forming the molding layer, the semiconductor packaging method further includes: removing the support material layer; After forming the molding layer, a side of the third redistribution structure having the largest distance from the chip facing away from the chip exposes the molding layer.

10. The semiconductor packaging method according to claim 9, wherein, The support material layer has the same material as the support layer; The step of removing the support layer is performed simultaneously with the step of removing the support material layer.

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