Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, including a first region for forming a first device and a second region for forming a second device, a channel length of the first device being greater than a channel length of the second device; forming a polysilicon gate layer on the substrate of the first region; forming, on the substrate of the second region, a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer stacked in sequence from bottom to top; forming an interlayer dielectric layer on the substrate at sides of the polysilicon gate layer and the dummy gate layer, the interlayer dielectric layer exposing a top of the dummy gate layer; removing the dummy gate layer, and forming a metal gate layer at a position of the dummy gate layer. The application does not form a metal barrier layer below the polysilicon gate layer, which is advantageous to enable the threshold voltage of the first device to meet the performance requirement of the device, thereby improving the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the existing semiconductor device, different working voltage devices are usually formed on the substrate, such as low voltage (LV) device, high voltage (HV) device and medium voltage (MV) device.

[0003] With the development of semiconductor manufacturing technology, the critical dimension of the semiconductor device is continuously reduced, which leads to more and more serious gate depletion effect. In order to better overcome the problem of gate depletion effect, the high-k last metal gate last process and the replacement gate process have become the commonly used processes.

[0004] Among them, compared with the low voltage device, the working voltage of the high voltage device and the medium voltage device is higher, and the size of the high voltage device and the medium voltage device is correspondingly larger, so the high voltage device and the medium voltage device still use polysilicon gate, and the low voltage device uses metal gate. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which improves the performance of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate comprising a first region for forming a first device and a second region for forming a second device, the channel length of the first device being greater than the channel length of the second device; a polysilicon gate layer located on the substrate of the first region; a high-k gate dielectric layer located on the substrate of the second region; a metal barrier layer located on the high-k gate dielectric layer; a metal gate layer located on the metal barrier layer; and an interlayer dielectric layer located on the substrate on the side of the polysilicon gate layer and the metal gate layer.

[0007] Correspondingly, embodiments of the present application also provide a forming method of a semiconductor structure, comprising: providing a substrate comprising a first region for forming a first device and a second region for forming a second device, the channel length of the first device being greater than the channel length of the second device; forming a polysilicon gate layer on the substrate of the first region; forming a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer stacked in turn from bottom to top on the substrate of the second region; forming an interlayer dielectric layer on the substrate on the side of the polysilicon gate layer and the dummy gate layer, the interlayer dielectric layer exposing the top of the dummy gate layer; after forming the interlayer dielectric layer, removing the dummy gate layer and forming a metal gate layer at the position of the dummy gate layer.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present application, the base of the first region has a polysilicon gate layer, the base of the second region has a high-k gate dielectric layer and a metal barrier layer located on the high-k gate dielectric layer, and a metal gate layer is located on the metal barrier layer; wherein the first region is used for forming a first device, the second region is used for forming a second device, the channel length of the first device is greater than the channel length of the second device, and the work function of the metal barrier layer is greater than that of polysilicon material, so that in the first region, the metal barrier layer is not formed under the polysilicon gate layer, thereby avoiding the problem that the threshold voltage of the first device becomes high due to the existence of the metal barrier layer in the case of using the polysilicon gate layer for the first device, and facilitating the threshold voltage of the first device to meet the performance requirement of the device, thereby improving the performance of the semiconductor structure.

[0010] In the forming method provided by the embodiment of the present application, a polysilicon gate layer is formed on the base of the first region, and a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer are sequentially stacked from bottom to top on the base of the second region; wherein the first region is used for forming a first device, the second region is used for forming a second device, the channel length of the first device is greater than the channel length of the second device, and the work function of the metal barrier layer is greater than that of polysilicon material, so that in the first region, the metal barrier layer is not formed under the polysilicon gate layer, thereby avoiding the problem that the threshold voltage of the first device becomes high due to the existence of the metal barrier layer in the case of using the polysilicon gate layer for the first device, and facilitating the threshold voltage of the first device to meet the performance requirement of the device, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1 to 4 is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure;

[0012] Figures 5 to 15 is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure. DETAILED DESCRIPTION

[0013] As known from the background, at present, high-voltage devices and medium-voltage devices use polysilicon gates, and low-voltage devices use metal gates. However, the performance of the semiconductor structure is poor at present.

[0014] Now, the reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a forming method of the semiconductor structure. Figures 1 to 4 is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure.

[0015] Referring to Figure 1 , a substrate 10 is provided, including a first region 10M for forming a first device and a second region 10L for forming a second device, a channel length of the first device being greater than a channel length of the second device.

[0016] Specifically, a working voltage of the first device is greater than a working voltage of the second device, the first device including one or both of a high-voltage device and a medium-voltage device, and the second device being a low-voltage device. Wherein, the working voltages of the low-voltage device, the medium-voltage device and the high-voltage device are sequentially increased.

[0017] Continuing to refer to Figure 1 , a gate oxide material layer 20 is formed on the surface of the substrate 10 in the first region 10M; a high-k gate dielectric material layer 21 covering the gate oxide material layer 20 and the substrate 10, a metal barrier material layer 22 covering the high-k gate dielectric material layer 21, and a polysilicon material layer 23 covering the metal barrier material layer 22 are formed.

[0018] It should be noted that according to process requirements, another gate oxide material layer (not shown in the figure) can also be formed on the surface of the substrate 10 in the second region 10L before the high-k gate dielectric material layer 21 is formed, and the thickness of the gate oxide material layer in the second region 10L is smaller than that of the gate oxide material layer 20 in the first region 10M.

[0019] Referring to Figure 2 , the gate oxide material layer 20, the high-k gate dielectric material layer 21, the metal barrier material layer 22 and the polysilicon material layer 23 are etched to form a gate oxide layer 33 on the substrate 10 in the first region 10M, a high-k gate dielectric layer 34 on the gate oxide layer 33 and on the substrate 10 in the second region 10L, a metal barrier layer 35 on the high-k gate dielectric layer 34, and a polysilicon gate layer 36 on the metal barrier layer 35.

[0020] In the first region 10M, the stacked gate oxide layer 33, high-k gate dielectric layer 34, metal barrier layer 35 and polysilicon gate layer 36 form a first gate structure 31.

[0021] It should be noted that when another gate oxide material layer is formed on the surface of the substrate 10 in the second region 10L, the gate oxide material layer in the second region 10L is also etched to form a gate oxide layer at the bottom of the high-k gate dielectric layer 34 in the second region 10L.

[0022] Referring to Figure 3An interlayer dielectric layer 40 is formed on the substrate 10 at the side of the polysilicon gate layer 36, which exposes the top of the polysilicon gate layer 36 of the second region 10L.

[0023] With reference to Figure 4 The polysilicon gate layer 36 of the second region 10L is removed, and a gate opening (not shown) exposing the metal barrier layer 35 is formed in the interlayer dielectric layer 40; and a metal gate layer 37 is formed in the gate opening.

[0024] In the second region 10L, the stacked high-k gate dielectric layer 34, metal barrier layer 35 and metal gate layer 37 constitute a second gate structure 32.

[0025] By forming the high-k gate dielectric layer 34 in the first region 10M and the second region 10L, and forming the polysilicon gate layer 36 in the first region 10M and the metal gate layer 37 in the second region 10L, the performance of the second device is maintained while the forming process of the first device still adopts the polysilicon gate technology, under the condition that the critical dimension of the semiconductor device is continuously reduced.

[0026] Moreover, in order to simplify the process flow, the high-k gate dielectric layer 34 and the metal barrier layer 35 are also formed in the first region 10M.

[0027] However, compared with the polysilicon material, the work function of the metal barrier layer 35 is larger, and therefore, in the first region 10M, the presence of the metal barrier layer 35 causes the threshold voltage of the first device to be higher, which makes it difficult to meet the performance requirement of the device, and further hinders the improvement of the performance of the semiconductor structure.

[0028] To solve the technical problem, an embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, including a first region for forming a first device and a second region for forming a second device, the channel length of the first device being larger than the channel length of the second device; forming a polysilicon gate layer on the substrate of the first region; forming, on the substrate of the second region, a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer stacked in turn from bottom to top; forming an interlayer dielectric layer on the substrate at the side of the polysilicon gate layer and the dummy gate layer, which exposes the top of the dummy gate layer; after forming the interlayer dielectric layer, removing the dummy gate layer, and forming a metal gate layer at the position of the dummy gate layer.

[0029] The forming method provided by the embodiment of the present application comprises the following steps: forming a polysilicon gate layer on a substrate in a first region, and forming, on a substrate in a second region, a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer which are stacked in sequence from bottom to top; wherein the first region is used for forming a first device, and the second region is used for forming a second device, the channel length of the first device is greater than the channel length of the second device, and the work function of the metal barrier layer is greater than that of the polysilicon material, so that, in the first region, the problem that the threshold voltage of the first device is increased due to the existence of the metal barrier layer can be avoided in the case that the first device adopts the polysilicon gate layer, and the threshold voltage of the first device can meet the performance requirement of the device, thereby improving the performance of the semiconductor structure.

[0030] In order to make the above object, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0031] Figures 5 to 15 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.

[0032] Reference Figure 5 A substrate 100 is provided, which comprises a first region 100M used for forming a first device and a second region 100L used for forming a second device, and the channel length of the first device is greater than the channel length of the second device.

[0033] The substrate 100 is used to provide a process platform for subsequent process procedures.

[0034] In the embodiment, the substrate 100 is taken as an example for forming a planar field effect transistor, and the substrate 100 is a planar substrate. In other embodiments, the substrate is used for forming a fin field effect transistor (FinFET), and accordingly, the substrate comprises a substrate and a fin portion protruding from the substrate.

[0035] In the embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates.

[0036] In the embodiment, the substrate is a P-type substrate (Psub), that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0037] In the embodiment, the substrate 100 includes a first region 100M for forming a first device and a second region 100L for forming a second device, the channel length of the first device is greater than the channel length of the second device.

[0038] As an example, the working voltage of the first device is greater than the working voltage of the second device, so that the channel length of the first device is greater than the channel length of the second device.

[0039] In the embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device, and the second device is a low-voltage device. The working voltage of the low-voltage device, the medium-voltage device and the high-voltage device increases in turn. As an example, the working voltage of the low-voltage device is less than 1V, the working voltage of the medium-voltage device is 1V to 10V, and the working voltage of the high-voltage device is greater than 10V.

[0040] It should be noted that when the first device includes a medium-voltage device and a high-voltage device, the first region 100M for forming the medium-voltage device and the first region 100M for forming the high-voltage device are isolated.

[0041] The first device can be an NMOS device or a PMOS device. Similarly, the second device can also be an NMOS device or a PMOS device.

[0042] As an example, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form first devices of different channel conduction types. For example, the first device formed in the first sub-region 100MN is an NMOS device, and the first device formed in the second sub-region 100MP is a PMOS device.

[0043] In the embodiment, taking the first region 100M for forming a medium-voltage device and the second region 100L for forming a low-voltage device as an example, a deep N-type well (DNW) region (not shown in the figure) is also formed in the substrate 100, a first well region (not marked) is formed in the deep N-type well region of the first region 100M, and a second well region (not marked) is formed in the deep N-type well region of the second region 100L.

[0044] The deep N-type well region is used to isolate the first well region from the P-type substrate and to isolate the second well region from the P-type substrate, thereby reducing the substrate coupling noise.

[0045] The type of doping ions in the first well region is opposite to the channel conduction type of the first device formed thereon.

[0046] When the first device is an NMOS device, the doping ions in the first well region are P-type ions, and when the first device is a PMOS device, the doping ions in the first well region are N-type ions. Similarly, the type of doping ions in the second well region is opposite to the channel conduction type of the second device formed thereon.

[0047] In other embodiments, when the first region is used to form a high-voltage device, a high-voltage well region is formed in the substrate, and correspondingly, no deep N-type well region is formed in the substrate. Similarly, the type of doping ions in the high-voltage well region is opposite to the channel conduction type of the first device formed thereon.

[0048] In this embodiment, an isolation structure 101 is also formed in the substrate 100.

[0049] Specifically, the isolation structure 101 is formed in the substrate 100 at the junction of the first region 100M and the second region 100L.

[0050] The first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and therefore, the isolation structure 101 is also formed in the substrate 100 at the junction of the first sub-region 100MN and the second sub-region 100MP.

[0051] The isolation structure 101 is used to achieve isolation between adjacent devices. In this embodiment, the isolation structure 101 is a shallow trench isolation (STI), so that the isolation structure 101 has a good isolation effect.

[0052] In this embodiment, the material of the isolation structure 101 is an insulating material, and the insulating material includes silicon oxide.

[0053] Continuing to refer to Figure 5 A gate oxide layer 210 is formed on the substrate 100 of the first region 100M.

[0054] Subsequently, a polysilicon gate layer is formed on the gate oxide layer 210 of the first region 100M, the polysilicon gate layer is used to control the opening or closing of the channel of the first device, the gate oxide layer 210 serves as the gate dielectric of the first device, and the gate oxide layer 210 is used to electrically isolate the polysilicon gate layer and the channel of the first device.

[0055] In this embodiment, the gate oxide layer 210 also extends to cover the substrate 100 of the second region 100L.

[0056] In this embodiment, the material of the gate oxide layer 210 is silicon oxide.

[0057] Continuing to refer to Figures 6 to 10A polysilicon gate layer 310 is formed on the substrate 100 in the first region 100M (e.g., ...). Figure 10 As shown), high-k gate dielectric layers 320 are formed on the substrate 100 of the second region 100L, stacked sequentially from bottom to top. Figure 10 As shown), metal barrier layer 330 (as shown) Figure 10 (as shown) and pseudo-gate layer 340.

[0058] The first region 100M is used to form the first device, and the second region 100L is used to form the second device. The channel length of the first device is greater than that of the second device. Compared with polysilicon, the work function of the metal barrier layer 330 is larger. Therefore, in the first region 100M, by not forming the metal barrier layer 330 below the polysilicon gate layer 310, the problem of the threshold voltage of the first device becoming higher due to the presence of the metal barrier layer 330 can be avoided when the first device uses the polysilicon gate layer 310. This is beneficial to ensure that the threshold voltage of the first device can meet the performance requirements of the device, thereby improving the performance of the semiconductor structure.

[0059] The following description, in conjunction with the accompanying drawings, details the formation of the polysilicon gate layer 310 and the high-k gate dielectric layer 320 (e.g., Figure 10 As shown), metal barrier layer 330 (as shown) Figure 10 The steps of (as shown) and pseudo-gate layer 340 are explained in detail.

[0060] refer to Figure 6 A polycrystalline silicon material layer 220 is formed on the substrate 100 in the first region 100M.

[0061] The polysilicon material layer 220 is used to prepare for the subsequent formation of a polysilicon gate layer on the substrate 100 in the first region 100M, thereby forming a polysilicon gate structure in the first region 100M.

[0062] In the fabrication process of forming a metal gate structure, a dummy gate layer is typically used to occupy the position of the metal gate layer. After forming the interlayer dielectric layer, the dummy gate layer is removed, and the metal gate layer is formed in the position of the dummy gate layer. The process of forming the metal gate layer includes a step of planarizing the metal gate material. The larger the size of the metal gate layer, the higher the probability of dishing at the top surface of the metal gate layer during the planarization process. Since the first region 100M is used to form the first device, and the channel length of the first device is longer, by using a polysilicon gate structure for the first device, the planarization step of the metal gate material is omitted in the first region 100M, thereby avoiding the problem of dishing at the top surface of the metal gate layer caused by its large size.

[0063] As an example, the polysilicon material layer 220 is formed by a furnace tube process or a chemical vapor deposition process.

[0064] Therefore, in the embodiment, the polysilicon material layer 220 also extends to cover the substrate 100 of the second region 100L.

[0065] Specifically, the polysilicon material layer 220 is formed on the gate oxide layer 210.

[0066] In the embodiment, the material of the polysilicon material layer 220 is polysilicon.

[0067] With reference to Figure 6 The forming method further includes: doping conductive ions 215 into the polysilicon material layer 220, and the conductive type of the conductive ions 215 is the same as the channel conductive type of the corresponding first device.

[0068] By doping the conductive ions 215 into the polysilicon material layer 220, the resistance of the polysilicon material layer 220 is reduced, and the gate resistance of the first device is reduced, and the contact resistance between the subsequently formed polysilicon gate layer and gate silicide layer is reduced. In the embodiment, the gate dielectric layer of the first device only includes the gate oxide layer 210, and therefore, by making the conductive type of the conductive ions 215 the same as the channel conductive type of the corresponding first device, the threshold voltage of the first device can be adjusted by adjusting the concentration of the conductive ions 215, which is beneficial to improving the performance of the semiconductor structure.

[0069] Specifically, the conductive ions 215 are doped into the polysilicon material layer 220 by ion implantation.

[0070] According to the channel conductive type of the first device, the conductive ions 215 can be N-type ions or P-type ions. Specifically, the P-type ions include B ions, Ga ions or In ions, and the N-type ions include P ions, As ions or Sb ions.

[0071] In the embodiment, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form first devices with different channel conductive types. Therefore, in the first region 100M, the conductive ions 215 in the polysilicon material layer 220 of the first sub-region 100MN and the second sub-region 100MP have different conductive types.

[0072] Therefore, in the embodiment, the photo mask is used to dope the polycrystalline silicon material layer 220 in the first sub-region 100MN and the second sub-region 100MP with conductive ions 215 of different conductive types.

[0073] Specifically, the first device formed in the first sub-region 100MN is an NMOS device, and the first device formed in the second sub-region 100MP is a PMOS device. Therefore, the conductive ions 215 doped in the polycrystalline silicon material layer 220 in the first sub-region 100MN are N-type ions, and the conductive ions 215 doped in the polycrystalline silicon material layer 220 in the second sub-region 100MP are P-type ions.

[0074] In the embodiment, the conductive ions 215 are doped in the polycrystalline silicon material layer 220 in each region before the polycrystalline silicon material layer 220 is patterned.

[0075] Specifically, the conductive ions 215 are also doped in the polycrystalline silicon material layer 220 in the second region 100L.

[0076] In the process of doping the conductive ions 215 in the polycrystalline silicon material layer 220, the polycrystalline silicon material layer 220 in the second region 100L can protect the substrate 100 and reduce the influence of the conductive ions 215 on the substrate 100 in the second region 100L. Since the polycrystalline silicon material layer 220 in the second region 100L will be removed later, the influence of the conductive ions 215 in the polycrystalline silicon material layer 220 in the second region 100L on the second device is very small.

[0077] For example, the second region 100L and the second sub-region 100MP are adjacent, so that the conductive ions 215 are doped in the polycrystalline silicon material layer 220 in the second region 100L and the second sub-region 100MP in the same step; or when the second device is an NMOS device, the conductive ions 215 are doped in the polycrystalline silicon material layer 220 in the first sub-region 100MN and the second region 100L in the same doping step; or when the second device is a PMOS device, the conductive ions 215 are doped in the polycrystalline silicon material layer 220 in the second sub-region 100MP and the second region 100L in the same doping step.

[0078] Reference Figure 7 After the conductive ions 215 are doped in the polycrystalline silicon material layer 220, the forming method further includes removing the polycrystalline silicon material layer 220 in the second region 100L.

[0079] The polycrystalline silicon material layer 220 of the second region 100L is removed to expose the substrate 100 of the second region 100L, thereby preparing for forming a gate material stack on the substrate 100 of the second region 100L.

[0080] The substrate 100 of the second region 100L further has a gate oxide layer 210 formed thereon. Therefore, after the polycrystalline silicon material layer 220 of the second region 100L is removed, the gate oxide layer 210 of the second region 100L is also removed.

[0081] In this embodiment, an anisotropic dry etching process is used to etch and remove the polycrystalline silicon material layer 220 and the gate oxide layer 210 of the second region 100L.

[0082] The anisotropic etching process has the characteristic of anisotropic etching, i.e., the longitudinal etching rate is much greater than the lateral etching rate, thereby obtaining a better etching profile. Moreover, by using the dry etching process, the polycrystalline silicon material layer 220 and the gate oxide layer 210 can be etched in sequence in the same etching chamber by changing the etching gas, and the etching process is simple.

[0083] It should be noted that, according to the process requirement, after the polycrystalline silicon material layer 220 and the gate oxide layer 210 of the second region 100L are removed, the forming method can further include: forming another gate oxide layer (not shown in the figure) on the surface of the substrate 100 of the second region 100L, and the thickness of the gate oxide layer of the second region 100L is smaller than that of the gate oxide layer 210 of the first region 100M.

[0084] A high-k gate dielectric material layer is formed on the gate oxide layer of the second region 100L. In the second region 100L, the gate oxide layer serves as an interface buffer layer of the high-k gate dielectric material layer and the substrate 100, for improving electron mobility, and improving interface stability and device reliability.

[0085] Reference Figure 8 A gate material stack (not labeled) is formed on the substrate 100 of the second region 100L, including a high-k gate dielectric material layer 230, a metal barrier material layer 240 located on the high-k gate dielectric material layer 230, and a dummy gate material layer 250 located on the metal barrier material layer 240.

[0086] The gate material stack is used to prepare for forming a metal gate structure in the second region 100L.

[0087] In this embodiment, the metal gate structure is formed by using a high-K first process in a gate last process. Therefore, a high-k gate dielectric material layer 230 and a metal barrier material layer 240 on the high-k gate dielectric material layer 230 are first formed on the substrate 100.

[0088] The high-k gate dielectric material layer 230 is used to prepare for the formation of a high-k gate dielectric layer. The high-k gate dielectric layer is used to form a gate dielectric layer of the second device, i.e., the gate dielectric layer of the second device includes the high-k gate dielectric layer.

[0089] The material of the high-k gate dielectric material layer 230 is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric material layer 230 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric material layer 230 is HfO2.

[0090] The dummy gate material layer 250 is used to prepare for the formation of a dummy gate layer in the second region 100L. The dummy gate layer in the second region 100L is used to occupy a space position for the subsequent formation of a metal gate layer.

[0091] In this embodiment, the material of the dummy gate material layer 250 is polysilicon.

[0092] The material of the dummy gate material layer 250 is the same as that of the polysilicon material layer 220, so that the dummy gate material layer 250 and the polysilicon material layer 220 can be etched in the same etching step, and the etching rate of the dummy gate material layer 250 and the polysilicon material layer 220 is the same, thereby simplifying the process steps and improving the uniformity of the etching effect of the dummy gate material layer 250 and the polysilicon material layer 220.

[0093] In other embodiments, the material of the dummy gate material layer can also be amorphous silicon.

[0094] The metal barrier material layer 240 is used to prepare for the formation of a metal barrier layer.

[0095] The metal barrier layer is used to isolate the high-k gate dielectric layer and the metal gate layer to protect the high-k gate dielectric layer. In the subsequent process of etching the dummy gate layer, the metal barrier layer acts as an etching stop layer, thereby reducing the probability of damage to the high-k gate dielectric layer. Moreover, after the formation of the metal gate layer, the metal barrier layer is also used to block the diffusion of easily diffusing ions (e.g., Al ions) in the metal gate layer into the high-k gate dielectric layer.

[0096] Specifically, the material of the metal barrier material layer 240 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier material layer 240 is titanium nitride.

[0097] The metal barrier material layer 240 also has an effect on the gate work function of the device.

[0098] In actual process, by reasonably setting the thickness of the metal barrier material layer 240, the metal barrier layer can be used as an etching stop layer in the subsequent process of etching the dummy gate layer, and the metal barrier layer has a better blocking effect on the easily diffusing ions in the metal gate layer.

[0099] In this embodiment, the gate material stack is formed by a deposition process, and therefore, the gate material stack also extends to cover the polysilicon material layer 220.

[0100] In this embodiment, the atomic layer deposition process is used to form the high-k gate dielectric material layer 230 and the metal barrier material layer 240 in sequence. By using the atomic layer deposition process, the step coverage and thickness uniformity of the high-k gate dielectric material layer 230 and the metal barrier material layer 240 are improved.

[0101] In other embodiments, the process of forming the high-k gate dielectric material layer can also be a physical vapor deposition process, and the process of forming the metal barrier material layer can also be a physical vapor deposition process.

[0102] In this embodiment, the furnace tube process or the chemical vapor deposition process is used to form the polysilicon material layer 220.

[0103] It should be noted that when another gate oxide layer (not shown in the figure) is formed on the surface of the substrate 100 of the second region 100L, in the second region 100L, the high-k gate dielectric material layer 230 covers the gate oxide layer correspondingly.

[0104] Correspondingly, referring to Figure 9 , the forming method further includes: removing the gate material stack located on top of the polysilicon material layer 220.

[0105] By removing the gate material stack located on top of the polysilicon material layer 220, the subsequent etching of the polysilicon material layer 220 is prepared.

[0106] In this embodiment, the anisotropic etching process is used to etch and remove the gate material stack located on top of the polysilicon material layer 220.

[0107] The longitudinal etching rate of the anisotropic etching process is greater than the lateral etching rate, thereby facilitating improvement of the integrity and profile quality of the remaining gate material stack in the second region 100L.

[0108] It should be noted that before removing the gate material stack located on top of the polysilicon material layer 220, the method further comprises: forming a mask layer covering the second region 100L; and correspondingly, etching to remove the gate material stack exposed by the mask layer.

[0109] The mask layer is used to protect the gate material stack of the second region 100L, thereby reducing the probability of damage to the gate material stack of the second region 100L during the process of removing the gate material stack located on top of the polysilicon material layer 220.

[0110] Therefore, after removing the gate material stack located on top of the polysilicon material layer 220, the method further comprises: removing the mask layer.

[0111] As an example, the material of the mask layer can be photoresist.

[0112] Reference Figure 9 and Figure 10 , after removing the gate material stack located on top of the polysilicon material layer 220, the forming method further comprises: forming a patterned gate mask layer 270 (as shown in Figure 10 ) on the polysilicon material layer 220 and the dummy gate material layer, respectively.

[0113] The gate mask layer 270 is used as a mask for subsequent etching of the polysilicon material layer 220 and the gate material stack.

[0114] Specifically, the step of forming the gate mask layer 270 comprises: forming a gate mask material layer 260 covering the top of the polysilicon material layer 220 and the gate material stack, as shown in Figure 9 ; and etching the gate mask material layer 260 to form the patterned gate mask layer 270, as shown in Figure 10 .

[0115] As an example, the material of the gate mask layer 270 is silicon nitride.

[0116] Continuing to refer to Figure 10 , etching the polysilicon material layer 220 to form a polysilicon gate layer 310 on the substrate 100 of the first region 100M; and etching the gate material stack to form, on the substrate 100 of the second region 100L, a high-k gate dielectric layer 320, a metal barrier layer 330, and a dummy gate layer 340 stacked in order from bottom to top.

[0117] In this embodiment, the polysilicon material layer and the gate material stack are etched in the same step, thereby simplifying the process steps.

[0118] Specifically, the polysilicon material layer 220 and the gate material stack are etched as the etching mask of the gate mask layer 270.

[0119] In this embodiment, the forming method further includes: etching and removing the gate oxide layer 210 exposed by the polysilicon gate layer 310, thereby exposing the surface of the source / drain doped region 350, further reducing the influence on the subsequent process of forming the source / drain doped region, and preparing for the subsequent formation of the source / drain silicide layer.

[0120] In this embodiment, after etching and removing the gate oxide layer 210 exposed by the polysilicon gate layer 310, in the first region 100M, the polysilicon gate layer 310 and the gate oxide layer 210 located thereunder form a polysilicon gate structure 410.

[0121] In this embodiment, when another gate oxide layer (not shown in the figure) is formed on the surface of the substrate 100 of the second region 100L, the forming method further includes: etching and removing the gate oxide layer exposed by the dummy gate layer 340 in the second region 100L.

[0122] It should be noted that in other embodiments, in the first region, the gate oxide layer exposed by the polysilicon gate layer can also be removed. For example, another gate oxide layer (not shown in the figure) is formed on the surface of the substrate of the second region, and the thickness of the gate oxide layer located in the second region is smaller than that of the gate oxide layer in the first region, and the time required for removing the gate oxide layer in the second region is correspondingly shorter. Therefore, after etching the stacked dummy gate material layer, metal barrier material layer, high-k gate dielectric material layer and gate oxide layer (not shown in the figure) in the second region from top to bottom, the gate oxide layer in the first region can not be completely removed.

[0123] It should be further noted that in this embodiment, the polysilicon material layer 220 is formed first, and then the conductive ions 215 are doped into the polysilicon material layer 220, and then the gate material stack is formed, thereby reducing or avoiding the influence of the process performed before the formation of the gate material stack on the gate material stack, and further reducing the probability of adversely affecting the performance of the gate material stack.

[0124] In other embodiments, according to the process requirements, other process sequences can also be used to form the polysilicon gate layer in the first region and form the high-k gate dielectric layer, metal barrier layer and dummy gate layer stacked from bottom to top in the second region, respectively.

[0125] For example, after forming a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer in sequence from bottom to top in the second region, a polysilicon material layer is formed on the gate oxide layer in the first region, the polysilicon material layer also extends to cover the dummy gate layer, then conductive ions are doped into the polysilicon material layer, and after the doping of the conductive ions, the polysilicon material layer in the second region is removed. Alternatively, after forming a polysilicon gate layer in the first region and forming a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer in sequence from bottom to top in the second region, conductive ions are doped into the polysilicon gate layer in the first region.

[0126] Referring to Figure 11 , source-drain doped regions 350 are formed in the substrate 100 on both sides of the polysilicon gate layer 310 and on both sides of the dummy gate layer 340.

[0127] The source-drain doped regions 350 serve as source regions or drain regions of the formed device.

[0128] The conductive type of the doped ions in the source-drain doped regions 350 is the same as the channel conductive type of the corresponding device. When the formed device is an NMOS device, the doped ions in the source-drain doped regions 350 are N-type ions, including P ions, As ions or Sb ions, and when the formed device is a PMOS device, the doped ions in the source-drain doped regions 350 are P-type ions, including B ions, Ga ions or In ions.

[0129] As an example, the source-drain doped regions 350 are formed by ion implantation.

[0130] Referring to Figure 12 , a first salicide layer 360 is formed on the surface of the source-drain doped regions 350.

[0131] Subsequently, a source-drain plug is formed on top of the source-drain doped regions 350, and by forming the source-drain salicide layer 360, the contact resistance between the source-drain doped regions 350 and the source-drain plug is reduced, thereby improving the performance of the semiconductor structure.

[0132] The material of the source-drain salicide layer 360 can be a nickel-silicon compound, a cobalt-silicon compound or a titanium-silicon compound.

[0133] Specifically, a metal layer is formed on the surface of the source-drain doped regions 350, and annealing is performed to cause the metal layer to react with the material of the source-drain doped regions 350, thereby converting the metal layer into the source-drain salicide layer 360, and after the formation of the source-drain salicide layer 360, the remaining unreacted metal layer is removed.

[0134] It is noted that before forming the silicide source / drain layer 360, a step of forming a salicide block (SAB) layer (not shown) is also included. By forming the SAB layer, the area for forming the silicide source / drain layer 360 is exposed, and the area where the silicide source / drain layer 360 is not desired to be formed is protected.

[0135] It is also noted that the top of the polysilicon gate layer 310 is formed with the gate mask layer 270, so that the silicide source / drain layer 360 is not formed on the top surface of the polysilicon gate layer 310.

[0136] In addition, before forming the silicide source / drain layer 360, the oxide layer (e.g., natural oxide layer) on the surface of the substrate 100 exposed by the SAB layer or the gate oxide layer 210 remaining in the first region 100M is removed, so as to expose the surface of the source / drain doped region 350, and to prepare for forming the silicide source / drain layer 360.

[0137] Reference is made to Figure 13 An inter layer dielectric (ILD) layer 370 is formed on the substrate 100 on the sides of the polysilicon gate layer 310 and the dummy gate layer 340, and the ILD layer 370 exposes the top of the dummy gate layer 340.

[0138] The ILD layer 370 is used to isolate adjacent devices.

[0139] The material of the ILD layer 370 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the ILD layer 370 is silicon oxide.

[0140] Specifically, the ILD layer 370 is formed by a deposition and planarization process (e.g., a chemical mechanical polishing process), so that the ILD layer 370 exposes the top of the dummy gate layer 340.

[0141] By exposing the top of the dummy gate layer 340 by the ILD layer 370, the dummy gate layer 340 is prepared to be removed later.

[0142] It is noted that the first device has a high operating voltage, and thus the thickness of the gate oxide layer 210 is usually large. Accordingly, the top of the polysilicon gate layer 310 is usually higher than the top of the dummy gate layer 340. Therefore, after forming the ILD layer 370 exposing the top of the dummy gate layer 340, the ILD layer 370 also exposes the top of the polysilicon gate layer 310.

[0143] It is also needed to be explained that the gate mask layer 270 is removed in the process of forming the interlayer dielectric layer 370.

[0144] Referring to Figure 14 After the interlayer dielectric layer 370 is formed, the dummy gate layer 340 is removed (as shown in Figure 13 , and a metal gate layer 380 is formed at the position of the dummy gate layer 340.

[0145] The metal gate layer 380, the metal barrier layer 330 and the high-k gate dielectric layer 320 are used to form a metal gate structure 420.

[0146] Since the working voltage of the second device is smaller, the short channel effect is improved by using the metal gate structure 420.

[0147] The metal gate layer 380 is used to lead out the electrical property of the metal gate structure 420.

[0148] Specifically, the step of forming the metal gate layer 380 includes: using one or both of a dry etching process and a wet etching process to etch and remove the dummy gate layer 340, and form a gate opening in the interlayer dielectric layer 370; filling a metal material into the gate opening; and performing a planarization treatment (for example, a chemical mechanical polishing treatment) on the metal material to remove the metal material above the top of the interlayer dielectric layer 370, and reserve the remaining metal material in the gate opening as the metal gate layer 380.

[0149] It is needed to be explained that before the metal gate layer 380 is formed, the top of the polysilicon gate layer 310 is not formed with a gate silicide layer, so that the problem of metal contamination can be avoided in the process of planarizing the metal material.

[0150] The material of the metal gate layer 380 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In the embodiment, the material of the metal gate layer 380 is Al.

[0151] It is also needed to be explained that when a gate oxide layer is further formed between the high-k gate dielectric layer 320 and the substrate 100 in the second region 100L, the metal gate structure 420 further includes the gate oxide layer.

[0152] In addition, before the metal material is filled into the gate opening, the step of forming a function layer in the gate opening is further included, which will not be described herein.

[0153] Referring to Figure 15 After the metal gate layer 380 is formed, the forming method further includes: forming a gate silicide layer 440 on the top surface of the polysilicon gate layer 310.

[0154] The gate silicide layer 440 is formed on the top surface of the polysilicon gate layer 310, so as to reduce the gate resistance of the first device.

[0155] In this embodiment, the material of the gate silicide layer 440 can be a nickel-silicon compound, a cobalt-silicon compound or a titanium-silicon compound.

[0156] Specifically, the step of forming the gate silicide layer 440 comprises: forming a covering layer 430 covering the metal gate layer 380, the covering layer 430 exposing the top surface of the polysilicon gate layer 310; and forming the gate silicide layer 440 on the top surface of the polysilicon gate layer 310 exposed by the covering layer 430.

[0157] The covering layer 430 is used to protect the metal gate layer 380 and define the forming position of the gate silicide layer 440.

[0158] As an example, the covering layer 430 covering the metal gate layer 380 is formed on the interlayer dielectric layer 370 by a deposition process, a photolithography process and an etching process, the covering layer 430 has an opening (not shown in the figure) exposing the top surface of the polysilicon gate layer 310, and the gate silicide layer 440 is formed in the opening.

[0159] It should be noted that, since the gate silicide layer is a self-aligned silicide and will not be formed on the surface of the interlayer dielectric layer, in other embodiments, the covering layer can also cover only the second region, the covering layer exposing the polysilicon gate layer and the interlayer dielectric layer of the first region, so as to increase the process window of the photolithography process.

[0160] The material of the covering layer 430 is a dielectric material, so that the covering layer 430 can be reserved to simplify the process steps.

[0161] In this embodiment, the material of the covering layer 430 comprises silicon oxide or silicon oxynitride.

[0162] The specific process of forming the gate silicide layer 440 will be described below with reference to the corresponding description of the source-drain silicide layer 360.

[0163] Correspondingly, the present application also provides a semiconductor structure. The structure of an embodiment of the semiconductor structure of the present application is shown in the structure schematic diagram of FIG. 4. Figure 15

[0164] ​The semiconductor structure comprises: a substrate 100, including a first region 100M for forming a first device and a second region 100L for forming a second device, a channel length of the first device being greater than a channel length of the second device; a polysilicon gate layer 310 located on the substrate 100 of the first region 100M; a high-k gate dielectric layer 320 located on the substrate 100 of the second region 100; a metal barrier layer 330 located on the high-k gate dielectric layer 320; a metal gate layer 380 located on the metal barrier layer 330; and an interlayer dielectric layer 370 located on the substrate 100 at sides of the polysilicon gate layer 310 and the metal gate layer 380.

[0165] Since the work function of the metal barrier layer 330 is greater than that of the polysilicon material, in the first region 100M, by not forming the metal barrier layer 330 under the polysilicon gate layer 310, the problem of the threshold voltage of the first device being higher due to the presence of the metal barrier layer 330 can be avoided in the case of the first device using the polysilicon gate layer 310, which is beneficial to enable the threshold voltage of the first device to meet the performance requirements of the device, thereby improving the performance of the semiconductor structure.

[0166] In the embodiment, the semiconductor structure is taken as an example of a planar field effect transistor, and the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure is a fin field effect transistor, and accordingly, the substrate includes a substrate and a fin portion protruding from the substrate.

[0167] In the embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0168] In the embodiment, the substrate is a P-type substrate (Psub), that is, P-type ions including B ions, Ga ions, or In ions are doped in the substrate.

[0169] In the embodiment, the substrate 100 includes a first region 100M for forming a first device and a second region 100L for forming a second device, a channel length of the first device being greater than a channel length of the second device.

[0170] As an example, the working voltage of the first device is greater than the working voltage of the second device, so that the channel length of the first device is greater than the channel length of the second device.

[0171] In this embodiment, the first device includes one or both of a medium voltage device and a high voltage device, and the second device is a low voltage device. As an example, the low voltage device has an operating voltage less than 1V, the medium voltage device has an operating voltage between 1V and 10V, and the high voltage device has an operating voltage greater than 10V.

[0172] It is to be noted that when the first device includes both a medium voltage device and a high voltage device, the first region 100M for forming the medium voltage device and the first region 100M for forming the high voltage device are isolated.

[0173] The first device can be an NMOS device or a PMOS device. Similarly, the second device can also be an NMOS device or a PMOS device.

[0174] As an example, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form first devices of different channel conductivity types. For example, the first device located in the first sub-region 100MN is an NMOS device, and the first device located in the second sub-region 100MP is a PMOS device.

[0175] In this embodiment, taking the first region 100M for forming a medium voltage device and the second region 100L for forming a low voltage device as an example, a deep N-type well (DNW) region (not shown in the figure) is also formed in the substrate 100, a first well region (not labeled) is formed in the deep N-type well region of the first region 100M, and a second well region (not labeled) is formed in the deep N-type well region of the second region 100L.

[0176] The deep N-type well region is used to isolate the first well region from the P-type substrate and to isolate the second well region from the P-type substrate, thereby reducing substrate coupling noise.

[0177] The type of doping ions in the first well region is opposite to the channel conductivity type of the first device located thereon.

[0178] When the first device is an NMOS device, the doping ions in the first well region are P-type ions, and when the first device is a PMOS device, the doping ions in the first well region are N-type ions. Similarly, the type of doping ions in the second well region is opposite to the channel conductivity type of the second device located thereon.

[0179] In the embodiment, the isolation structure 101 is formed in the substrate 100. Specifically, the isolation structure 101 is formed in the substrate 100 at the boundary between the first region 100M and the second region 100L. The first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and thus the isolation structure 101 is also formed in the substrate 100 at the boundary between the first sub-region 100MN and the second sub-region 100MP.

[0180] In other embodiments, when the first region is used to form a high-voltage device, a high-voltage well region is formed in the substrate, and correspondingly, no deep N-type well region is formed in the substrate. Similarly, the type of the doping ions in the high-voltage well region is opposite to the channel conduction type of the first device formed thereon.

[0181] The isolation structure 101 is used to achieve isolation between adjacent devices. In the embodiment, the isolation structure 101 is a shallow trench isolation, so that the isolation structure 101 has a good isolation effect.

[0182] In the embodiment, the material of the isolation structure 101 is an insulating material, and the insulating material includes silicon oxide.

[0183] The first device adopts a polysilicon gate structure 410, and the polysilicon gate layer 310 is used as a part of the polysilicon gate structure 410, and the polysilicon gate layer 310 is used to control the opening or closing of the channel of the first device.

[0184] In the embodiment, the material of the polysilicon gate layer 310 is polysilicon.

[0185] To this end, in the embodiment, the semiconductor structure further includes a gate oxide layer 210 located between the polysilicon gate layer 310 and the substrate 100. The gate oxide layer 210 is used as the gate dielectric of the first device, and the gate oxide layer 210 is used to electrically isolate the polysilicon gate layer 310 and the channel of the first device.

[0186] In the embodiment, the material of the gate oxide layer 210 is silicon oxide.

[0187] In the embodiment, the polysilicon gate layer 310 is doped with conductive ions 215, and the conduction type of the conductive ions 215 is the same as the conduction type of the channel of the corresponding first device.

[0188] By doping the conductive ions 215 into the polysilicon gate layer 310, the resistance of the polysilicon gate layer 310 is reduced, thereby reducing the gate resistance of the first device and reducing the contact resistance between the polysilicon gate layer 310 and the gate silicide layer; and in the embodiment, the gate dielectric layer of the first device only includes the gate oxide layer 210, so by making the conductivity type of the conductive ions 215 the same as the channel conductivity type of the corresponding first device, the threshold voltage of the first device can be adjusted by adjusting the concentration of the conductive ions 215, which is conducive to improving the performance of the semiconductor structure.

[0189] According to the channel conductivity type of the first device, the conductive ions 215 can be N-type ions or P-type ions. Specifically, the P-type ions include B ions, Ga ions, and In ions, and the N-type ions include P ions, As ions, or Sb ions.

[0190] In the embodiment, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form first devices of different channel conductivity types, so in the first region 100M, the conductive ions 215 in the polysilicon gate layer 310 of the first sub-region 100MN and the second sub-region 100MP have different conductivity types.

[0191] Specifically, the first device located in the first sub-region 100MN is an NMOS device, and the first device located in the second sub-region 100MP is a PMOS device, so the conductive ions 215 doped in the polysilicon gate layer 310 of the first sub-region 100MN are N-type ions, and the conductive ions 215 doped in the polysilicon gate layer 310 of the second sub-region 100MP are P-type ions.

[0192] The substrate 100 of the second region 100L is formed with a high-k gate dielectric layer 320, a metal barrier layer 330, and a metal gate layer 380 stacked in order from bottom to top, which are used to form a metal gate structure 420.

[0193] Since the operating voltage of the second device is small, by using the metal gate structure 420, the short channel effect is improved.

[0194] The high-k gate dielectric layer 320 is used to form the gate dielectric layer of the second device.

[0195] The material of the high-k gate dielectric layer 320 is a high-k dielectric material. Specifically, the material of the high-k gate dielectric layer 320 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 320 is HfO2.

[0196] The metal barrier layer 330 is used to isolate the high-k gate dielectric layer 320 and the metal gate layer 380, so as to protect the high-k gate dielectric layer 320. The metal barrier layer 330 is also used to block the diffusion of the easily diffusing ions (e.g. Al ions) in the metal gate layer 380 into the high-k gate dielectric layer 320.

[0197] Specifically, the material of the metal barrier layer 330 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 330 is titanium nitride.

[0198] The metal barrier layer 330 also has certain influence on the gate work function of the device.

[0199] The metal gate layer 380 is used to lead out the electrical property of the metal gate structure 420.

[0200] The material of the metal gate layer 380 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal gate layer 380 is Al.

[0201] It is to be noted that in the second region 100L, a gate oxide layer (not shown in the figure) can also be formed between the high-k gate dielectric layer 320 and the substrate 100, and the thickness of the gate oxide layer in the second region 100L is smaller than that of the gate oxide layer 210 in the first region 100M. Accordingly, the gate dielectric layer of the second device includes the gate oxide layer and the high-k gate dielectric layer 320, and the gate oxide layer in the second region 100L also serves as a part of the metal gate structure 420.

[0202] In this embodiment, the semiconductor structure further includes source-drain doped regions 350 in the substrate 100 on both sides of the polysilicon gate layer 310 and on both sides of the metal gate layer 380, and source-drain silicide layers 360 on the surfaces of the source-drain doped regions 350.

[0203] The source-drain doped regions 350 serve as source regions or drain regions of the device.

[0204] The conductive type of the dopant ions in the source-drain doped region 350 is the same as the conductive type of the corresponding device. When the corresponding device is an NMOS device, the dopant ions in the source-drain doped region 350 are N-type ions, including P ions, As ions or Sb ions. When the corresponding device is a PMOS device, the dopant ions in the source-drain doped region 350 are P-type ions, including B ions, Ga ions or In ions.

[0205] A top portion of the source-drain doped region 350 is usually formed with a source-drain plug, through a source-drain silicide layer 360, so as to reduce the contact resistance between the source-drain doped region 350 and the source-drain plug, and thus improve the performance of the semiconductor structure.

[0206] The material of the source-drain silicide layer 360 can be a nickel silicon compound, a cobalt silicon compound or a titanium silicon compound.

[0207] The interlayer dielectric layer 370 is used to isolate adjacent devices.

[0208] The material of the interlayer dielectric layer 370 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 370 is silicon oxide.

[0209] In this embodiment, the interlayer dielectric layer 370 covers the sidewalls of the polysilicon gate layer 310 and the metal gate layer 380.

[0210] In this embodiment, the semiconductor structure further includes a gate silicide layer 440 located on a top surface of the polysilicon gate layer 310.

[0211] The gate silicide layer 440 is used to reduce the gate resistance of the first device.

[0212] In this embodiment, the material of the gate silicide layer 440 can be a nickel silicon compound, a cobalt silicon compound or a titanium silicon compound.

[0213] In this embodiment, the semiconductor structure further includes a cover layer 430 covering the metal gate layer 380 and exposing a top surface of the polysilicon gate layer 310; the gate silicide layer 440 is located on the top surface of the polysilicon gate layer 310 exposed by the cover layer 430.

[0214] In the process of forming the semiconductor structure, the metal gate layer 380 is formed by using a gate last process, and therefore, the step of forming the metal gate layer 380 generally includes: removing the dummy gate layer, forming a gate opening in the interlayer dielectric layer 370; filling the metal material into the gate opening; and performing a planarization process (for example, a chemical mechanical polishing process) on the metal material, removing the metal material above the top of the interlayer dielectric layer 370, and retaining the remaining metal material in the gate opening as the metal gate layer 380. Therefore, after the metal gate layer 380 is formed, the gate silicide layer 440 is formed, so as to avoid the problem of metal contamination in the process of planarizing the metal material.

[0215] The cover layer 430 is used to protect the metal gate layer 380 and define the forming position of the gate silicide layer 440 in the process of forming the gate silicide layer 440.

[0216] As an example, the cover layer 430 also covers the interlayer dielectric layer 370.

[0217] It should be noted that, since the gate silicide layer 440 is a self-aligned silicide and will not be formed on the surface of the interlayer dielectric layer 370, in other embodiments, the cover layer can also only cover the second region, and the cover layer exposes the polysilicon gate layer and the interlayer dielectric layer in the first region, so as to increase the process window of the photolithography process in the process of forming the cover layer.

[0218] The material of the cover layer 430 is a dielectric material, so that the cover layer 430 can be retained to simplify the process steps.

[0219] In this embodiment, the material of the cover layer 430 includes silicon oxide or silicon oxynitride.

[0220] The semiconductor structure can be formed by using the forming method described in the foregoing embodiments, or can be formed by using other forming methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be described herein again.

[0221] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a first region for forming a first device and a second region for forming a second device, the first device having a channel length greater than the channel length of the second device; a polysilicon gate layer on the substrate in the first region; a high-k gate dielectric layer on the substrate in the second region; a metal barrier layer on the high-k gate dielectric layer; a metal gate layer on the metal barrier layer; an interlayer dielectric layer on the substrate laterally to the polysilicon gate layer and the metal gate layer; the semiconductor structure further comprises a gate silicide layer on the top surface of the polysilicon gate layer; a capping layer covering the top of the metal gate layer and the top of the interlayer dielectric layer and exposing the top surface of the gate silicide layer.

2. The semiconductor structure of claim 1, wherein, The polysilicon gate layer is doped with conductive ions, and the conductive ions have the same conductivity type as the channel conductivity type of the corresponding first device.

3. The semiconductor structure of claim 2, wherein, The conductive ions comprise B ions, Ga ions, In ions, P ions, As ions or Sb ions.

4. The semiconductor structure of claim 1, wherein, The material of the capping layer comprises silicon oxide or silicon oxynitride.

5. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a gate oxide layer between the polysilicon gate layer and the substrate.

6. The semiconductor structure of claim 1, wherein, The material of the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride.

7. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: a substrate comprising a first region for forming a first device and a second region for forming a second device, the first device having a channel length greater than the channel length of the second device; forming a polysilicon material layer on the substrate in the first region and forming a gate material stack on the substrate in the second region in different steps, the gate material stack comprising a high-k gate dielectric material layer, a metal barrier material layer on the high-k gate dielectric material layer, and a dummy gate material layer on the metal barrier material layer; after forming the polysilicon material layer and the gate material stack, etching the polysilicon material layer to form a polysilicon gate layer on the substrate in the first region, and etching the gate material stack to form a high-k gate dielectric layer, a metal barrier layer and a dummy gate layer stacked in order from bottom to top on the substrate in the second region; forming an interlayer dielectric layer on the substrate laterally to the polysilicon gate layer and the dummy gate layer, the interlayer dielectric layer exposing the top of the dummy gate layer; after forming the interlayer dielectric layer, removing the dummy gate layer and forming a metal gate layer at the location of the dummy gate layer.

8. The method of forming a semiconductor structure of claim 7, wherein, The gate material stack is formed after forming the polysilicon material layer.

9. The method of forming a semiconductor structure of claim 7, wherein, The forming method further comprises, after forming the polysilicon material layer and before forming the gate material stack, doping the polysilicon material layer with conductive ions, and the conductive ions have the same conductivity type as the channel conductivity type of the corresponding first device.

10. The method of forming a semiconductor structure of claim 9, wherein, In the step of forming the polysilicon material layer on the substrate in the first region, the polysilicon material layer also extends to cover the substrate in the second region; after doping the polysilicon material layer with conductive ions, the forming method further comprises removing the polysilicon material layer in the second region.

11. The method of forming a semiconductor structure of claim 7, wherein, In the step of forming a gate material stack on the substrate in the second region, the gate material stack also extends to cover the polysilicon material layer; Before etching the polysilicon material layer and the gate material stack, the forming method further comprises: removing the gate material stack on top of the polysilicon material layer.

12. The method of forming a semiconductor structure of claim 11, wherein, The step of removing the gate material stack on top of the polysilicon material layer comprises: etching the gate material stack by using an anisotropic etching process.

13. The method of forming a semiconductor structure of claim 7, wherein, In the same step, the polysilicon material layer and the gate material stack are etched.

14. The method of forming a semiconductor structure of claim 13, wherein, Before etching the polysilicon material layer and the gate material stack, the forming method further comprises: forming a patterned gate mask layer on the polysilicon material layer and the dummy gate material layer respectively; In the step of etching the polysilicon material layer and the gate material stack, the gate mask layer is used as an etching mask; Before forming the interlayer dielectric layer, the forming method further comprises: forming source-drain doped regions in the substrate on both sides of the polysilicon gate layer and both sides of the dummy gate layer respectively; forming source-drain silicide layers on the surface of the source-drain doped regions; In the process of forming the interlayer dielectric layer, the gate mask layer is removed.

15. The method of forming a semiconductor structure of claim 7 or 14, wherein, After forming the metal gate layer, the forming method further comprises: forming a gate silicide layer on the top surface of the polysilicon gate layer.

16. The method of forming a semiconductor structure of claim 15, wherein, The step of forming the gate silicide layer comprises: forming a cover layer covering the metal gate layer, the cover layer exposing the top surface of the polysilicon gate layer; The gate silicide layer is formed on the top surface of the polysilicon gate layer exposed by the cover layer.

17. The method of forming a semiconductor structure of claim 7, wherein, The material of the dummy gate layer comprises polysilicon or amorphous silicon.

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