A semiconductor device and a method of fabricating the same
By creating a source hole on the bottom surface of the substrate and eliminating the source hole of the first sub-electrode, and connecting the first sub-electrode and the second sub-electrode with a connecting bridge, the problem of excessive device area in the prior art is solved, the device area and cost are reduced, and the inductance and parasitic capacitance are optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SHIDAI SUXIN TECH CO LTD
- Filing Date
- 2022-03-22
- Publication Date
- 2026-05-19
AI Technical Summary
Existing herringbone gate structure semiconductor devices require active vias at the source, resulting in a larger device area and increased manufacturing costs.
By creating a source via on the bottom surface of the substrate and eliminating the source via of the first sub-electrode, the first sub-electrode and the second sub-electrode are electrically connected by a connecting bridge, thereby reducing the width of the first sub-electrode and thus reducing the occupied area of the source structure.
This effectively reduces the area and manufacturing cost of semiconductor devices, while also reducing inductance and parasitic capacitance.
Smart Images
Figure CN114664935B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology
[0002] Gallium nitride (GaN) possesses a high breakdown electric field and high electron saturation drift velocity, typical of wide-bandgap semiconductors. Furthermore, due to the very strong spontaneous and piezoelectric polarization effects of AlGaN / GaN, deep triangular quantum wells can be formed at the heterojunction, inducing quantum energies as high as 10-10. 13 cm -2 Gallium nitride's massive 2D electron gas (2DEG) gives it a significant advantage over other compound semiconductors such as GaAs and InP in high-power radio frequency (RF) electronic devices. For RF power devices, especially gallium nitride, the gate resistance and inductance become crucial factors determining device gain as the operating frequency increases.
[0003] To reduce gate resistance and inductance while improving heat dissipation, the herringbone gate structure was proposed. The herringbone gate structure can also improve the phase shift difference between signals at different locations, thereby increasing power-added efficiency (PAE). However, in existing devices using the herringbone gate structure, each source electrode requires a source via to be led out from the back of the substrate. Therefore, to achieve connection between the source metal and the back via metal, the source electrode width is usually required to completely cover the source via, resulting in a large overall device area and high manufacturing costs. Summary of the Invention
[0004] The purpose of this application is to address the shortcomings of the prior art by providing a semiconductor device and its fabrication method, thereby reducing the area occupied by the source portion, reducing the overall device area, and thus lowering manufacturing costs.
[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:
[0006] In one aspect of this application, a semiconductor device is provided, comprising: a substrate and a functional layer located on the substrate; a source structure, a drain structure, and a herringbone gate structure are disposed on the top surface of the functional layer; the source structure and the drain structure are used to cooperate with the herringbone gate structure to form a plurality of transistor devices; a source via is formed on the bottom surface of the substrate, extending from the bottom surface of the substrate to the top surface of the functional layer; the source structure includes a first sub-electrode and a second sub-electrode covering the source via located on the top surface of the functional layer; the first sub-electrode is electrically connected to the second sub-electrode through a connecting bridge.
[0007] Optionally, the fishbone grid structure includes a grid bone and multiple grid fingers connected to the grid bone and distributed on opposite sides of the grid bone, the multiple grid fingers being divided into two groups; the drain structure includes multiple drain fingers distributed on opposite sides of the grid bone; the source structure includes multiple first sub-electrodes distributed on opposite sides of the grid bone and multiple second sub-electrodes distributed on opposite sides of the grid bone; in one group, each grid finger has a first sub-electrode and a drain finger distributed on opposite sides, and in the other group, each grid finger has a second sub-electrode and a drain finger distributed on opposite sides.
[0008] Optionally, the first and second sub-electrodes located on the same side of the grid are alternately distributed.
[0009] Optionally, the first and second sub-electrodes located on the same side of the grid are electrically connected via a connecting bridge.
[0010] Optionally, when there is only a grid between the first sub-electrode and the second sub-electrode located on opposite sides of the grid, the connecting bridge for connecting the first sub-electrode and the second sub-electrode only spans across the grid.
[0011] Optionally, the connecting bridge can be an air bridge or a medium bridge.
[0012] Optionally, the width of the first sub-electrode along the extension direction of the grid is smaller than the width of the second sub-electrode along the extension direction of the grid.
[0013] Optionally, the width of the first sub-electrode along the extension direction of the grid is 10% to 90% of the width of the second sub-electrode along the extension direction of the grid.
[0014] Optionally, the semiconductor device may also include a metal layer disposed in the source hole, the metal layer being connected to the second sub-electrode.
[0015] In another aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided for fabricating any of the above-described semiconductor devices.
[0016] The beneficial effects of this application include:
[0017] This application provides a semiconductor device and its fabrication method, comprising: a substrate and a functional layer on the substrate; a source structure, a drain structure, and a herringbone gate structure are disposed on the top surface of the functional layer, the source structure and drain structure being used in conjunction with the herringbone gate structure to form multiple transistor devices; a source via is formed on the bottom surface of the substrate, extending from the bottom surface of the substrate to the top surface of the functional layer; the source structure includes a first sub-electrode and a second sub-electrode covering the source via located on the top surface of the functional layer, the first sub-electrode being electrically connected to the second sub-electrode via a connecting bridge. Thus, by eliminating the source via on the first sub-electrode, the width of the first sub-electrode can be reduced, thereby reducing the area occupied by the entire source structure, effectively reducing the area and manufacturing cost of the entire device; the lead-out of the first sub-electrode can be connected to the second sub-electrode via a connecting bridge, and the source via covered by the second sub-electrode is led out to the bottom surface of the substrate. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is one of the top view schematic diagrams of a semiconductor device provided in an embodiment of this application;
[0020] Figure 2 A second top view schematic diagram of a semiconductor device provided in an embodiment of this application;
[0021] Figure 3 A third top view schematic diagram of a semiconductor device provided in an embodiment of this application;
[0022] Figure 4 This is a fourth top view schematic diagram of a semiconductor device provided in an embodiment of this application.
[0023] Icons: 110 - Functional layer; 120 - Fishbone grid structure; 121 - Grid bone; 122 - First type of grid finger; 123 - Second type of grid finger; 130 - Drain structure; 131 - Drain finger; 140 - Source structure; 141 - Second sub-electrode; 142 - Source via; 143 - First sub-electrode; 150 - Connecting bridge. Detailed Implementation
[0024] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.
[0025] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0026] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," there is no intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "above another element" or "extending above another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "extending directly to another element," there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.
[0027] Related terms such as “below”, “above”, “upper”, “lower”, “horizontal”, or “vertical” are used herein to describe the relationship of one element, layer, or region to another, as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.
[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.
[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless explicitly defined herein.
[0030] One aspect of this application provides a semiconductor device, such as... Figure 1 As shown, it includes: a substrate (not shown) and a functional layer 110 located on the substrate. A source structure 140, a drain structure 130 and a fishbone gate structure 120 are disposed on the top surface of the functional layer 110. Multiple transistor devices are formed by the source structure 140 and the drain structure 130 respectively cooperating with the fishbone gate structure 120. Each transistor device has a source, a drain and a gate.
[0031] Please continue to refer to Figure 1 As shown, the source structure 140 includes two types of electrodes: a first sub-electrode 143 and a second sub-electrode 141. Both the first sub-electrode 143 and the second sub-electrode 141 are distributed on the top surface of the functional layer 110, and both can cooperate with the drain structure 130 and the fishbone gate structure 120 to form corresponding transistor structures. In this embodiment, the number of the first sub-electrode 143 and the second sub-electrode 141 is not limited, and can be flexibly determined according to the actual number of devices.
[0032] A source hole 142 is provided on the bottom surface of the substrate, extending from the bottom surface of the substrate to the top surface of the functional layer 110. The second sub-electrode 141 covers the opening of the source hole 142 on the top surface of the functional layer 110. In this way, the second sub-electrode 141 located on the top surface of the functional layer 110 can be led out to the bottom surface of the substrate through the source hole 142, which facilitates connection. The first sub-electrode 143 located on the top surface of the functional layer 110 is not led out by the source hole 142, that is, the first sub-electrode 143 does not correspond to the source hole 142. Therefore, the first sub-electrode 143 does not need to cover the opening of the source hole 142 on the top surface of the functional layer 110. Thus, the width of the first sub-electrode 143 can be reduced, that is, the width W2 of the first sub-electrode 143 is smaller than the width W1 of the second sub-electrode 141, thereby reducing the area occupied by the entire source structure 140, so that the entire device can effectively reduce the area and manufacturing cost. The lead-out of the first sub-electrode 143 can be connected to the second sub-electrode 141 by the connecting bridge 150, and the source hole 142 covered by the second sub-electrode 141 is led out to the bottom surface of the substrate.
[0033] In some embodiments, the substrate may be a silicon carbide substrate, a gallium nitride substrate, a silicon substrate, a sapphire substrate, a diamond substrate, etc. This application does not limit the substrate, and a reasonable selection can be made according to actual needs.
[0034] In some embodiments, a functional layer 110 is formed on a substrate by epitaxial growth. The functional layer 110 may include a plurality of active semiconductor layers, and a two-dimensional electron gas can be formed at the interface of at least two of the plurality of active semiconductor layers to serve as a current channel between the source structure 140 and the drain structure 130 when the transistor device is turned on.
[0035] Optional, such as Figures 1 to 4 As shown, the fishbone gate structure 120 includes a gate bone 121 and a plurality of gate fingers. One end of each gate finger is connected to the gate bone 121, and the other end of each gate finger extends away from the gate bone 121. The gate fingers are distributed on opposite sides of the gate bone 121, and the gate fingers on the same side of the gate bone 121 are arranged in a straight line along the extension direction A of the gate bone 121. Since the gate fingers need to cooperate with electrodes in different types of source structures 140 to form transistor devices, for ease of differentiation, the gate fingers are divided into two groups. One group includes a plurality of first-type gate fingers 122, and the other group includes a plurality of second-type gate fingers 123. The first-type gate fingers 122 cooperate with the second sub-electrode 141, and the second-type gate fingers 123 cooperate with the first sub-electrode 143.
[0036] Please continue to refer to Figures 1 to 4The drain structure 130 includes multiple drain fingers 131 distributed on opposite sides of the grid 121. The multiple drain fingers 131 located on the same side of the grid 121 are arranged in a line along the extension direction A of the grid 121. The drain fingers 131 can be used as shared drain fingers 131. Therefore, the drain fingers 131 are no longer distinguished.
[0037] There are multiple first sub-electrodes 143 and multiple second sub-electrodes 141. The multiple first sub-electrodes 143 are distributed on opposite sides of the grid 121, and the multiple first sub-electrodes 143 located on the same side of the grid 121 are arranged in a line along the extension direction A of the grid 121. The multiple second sub-electrodes 141 are also distributed on opposite sides of the grid 121, and the multiple second sub-electrodes 141 located on the same side of the grid 121 are arranged in a line along the extension direction A of the grid 121.
[0038] Please refer to Figures 1 to 4 As shown, a second sub-electrode 141 and a drain finger 131 are distributed on both sides of each first type gate finger 122. Thus, the second sub-electrode 141, the drain finger 131, and the first type gate finger 122 can form a transistor device. A first sub-electrode 143 and a drain finger 131 are distributed on both sides of each second type gate finger 123. Thus, the first sub-electrode 143, the drain finger 131, and the second type gate finger 123 can form a transistor device. The drain finger 131 distributed on one side of the first type gate finger 122 and the other side of the second type gate finger 123 can be the same, thus forming a shared drain finger 131. This allows for a reduction in the overall device area while maintaining the same number of transistors.
[0039] Since the first sub-electrode 143 and the second sub-electrode 141 are distributed on opposite sides of the grid 121 (e.g. Figure 1 (on the left and right sides of the grid), thus the source structure 140 can reduce the area occupied on both sides of the grid 121, thereby reducing the overall area of the device in direction A.
[0040] Optional, such as Figures 1 to 4 As shown, the first sub-electrode 143 and the second sub-electrode 141 on the left side of the grid 121 are alternately distributed, and the first sub-electrode 143 and the second sub-electrode 141 on the right side of the grid 121 are also alternately distributed. In this way, the area occupied by the source structure 140 can be effectively reduced, and the first sub-electrode 143 can be closer to the second sub-electrode 141, thereby shortening the span of the connecting bridge 150, and thus effectively reducing the inductance and parasitic capacitance generated therefrom.
[0041] Due to the different distribution positions and patterns of the first sub-electrode 143 and the second sub-electrode 141, and the different parity of the total number of the first sub-electrode 143 and the second sub-electrode 141 located on the same side of the grid 121, the following multiple embodiments exist:
[0042] In one implementation, such as Figure 1 As shown, the first sub-electrode 143 located on the left side of the grid 121 and the first sub-electrode 143 located on the right side of the grid 121 are arranged in the same row. Similarly, the second sub-electrode 141 located on the left side of the grid 121 and the second sub-electrode 141 located on the right side of the grid 121 are arranged in the same row. Thus, when connecting the first sub-electrode 143 and the second sub-electrode 141, the first sub-electrode 143 and the second sub-electrode 141 connected by the connecting bridge 150 are both located on the same side of the grid 121. In this way, the span of the connecting bridge 150 is shorter. Since the connecting bridge 150 spans the grid finger and the drain finger, it will overlap with the grid finger and the drain finger to a certain extent, thereby generating a smaller inductance and parasitic capacitance.
[0043] In another implementation, such as Figure 2 As shown, the first sub-electrode 143 located on the left side of the grid 121 and the first sub-electrode 143 located on the right side of the grid 121 are staggered. Similarly, the second sub-electrode 141 located on the left side of the grid 121 and the second sub-electrode 141 located on the right side of the grid 121 are also staggered. Thus, when connecting the first sub-electrode 143 and the second sub-electrode 141, the first sub-electrode 143 and the second sub-electrode 141 connected by the connecting bridge 150 can also be located on the same side of the grid 121.
[0044] In another embodiment, when only the grid 121 exists between the first sub-electrode 143 and the second sub-electrode 141 located on opposite sides of the grid 121, the connecting bridge 150 for connecting the first sub-electrode 143 and the second sub-electrode 141 only spans across the grid 121; in other words, as shown... Figure 3 As shown, the first sub-electrode 143 located on the left side of the grid 121 and the first sub-electrode 143 located on the right side of the grid 121 are staggered. Similarly, the second sub-electrode 141 located on the left side of the grid 121 and the second sub-electrode 141 located on the right side of the grid 121 are also staggered, so that only the grid 121 exists between the first sub-electrode 143 and the second sub-electrode 141 located on opposite sides of the grid 121. At this time, when connecting the first sub-electrode 143 and the second sub-electrode 141, the first sub-electrode 143 and the second sub-electrode 141 connected by the connecting bridge 150 can be located in the same row, and the first sub-electrode 143 and the second sub-electrode 141 in the same row are located on the left and right sides of the grid 121, respectively. In this way, the span of the connecting bridge 150 can be further shortened, and the inductance can be further reduced. At the same time, since the connecting bridge 150 only spans the grid 121, it does not need to be connected to the aforementioned Figure 1 and Figure 2 As in the illustrated embodiment, it is necessary to span the gate finger and drain finger 131, thus enabling further reduction of parasitic capacitance, especially source-drain parasitic capacitance.
[0045] It should be noted that, in combination Figures 1 to 3 As shown, since the sum of the number of first sub-electrodes 143 and second sub-electrodes 141 located on the same side of the grid 121 is odd, even if one of the two second sub-electrodes 141 in the first row is set as the first sub-electrode 143, the overall area of the device will not be reduced. Therefore, the source hole 142 of the second sub-electrodes 141 in the first row is not removed.
[0046] In another implementation, combined with Figure 4 As shown, the first sub-electrode 143 located on the left side of the grid 121 and the first sub-electrode 143 located on the right side of the grid 121 are staggered. Similarly, the second sub-electrode 141 located on the left side of the grid 121 and the second sub-electrode 141 located on the right side of the grid 121 are also staggered. The total number of the first sub-electrode 143 and the second sub-electrode 141 located on the same side of the grid 121 is even. Therefore, when connecting the first sub-electrode 143 and the second sub-electrode 141, the first sub-electrode 143 and the second sub-electrode 141 connected by the connecting bridge 150 can be located in the same row, and the first sub-electrode 143 and the second sub-electrode 141 in the same row are located on the left and right sides of the grid 121, respectively. In this way, the span of the connecting bridge 150 can be further shortened, the inductance and parasitic capacitance can be further reduced, and the source-drain parasitic capacitance can be reduced, especially the source-drain parasitic capacitance. Based on this, since the sum of the number of first sub-electrodes 143 and second sub-electrodes 141 located on the same side of the grid 121 is an even number, each row consists of first sub-electrodes 143 and second sub-electrodes 141, thus effectively reducing the area of the device.
[0047] It should be noted that when the first sub-electrode 143 and the second sub-electrode 141 connected by the same connecting bridge 150 are located on opposite sides of the grid 121, the extension direction of the connecting bridge 150 can be perpendicular to the extension direction of the grid 121 or intersecting with it.
[0048] In some implementations, the connecting bridge 150 is an air bridge.
[0049] In some implementations, the connecting bridge 150 is a medium bridge.
[0050] Optional, such as Figures 1 to 4 As shown, the width W2 of the first sub-electrode 143 along the extension direction of the grid 121 is smaller than the width W1 of the second sub-electrode 141 along the extension direction of the grid 121.
[0051] Optionally, the width of the first sub-electrode 143 extending along the gate 121 is 10% to 90% of the width of the second sub-electrode 141 extending along the gate 121. This ensures the performance of the transistor device while reducing the area occupied by the source structure 140.
[0052] Optionally, the semiconductor device also includes a metal layer disposed in the source hole 142, the metal layer being connected to the second sub-electrode 141, thereby leading the source structure 140 located on the top surface of the functional layer 110 to the bottom surface of the substrate through the metal layer for easy connection.
[0053] In another aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided for fabricating any of the above-mentioned semiconductor devices. In this way, by eliminating the source hole 142 on the first sub-electrode 143, the width of the first sub-electrode 143 can be reduced, thereby reducing the area occupied by the entire source structure 140, so that the entire device can effectively reduce the area and manufacturing cost. The lead-out of the first sub-electrode 143 can be connected to the second sub-electrode 141 by the connecting bridge 150, and the source hole 142 covered by the second sub-electrode 141 is led out to the bottom surface of the substrate.
[0054] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor device, characterized in that, include: A substrate and a functional layer located on the substrate, wherein a source structure, a drain structure and a fishbone gate structure are disposed on the top surface of the functional layer, and the source structure and the drain structure are used in conjunction with the fishbone gate structure to form multiple transistor devices; A source hole is formed on the bottom surface of the substrate, extending from the bottom surface of the substrate to the top surface of the functional layer; The source structure includes a first sub-electrode and a second sub-electrode covering the source hole located on the top surface of the functional layer. The first sub-electrode is electrically connected to the second sub-electrode via a connecting bridge.
2. The semiconductor device as claimed in claim 1, characterized in that, The fishbone grid structure includes a grid bone and a plurality of grid fingers connected to the grid bone and distributed on opposite sides of the grid bone, wherein the plurality of grid fingers are divided into two groups; The drain structure includes multiple drain fingers distributed on opposite sides of the grid; The source structure includes a plurality of first sub-electrodes distributed on opposite sides of the grid and a plurality of second sub-electrodes distributed on opposite sides of the grid; In one group, the first sub-electrode and the drain finger are distributed on opposite sides of each of the gate fingers, and in another group, the second sub-electrode and the drain finger are distributed on opposite sides of each of the gate fingers.
3. The semiconductor device as described in claim 2, characterized in that, The first sub-electrode and the second sub-electrode, located on the same side of the grid, are alternately distributed.
4. The semiconductor device as described in claim 3, characterized in that, The first sub-electrode and the second sub-electrode, located on the same side of the grid, are electrically connected through the connecting bridge.
5. The semiconductor device as described in claim 3, characterized in that, When the first sub-electrode and the second sub-electrode located on opposite sides of the grid have only the grid, the connecting bridge for connecting the first sub-electrode and the second sub-electrode only spans across the grid.
6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The connecting bridge is an air bridge or a medium bridge.
7. The semiconductor device according to any one of claims 2 to 5, characterized in that, The width of the first sub-electrode along the extension direction of the grid is smaller than the width of the second sub-electrode along the extension direction of the grid.
8. The semiconductor device as claimed in claim 7, characterized in that, The width of the first sub-electrode along the extension direction of the grid is 10% to 90% of the width of the second sub-electrode along the extension direction of the grid.
9. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes a metal layer disposed in the source aperture, the metal layer being connected to the second sub-electrode.