LVDS multi-channel driver

Abstract

The present application is applicable to the field of signal transmission technology and provides an LVDS multi-channel driver, including a buffer circuit and a multi-channel driver circuit; the multi-channel driver circuit includes a plurality of dual-loop negative feedback LVDS driver circuits; the buffer circuit is electrically connected to each of the dual-loop negative feedback LVDS driver circuits; the buffer circuit is used to receive a target signal, enhance the voltage of the target signal, and transmit the enhanced target signal to each of the dual-loop negative feedback LVDS driver circuits; each of the dual-loop negative feedback LVDS driver circuits is used to increase the operating frequency of the enhanced target signal and output a high-speed differential LVDS signal according to the enhanced target signal. The LVDS multi-channel driver provided in the embodiment of the present application can solve the problem that existing high-speed drivers cannot achieve multi-channel transmission.

Description

Technical Field

[0001] The present application relates to the field of signal transmission technology, and in particular to an LVDS multi-channel driver. Background Art

[0002] With the rapid development of information technology, CPU (central processing unit) clock frequencies are increasing, processing speeds are accelerating, and massive amounts of data are being transmitted between various devices. However, during signal transmission, the high-speed signals within the CPU chip are weak and susceptible to interference. High-speed drivers are often used to increase the signal driving capability and transmit the signals to a signal receiver, allowing the device to receive the data sent by the CPU. However, existing high-speed drivers can only achieve single-channel transmission and are unable to achieve multi-channel transmission. Summary of the Invention

[0003] An embodiment of the present application provides an LVDS (Low-Voltage Differential Signaling) multi-channel driver, which can solve the problem that existing high-speed drivers cannot achieve multi-channel transmission.

[0004] In a first aspect, an embodiment of the present application provides an LVDS multi-channel driver, comprising a buffer circuit and a multi-channel driving circuit;

[0005] The multi-channel driving circuit includes a plurality of dual-loop negative feedback LVDS driving circuits;

[0006] The buffer circuit is electrically connected to each of the dual-loop negative feedback LVDS driving circuits respectively;

[0007] The buffer circuit is used to receive a target signal, enhance the voltage of the target signal, and transmit the enhanced target signal to each of the dual-loop negative feedback LVDS driving circuits;

[0008] Each of the dual-loop negative feedback LVDS driving circuits is used to increase the operating frequency of the enhanced target signal and output a high-speed differential LVDS signal according to the enhanced target signal.

[0009] In a possible implementation of the first aspect, the buffer circuit includes a first buffer branch, a second buffer branch, and a phase adjustment circuit;

[0010] The first buffer branch is electrically connected to each of the dual-loop negative feedback LVDS driving circuits, and is used to receive the first signal in the target signal, enhance the voltage of the first signal, and transmit the enhanced first signal to each of the dual-loop negative feedback LVDS driving circuits;

[0011] The second buffer branch is electrically connected to each of the dual-loop negative feedback LVDS driving circuits, and is used to receive the second signal in the target signal, enhance the voltage of the second signal, and transmit the enhanced second signal to each of the dual-loop negative feedback LVDS driving circuits;

[0012] The first signal and the second signal are full-swing clock signals or data signals with opposite phases;

[0013] The phase adjustment circuit is electrically connected to the first buffer branch and the second buffer branch respectively, and is used to adjust the phase relationship between the first signal and the second signal.

[0014] In a possible implementation of the first aspect, the first buffer branch includes a first inverter, a third inverter, and a seventh inverter;

[0015] The input end of the first inverter is used to receive the first signal, the output end of the first inverter is electrically connected to the input end of the third inverter, the output end of the third inverter is electrically connected to the input end of the seventh inverter, and the output end of the seventh inverter is electrically connected to each of the dual-loop negative feedback LVDS driving circuits.

[0016] In a possible implementation of the first aspect, the second buffer branch includes a second inverter, a fourth inverter, and an eighth inverter;

[0017] The input end of the second inverter is used to receive the second signal, the output end of the second inverter is electrically connected to the input end of the fourth inverter, the output end of the fourth inverter is electrically connected to the input end of the eighth inverter, and the output end of the eighth inverter is electrically connected to each of the dual-loop negative feedback LVDS driving circuits.

[0018] In a possible implementation of the first aspect, the phase adjustment circuit includes a fifth inverter and a sixth inverter;

[0019] The input end of the fifth inverter is electrically connected to the output end of the third inverter, the output end of the fifth inverter is electrically connected to the output end of the fourth inverter, the input end of the sixth inverter is electrically connected to the output end of the fourth inverter, and the output end of the sixth inverter is electrically connected to the output end of the third inverter.

[0020] In a possible implementation of the first aspect, each of the dual-loop negative feedback LVDS driving circuits includes a first negative feedback circuit, a second negative feedback circuit, and a driving output circuit;

[0021] The first negative feedback circuit and the second negative feedback circuit are both electrically connected to the drive output circuit, the first negative feedback circuit is electrically connected to the second negative feedback circuit, and the output end of the seventh inverter and the output end of the eighth inverter are both electrically connected to the drive output circuit;

[0022] The first negative feedback circuit is used to receive a first bias voltage and output a first voltage to the drive output circuit according to the first bias voltage, wherein the first voltage is equal to the first bias voltage;

[0023] The second negative feedback circuit is used to receive a second bias voltage and output a second voltage to the drive output circuit according to the second bias voltage, wherein the second voltage is equal to the second bias voltage;

[0024] The driver output circuit is used to receive the enhanced first signal and the enhanced second signal. The enhanced first signal and the enhanced second signal trigger the driver output circuit to operate. When the driver output circuit is operating, the driver output circuit is used to output a high-speed differential LVDS signal according to the first voltage and the second voltage.

[0025] In a possible implementation of the first aspect, the first negative feedback circuit includes a first operational amplifier, a first tail current source, a seventh field-effect transistor, a third capacitor, a ninth field-effect transistor, and a first capacitor; the first tail current source is a fifth field-effect transistor;

[0026] The inverting input terminal of the first operational amplifier is used to receive the first bias voltage. The non-inverting input terminal of the first operational amplifier is electrically connected to the drain of the fifth field-effect transistor, the first terminal of the first capacitor, the gate of the ninth field-effect transistor, and the drive output circuit, respectively. The output terminal of the first operational amplifier is electrically connected to the gate of the seventh field-effect transistor, the gate of the fifth field-effect transistor, and the first terminal of the third capacitor, respectively. The second terminal of the third capacitor is electrically connected to the source of the ninth field-effect transistor. The source of the seventh field-effect transistor, the source of the fifth field-effect transistor, the drain of the ninth field-effect transistor, and the second terminal of the first capacitor are all electrically connected to a first power supply. The drain of the seventh field-effect transistor and the source of the ninth field-effect transistor are both electrically connected to the second negative feedback circuit.

[0027] The drain of the fifth field effect transistor is used to output the first voltage;

[0028] The first operational amplifier is used to adjust the gate voltage of the fifth field-effect transistor and control the drain current output by the fifth field-effect transistor so that the first voltage is equal to the first bias voltage;

[0029] The first capacitor is used to stabilize the first voltage;

[0030] The seventh field effect transistor, the ninth field effect transistor and the third capacitor are used to adjust the operating frequency of the first negative feedback circuit to prevent the first negative feedback circuit from oscillating.

[0031] In a possible implementation of the first aspect, the second negative feedback circuit includes a second operational amplifier, a second tail current source, an eighth field-effect transistor, a tenth field-effect transistor, a second capacitor, and a fourth capacitor; the second tail current source is a sixth field-effect transistor;

[0032] The inverting input terminal of the second operational amplifier is used to receive the second bias voltage. The non-inverting input terminal of the second operational amplifier is electrically connected to the drain of the sixth field-effect transistor, the first terminal of the second capacitor, the gate of the eighth field-effect transistor, and the drive output circuit, respectively. The output terminal of the second operational amplifier is electrically connected to the gate of the tenth field-effect transistor, the gate of the sixth field-effect transistor, and the first terminal of the fourth capacitor, respectively. The second terminal of the fourth capacitor is electrically connected to the source of the eighth field-effect transistor. The source of the tenth field-effect transistor, the source of the sixth field-effect transistor, the drain of the eighth field-effect transistor, and the second terminal of the second capacitor are all grounded. The source of the eighth field-effect transistor is electrically connected to the drain of the seventh field-effect transistor, and the drain of the tenth field-effect transistor is electrically connected to the source of the ninth field-effect transistor.

[0033] The drain of the sixth field effect transistor is used to output the second voltage;

[0034] The second operational amplifier is used to adjust the gate voltage of the sixth field-effect transistor and control the drain current output by the sixth field-effect transistor so that the second voltage is equal to the second bias voltage;

[0035] The second capacitor is used to stabilize the second voltage;

[0036] The eighth field-effect transistor, the tenth field-effect transistor, and the fourth capacitor are used to adjust the operating frequency of the second negative feedback circuit to prevent the second negative feedback circuit from oscillating.

[0037] In a possible implementation of the first aspect, the drive output circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first buffer, and a second buffer;

[0038] The gate of the third field-effect transistor is electrically connected to the gate of the fourth field-effect transistor, serving as a first signal input terminal; the gate of the first field-effect transistor is electrically connected to the gate of the second field-effect transistor, serving as a second signal input terminal; the output terminal of the seventh inverter is electrically connected to the input terminal of the second buffer, and the output terminal of the second buffer is electrically connected to the first signal input terminal; the output terminal of the eighth inverter is electrically connected to the input terminal of the first buffer, and the output terminal of the first buffer is electrically connected to the second signal input terminal; the source of the first field-effect transistor is electrically connected to the source of the third field-effect transistor and the drain of the fifth field-effect transistor respectively; the source of the second field-effect transistor is electrically connected to the source of the fourth field-effect transistor and the drain of the sixth field-effect transistor respectively; the drain of the third field-effect transistor and the drain of the fourth field-effect transistor are electrically connected as a first output terminal; the drain of the first field-effect transistor and the drain of the second field-effect transistor are electrically connected as a second output terminal; the first output terminal is used to be electrically connected to the first terminal of a terminal resistor, and the second output terminal is used to be electrically connected to the second terminal of the terminal resistor, and the two ends of the terminal resistor output a high-speed differential LVDS signal.

[0039] In a possible implementation of the first aspect, the first field effect transistor and the third field effect transistor are P-channel field effect transistors, and the second field effect transistor and the fourth field effect transistor are N-channel field effect transistors.

[0040] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0041] An embodiment of the present application provides an LVDS multi-channel driver, comprising a buffer circuit and a multi-channel driving circuit. The multi-channel driving circuit is composed of a plurality of dual-loop negative feedback LVDS driving circuits, and the number of channels thereof can be set according to actual needs. The buffer circuit is electrically connected to each dual-loop negative feedback LVDS driving circuit respectively. When the CPU transmits data to the target device, the voltage of the target signal is first enhanced through the buffer circuit to improve the driving ability of the target signal, so that the target signal is not easily interfered with, and the enhanced target signal is transmitted to each dual-loop negative feedback LVDS driving circuit respectively. The dual-loop negative feedback LVDS driving circuit can increase the operating frequency of the enhanced target signal and output a high-speed differential LVDS signal according to the enhanced target signal. The plurality of dual-loop negative feedback LVDS driving circuits output a plurality of high-speed differential LVDS signals according to the enhanced target signal respectively, and stably and reliably transmit the plurality of high-speed differential LVDS signals to a plurality of target devices, so that the plurality of target devices receive the data sent by the CPU at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 This is a schematic diagram of the structure of an LVDS multi-channel driver provided by an embodiment of the present application;

[0044] Figure 2 1 is a schematic structural diagram of an LVDS multi-channel driver provided by another embodiment of the present application;

[0045] Figure 3 1 is a schematic structural diagram of an LVDS multi-channel driver provided by another embodiment of the present application;

[0046] Figure 4 This is a schematic diagram showing the connection between a buffer circuit and a dual-loop negative feedback LVDS driver circuit provided by another embodiment of the present application;

[0047] Figure 5 This is a schematic diagram of the connection between a buffer circuit and a dual-loop negative feedback LVDS drive circuit provided by another embodiment of the present application. DETAILED DESCRIPTION

[0048] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0049] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0050] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0051] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0052] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0053] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0054] like Figure 1 As shown, an embodiment of the present application provides an LVDS multi-channel driver, including a buffer circuit 1 and a multi-channel driving circuit 3. The multi-channel driving circuit 3 includes multiple dual-loop negative feedback LVDS driving circuits 30, and the buffer circuit 1 is electrically connected to each dual-loop negative feedback LVDS driving circuit 30.

[0055] The plurality of dual-loop negative feedback LVDS driving circuits 30 correspond to channel 1, channel 2, ..., channel n, respectively, where n is an integer greater than 1, and the number of channels can be set according to actual needs.

[0056] Specifically, when the CPU transmits data to a target device, the buffer circuit 1 receives the target signals VINP / VINN and boosts the voltage of the target signals VINP / VINN, improving the drive capability of the target signals VINP / VINN and making them less susceptible to interference. The boosted target signals VINP / VINN are then transmitted to each dual-loop negative feedback LVDS driver circuit 30.

[0057] The dual-loop negative feedback LVDS driving circuit 30 can increase the operating frequency of the enhanced target signals VINP / VINN and output high-speed differential LVDS signals VOUTnP / VOUTnN corresponding to the channels according to the enhanced target signals VINP / VINN.

[0058] Multiple dual-loop negative feedback LVDS driver circuits 30 output multiple high-speed differential LVDS signals based on the enhanced target signal, and simultaneously transmit the multiple high-speed differential LVDS signals to multiple target devices, allowing the multiple target devices to simultaneously receive data sent by the CPU. The multiple high-speed differential LVDS signals are respectively high-speed differential LVDS signals VOUT1P / VOUT1N, high-speed differential LVDS signals VOUT2P / VOUT2N, ..., and high-speed differential LVDS signals VOUTnP / VOUTnN.

[0059] like Figure 2 As shown, the buffer circuit 1 includes a first buffer branch 10, a second buffer branch 11, and a phase adjustment circuit 12. The first buffer branch 10 is electrically connected to each dual-loop negative feedback LVDS driver circuit 30. The second buffer branch 12 is electrically connected to each dual-loop negative feedback LVDS driver circuit 30. The phase adjustment circuit 11 is electrically connected to the first buffer branch 10 and the second buffer branch 12.

[0060] Specifically, the first buffer branch 10 receives the first signal VINP of the target signals VINP / VINN and boosts the voltage of the first signal VINP, thereby improving the driving capability of the first signal VINP and making the first signal VINP less susceptible to interference. The boosted first signal VINP is then transmitted to each dual-loop negative feedback LVDS driver circuit 30.

[0061] The second buffer branch 12 receives the second signal VINN in the target signal VINP / VINN and boosts the voltage of the second signal VINN, thereby improving the driving capability of the second signal VINN and making the second signal VINN less susceptible to interference. The boosted second signal VINN is then transmitted to each dual-loop negative feedback LVDS driver circuit 30.

[0062] The phase adjustment circuit 11 adjusts the phase relationship between the first signal VINP and the second signal VINN to achieve a better differential relationship between the first signal VINP and the second signal VINN, wherein the first signal VINP and the second signal VINN are full-swing clock signals or data signals with opposite phases.

[0063] like Figure 3As shown, the first buffer branch 10 includes a first inverter 101, a third inverter 103, and a seventh inverter 107. The input of the first inverter 101 receives the first signal VINP, the output of the first inverter 101 is electrically connected to the input of the third inverter 103, the output of the third inverter 103 is electrically connected to the input of the seventh inverter 107, and the output of the seventh inverter 107 is electrically connected to each dual-loop negative feedback LVDS driver circuit 30.

[0064] Specifically, the input of first inverter 101 receives first signal VINP. First inverter 101, third inverter 103, and seventh inverter 107 amplify the voltage of first signal VINP, improving the drive capability of first signal VINP and making first signal VINP less susceptible to interference. The output of seventh inverter 107 transmits the amplified voltage of first signal VINP to each dual-loop negative feedback LVDS driver circuit 30.

[0065] like Figure 3 As shown, the second buffer branch 12 includes a second inverter 122, a fourth inverter 124, and an eighth inverter 128. The input of the second inverter 122 receives the second signal VINN, the output of the second inverter 122 is electrically connected to the input of the fourth inverter 124, the output of the fourth inverter 124 is electrically connected to the input of the eighth inverter 128, and the output of the eighth inverter 128 is electrically connected to each dual-loop negative feedback LVDS driver circuit 30.

[0066] Specifically, the input of second inverter 122 receives second signal VINN. Second inverter 122, fourth inverter 124, and eighth inverter 128 amplify the voltage of second signal VINN, improving the drive capability of second signal VINN and making second signal VINN less susceptible to interference. The output of eighth inverter 128 transmits the amplified second signal VINN to each dual-loop negative feedback LVDS driver circuit 30.

[0067] like Figure 3 As shown, the phase adjustment circuit 11 includes a fifth inverter 115 and a sixth inverter 116. The input terminal of the fifth inverter 115 is electrically connected to the output terminal of the third inverter 103, the output terminal of the fifth inverter 115 is electrically connected to the output terminal of the fourth inverter 124, the input terminal of the sixth inverter 116 is electrically connected to the output terminal of the fourth inverter 124, and the output terminal of the sixth inverter 116 is electrically connected to the output terminal of the third inverter 103.

[0068] Specifically, the fifth inverter 115 and the sixth inverter 116 are used to adjust the phase relationship between the first signal VINP and the second signal VINN so that the first signal VINP and the second signal VINN have a better differential relationship, while ensuring that a fixed logic signal is output when no target signal is input.

[0069] like Figure 4 As shown, each dual-loop negative feedback LVDS driver circuit 30 includes a first negative feedback circuit 301, a second negative feedback circuit 303, and a driver output circuit 302. The first negative feedback circuit 301 and the second negative feedback circuit 303 are both electrically connected to the driver output circuit 302, and the first negative feedback circuit 301 is electrically connected to the second negative feedback circuit 303. The output end of the seventh inverter 107 and the output end of the eighth inverter 128 are both electrically connected to the driver output circuit 302.

[0070] Specifically, the first negative feedback circuit 301 receives the first bias voltage VREF_H, and outputs a first voltage to the driving output circuit 302 according to the first bias voltage VREF_H, where the first voltage is equal to the first bias voltage VREF_H.

[0071] The second negative feedback circuit receives the second bias voltage VREF_L and outputs a second voltage to the driving output circuit 302 according to the second bias voltage VREF_L. The second voltage is equal to the second bias voltage VREF_L.

[0072] The driver output circuit 302 receives the enhanced first signal VINP and the enhanced second signal VINN, which trigger the driver output circuit 302 to operate. When the driver output circuit 302 operates, the driver output circuit 302 outputs high-speed differential LVDS signals VOUTnP / VOUTnN based on the first voltage and the second voltage.

[0073] Exemplarily, the first bias voltage VREF_H and the second bias voltage VREF_L are both generated by a bias circuit, and the bias circuit can be implemented by dividing the power supply voltage with resistors.

[0074] like Figure 5As shown, the first negative feedback circuit 301 includes a first operational amplifier 3011, a first tail current source, a seventh field-effect transistor M7, a third capacitor C3, a ninth field-effect transistor M9, and a first capacitor C1. The first tail current source is the fifth field-effect transistor M5. The inverting input terminal of the first operational amplifier 3011 is used to receive a first bias voltage VREF_H. The non-inverting input terminal of the first operational amplifier 3011 is electrically connected to the drain of the fifth field-effect transistor M5, the first end of the first capacitor C1, the gate of the ninth field-effect transistor M9, and the driver output circuit 302. The output terminal of the first operational amplifier 3011 is electrically connected to the gate of the seventh field-effect transistor M7, the gate of the fifth field-effect transistor M5, and the first end of the third capacitor C3. The second end of the third capacitor C3 is electrically connected to the source of the ninth field-effect transistor M9. The source of the seventh field effect transistor M7, the source of the fifth field effect transistor M5, the drain of the ninth field effect transistor M9 and the second end of the first capacitor C1 are all used to be electrically connected to the first power supply VDD, and the drain of the seventh field effect transistor M7 and the source of the ninth field effect transistor M9 are both electrically connected to the second negative feedback circuit 303.

[0075] Specifically, the first operational amplifier 3011 and the fifth field-effect transistor M5 form a negative feedback loop. The first operational amplifier 3011 regulates the gate voltage of the fifth field-effect transistor M5, thereby controlling the drain current output by the fifth field-effect transistor M5, ultimately making the first voltage equal to the first bias voltage VREF_H. The first voltage is the voltage at node net1. The first capacitor C1 is used to stabilize the first voltage. The seventh field-effect transistor M7, the ninth field-effect transistor M9, and the third capacitor C3 are used to adjust the operating frequency of the first negative feedback circuit 301 to prevent oscillation of the first negative feedback circuit 301.

[0076] like Figure 5 As shown, the second negative feedback circuit 303 includes a second operational amplifier 3032, a second tail current source, an eighth field-effect transistor M8, a tenth field-effect transistor M10, a second capacitor C2, and a fourth capacitor C4. The second tail current source is the sixth field-effect transistor M6. The inverting input terminal of the second operational amplifier 3032 is used to receive the second bias voltage VREF_L. The non-inverting input terminal of the second operational amplifier 3032 is electrically connected to the drain of the sixth field-effect transistor M6, the first end of the second capacitor C2, the gate of the eighth field-effect transistor M8, and the driver output circuit 302, respectively. The output terminal of the second operational amplifier 3032 is electrically connected to the gate of the tenth field-effect transistor M10, the gate of the sixth field-effect transistor M6, and the first end of the fourth capacitor C4, respectively. The second end of the fourth capacitor C4 is electrically connected to the source of the eighth field-effect transistor M8. The source of the tenth field-effect transistor M10, the source of the sixth field-effect transistor M6, the drain of the eighth field-effect transistor M8, and the second end of the second capacitor C2 are all grounded. The source of the eighth field effect transistor M8 is electrically connected to the drain of the seventh field effect transistor M7 , and the drain of the tenth field effect transistor M10 is electrically connected to the source of the ninth field effect transistor M9 .

[0077] Specifically, the second operational amplifier 3032 and the sixth field-effect transistor M6 form a negative feedback loop. The second operational amplifier 3032 regulates the gate voltage of the sixth field-effect transistor M6, thereby controlling the drain current output by the sixth field-effect transistor M6, ultimately making the second voltage equal to the second bias voltage VREF_L. The second voltage is the voltage at node net2. The second capacitor C2 is used to stabilize the second voltage. The eighth field-effect transistor M8, the tenth field-effect transistor M10, and the fourth capacitor C4 are used to adjust the operating frequency of the second negative feedback circuit 303 to prevent oscillation of the second negative feedback circuit 303.

[0078] like Figure 5 As shown, the driver output circuit 302 includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a first buffer 3021, and a second buffer 3022. The gate of the third field-effect transistor (FET) M3 is electrically connected to the gate of the fourth field-effect transistor (FET) M4, serving as a first signal input. The gate of the first field-effect transistor (FET) M1 is electrically connected to the gate of the second field-effect transistor (FET) M2, serving as a second signal input. The output of the seventh inverter 107 is electrically connected to the input of the second buffer 3022, and the output of the second buffer 3022 is electrically connected to the first signal input. The output of the eighth inverter 128 is electrically connected to the input of the first buffer 3021, and the output of the first buffer 3021 is electrically connected to the second signal input. The source of the first field-effect transistor (FET) M1 is electrically connected to the source of the third field-effect transistor (FET) M3 and the drain of the fifth field-effect transistor (FET) M5, respectively. The source of the second field-effect transistor M2 is electrically connected to the source of the fourth field-effect transistor M4 and the drain of the sixth field-effect transistor M6, respectively. The drain of the third field-effect transistor M3 is electrically connected to the drain of the fourth field-effect transistor M4, serving as a first output terminal. The drain of the first field-effect transistor M1 is electrically connected to the drain of the second field-effect transistor M2, serving as a second output terminal. The first output terminal is electrically connected to the first terminal of the terminal resistor RT, and the second output terminal is electrically connected to the second terminal of the terminal resistor RT. The two ends of the terminal resistor RT output high-speed differential LVDS signals VOUTnP / VOUTnN.

[0079] Specifically, the first buffer 3021 is used to further improve the driving capability of the enhanced second signal VINN. The second buffer 3022 is used to further improve the driving capability of the enhanced first signal VINP. The enhanced second signal VINN is applied to the gates of the first field-effect transistor M1 and the second field-effect transistor M2 to control the on / off switching of the first field-effect transistor M1 and the on / off switching of the second field-effect transistor M2. When the first field-effect transistor M1 is on and the second field-effect transistor M2 is off, the source-drain voltage of the first field-effect transistor M1 is subtracted from the first voltage to obtain the high-level value of the high-speed differential LVDS signal VOUTnN. When the first field-effect transistor M1 is off and the second field-effect transistor M2 is on, the source-drain voltage of the second field-effect transistor M2 is added to the second voltage to obtain the low-level value of the high-speed differential LVDS signal VOUTnN. The amplified first signal VINP is applied to the gates of the third and fourth field-effect transistors M3 and M4 to control the on / off switching of the third and fourth field-effect transistors M3 and M4. When the third field-effect transistor M3 is on and the fourth field-effect transistor M4 is off, the source-drain voltage of the third field-effect transistor M3 is subtracted from the first voltage to produce the high-level value of the high-speed differential LVDS signal VOUTnP. When the third field-effect transistor M4 is on and the third field-effect transistor M3 is off, the source-drain voltage of the fourth field-effect transistor M4 is added to the second voltage to produce the low-level value of the high-speed differential LVDS signal VOUTnP. Ultimately, the high-speed differential LVDS signals VOUTnP / VOUTnN are output across the termination resistor RT.

[0080] Exemplarily, the first field effect transistor M1 and the third field effect transistor M3 are P-channel field effect transistors, and the second field effect transistor M2 and the fourth field effect transistor M4 are N-channel field effect transistors.

[0081] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0082] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. An LVDS multi-channel driver, characterized in that: Including a buffer circuit and a multi-channel driving circuit; The multi-channel driving circuit includes a plurality of dual-loop negative feedback LVDS driving circuits; The buffer circuit is electrically connected to each of the dual-loop negative feedback LVDS driving circuits respectively; The buffer circuit is used to receive a target signal, enhance the voltage of the target signal, and transmit the enhanced target signal to each of the dual-loop negative feedback LVDS driving circuits; Each of the dual-loop negative feedback LVDS driving circuits is used to increase the operating frequency of the enhanced target signal and output a high-speed differential LVDS signal according to the enhanced target signal; The buffer circuit includes a first buffer branch, a second buffer branch and a phase adjustment circuit; The first buffer branch is electrically connected to each of the dual-loop negative feedback LVDS driving circuits, and is used to receive the first signal in the target signal; The second buffer branch is electrically connected to each of the dual-loop negative feedback LVDS driving circuits, and is used to receive the second signal in the target signal; The first buffer branch includes a first inverter, a third inverter and a seventh inverter; The input end of the first inverter is used to receive the first signal, the output end of the first inverter is electrically connected to the input end of the third inverter, the output end of the third inverter is electrically connected to the input end of the seventh inverter, and the output end of the seventh inverter is electrically connected to each of the dual-loop negative feedback LVDS driving circuits; The second buffer branch includes a second inverter, a fourth inverter and an eighth inverter; The input end of the second inverter is used to receive the second signal, the output end of the second inverter is electrically connected to the input end of the fourth inverter, the output end of the fourth inverter is electrically connected to the input end of the eighth inverter, and the output end of the eighth inverter is electrically connected to each of the dual-loop negative feedback LVDS driving circuits; Each of the dual-loop negative feedback LVDS driving circuits includes a first negative feedback circuit, a second negative feedback circuit and a driving output circuit; The first negative feedback circuit and the second negative feedback circuit are both electrically connected to the drive output circuit, the first negative feedback circuit is electrically connected to the second negative feedback circuit, and the output end of the seventh inverter and the output end of the eighth inverter are both electrically connected to the drive output circuit; The first negative feedback circuit is used to receive a first bias voltage and output a first voltage to the drive output circuit according to the first bias voltage, wherein the first voltage is equal to the first bias voltage; The second negative feedback circuit is used to receive a second bias voltage and output a second voltage to the drive output circuit according to the second bias voltage, wherein the second voltage is equal to the second bias voltage; The driver output circuit is used to receive an enhanced first signal and an enhanced second signal, and the enhanced first signal and the enhanced second signal trigger the driver output circuit to operate. When the driver output circuit is operating, the driver output circuit is used to output a high-speed differential LVDS signal according to the first voltage and the second voltage.

2. The LVDS multi-channel driver according to claim 1, wherein: The first signal and the second signal are full-swing clock signals or data signals with opposite phases; The phase adjustment circuit is electrically connected to the first buffer branch and the second buffer branch respectively, and is used to adjust the phase relationship between the first signal and the second signal; The phase adjustment circuit includes a fifth inverter and a sixth inverter; The input end of the fifth inverter is electrically connected to the output end of the third inverter, the output end of the fifth inverter is electrically connected to the output end of the fourth inverter, the input end of the sixth inverter is electrically connected to the output end of the fourth inverter, and the output end of the sixth inverter is electrically connected to the output end of the third inverter.

3. The LVDS multi-channel driver according to claim 1, wherein: The first negative feedback circuit includes a first operational amplifier, a first tail current source, a seventh field effect transistor, a third capacitor, a ninth field effect transistor and a first capacitor; the first tail current source is a fifth field effect transistor; The inverting input terminal of the first operational amplifier is used to receive the first bias voltage. The non-inverting input terminal of the first operational amplifier is electrically connected to the drain of the fifth field-effect transistor, the first terminal of the first capacitor, the gate of the ninth field-effect transistor, and the drive output circuit, respectively. The output terminal of the first operational amplifier is electrically connected to the gate of the seventh field-effect transistor, the gate of the fifth field-effect transistor, and the first terminal of the third capacitor, respectively. The second terminal of the third capacitor is electrically connected to the source of the ninth field-effect transistor. The source of the seventh field-effect transistor, the source of the fifth field-effect transistor, the drain of the ninth field-effect transistor, and the second terminal of the first capacitor are all electrically connected to a first power supply. The drain of the seventh field-effect transistor and the source of the ninth field-effect transistor are both electrically connected to the second negative feedback circuit. The drain of the fifth field effect transistor is used to output the first voltage; The first operational amplifier is used to adjust the gate voltage of the fifth field-effect transistor and control the drain current output by the fifth field-effect transistor so that the first voltage is equal to the first bias voltage; The first capacitor is used to stabilize the first voltage; The seventh field effect transistor, the ninth field effect transistor and the third capacitor are used to adjust the operating frequency of the first negative feedback circuit to prevent the first negative feedback circuit from oscillating.

4. The LVDS multi-channel driver according to claim 3, wherein: The second negative feedback circuit includes a second operational amplifier, a second tail current source, an eighth field effect transistor, a tenth field effect transistor, a second capacitor and a fourth capacitor; the second tail current source is a sixth field effect transistor; The inverting input terminal of the second operational amplifier is used to receive the second bias voltage. The non-inverting input terminal of the second operational amplifier is electrically connected to the drain of the sixth field-effect transistor, the first terminal of the second capacitor, the gate of the eighth field-effect transistor, and the drive output circuit, respectively. The output terminal of the second operational amplifier is electrically connected to the gate of the tenth field-effect transistor, the gate of the sixth field-effect transistor, and the first terminal of the fourth capacitor, respectively. The second terminal of the fourth capacitor is electrically connected to the source of the eighth field-effect transistor. The source of the tenth field-effect transistor, the source of the sixth field-effect transistor, the drain of the eighth field-effect transistor, and the second terminal of the second capacitor are all grounded. The source of the eighth field-effect transistor is electrically connected to the drain of the seventh field-effect transistor, and the drain of the tenth field-effect transistor is electrically connected to the source of the ninth field-effect transistor. The drain of the sixth field effect transistor is used to output the second voltage; The second operational amplifier is used to adjust the gate voltage of the sixth field-effect transistor and control the drain current output by the sixth field-effect transistor so that the second voltage is equal to the second bias voltage; The second capacitor is used to stabilize the second voltage; The eighth field-effect transistor, the tenth field-effect transistor, and the fourth capacitor are used to adjust the operating frequency of the second negative feedback circuit to prevent the second negative feedback circuit from oscillating.

5. The LVDS multi-channel driver according to claim 4, wherein: The driving output circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first buffer and a second buffer; The gate of the third field-effect transistor is electrically connected to the gate of the fourth field-effect transistor, serving as a first signal input terminal; the gate of the first field-effect transistor is electrically connected to the gate of the second field-effect transistor, serving as a second signal input terminal; the output terminal of the seventh inverter is electrically connected to the input terminal of the second buffer, and the output terminal of the second buffer is electrically connected to the first signal input terminal; the output terminal of the eighth inverter is electrically connected to the input terminal of the first buffer, and the output terminal of the first buffer is electrically connected to the second signal input terminal; the source of the first field-effect transistor is electrically connected to the source of the third field-effect transistor and the drain of the fifth field-effect transistor respectively; the source of the second field-effect transistor is electrically connected to the source of the fourth field-effect transistor and the drain of the sixth field-effect transistor respectively; the drain of the third field-effect transistor and the drain of the fourth field-effect transistor are electrically connected as a first output terminal; the drain of the first field-effect transistor and the drain of the second field-effect transistor are electrically connected as a second output terminal; the first output terminal is used to be electrically connected to the first terminal of a terminal resistor, and the second output terminal is used to be electrically connected to the second terminal of the terminal resistor, and the two ends of the terminal resistor output a high-speed differential LVDS signal.

6. The LVDS multi-channel driver according to claim 5, wherein: The first field effect transistor and the third field effect transistor are P-channel field effect transistors, and the second field effect transistor and the fourth field effect transistor are N-channel field effect transistors.

Images