A power-on detection circuit and a detection method

Abstract

Embodiments of the present application provide a power-on detection circuit and a detection method, the power-on detection circuit comprising an input unit, a switching unit and an output unit connected in sequence; the input unit comprises a first input power supply and a second input power supply, and the switching unit comprises a first MOS tube and a second MOS tube; the drain of the first MOS tube is connected to the gate of the second MOS tube, the source of the second MOS tube is grounded, the first input power supply is connected to the source of the first MOS tube, and the second input power supply is connected to the drain of the second MOS tube and the output unit respectively; the first MOS tube and the second MOS tube change the on-off state according to the voltage signals provided by the first input power supply and the second input power supply; and the output unit is used for outputting a power-on detection signal according to the on-off state of the second MOS tube, realizing power-on detection of multiple voltage values, and the circuit design is simple and the use cost is low.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a power-on detection circuit and detection method. Background Technology

[0002] In the field of circuit design, the design of power-on detection circuits is becoming increasingly important. For example, for some automated equipment, after mechanical installation and electrical wiring are completed, the mechatronic equipment faces the step of powering on. Powering on must follow a specific procedure; adhering to this procedure step by step can reduce the risk of burning out critical components and unnecessary losses due to errors by fitters or electricians. Furthermore, power-on detection for localized systems and computer equipment ensures the safe operation of these systems and devices, preventing unnecessary losses.

[0003] However, conventional power-on detection circuits can only detect a single voltage. If there is a need to detect multiple voltage values, the circuit needs to be redesigned, which is not only limited but also complex and variable, resulting in low practicality. Summary of the Invention

[0004] In view of this, one of the objectives of this application is to provide a power-on detection circuit and a power-on detection method, which at least solves some of the above-mentioned technical problems.

[0005] In a first aspect, embodiments of this application provide a power-on detection circuit, which includes an input unit, a switching unit, and an output unit connected in sequence, wherein...

[0006] The input unit includes a first input power supply and a second input power supply, and the switching unit includes a first MOSFET and a second MOSFET.

[0007] The drain of the first MOSFET is connected to the gate of the second MOSFET, the source of the second MOSFET is grounded, the first input power supply is connected to the source of the first MOSFET, and the second input power supply is connected to the drain of the second MOSFET and the output unit, respectively.

[0008] The first MOSFET and the second MOSFET change their on / off states according to the voltage signals provided by the first input power supply and the second input power supply. The output unit is used to output a power-on detection signal according to the on / off state of the second MOSFET.

[0009] In one possible implementation, the input unit further includes a third input power supply, and the switching unit further includes a third MOS transistor, wherein the third MOS transistor is a P-channel MOS transistor;

[0010] The third input power supply is connected to the gate of the third MOS transistor;

[0011] The source of the third MOS transistor is connected to the gate of the first MOS transistor, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor.

[0012] In one possible implementation, the output unit includes a first inverter and a second inverter;

[0013] The input terminal of the first inverter is connected to the second input power supply, and the output terminal of the first inverter is connected to the input terminal of the second inverter.

[0014] Specifically, if the output terminal of the first inverter outputs a high-level signal, then the output terminal of the second inverter outputs a low-level signal; conversely, if the output terminal of the first inverter outputs a low-level signal, then the output terminal of the second inverter outputs a high-level signal.

[0015] In one possible implementation, the power-on detection circuit further includes a step-down circuit, one end of which is connected to the drain of the first MOS transistor, and the other end of which is grounded.

[0016] In one possible implementation, the step-down circuit includes a first resistor, a second resistor, and a third resistor connected in series.

[0017] The first end of the first resistor is connected to the drain of the first MOS transistor, the second end of the first resistor is connected in series with the first end of the second resistor, and the first end of the second resistor is connected to the second end of the first resistor and the gate of the second MOS transistor respectively.

[0018] The first end of the third resistor is connected to the second end of the second resistor and the drain of the third MOS transistor.

[0019] In one possible implementation, the power-on detection circuit further includes a protection circuit, which includes a fourth resistor, a fifth resistor, and a sixth resistor.

[0020] One end of the fourth resistor is connected to the second input power supply, and the other end of the fourth resistor is connected to the drain of the second MOS transistor.

[0021] One end of the fifth resistor is connected to the second end of the third resistor, and the other end of the fifth resistor is grounded;

[0022] One end of the sixth resistor is connected to the third input power supply, and the other end of the sixth resistor is connected to the gate of the third MOS transistor.

[0023] In one possible implementation, the protection circuit further includes a seventh resistor, one end of which is connected to the source of the second MOS transistor, and the other end of which is grounded.

[0024] In one possible implementation, the power-on detection circuit further includes a diode, the anode of which is connected to the gate of the third MOS transistor, and the cathode of which is connected to the source of the third MOS transistor and the gate of the first MOS transistor.

[0025] In one possible implementation, the first MOSFET is a P-channel MOSFET, and the second MOSFET is an N-channel MOSFET.

[0026] Secondly, embodiments of this application provide a power-on detection method, the method comprising:

[0027] The first MOSFET changes its on / off state according to the first voltage of the first input power supply.

[0028] The second MOSFET changes its on / off state according to the second voltage of the second input power supply;

[0029] The output unit outputs a power-on detection signal based on the on / off state of the second MOS transistor.

[0030] This application provides a power-on detection circuit and method, comprising an input unit, a switching unit, and an output unit connected in sequence. The input unit includes a first input power supply and a second input power supply, and the switching unit includes two MOSFETs. The two MOSFETs can change their on / off state according to the voltage signals provided by the two input power supplies. The output unit can output a power-on detection signal according to the on / off state of the MOSFETs, enabling power-on detection of various voltage values. Furthermore, the circuit design is simple and the operating cost is low. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A circuit schematic diagram of a power-on detection circuit provided in an embodiment of this application is shown;

[0033] Figure 2 The diagram shows a circuit schematic of an output unit included in a power-on detection circuit according to an embodiment of this application.

[0034] Figure 3 This illustration shows a schematic diagram of the diode connections involved in a power-on detection circuit provided in an embodiment of this application;

[0035] Figure 4 A flowchart of a power-on detection method provided in an embodiment of this application is shown.

[0036] icon:

[0037] First input power supply 111, second input power supply 112, third input power supply 113, output unit 120;

[0038] The first MOSFET is PMOS1, the second MOSFET is NMOS, and the third MOSFET is PMOS2;

[0039] First inverter U1, second inverter U2, diode D, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0042] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0043] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0044] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0045] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0046] Please refer to Figure 1 The power-on detection circuit includes an input unit, a switching unit, and an output unit 120 connected in sequence, wherein...

[0047] The input unit includes a first input power supply 111 and a second input power supply 112, and the switching unit includes a first MOS transistor PMOS1 and a second MOS transistor NMOS.

[0048] The input unit in this embodiment provides an input power supply, which can provide voltage input to the power-on detection circuit in this embodiment. Specifically, the second input power supply 112 in this embodiment can provide a stable voltage to the powered device, such as a chip, that may be connected in this embodiment. When the power supply requirements of the powered device, such as the chip, change, a new power supply needs to be introduced, namely the first input power supply 111 in this embodiment. The power-on detection of the first and second power supplies can be easily and quickly realized through the switching unit and output unit 120 in this embodiment. Generally, the rated supply voltage of the powered device, such as the chip, is 1.8V. In this embodiment, the second input power supply 112 with a rated voltage of 1.8V can be selected accordingly. Correspondingly, when introducing a new power supply, the first input power supply 111 with a rated voltage switchable between 1.8V and 3.3V can be selected.

[0049] Considering the low cost, low power dissipation, and high efficiency of MOSFETs, they are selected to form the switching unit in this embodiment. Specifically, the switching unit consists of one PMOS and one NMOS transistor; the first MOSFET is a PMOS and the second MOSFET is an NMOS. The switching on and off of the unit affects the power-on detection signal of the output unit 120.

[0050] In this embodiment, the specific connection relationship between each MOS transistor and each input power supply is as follows: the drain of the first MOS transistor PMOS1 is connected to the gate of the second MOS transistor NMOS, the source of the second MOS transistor NMOS is grounded, the first input power supply 111 is connected to the source of the first MOS transistor PMOS1, and the second input power supply 112 is connected to the drain of the second MOS transistor NMOS and the output unit 120 respectively.

[0051] The first MOS transistor PMOS1 and the second MOS transistor NMOS change their on / off states according to the voltage signals provided by the first input power supply 111 and the second input power supply 112. The output unit 120 is used to output a power-on detection signal according to the on / off state of the second MOS transistor NMOS.

[0052] Please refer to Figure 2 In one possible implementation, the output unit 120 includes a first inverter U1 and a second inverter U2;

[0053] The input terminal of the first inverter U1 is connected to the second input power supply 112, and the output terminal of the first inverter U1 is connected to the input terminal of the second inverter U2.

[0054] Specifically, if the output terminal of the first inverter U1 outputs a high-level signal, then the output terminal of the second inverter U2 outputs a low-level signal; if the output terminal of the first inverter U1 outputs a low-level signal, then the output terminal of the second inverter U2 outputs a high-level signal.

[0055] In this embodiment, an inverter can be selected to form the output unit 120. The power-on status of the first power supply and the second power supply in the above embodiment can be determined by the high-level signal or low-level signal output by the inverter.

[0056] For example, if the second input power supply 112 is 1.8V and power is turned on, the second MOS transistor NMOS is in the off state. That is, the input terminal of the first inverter U1 is a high-level signal. Correspondingly, the output terminal of the first inverter U1 and the input terminal of the second inverter U2 are both low-level signals, and the output terminal of the second inverter U2 is a high-level signal.

[0057] If the gate of the first MOSFET PMOS1 is connected to a 1.8V power supply, and the first input power supply 111 is set to 1.8V and powered on, the first MOSFET PMOS1 is in the off state, and the second MOSFET NMOS connected to the first MOSFET PMOS1 is also in the off state. At this time, the output of the first inverter U1 outputs a low-level signal, and the output of the second inverter U2 outputs a high-level signal. If the first input power supply 111 is set to 3.3V and powered on, the first MOSFET PMOS1 is in the on state, and the second MOSFET NMOS connected to the first MOSFET PMOS1 is also in the on state. At this time, the output of the first inverter U1 outputs a high-level signal, and the output of the second inverter U2 outputs a low-level signal.

[0058] Optionally, the input unit further includes a third input power supply 113, and the switching unit further includes a third MOS transistor PMOS2, wherein the third MOS transistor PMOS2 is a P-channel MOS transistor;

[0059] The third input power supply 113 is connected to the gate of the third MOS transistor PMOS2;

[0060] The source of the third MOS transistor PMOS2 is connected to the gate of the first MOS transistor PMOS1, and the drain of the third MOS transistor PMOS2 is connected to the drain of the first MOS transistor PMOS1.

[0061] In this embodiment, by introducing a third input power supply 113 and a third MOS transistor PMOS2, the gate voltage of the first MOS transistor PMOS1 can be controlled, and then the on / off state of the three MOS transistors can be accurately realized through the voltage signals output by the three input power supplies.

[0062] As can be seen from the above analysis, the power-on detection circuit in this embodiment includes an input unit, a switching unit, and an output unit connected in sequence. The input unit includes a first input power supply and a second input power supply, and the switching unit includes two MOSFETs. The two MOSFETs can change their on / off state according to the voltage signals provided by the two input power supplies. The output unit can output a power-on detection signal according to the on / off state of the MOSFETs, realizing power-on detection of multiple voltage values. Furthermore, the circuit design is simple and the cost is low.

[0063] Considering the addition of a first input power supply 111 to the existing second input power supply 112 for detection, in order to protect the components in the power-on detection circuit, especially the MOSFETs, from the risk of breakdown.

[0064] In one possible implementation, the power-on detection circuit further includes a step-down circuit 130, one end of which is connected to the drain of the first MOS transistor PMOS1, and the other end of which is grounded.

[0065] In this embodiment, by introducing a step-down circuit 130, the protection of the components in the power-on detection circuit can still be achieved even with the addition of a first input power supply 111. A specific step-down circuit 130 will be described in detail below.

[0066] Specifically, the step-down circuit 130 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series.

[0067] The first end of the first resistor R1 is connected to the drain of the first MOS transistor PMOS1, the second end of the first resistor R1 is connected in series with the first end of the second resistor R2, and the first end of the second resistor R2 is connected to the second end of the first resistor R1 and the gate of the second MOS transistor NMOS.

[0068] The first end of the third resistor R3 is connected to the second end of the second resistor R2 and the drain of the third MOS transistor PMOS2.

[0069] This embodiment uses the first resistor R1, the second resistor R2, and the third resistor R3 to perform voltage division on the circuit when the first input power supply 111 is introduced. That is, while controlling the on / off state of the first MOSFET PMOS1, the second MOSFET NMOS, and the third MOSFET PMOS2, this embodiment can also protect each MOSFET, effectively preventing the MOSFETs from being broken down and avoiding damage to the components in the power-on detection circuit.

[0070] Additionally, please refer to Figure 3 The power-on detection circuit further includes a diode D, the anode of which is connected to the gate of the third MOS transistor PMOS2, and the cathode of which is connected to the source of the third MOS transistor PMOS2 and the gate of the first MOS transistor PMOS1.

[0071] Diode D serves as electrostatic discharge (ESD) protection, preventing the third MOSFET PMOS2 from being electrostatically damaged. Furthermore, diode D can form a circuit with the parasitic diode in PMOS2, generating a very small current. In this case, diode D and the parasitic diode can be used as resistors. By replacing diode D with different models and / or sizes, the voltage at the source terminal of PMOS2 can be changed, and its on / off state can be controlled by adjusting the voltage at the gate and source terminals.

[0072] It should be noted that, assuming the output voltage of the first input power supply 111 is 3.3V, and the output voltages of the second input power supply 112 and the third input power supply 113 are both 1.8V, and the power-on detection circuit contains only 1.8V components and no 3.3V components, it can be understood that the process withstand voltage of the components in this power-on detection circuit is 1.8V + 1.8V * 10% = 1.98V. In this case, after the output voltage of the first input power supply 111 reaches 1.98V, the output terminal of the first inverter U1 corresponding to the first input power supply 111 should immediately output a high level, so that the power-on detection circuit generates a clamping voltage to protect the circuit nodes connected to the 3.3V power supply from exceeding the withstand voltage value, thereby protecting the 1.8V components in the power-on detection circuit.

[0073] The following examples will provide a detailed description of the specific functions of the power-on detection circuit in the above embodiments:

[0074] Example 1: If the output voltage of the first input power supply 111 is 3.3V, and the output voltages of the second input power supply 112 and the third input power supply 113 are both 1.8V, the first input power supply 111 is powered on first, followed by the second input power supply 112 and the third input power supply 113.

[0075] At this point, when the 3.3V power-on voltage is applied first, the second input power supply 112 and the third input power supply 113, corresponding to the 1.8V voltage, are at a low level. The source voltage of the first MOSFET PMOS1 is greater than its gate voltage, so PMOS1 is turned on. After voltage reduction through the first resistor R1, the voltage at node c is 1.65V, and the voltages at nodes f and a are both at a low level. The third MOSFET PMOS2 is turned on, and the voltages at nodes a, b, and c begin to rise. When the 3.3V power-on voltage increases to 1.98V, the voltage at node c is 0.99V. Since the source of the second MOSFET NMOS is grounded, NMOS is turned on. The input of the first inverter U1, which is connected to the drain of the second MOSFET NMOS, is at a low level, and the output of the first inverter U1 directly outputs a high-level signal.

[0076] When the 3.3V power-on is complete, the source voltage of the first MOSFET PMOS1 is 3.3V. At this time, the voltage at node a must be at least 1.32V to avoid the risk of breakdown. By dividing the voltage through the second resistor R2, the voltage at node a can be made 1.5V. At this time, the two 1.8V power supplies of the second input power supply 112 and the third input power supply 113 start to power on, the potential of node d is high, the third MOSFET PMOS2 is turned off, and by adjusting the size of diode D, the voltage at point F is made 1.62V. The circuit is now powered on, and the output of the first inverter U1 is high.

[0077] Example 2: If the output voltage of the first input power supply 111 is 3.3V, and the output voltages of the second input power supply 112 and the third input power supply 113 are both 1.8V, then the second input power supply 112 and the third input power supply 113 are powered on first, followed by the first input power supply 111.

[0078] After the 1.8V power-on is complete, the gate voltage of the third MOSFET PMOS2 is greater than the source voltage, and PMOS2 is turned off. According to Example 1, the voltage at node f is 1.62V. At this time, the 3.3V power-on begins. When the voltage of the first input power supply 111 approaches 1.62V, due to the threshold voltage, the voltage of the second input power supply 112 is between 1.62V and 1.98V. The first MOSFET PMOS1 turns on, and the voltage at node c causes the second MOSFET NMOS to turn on, resulting in a high-level signal output from the first inverter U1. Furthermore, during the entire power-on process, no node voltage exceeds the withstand voltage of 1.98V, and the power-on detection circuit has no risk of breakdown.

[0079] Example 3: If the output voltage of the first input power supply 111 is 3.3V, and the output voltages of the second input power supply 112 and the third input power supply 113 are both 1.8V, the first input power supply 111, the second input power supply 112 and the third input power supply 113 are powered on simultaneously.

[0080] During the initial power-on phase, the voltage at node d is insufficient to turn on diode D, so the third MOSFET PMOS2 turns on, the voltage at node f is low, and the first MOSFET PMOS1 turns on. When the voltage at node d increases, diode D turns on, the third MOSFET PMOS2 turns off, and the output of the first inverter outputs a high-level signal. Throughout the entire power-on process, no node voltage exceeds the withstand voltage value, and the power-on detection circuit has no risk of breakdown.

[0081] Example 4: If the output voltages of the first input power supply 111, the second input power supply 112, and the third input power supply 113 are all 1.8V, and the three power supplies are powered on simultaneously.

[0082] After power-on, the voltage at node f is 1.62V, which is insufficient to turn on the first MOS transistor PMOS1. The voltage at node c is low, and the output of the second inverter U2 outputs a high-level signal, detecting that the 1.8V power supply has completed power-on. During the entire power-on process, no node voltage exceeds the withstand voltage value, and the power-on detection circuit has no risk of breakdown.

[0083] It should be noted that the output voltage of the first input power supply 111 used in the above example is 3.3V, and the output voltages of the second input power supply 112 and the third input power supply 113 are both 1.8V. These are only for example purposes, and different power supply voltages can be selected according to actual needs.

[0084] Optionally, the power-on detection circuit further includes a protection circuit, which includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

[0085] One end of the fourth resistor R4 is connected to the second input power supply 112, and the other end of the fourth resistor R4 is connected to the drain of the second MOS transistor NMOS.

[0086] One end of the fifth resistor R5 is connected to the second end of the third resistor R3, and the other end of the fifth resistor R5 is grounded.

[0087] One end of the sixth resistor R6 is connected to the third input power supply 113, and the other end of the sixth resistor R6 is connected to the gate of the third MOS transistor PMOS2.

[0088] In this embodiment, the sixth resistor R6 can serve as the gate resistor for the third MOSFET PMOS2, rapidly attenuating oscillations generated in the gate circuit. Furthermore, if a small-value resistor is chosen for R6, the switching speed of the third MOSFET PMOS2 can be accelerated. The fifth resistor R5, when the second MOSFET NMOS is off, can limit the drain of the first MOSFET PMOS1 to a low level. The fourth resistor R4 can protect the second MOSFET NMOS when it is connected to the second input power supply.

[0089] Optionally, the protection circuit further includes a seventh resistor R7, one end of which is connected to the source of the second MOSFET NMOS, and the other end of which is grounded. Here, VSS represents the grounding terminals of the fifth and seventh resistors.

[0090] In summary, the power-on detection circuit in this embodiment includes an input unit, a switching unit, and an output unit connected in sequence. The input unit includes a first input power supply and a second input power supply, and the switching unit includes two MOSFETs. The two MOSFETs can change their on / off state according to the voltage signals provided by the two input power supplies. The output unit can output a power-on detection signal according to the on / off state of the MOSFETs, realizing power-on detection of various voltage values. Furthermore, the circuit design is simple, the cost is low, and by limiting the withstand voltage, no voltage exceeds the withstand voltage during the entire power-on process, eliminating the risk of breakdown in the power-on detection circuit.

[0091] Please refer to Figure 4 Corresponding to the above-described power-on detection circuit embodiment, this application also provides a power-on detection method, the method comprising:

[0092] S410, the first MOSFET changes its on / off state according to the first voltage of the first input power supply;

[0093] S420, the second MOSFET changes its on / off state according to the second voltage of the second input power supply;

[0094] S430, the output unit outputs a power-on detection signal according to the on / off state of the second MOS transistor.

[0095] This application provides a power-on detection method, comprising an input unit, a switching unit, and an output unit connected in sequence. The input unit includes a first input power supply and a second input power supply, and the switching unit includes two MOSFETs. The two MOSFETs can change their on / off state according to the voltage signals provided by the two input power supplies. The output unit can output a power-on detection signal according to the on / off state of the MOSFETs, enabling power-on detection of multiple voltage values. Furthermore, the circuit design is simple and the cost is low.

[0096] The specific implementation process of the power-on detection method provided in this embodiment can be found in the specific implementation process of the power-on detection circuit described above, and will not be repeated here.

[0097] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A power-on detection circuit, characterized in that, The power-on detection circuit includes an input unit, a switching unit, and an output unit connected in sequence, wherein, The input unit includes a first input power supply and a second input power supply, and the switching unit includes a first MOSFET and a second MOSFET. The drain of the first MOSFET is connected to the gate of the second MOSFET, the source of the second MOSFET is grounded, the first input power supply is connected to the source of the first MOSFET, and the second input power supply is connected to the drain of the second MOSFET and the output unit, respectively; the gate of the first MOSFET is connected to the power supply. The first MOSFET and the second MOSFET change their on / off states according to the voltage signals provided by the first input power supply and the second input power supply. The output unit is used to output a power-on detection signal according to the on / off state of the second MOSFET.

2. The power-on detection circuit according to claim 1, characterized in that, The input unit further includes a third input power supply, and the switching unit further includes a third MOS transistor, wherein the third MOS transistor is a P-channel MOS transistor; The third input power supply is connected to the gate of the third MOS transistor; The source of the third MOS transistor is connected to the gate of the first MOS transistor, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor.

3. The power-on detection circuit according to claim 1, characterized in that, The output unit includes a first inverter and a second inverter; The input terminal of the first inverter is connected to the second input power supply, and the output terminal of the first inverter is connected to the input terminal of the second inverter. Specifically, if the output terminal of the first inverter outputs a high-level signal, then the output terminal of the second inverter outputs a low-level signal; conversely, if the output terminal of the first inverter outputs a low-level signal, then the output terminal of the second inverter outputs a high-level signal.

4. The power-on detection circuit according to claim 2, characterized in that, The power-on detection circuit also includes a step-down circuit, one end of which is connected to the drain of the first MOS transistor, and the other end of which is grounded.

5. The power-on detection circuit according to claim 4, characterized in that, The step-down circuit includes a first resistor, a second resistor, and a third resistor connected in series. The first end of the first resistor is connected to the drain of the first MOS transistor, the second end of the first resistor is connected in series with the first end of the second resistor, and the first end of the second resistor is connected to the second end of the first resistor and the gate of the second MOS transistor respectively. The first end of the third resistor is connected to the second end of the second resistor and the drain of the third MOS transistor.

6. The power-on detection circuit according to claim 5, characterized in that, The power-on detection circuit also includes a protection circuit, which includes a fourth resistor, a fifth resistor, and a sixth resistor. One end of the fourth resistor is connected to the second input power supply, and the other end of the fourth resistor is connected to the drain of the second MOS transistor. One end of the fifth resistor is connected to the second end of the third resistor, and the other end of the fifth resistor is grounded; One end of the sixth resistor is connected to the third input power supply, and the other end of the sixth resistor is connected to the gate of the third MOS transistor.

7. The power-on detection circuit according to claim 6, characterized in that, The protection circuit also includes a seventh resistor, one end of which is connected to the source of the second MOS transistor, and the other end of which is grounded.

8. The power-on detection circuit according to claim 2, characterized in that, The power-on detection circuit also includes a diode, the anode of which is connected to the gate of the third MOS transistor, and the cathode of which is connected to the source of the third MOS transistor and the gate of the first MOS transistor.

9. The power-on detection circuit according to claim 1, characterized in that, The first MOSFET is a P-channel MOSFET, and the second MOSFET is an N-channel MOSFET.

10. A power-on detection method, characterized in that, The method, applied to the power-on detection circuit according to any one of claims 1 to 8, comprises: The first MOSFET changes its on / off state according to the first voltage of the first input power supply. The second MOSFET changes its on / off state according to the second voltage of the second input power supply; The output unit outputs a power-on detection signal based on the on / off state of the second MOS transistor.

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