A closed-loop adaptive zero-crossing detection circuit suitable for BOOST type switching power supply

Abstract

The present invention relates to a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST-type switching power supply. The circuit comprises a state detector, a state encoder, an up-down counter, a digital-to-analog converter, and a comparator connected in sequence. The state encoder comprises a delay circuit, a first trigger and a second trigger connected to the delay circuit, and a first AND gate, a second AND gate, and a third AND gate connected to the first trigger, wherein the first AND gate, the second AND gate, and the third AND gate are all connected to the second trigger. The present invention uses a closed-loop adaptive zero-crossing detection circuit to detect the inductor current in the switching power supply, samples the current of a synchronous rectifier, and utilizes the state detector, the state encoder, the up-down counter, and the digital-to-analog converter to dynamically adjust the reference voltage of the comparator, adaptively and accurately detecting the inductor zero-crossing signal, reducing the impact of delay or circuit imbalance on zero-crossing detection, thereby reducing the power consumption of the switching power supply and increasing system efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of power supplies, and more particularly to a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply. Background Art

[0002] Most current BOOST-type switching power converters use a synchronous rectification structure. Compared to asynchronous rectification, this structure can reduce the power loss caused by the freewheeling diode and improve system efficiency. In synchronous BOOST converter applications, when the system is heavily loaded, the inductor current operates in CCM mode, where the current does not drop to zero during the duty cycle. The synchronous rectifier's low on-resistance reduces conduction losses. However, when the system is lightly loaded, the inductor current operates in DCM mode, where the current drops to zero. If the synchronous rectifier is not shut down in a timely manner, current backflow will occur, affecting system performance. Therefore, the synchronous rectification structure requires a zero-crossing detection unit to promptly shut down the synchronous rectifier when the inductor current reaches zero. However, due to the influence of the offset voltage caused by the converter's delay, comparator offset, and some parasitic parameters, the signal generated by the zero-crossing detection circuit cannot exactly turn off the synchronous rectifier when the inductor current reaches zero. This causes some defects: 1) When the synchronous rectifier is turned off too late, the current will flow back through the substrate of the synchronous rectifier, causing additional losses; 2) When the synchronous rectifier is turned off too early, the inductor will continue to flow through the body diode of the synchronous rectifier, causing greater body diode power consumption; 3) The backflow of current can also cause input voltage jitter, resulting in system instability.

[0003] Existing zero-crossing detection technology detects the state of the inductor current by sampling the SW terminal voltage. That is, the SW terminal voltage is amplified and then connected to the input of the zero-crossing detection circuit. This method reduces the delay of the zero-crossing detection circuit, but does not eliminate the impact of the zero-crossing detection circuit offset. Alternatively, the impact on accuracy is reduced by reducing the delay time of the zero-crossing detection circuit output signal transmission. This method does not consider the delay of the zero-crossing detection circuit itself. Alternatively, the synchronous rectifier is turned off early according to the delay time that has been tested in advance. This method is only suitable for specific circuits and cannot obtain a universal delay time. Summary of the Invention

[0004] To solve the above-mentioned problems in the prior art, the present invention proposes a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST-type switching power supply. While adjusting the offset of the zero-crossing detection circuit, the invention eliminates the influence of various delays on the accuracy of the zero-crossing detection circuit, and can accurately detect the inductor current.

[0005] The present invention provides a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST-type switching power supply, comprising a state detector, a state encoder, an up-down counter, a digital-to-analog converter, and a comparator connected in sequence, wherein the state encoder includes a delay circuit, a first trigger and a second trigger connected to the delay circuit, and a first AND gate, a second AND gate, and a third AND gate connected to the first trigger, and the first AND gate, the second AND gate, and the third AND gate are all connected to the second trigger.

[0006] Furthermore, the input end of the state detector is connected to the SW end of the BOOST type switching power supply, and the output end of the state detector is connected to the data input end of the first trigger and the data input end of the second trigger respectively.

[0007] Furthermore, the input end of the delay circuit is connected to the gate of the synchronous rectifier tube in the BOOST type switching power supply, the first output end of the delay circuit is connected to the clock input end of the first trigger, and the second output end of the delay circuit is connected to the clock input end of the second trigger.

[0008] Furthermore, the first output terminal of the first trigger is connected to the first input terminal of the first AND gate and the first input terminal of the second AND gate respectively, and the second output terminal of the first trigger is connected to the first input terminal of the third AND gate.

[0009] Furthermore, the first output terminal of the second trigger is connected to the second input terminal of the first AND gate, and the second output terminal of the second trigger is connected to the second input terminal of the second AND gate and the second input terminal of the third AND gate respectively.

[0010] Furthermore, the output end of the first AND gate, the output end of the second AND gate, and the output end of the third AND gate are all connected to the up-down counter.

[0011] Furthermore, the inverting input of the comparator is connected to the digital-to-analog converter, the non-inverting input of the comparator is connected to a current / voltage conversion module, and the output of the comparator is connected to the logic drive module in the BOOST type switching power supply.

[0012] Furthermore, the current / voltage conversion module is connected to the drain of the synchronous rectifier in the BOOST type switching power supply to convert the current of the synchronous rectifier into the voltage across the synchronous rectifier.

[0013] Furthermore, the state detector is configured to detect the voltage at the SW end of the BOOST-type switching power supply and output a state signal; the state encoder is configured to encode the state signal and output an encoded signal; the up-down counter is configured to add and subtract the encoded signal, convert the encoded signal into a counting signal, and output the counting signal; the digital-to-analog converter is configured to convert the counting signal into a reference voltage, and input the reference voltage to the inverting input end of the comparator; the comparator is configured to compare the reference voltage with the voltage across the synchronous rectifier and output a zero-crossing detection signal.

[0014] The present invention adopts a closed-loop adaptive zero-crossing detection circuit to detect the inductor current in the switching power supply, samples the current of the synchronous rectifier tube, and utilizes a state detector, a state encoder, an up-down counter and a digital-to-analog converter to dynamically adjust the reference voltage of the comparator, adaptively and accurately detecting the inductor zero-crossing signal, reducing the impact of delay or circuit imbalance on zero-crossing detection, thereby reducing the power consumption of the switching power supply and increasing system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is the topology of the BOOST type switching power converter.

[0016] Figure 2 The invention is a block diagram of a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST-type switching power supply.

[0017] Figure 3 yes Figure 2 Schematic diagram of the digital-to-analog conversion waveform of the reference voltage Vref.

[0018] Figure 4(a)-Figure 4(c) The present invention is a timing diagram of the operation of a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply. DETAILED DESCRIPTION

[0019] The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings and described in detail.

[0020] The closed-loop adaptive zero-crossing detection circuit provided by the present invention is applied to a BOOST type switching power supply. Figure 1 As shown, it includes input voltage Vin, inductor L, power tube M1, synchronous rectifier tube M2, logic driver module DRIVER, load capacitor C L and the load resistor R L Among them, one end of the inductor L is connected to the positive electrode of the input voltage Vin, and the other end is connected to the drain of the power tube M1 and the drain of the synchronous rectifier tube M2. LOne end is connected to the source of the synchronous rectifier M2, and the other end is grounded. L With the load capacitance C L In parallel, the load resistance R L One end of the inductor L is also connected to the source of the synchronous rectifier M2, and the other end is grounded. In addition, the negative electrode of the input voltage Vin and the source of the power tube M1 are both grounded. The gate of the power tube M1 and the gate of the synchronous rectifier M2 are set to LG and UG respectively, and both are connected to the output end of the logic driver module DRIVER. At the same time, the common connection point of the inductor L connected to the drain of the power tube M1 and the drain of the synchronous rectifier M2 is set to the SW end, and the load resistor R is set to L The voltage across the two ends is Vout.

[0021] like Figure 2 As shown, the closed-loop adaptive zero-crossing detection circuit for a BOOST-type switching power supply of the present invention includes a state detector 1, a state encoder 2, an up-down counter 3, a digital-to-analog converter 4, and a comparator 5 connected in sequence. The state encoder 2 includes a delay circuit 21, a first trigger 22 and a second trigger 23 connected to the delay circuit 21, and a first AND gate 24, a second AND gate 25, and a third AND gate 26 connected to the first trigger 22. The first AND gate 24, the second AND gate 25, and the third AND gate 26 are also connected to the second trigger 23.

[0022] Specifically, the input end of the state detector 1 is connected to the SW end of the BOOST type switching power supply for detecting the voltage at the SW end of the switching power supply, and the output end of the state detector 1 outputs the state signal SWDET.

[0023] The state encoder 2 is configured to encode the state signal SWDET output by the state detector 1 and output the encoded signal. Specifically, the output terminal of the state detector 1 is connected to the data input terminal of the first trigger 22 and the data input terminal of the second trigger 23 respectively. The input terminal of the delay circuit 21 is connected to the gate UG of the synchronous rectifier tube M2, the first output terminal CLK1 is connected to the clock input terminal of the first trigger 22, and the second output terminal CLK2 is connected to the clock input terminal of the second trigger 23. The first output terminal P1 of the first trigger 22 is connected to the first input terminal of the first AND gate 24 and the first input terminal of the second AND gate 25 respectively, and the second output terminal The first output terminal P2 of the second trigger 23 is connected to the second input terminal of the first AND gate 24, and the second output terminal P2 is connected to the first input terminal of the third AND gate 26. The outputs of the first AND gate 24, the second AND gate 25, and the third AND gate 26 are connected to the up / down counter 3. If the outputs of the first AND gate 24, the second AND gate 25, and the third AND gate 26 are Q1, Q2, and Q3, respectively, the state encoder 2 outputs the coded signals Q1 / Q2 / Q3.

[0024] The up / down counter 3 is configured to perform up / down counting on the coded signal Q1 / Q2 / Q3 output by the state encoder 2, and convert the coded signal Q1 / Q2 / Q3 into a counting signal.<C7~C0> , and output counting signal<C7~C0> .

[0025] The digital-to-analog converter 4 is configured to convert the count signal<C7~C0> The reference voltage Vref is converted into a reference voltage Vref, and the reference voltage Vref is input to the inverting input terminal of the comparator 5. The non-inverting input terminal of the comparator 5 is connected to a current / voltage conversion module 6, and the current / voltage (I / V) conversion module 6 is connected to the drain of the synchronous rectifier M2 to convert the current I flowing through the synchronous rectifier M2 into M2 Converted to voltage V M2 Comparator 5 is used to compare the reference voltage Vref with V M2 , and outputs a zero-crossing detection signal ZCD. The output end of the comparator 5 is connected to the logic drive module DRIVER of the switching power supply to control the on / off of the switching power supply via the zero-crossing detection signal ZCD. The principle of the zero-crossing detection signal ZCD controlling the on / off of the switching power supply is as follows: when the rising edge of the output signal CLK1 / CLK2 of the delay circuit 21 arrives, when the current flowing through the synchronous rectifier M2 is a forward current, indicating that the synchronous rectifier M2 is turned off too early and there is a body diode current in the synchronous rectifier M2, the zero-crossing detection signal ZCD output by the comparator 5 changes from low to high; when the current flowing through the synchronous rectifier M2 is a reverse current, indicating that the synchronous rectifier M2 is turned off too late and current backflow occurs, the zero-crossing detection signal ZCD output by the comparator 5 changes from high to low.

[0026] The working principle of the closed-loop adaptive zero-crossing detection circuit of the present invention is as follows: when the zero-crossing shutdown signal of the synchronous rectifier tube M2 is too early, the voltage at the SW end of the switching power supply is higher than the set high-voltage threshold (the set high-voltage threshold is between the input voltage Vin and the output voltage Vout of the switching power supply), and the output signal SWDET of the state detector 1 is high at this time; when the zero-crossing shutdown signal of the synchronous rectifier tube M2 is too late, the voltage at the SW end is less than the set low-voltage threshold (the set low-voltage threshold is determined according to the input voltage Vin of the switching power supply), and the output signal SWDET of the state detector 1 is low at this time. The rising edge of the gate signal UG of the synchronous rectifier tube M2 is delayed by Tdelay1 and Tdelay2 (Tdelay2>Tdelay1) respectively to obtain the pulse signals CLK1 and CLK2, and the output signals of the triggers 22 and 23 are The level of the signal SWDET changes (from 1 to 0 or from 0 to 1) at the rising edge of CLK1 and CLK2 respectively, and remains unchanged at other times. The output signals of triggers 22 and 23 are The output signals Q1 / Q2 / Q3 of the state encoder 2 are transmitted to the AND gates 24, 25, and 26, and are obtained through logic synthesis. When the turn-off time of the signal UG is too early, the output Q1 is high and the counter 3 increases by 1; when the turn-off time of the signal UG is too late, the output Q3 is high and the counter 3 decreases by 1; when the turn-off time of the signal UG is just when the inductor current drops to zero, the output Q2 is high and the counter 3 remains unchanged. The digital-to-analog converter 4 is used to convert the data output by the counter 3 into the reference voltage Vref of the comparator 5. When the 8-bit binary number<C7:C0> When the value of increases, the reference voltage Vref increases; when<C7:C0> When the value of decreases, the reference voltage Vref decreases; when<C7:C0> When the value of remains unchanged, the reference voltage Vref remains unchanged. Comparator 5 is used to compare the output voltage of the synchronous rectifier tube M2 after I / V conversion with the reference voltage Vref output by the digital-to-analog converter 4, and output a zero-crossing detection signal ZCD to the logic drive module DRIVER of the switching power supply to control the on and off of the switches M1 and M2. The present invention obtains an accurate zero-crossing detection signal based on the closed-loop adaptive adjustment of the state detector 1, state encoder 2, up-down counter 3, digital-to-analog converter 4, and comparator 5.

[0027] Figure 3The following is a schematic diagram of the digital-to-analog conversion waveform of the reference voltage Vref. As can be seen from the figure, as state detector 1 samples the SW terminal voltage and state encoder 2 outputs the signal, counter 3 decrements by 1, while Vref gradually decreases with the value of counter 3. This adaptive zero-crossing detection process continues until the circuit's zero-crossing signal can be accurately detected. Finally, Vref remains stable near the value Vm, completing the closed-loop adaptive zero-crossing detection process. After the continuous adaptive zero-crossing detection process stabilizes, the zero-crossing detection state switches back and forth between slightly early and slightly late, and the reference voltage Vref also switches back and forth between increasing and decreasing around a fixed value, which is Vm.

[0028] Figure 4(a)-Figure 4(b) This is the working timing diagram of the closed-loop adaptive zero-crossing detection circuit for BOOST type switching power supply of the present invention. In Figure 4(a), when LG is high and UG is high, the inductor current is charged. When LG and UG become low at the same time, the inductor starts to flow and the voltage at the SW terminal jumps to Vout; the inductor current I L When UG does not drop to zero, it becomes high and the synchronous rectifier M2 is turned off. At this time, the inductor L continues to discharge through the body diode of the synchronous rectifier M2. The voltage at the SW end is about Vout+0.7V. The rising edge of UG is delayed to obtain the pulse signals CLK1 and CLK2. The state encoder 2 is triggered at the rising edge of CLK1 and CLK2, the output Q1 is high, and the counter 3 is incremented by 1. Its output <c7:c0>The value of is transmitted to the digital-to-analog converter 4, which increases the reference voltage Vref. The voltage at the SW terminal is maintained near Vin until the next inductor charging cycle, when it drops back to zero. This process continues, increasing Vref until an accurate current state signal is obtained. In Figure 4(b), the inductor current I L After the voltage drops to zero, the synchronous rectifier M2 is still not turned off, Vout reversely charges the inductor L, and the inductor current IL drops to a negative value. At the moment the synchronous rectifier M2 is turned off, the voltage at the SW terminal suddenly drops from Vout to about -0.7V. At the same time, the output signals CLK1 and CLK2 of the delay circuit 21 are obtained. After the rising edges of CLK1 and CLK2 are triggered and logic synthesis is performed, the output Q3 of the state encoder 2 is high, and the counter 3 decreases by 1. <c7:c0>The code value is input to the digital-to-analog converter 4, reducing the reference voltage Vref. The voltage at the SW terminal is stabilized near the Vin value until it drops to zero again during the next inductor charging cycle. This process continues, reducing Vref until an accurate state signal is obtained. In Figure 4(c), the synchronous rectifier tube M2 is just at the inductor current I L The SW terminal voltage drops to zero when the UG turns off, and the SW terminal voltage drops from Vout to Vin at the moment the UG turns off, until the SW terminal voltage drops back to zero during the next inductor charging cycle. State encoder 2 output Q2 is high, the value of counter 3 remains unchanged, and the value of reference voltage Vref also remains unchanged. Thus, the closed-loop adaptive zero-crossing detection circuit of the present invention achieves precise adjustment of the zero-crossing detection signal in all situations, eliminating the influence of circuit delay or offset voltage, allowing the BOOST-type switching power supply to accurately detect the inductor current.

[0029] The closed-loop adaptive zero-crossing detection circuit of the present invention has been subjected to transient simulation. Under the conditions of a simulation temperature range of -40 to 125°C, an input voltage range of 2.1 to 5.5V, and an output voltage range of 6.5 to 10.5V, the purpose of the present invention can be achieved and an accurate status signal can be obtained.

[0030] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Various variations of the above embodiment of the present invention are possible. For example, the principles of the present invention are equally applicable to buck-type and buck-boost-type circuits. In other words, any simple, equivalent variations and modifications made in accordance with the claims and description of the present invention fall within the scope of protection of the patent claims. Anything not fully described in this invention constitutes conventional technology.

Claims

1. A closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply, characterized in that: The device comprises a state detector, a state encoder, an up-down counter, a digital-to-analog converter, and a comparator connected in sequence, wherein the state encoder comprises a delay circuit, a first trigger and a second trigger connected to the delay circuit, and a first AND gate, a second AND gate, and a third AND gate connected to the first trigger, and the first AND gate, the second AND gate, and the third AND gate are all connected to the second trigger; The input end of the state detector is connected to the SW end of the BOOST type switching power supply, and the output end of the state detector is connected to the data input end of the first trigger and the data input end of the second trigger respectively; The input end of the delay circuit is connected to the gate of the synchronous rectifier tube in the BOOST type switching power supply, the first output end of the delay circuit is connected to the clock input end of the first trigger, and the second output end of the delay circuit is connected to the clock input end of the second trigger; The first output terminal of the first trigger is connected to the first input terminal of the first AND gate and the first input terminal of the second AND gate respectively, and the second output terminal of the first trigger is connected to the first input terminal of the third AND gate; The first output terminal of the second trigger is connected to the second input terminal of the first AND gate, and the second output terminal of the second trigger is connected to the second input terminal of the second AND gate and the second input terminal of the third AND gate respectively.

2. The closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply according to claim 1, characterized in that: The output end of the first AND gate, the output end of the second AND gate, and the output end of the third AND gate are all connected to the up-down counter.

3. The closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply according to claim 1, characterized in that: The inverting input terminal of the comparator is connected to the digital-to-analog converter, the non-inverting input terminal of the comparator is connected to a current / voltage conversion module, and the output terminal of the comparator is connected to the logic drive module in the BOOST type switching power supply.

4. The closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply according to claim 3, characterized in that: The current / voltage conversion module is connected to the drain of the synchronous rectifier in the BOOST type switching power supply to convert the current of the synchronous rectifier into the voltage across the synchronous rectifier.

5. The closed-loop adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply according to claim 4, characterized in that: The state detector is configured to detect the voltage at the SW terminal of the BOOST type switching power supply and output a state signal; The state encoder is configured to encode the state signal and output an encoded signal; The up-down counter is configured to perform up-down counting on the coded signal, convert the coded signal into a counting signal, and output the counting signal; The digital-to-analog converter is configured to convert the counting signal into a reference voltage, and input the reference voltage into the inverting input terminal of the comparator; The comparator is configured to compare the reference voltage with the voltage across the synchronous rectifier and output a zero-crossing detection signal.

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