An unsupervised learning circuit for Hall bar synapses based on pulse amplitude

Abstract

The present invention discloses an unsupervised learning circuit of Hall bar synapse based on pulse amplitude, including an STDP algorithm circuit, a front amplitude control circuit, a rear amplitude control circuit and a weight adjustment circuit. The STDP algorithm circuit is used to generate an enhancement signal or an inhibition signal according to the arrival order of the pre-synaptic and post-synaptic neuron pulses, and control the direction of the pulses applied to the two ends of the Hall bar in the weight adjustment circuit. The amplitude control circuit generates a pulse signal of corresponding duration according to the action time of the synaptic neuron pulse, and adjusts the abnormal Hall resistance value. The weight adjustment circuit receives the enhancement signal or inhibition signal output by the STDP algorithm circuit, determines the direction of applying the pulse signal to the Hall bar, and realizes the increase or decrease of the abnormal Hall resistance value of the Hall bar. The present invention can be used to store the energy of the time difference between the front and rear neuron pulses and to adjust the abnormal Hall resistance value, and has the advantages of high adjustment accuracy and simple circuit structure.

Description

Technical Field

[0001] The invention belongs to the application field of novel electronic material devices, relates to the regulation of Hall resistance value of Hall bars in artificial neural network hardware circuits, and specifically relates to an unsupervised learning circuit of Hall bar synapses based on pulse amplitude. Background Art

[0002] Computers with traditional von Neumann architecture have developed rapidly with the advent of the big data era. However, due to the separation of storage units and computing units, the data transfer process between the two consumes a lot of resources, making the computer's energy efficiency gradually unable to meet people's needs for complex problem processing and large-scale data storage. Therefore, artificial neural network hardware circuits with integrated storage and computing functions have received widespread attention.

[0003] The hardware circuit of artificial neural network imitates the structure of brain neural network, and uses devices with non-volatile storage function to simulate brain synapses to realize storage and calculation integration. Hall bars are often used as artificial synapses in artificial neural network hardware circuits because of their advantages such as non-volatile storage, continuous change and simple preparation of anomalous Hall resistance. At present, artificial neural networks mainly use pulses for neuromorphic calculations. The learning algorithm of spiking neural networks is mainly spike time dependent plasticity (STDP). Its principle is to use the time difference between the arrival of the previous and next neuronal pulses at the synapse to generate a pulse with a certain voltage amplitude to adjust the synaptic weight value. However, the STDP algorithm usually detects and generates adjustment pulses in the form of software to control and change the synaptic weight value. The processing speed is relatively slow and the transplantability is poor. These have become unfavorable factors affecting the widespread application of artificial neural network hardware circuits. The way to adjust the synaptic weight value is single, the time accuracy requirement is high, and there will be a high implementation cost. It cannot adjust the synaptic resistance value in a more direct and effective way. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes an unsupervised learning circuit of Hall bar synapses based on pulse amplitude, implements the STDP algorithm through hardware circuits, adjusts the abnormal Hall resistance value in the artificial neural network, and improves the adjustment accuracy of the network weight at a lower cost.

[0005] A Hall bar synapse unsupervised learning circuit based on pulse amplitude comprises an STDP algorithm circuit, a front amplitude control circuit, a rear amplitude control circuit and a weight adjustment circuit.

[0006] The STDP algorithm circuit is used to receive the pre-synaptic and post-synaptic neuron pulses of the current synapse, and generate an enhancement signal or an inhibition signal according to the order in which the pre-synaptic and post-synaptic neuron pulses arrive, and control the direction of the pulses applied to the two ends of the Hall bar in the weight adjustment circuit.

[0007] The front amplitude control circuit is used to generate a pulse signal of corresponding duration according to the action time of the presynaptic neuron pulse, and the pulse signal is applied to both ends of the Hall bar in the weight adjustment circuit as a forward pulse signal.

[0008] The post-amplitude control circuit is used to generate a pulse signal of corresponding duration according to the action time of the post-synaptic neuron pulse, and the pulse signal is applied to both ends of the Hall bar in the weight adjustment circuit as a negative pulse signal.

[0009] The weight adjustment circuit receives the enhancement signal or the suppression signal output by the STDP algorithm circuit, and determines to apply a positive pulse signal or a negative pulse signal to the Hall bar, thereby increasing or decreasing the abnormal Hall resistance value of the Hall bar.

[0010] When the presynaptic neuron pulse arrives earlier than the postsynaptic neuron pulse, the STDP algorithm circuit generates an enhancement signal, and the weight adjustment circuit applies the pulse signal output by the front amplitude control circuit to both ends of the Hall bar, and the abnormal Hall resistance value of the Hall bar increases. When the presynaptic neuron pulse arrives later than the postsynaptic neuron pulse, the STDP algorithm circuit generates an inhibition signal, and the weight adjustment circuit applies the pulse signal output by the rear amplitude control circuit to both ends of the Hall bar, and the abnormal Hall resistance value of the Hall bar decreases.

[0011] The present invention has the following beneficial effects:

[0012] The adjustment of the Hall bar is realized in the form of hardware, which has better portability, fast processing speed and simple circuit structure. The pulse amplitude is used for adjustment, the pulse width is converted into the corresponding amplitude, the energy of the pulse time difference is stored and used to adjust the abnormal Hall resistance value, which is more direct and effective, and has low requirements on time accuracy and fast adjustment speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a block diagram of the unsupervised learning circuit of Hall bar synapse based on pulse amplitude.

[0014] Figure 2 : is a schematic diagram of a STDP algorithm circuit in an embodiment;

[0015] Figure 3 is a schematic diagram of the front and rear amplitude control circuits in the embodiment;

[0016] Figure 4 is a schematic diagram of a weight adjustment circuit in an embodiment;

[0017] Figure 5 It is the curve of the change of component parameters over time in the embodiment. DETAILED DESCRIPTION

[0018] In order to make the implementation purpose, technical solution and advantages of the present invention clearer, the technical solution in the example of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. It should be understood that the described embodiments are intended to explain the present invention and cannot be understood as limiting the present invention. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, a pulse amplitude-based Hall bar synapse unsupervised learning circuit includes an STDP algorithm circuit, a front amplitude control circuit, a rear amplitude control circuit and a weight adjustment circuit.

[0020] like Figure 2 As shown, the STDP algorithm circuit includes a first AND gate G1, a first NAND gate G2, a first P-type field effect transistor P1, a first resistor R1, a first capacitor C1, a first N-type field effect transistor N1, a second resistor R2, a first voltage comparator U1, a third resistor R3, a second AND gate G3, a second NAND gate G4, a second P-type field effect transistor P2, a fourth resistor R4, a second capacitor C2, a second N-type field effect transistor N2, a fifth resistor R5, a second voltage comparator U2 and a sixth resistor R6.

[0021] Among them, the input end of the first NOT gate G1 is connected to the drain of the second P-type field effect transistor P2, one input end of the first NAND gate G2 is connected to the output end of the first NOT gate G1, the other input end is used to receive the presynaptic neuron pulse signal pre, and the output end is connected to the gate of the first P-type field effect transistor P1. The source of the first P-type field effect transistor P1 is connected to VCC, and the drain is connected to one end of the first resistor R1, one end of the first capacitor C1 and the drain of the first N-type field effect transistor N1. The other ends of the first resistor R1 and the first capacitor C1 are grounded. The gate of the first N-type field effect transistor N1 receives the postsynaptic neuron pulse signal post, and the source is connected to one end of the second resistor R2 and the in-phase input end of the first voltage comparator U1. The other end of the second resistor is grounded. The inverting input end of the first voltage comparator U1 is connected to the control voltage Vth, and the Vth voltage is adjustable from 0.1v to the power supply voltage. The positive power supply end of the first voltage comparator U1 is connected to VCC and one end of the third resistor R3, the negative power supply end is grounded, and the output end outputs the enhanced signal Stren. The other end of the third resistor R3 is connected to the output end of the first voltage comparator U1.

[0022] The input end of the second NOT gate G3 is connected to the drain of the first P-type field effect transistor P1, and the output end is connected to an input end of the second NAND gate G4. The other input end of the second NAND gate G4 receives the postsynaptic neuron pulse signal post, and the output end is connected to the gate of the second P-type field effect transistor P2. The source of the second P-type field effect transistor P2 is connected to VCC, and the drain is connected to one end of the fourth resistor R4, one end of the second capacitor C2, the input end of the first AND gate G1, and the drain of the second N-type field effect transistor N2. The other end of the fourth resistor R4 and the second capacitor C2 is grounded. The source of the second N-type field effect transistor N2 is connected to one end of the fifth resistor R5 and the in-phase input end of the second voltage comparator U2, and the gate receives the presynaptic neuron pulse signal pre. The other end of the fifth resistor R5 is grounded. The inverting input end of the second voltage comparator U2 is connected to the control voltage Vth, the positive power supply end of the second voltage comparator U2 is connected to VCC and one end of the sixth resistor R6, the negative power supply end is grounded, and the output end outputs the inhibition signal Restr. The other end of the sixth resistor R6 is connected to the output end of the second voltage comparator U2.

[0023] like Figure 3 As shown, the left side is the front amplitude control circuit and the right side is the rear amplitude control circuit.

[0024] The pre-amplitude control circuit includes a third voltage comparator U3, a seventh resistor R7, an eighth resistor R8, a third NOT gate G5, a third P-type field effect transistor P3, a ninth resistor R9, a tenth resistor R10 and a third capacitor C3. Among them, the in-phase input end of the third voltage comparator U3 receives the presynaptic neuron pulse signal pre, and the inverting input end receives the control voltage Vth2, the Vth2 voltage is adjustable from 0.1v to the power supply voltage, the positive power supply end is connected to VCC, the negative power supply end is grounded, and the output end is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the input end of the third NOT gate G5. The other end of the eighth resistor R8 is connected to VCC. The output end of the third NOT gate G5 is connected to the gate of the third P-type field effect transistor P3. The source of the third P-type field effect transistor P3 is connected to VCC, and the drain is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the tenth resistor R10 and one end of the third capacitor C3 to output a pulse signal. The other ends of the tenth resistor R10 and the third capacitor C3 are grounded.

[0025] The post-amplitude control circuit includes a fourth voltage comparator U4, an eleventh resistor R11, a twelfth resistor R12, a fourth NOT gate G6, a fourth P-type field effect transistor P4, a thirteenth resistor R13, a fourteenth resistor R14 and a fourth capacitor C4. Among them, the positive input terminal of the fourth voltage comparator U4 receives the postsynaptic neuron pulse signal post, the negative input terminal receives the control voltage Vth2, the positive electrode is connected to VCC, the negative electrode is grounded, and the output terminal is connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the input end of the fourth NOT gate G6. The other end of the twelfth resistor R12 is connected to VCC. The output end of the fourth NOT gate G6 is connected to the gate of the fourth P-type field effect transistor P4. The source of the fourth P-type field effect transistor P4 is connected to VCC, and the drain is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and one end of the fourth capacitor C4, and a pulse signal is output. The other ends of the fourteenth resistor R14 and the fourth capacitor C4 are grounded.

[0026] like Figure 4 As shown, the weight adjustment circuit includes a fifth DC blocking capacitor C5, a fifteenth resistor R15, a sixteenth resistor R16, a first voltage zener diode D1, a fifth P-type field effect transistor P5, a third N-type field effect transistor N3, a fifth NOT gate G7, a sixth DC blocking capacitor C6, a seventeenth resistor R17, an eighteenth resistor R18, a second voltage zener diode D2, a sixth P-type field effect transistor P6, a fourth N-type field effect transistor N4, a sixth NOT gate G8 and a Hall bar.

[0027] Among them, one end of the fifth DC blocking capacitor C5 is connected to the output end of the first voltage comparator U1 to receive the enhanced signal Stren, and the other end of the fifth DC blocking capacitor C5 is connected to one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16. The other end of the fifteenth resistor R15 is connected to VCC, and the other end of the sixteenth resistor R16 is connected to the gate of the fifth P-type field effect transistor P5 and the positive electrode of the first voltage zener diode D1. The source of the fifth P-type field effect transistor P5 is connected to the other end of the ninth resistor R9 and the negative electrode of the first voltage zener diode D1, and the drain is connected to the drain of the third N-type field effect transistor N3 and the input end of the Hall bar in the direction of increasing resistance. The gate of the third N-type field effect transistor N3 is connected to the output end of the fifth NOT gate G7, and the source is grounded.

[0028] One end of the sixth DC-blocking capacitor C6 is connected to the output end of the second voltage comparator U2, and is connected to the suppression signal Restr, and the other end of the sixth DC-blocking capacitor C6 is connected to one end of the seventeenth resistor R17, the eighteenth resistor R18, and the input end of the fifth NOT gate G7. The other end of the seventeenth resistor R17 is connected to VCC, and the other end of the eighteenth resistor R18 is connected to the gate of the sixth P-type field effect transistor P6 and the positive electrode of the second voltage-stabilizing diode D2. The source of the sixth P-type field effect transistor P6 is connected to the other end of the thirteenth resistor R13 and the negative electrode of the second voltage-stabilizing diode D2, and the drain is connected to the drain of the fourth N-type field effect transistor N4 and the input end of the Hall bar in the direction of reducing the resistance. The gate of the fourth N-type field effect transistor N4 is connected to the output end of the sixth NOT gate G8, and the source is grounded. The input end of the sixth NOT gate G8 is connected to the other end of the fifth DC-blocking capacitor C5.

[0029] When the STDP algorithm circuit first receives the presynaptic neuron pulse signal pre, both input terminals of the NAND gate G2 receive a high level, and the output terminal outputs a low level. The gate-source voltage of the first P-type field effect transistor P1 reaches the turn-on voltage, the first P-type field effect transistor P1 is turned on, and the first capacitor C1 starts to charge. The potential at the drain of the first P-type field effect transistor P1 rises to a high potential. When the action time of the presynaptic neuron pulse signal pre ends and the postsynaptic neuron pulse signal post has not yet arrived, the first capacitor C1 discharges through the first resistor R1. At the same time, the high level output by the output terminal of the fourth NAND gate G4 locks the second P-type field effect transistor P2.

[0030] When the STDP algorithm circuit receives the postsynaptic neuron pulse signal post again, the first N-type field effect transistor N1 is turned on, and part of the charge in the first capacitor C1 flows into the source end through the drain end of the first N-type field effect transistor N1, and then flows through the second resistor R2. At this time, the voltage value across the second resistor R2 is the voltage value across the first capacitor C1 when the postsynaptic neuron pulse signal post arrives, and the first capacitor C1 is discharged through the first resistor R1 and the second resistor R2. When the postsynaptic neuron pulse signal post action time ends, the voltage across the second resistor R2 is 0. It can be seen that the smaller the time difference between the presynaptic and postsynaptic neuron pulse signals pre and post arriving at the STDP algorithm circuit, the greater the maximum voltage across the second resistor R2.

[0031] When the voltage across the second resistor R2 is higher than the control voltage Vth, the first voltage comparator U1 outputs a high voltage. Changing the amplitude of the control voltage Vth can change the width of the enhanced signal Stren output by the first voltage comparator U1.

[0032] When the current amplitude control circuit receives the presynaptic neuron pulse signal pre, it is compared with the control voltage Vth2 through the third voltage comparator U3. When the amplitude of the presynaptic neuron pulse signal pre is greater than the control voltage Vth2, the third voltage comparator U3 outputs a high level to the input end of the third NOT gate G5, and the third NOT gate G5 outputs a low level. The gate-source voltage of the third P-type field effect transistor P3 reaches the turn-on voltage, the third P-type field effect transistor P3 is turned on, the third capacitor C3 is charged, and the potential at the third capacitor C3 and the ninth resistor R9 rises to a high potential. At the same time, the high level output by the fourth NOT gate G6 locks the fourth P-type field effect transistor P4, and the potential between the thirteenth resistor R13 and the fourteenth resistor R14 is kept at zero.

[0033] When the presynaptic neuron pulse signal pre action time ends, the third capacitor C3 discharges through the tenth resistor R10 and acts on the source of the fifth P-type field effect transistor P5. When the postsynaptic neuron pulse signal post action time ends, the enhancement signal Stren changes from a high level to a low level, the potential between the fifteenth resistor R15 and the sixteenth resistor R16 changes from a high potential to a low potential, the gate-source voltage of the fifth P-type field effect transistor P5 reaches the turn-on voltage, the fifth P-type field effect transistor P5 is turned on, the output end of the sixth NOT gate G8 outputs a high level, the gate-source voltage of the fourth N-type field effect transistor N4 reaches the turn-on voltage, the fourth N-type field effect transistor N4 is turned on, and the pulse signal at the third capacitor C3 and the ninth resistor R9 supplies power to the fifth P-type field effect transistor P5 and the fourth N-type field effect transistor N4, which is equivalent to applying a positive pulse signal to the input end of the Hall bar, causing the abnormal Hall resistance value of the Hall bar to rise, such as Figure 5 shown.

[0034] Similarly, when the postsynaptic neuron pulse signal post arrives before the presynaptic neuron pulse signal pre, it is equivalent to applying a negative pulse signal to the input end of the Hall bar, causing the abnormal Hall resistance value of the Hall bar to decrease.

[0035] This method uses the STDP algorithm circuit to output a certain amplitude of DC level according to the time difference of the arrival of the presynaptic and postsynaptic neuron pulse signals. The smaller the time difference, the larger the output level amplitude. The fifth P-type field effect transistor P5, the sixth P-type field effect transistor P6, the third N-type field effect transistor N3 and the fourth N-type field effect transistor N4 form an H-bridge circuit to control the direction of the pulse signal input to the Hall bar, so as to realize the increase or decrease of the abnormal Hall resistance value of the Hall bar.

Claims

1. A Hall bar synapse unsupervised learning circuit based on pulse amplitude, characterized in that: It includes an STDP algorithm circuit, a front amplitude control circuit, a rear amplitude control circuit and a weight adjustment circuit; The STDP algorithm circuit is used to receive the pre-synaptic and post-synaptic neuron pulses of the current synapse, and generate an enhancement signal or an inhibition signal according to the order in which the pre-synaptic and post-synaptic neuron pulses arrive, and output it to the control weight adjustment circuit; The front and rear amplitude control circuits are used to generate pulse signals of corresponding duration according to the action time of the pre-synaptic and post-synaptic neuron pulses; the weight adjustment circuit receives the enhancement signal or the inhibition signal output by the STDP algorithm circuit, and determines to apply the pulse signal generated by the front amplitude control circuit or the rear amplitude control circuit to the Hall bar, so as to increase or decrease the abnormal Hall resistance value of the Hall bar; When the presynaptic neuron pulse arrives earlier than the postsynaptic neuron pulse, the STDP algorithm circuit generates an enhancement signal, and the weight adjustment circuit applies the pulse signal output by the front amplitude control circuit to both ends of the Hall bar, and the abnormal Hall resistance value of the Hall bar increases; when the presynaptic neuron pulse arrives later than the postsynaptic neuron pulse, the STDP algorithm circuit generates an inhibition signal, and the weight adjustment circuit applies the pulse signal output by the rear amplitude control circuit to both ends of the Hall bar, and the abnormal Hall resistance value of the Hall bar decreases; the STDP algorithm circuit includes a first AND gate G1, a first NAND gate G2, a first P-type field effect transistor P1, a first resistor R1, a first capacitor C1, a first N-type field effect transistor N1, a second resistor R2, a first voltage comparator U1, a third resistor R3, a second AND gate G3, a second NAND gate G4, a second P-type field effect transistor P2, a fourth resistor R4, a second capacitor C2, a second N-type field effect transistor N2, a fifth resistor R5, a second voltage comparator U2 and a sixth resistor R6; Among them, the input end of the first NOT gate G1 is connected to the drain of the second P-type field effect transistor P2, one input end of the first NAND gate G2 is connected to the output end of the first NOT gate G1, the other input end is used to receive the presynaptic neuron pulse signal pre, and the output end is connected to the gate of the first P-type field effect transistor P1; the source of the first P-type field effect transistor P1 is connected to VCC, and the drain is connected to one end of the first resistor R1, one end of the first capacitor C1 and the drain of the first N-type field effect transistor N1; the other ends of the first resistor R1 and the first capacitor C1 are grounded; the gate of the first N-type field effect transistor N1 receives the postsynaptic neuron pulse signal post, and the source is connected to one end of the second resistor R2 and the in-phase input end of the first voltage comparator U1; the other end of the second resistor is grounded; the inverting input end of the first voltage comparator U1 is connected to the control voltage Vth, the positive power supply end of the first voltage comparator U1 is connected to VCC and one end of the third resistor R3, the negative power supply end is grounded, and the output end outputs the enhanced signal Stren; the other end of the third resistor R3 is connected to the output end of the first voltage comparator U1; The input end of the second NOT gate G3 is connected to the drain of the first P-type field effect transistor P1, and the output end is connected to an input end of the second NAND gate G4; the other input end of the second NAND gate G4 receives the post-synaptic neuron pulse signal post, and the output end is connected to the gate of the second P-type field effect transistor P2; the source of the second P-type field effect transistor P2 is connected to VCC, and the drain is connected to one end of the fourth resistor R4, one end of the second capacitor C2, the input end of the first AND gate G1 and the drain of the second N-type field effect transistor N2; the other end of the fourth resistor R4 and the second capacitor C2 is grounded; the source of the second N-type field effect transistor N2 is connected to one end of the fifth resistor R5 and the in-phase input end of the second voltage comparator U2, and the gate receives the pre-synaptic neuron pulse signal pre; The other end of the fifth resistor R5 is grounded; the inverting input end of the second voltage comparator U2 is connected to the control voltage Vth, the positive power supply end of the second voltage comparator U2 is connected to VCC and one end of the sixth resistor R6, the negative power supply end is grounded, and the output end outputs the inhibition signal Restr; the other end of the sixth resistor R6 is connected to the output end of the second voltage comparator U2.

2. The unsupervised learning circuit of Hall bar synapse based on pulse amplitude as claimed in claim 1, characterized in that: The front amplitude control circuit includes a third voltage comparator U3, a seventh resistor R7, an eighth resistor R8, a third NOT gate G5, a third P-type field effect transistor P3, a ninth resistor R9, a tenth resistor R10 and a third capacitor C3; wherein, the in-phase input terminal of the third voltage comparator U3 receives a presynaptic neuron pulse signal pre, and the inverting input terminal receives a control voltage Vth2, the Vth2 voltage is adjustable from 0.1v to the power supply voltage, the positive power supply terminal is connected to VCC, the negative power supply terminal is grounded, and the output terminal is connected to one end of the seventh resistor R7; the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the input end of the third NOT gate G5; the other end of the eighth resistor R8 is connected to VCC; the output end of the third NOT gate G5 is connected to the gate of the third P-type field effect transistor P3; the source of the third P-type field effect transistor P3 is connected to VCC, and the drain is connected to one end of the ninth resistor R9; the other end of the ninth resistor R9 is connected to the tenth resistor R10 and one end of the third capacitor C3 to output a pulse signal; the other ends of the tenth resistor R10 and the third capacitor C3 are grounded.

3. The unsupervised learning circuit of Hall bar synapse based on pulse amplitude as claimed in claim 2, characterized in that: The post-amplitude control circuit includes a fourth voltage comparator U4, an eleventh resistor R11, a twelfth resistor R12, a fourth NOT gate G6, a fourth P-type field effect transistor P4, a thirteenth resistor R13, a fourteenth resistor R14 and a fourth capacitor C4; wherein the fourth voltage comparator U4 has a positive input terminal that receives a postsynaptic neuron pulse signal post, a negative input terminal that receives a control voltage Vth2, a positive terminal connected to VCC, a negative terminal connected to ground, and an output terminal connected to one end of the eleventh resistor R11; the eleventh resistor R11 has a positive terminal that receives a postsynaptic neuron pulse signal post, a negative terminal that receives a control voltage Vth2, a positive terminal connected to VCC, a negative terminal connected to ground, and an output terminal connected to one end of the eleventh resistor R11; The other end is connected to one end of the twelfth resistor R12 and the input end of the fourth NOT gate G6; the other end of the twelfth resistor R12 is connected to VCC; the output end of the fourth NOT gate G6 is connected to the gate of the fourth P-type field effect transistor P4; the source of the fourth P-type field effect transistor P4 is connected to VCC, and the drain is connected to one end of the thirteenth resistor R13; the other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and one end of the fourth capacitor C4 to output a pulse signal; the other ends of the fourteenth resistor R14 and the fourth capacitor C4 are grounded.

4. The unsupervised learning circuit of Hall bar synapse based on pulse amplitude as claimed in claim 2, characterized in that: The voltage values ​​of the control voltage Vth and the control voltage Vth2 are greater than 0.1V and less than the power supply voltage.

5. The unsupervised learning circuit of Hall bar synapse based on pulse amplitude as claimed in claim 3, characterized in that: The weight adjustment circuit includes a fifth DC blocking capacitor C5, a fifteenth resistor R15, a sixteenth resistor R16, a first voltage stabilizing diode D1, a fifth P-type field effect transistor P5, a third N-type field effect transistor N3, a fifth NOT gate G7, a sixth DC blocking capacitor C6, a seventeenth resistor R17, an eighteenth resistor R18, a second voltage stabilizing diode D2, a sixth P-type field effect transistor P6, a fourth N-type field effect transistor N4, a sixth NOT gate G8 and a Hall bar; Among them, one end of the fifth DC blocking capacitor C5 is connected to the output end of the first voltage comparator U1 to receive the enhanced signal Stren, and the other end of the fifth DC blocking capacitor C5 is connected to one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16; the other end of the fifteenth resistor R15 is connected to VCC, and the other end of the sixteenth resistor R16 is connected to the gate of the fifth P-type field effect transistor P5 and the positive electrode of the first voltage zener diode D1; the source of the fifth P-type field effect transistor P5 is connected to the other end of the ninth resistor R9 and the negative electrode of the first voltage zener diode D1, and the drain is connected to the drain of the third N-type field effect transistor N3 and the input end of the Hall bar in the direction of increasing the resistance; the gate of the third N-type field effect transistor N3 is connected to the output end of the fifth NOT gate G7, and the source is grounded; One end of the sixth DC blocking capacitor C6 is connected to the output end of the second voltage comparator U2 and to the suppression signal Restr, and the other end of the sixth DC blocking capacitor C6 is connected to the seventeenth resistor R17, one end of the eighteenth resistor R18 and the input end of the fifth NOT gate G7; the other end of the seventeenth resistor R17 is connected to VCC, and the other end of the eighteenth resistor R18 is connected to the gate of the sixth P-type field effect transistor P6 and the positive electrode of the second voltage zener diode D2; the source of the sixth P-type field effect transistor P6 is connected to the other end of the thirteenth resistor R13 and the negative electrode of the second voltage zener diode D2, and the drain is connected to the drain of the fourth N-type field effect transistor N4 and the input end of the Hall bar in the direction of reducing the resistance; the gate of the fourth N-type field effect transistor N4 is connected to the output end of the sixth NOT gate G8, and the source is grounded; the input end of the sixth NOT gate G8 is connected to the other end of the fifth DC blocking capacitor C5.

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