Method for manufacturing memory, memory, and memory system

Abstract

The present application provides a method for manufacturing a memory, a memory, and a memory system, the method comprising: forming a stacked layer on a substrate, the stacked layer having a first side close to the substrate and a second side away from the substrate; forming a memory channel hole penetrating the stacked layer and extending into the substrate; removing the substrate; forming a memory channel structure in the memory channel hole from the first side, the memory channel structure comprising a memory function layer and a channel layer, and having a second end close to the second side; removing the memory function layer in the second end and exposing the channel layer in the second end; forming a semiconductor layer on the second side of the stacked layer, the semiconductor layer covering the exposed channel layer, thereby being able to manufacture a highly uniform memory channel structure without damaging the memory channel structure, thereby improving memory performance, and facilitating lowering channel hole manufacturing requirements and reducing process difficulty.

Description

Technical field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a memory, a memory, and a memory system. [Background Technology]

[0002] Three-dimensional NAND (3D NAND) is an emerging type of memory. Unlike 2D NAND, which places storage cells on a plane, 3D NAND technology stacks multiple layers of storage cells vertically, creating a memory with a storage capacity several times higher than that of 2D NAND technology.

[0003] Among the various process steps in 3D NAND manufacturing, the etching of channel holes has always been a very important step. Since the low-temperature etching process can achieve higher aspect ratio etching and can bring faster etching rates to the nitride oxide film layer and polysilicon, in existing 3D NAND, channel holes are usually manufactured using a low-temperature etching process. However, as the number of stacked layers gradually increases, channel holes with high aspect ratios are becoming increasingly difficult to manufacture, and the depth of the hole is too deep or too shallow, which can easily affect subsequent processes. For example, in the subsequent CMP (Chemical Mechanical Polishing) process of thinning the substrate, it is easy to damage the storage channel structure, thereby affecting the performance of the memory. [Summary of the invention]

[0004] The present invention provides a method for manufacturing a memory, a memory and a memory system, which can avoid damage to a memory channel structure during the manufacturing process and improve memory performance.

[0005] An embodiment of the present application provides a method for manufacturing a memory, wherein the memory includes a memory array device, and the manufacturing method includes:

[0006] forming a stacked layer on a substrate, wherein the stacked layer has a first side close to the substrate and a second side facing away from the substrate;

[0007] forming a storage channel hole penetrating the stacked layers and extending into the substrate;

[0008] removing the substrate;

[0009] forming a storage channel structure in the storage channel hole from the first side, the storage channel structure including a storage function layer and a channel layer, and having a second end portion close to the second side;

[0010] removing the storage functional layer in the second end portion and exposing the channel layer in the second end portion;

[0011] A semiconductor layer is formed on the second side of the stacked layer, where the semiconductor layer covers the exposed channel layer, so as to obtain the memory array device.

[0012] In some embodiments, after forming a storage channel structure in the storage channel hole from the first side, the method further includes:

[0013] The memory array device is bonded to a peripheral circuit device from the first side of the stacked layer.

[0014] In some embodiments, the storage channel structure further includes a first end portion close to the first side, and before the step of bonding the memory array device to the peripheral circuit device from the first side of the stacked layer, further includes:

[0015] forming a dielectric layer on the first side of the stack;

[0016] A plug structure is formed in the dielectric layer, wherein the plug structure penetrates the dielectric layer and connects the channel layer in the first end portion.

[0017] In some embodiments, before removing the substrate, the method further includes:

[0018] forming a sacrificial channel structure in the storage channel hole from the second side, the sacrificial channel structure filling the storage channel hole; and

[0019] After removing the substrate, the method further includes removing the sacrificial channel structure from the first side.

[0020] In some embodiments, the material of the sacrificial channel structure includes carbide.

[0021] In some embodiments, before removing the substrate, the method further includes:

[0022] The memory array device is bonded to a sacrificial substrate from the second side of the stacked layer.

[0023] In some embodiments, before the step of bonding the second side of the stacked layer to a sacrificial substrate, the method further includes:

[0024] forming a spacer layer on the second side of the stack;

[0025] forming an interconnection layer on the spacer layer;

[0026] The step of bonding the memory array device to a sacrificial substrate from the second side of the stacked layer includes bonding the interconnect layer to a sacrificial substrate.

[0027] In some embodiments, the stacked layer includes a stop layer near the second end portion, and the step of removing the storage function layer in the second end portion includes:

[0028] removing the sacrificial substrate and the interconnect layer to expose the spacer layer;

[0029] The exposed spacer layer is selectively etched, and the etching is stopped at the stop layer.

[0030] In some embodiments, the stacked layers further include gate spacer layers and sacrificial layers alternately stacked, the stop layer is located between the gate spacer layers and the sacrificial layers, and after the step of forming a storage channel structure in the storage channel hole from the first side, the method further includes:

[0031] forming a gate slit in the stacked layer from the first side, the gate slit extending into the stop layer;

[0032] Removing the corresponding sacrificial layer through the gate gap to form a filling gap;

[0033] A gate layer is formed in the filling gap, and a gate gap structure is formed in the gate gap.

[0034] An embodiment of the present application further provides a memory, including a memory array device, wherein the memory array device includes:

[0035] stacked structure;

[0036] a storage channel structure, the storage channel structure being located in the stacked structure and penetrating the stacked structure, the storage channel structure comprising a storage function layer and a channel layer, and having a second end portion having a larger critical dimension and a first end portion having a smaller critical dimension;

[0037] A semiconductor layer is located on a side of the stacked structure close to the second end, and the channel layer in the second end extends into the semiconductor layer.

[0038] In some embodiments, the memory further includes a peripheral circuit device, wherein the peripheral circuit device is bonded to a side of the memory array device close to the first end.

[0039] In some embodiments, the memory array device further includes a dielectric layer and a plug structure in the dielectric layer, wherein the dielectric layer is located between the stacked structure and the peripheral circuit device, and the plug structure penetrates the dielectric layer and is connected to the channel layer in the first end portion.

[0040] In some embodiments, the stacked structure includes a stop layer near the second end portion, and gate spacer layers and gate layers that are alternately stacked.

[0041] In some embodiments, the memory array device further includes a gate gap structure, wherein the gate gap structure is located in the stack structure and extends from a side of the stack structure close to the first end portion into the stop layer.

[0042] An embodiment of the present application further provides a memory system, which includes at least one memory of any one of the above-mentioned types, and a controller coupled to the memory, wherein the controller is used to control the memory to perform data writing and reading operations.

[0043] The memory manufacturing method, memory and memory system provided by the embodiments of the present application are achieved by forming a stacking layer on a substrate, the stacking layer having a first side close to the substrate and a second side away from the substrate, then forming a memory channel hole that penetrates the stacking layer and extends into the substrate, then removing the substrate, and forming a memory channel structure in the memory channel hole from the first side, the memory channel structure including a memory function layer and a channel layer, and having a second end close to the second side, then removing the memory function layer in the second end and exposing the channel layer in the second end, finally forming a semiconductor layer on the second side of the stacking layer, the semiconductor layer covering the exposed channel layer, thereby being able to manufacture a highly unified memory channel structure without damaging the memory channel structure, thereby improving memory performance, and helping to reduce the manufacturing requirements of the channel hole and reduce the difficulty of the process.

Brief Description of the Drawings

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 1 is a flow chart of a method for manufacturing a memory provided in an embodiment of the present application;

[0046] Figures 2a to 2c 1 is a schematic diagram of a cross-sectional structure of a memory device at different process steps in another manufacturing method provided in an embodiment of the present application;

[0047] Figures 3a to 31 yes Figure 1 Schematic diagram of the cross-sectional structure of the memory at different process steps in the provided manufacturing method;

[0048] Figure 4It is a structural diagram of the memory system provided in an embodiment of the present application. [Specific implementation method]

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It is particularly noted that the following examples are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Similarly, the following examples are only some embodiments of the present invention and are not intended to be exhaustive. All other embodiments obtained by those of ordinary skill in the art without creative effort are intended to fall within the scope of protection of the present invention.

[0050] In the description herein, it should be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting this application. In addition, the terms "first" and "second" are used for descriptive purposes only, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of such features.

[0051] In this description, it should be noted that, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0052] It will be understood that the meanings of “on,” “over,” and “over” in the description herein should be interpreted in the broadest manner, such that “on” not only means “on” something with no intervening features or layers (i.e., directly on something), but also includes “on” something with intervening features or layers.

[0053] The terms used herein are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural form. The meaning of "plurality" is two or more. It should also be understood that the terms "include" and / or "comprising" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not exclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0054] Embodiments of the present application provide a method for manufacturing a memory, a memory, and a memory system.

[0055] See Figure 1 , Figure 1 A method for manufacturing a memory provided in an embodiment of the present application, wherein the memory includes a memory array device, and the manufacturing method includes the following steps:

[0056] Step S101: forming a stacked layer on a substrate, wherein the stacked layer has a first side close to the substrate and a second side away from the substrate;

[0057] Step S102: forming a storage channel hole penetrating the stacked layer and extending into the substrate;

[0058] Step S103, removing the substrate;

[0059] Step S104: forming a storage channel structure in the storage channel hole from the first side, the storage channel structure including a storage function layer and a channel layer, and having a second end portion close to the second side;

[0060] Step S105: removing the storage functional layer in the second end portion, and exposing the channel layer in the second end portion;

[0061] Step S106 : forming a semiconductor layer on the second side of the stacked layer, wherein the semiconductor layer covers the exposed channel layer, so as to obtain the memory array device.

[0062] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0063] Under normal circumstances, although the storage channel hole is etched from top to bottom, resulting in the side of the storage channel hole with the smaller aperture (i.e., the side located within the substrate) having different depths, the side with the larger aperture can maintain the same height. Because the storage channel structure in this embodiment is formed after removing the substrate, the uneven depths of the storage channel hole within the substrate can be removed when the substrate is removed, so that the side with the smaller aperture and the side with the larger aperture of the storage channel hole can maintain the same height. As a result, not only can both ends of the storage channel structure subsequently filled therein (including the second end with the larger critical dimension and the first end with the smaller critical dimension) have the same height (extended depth), but this manufacturing method also does not damage the storage channel structure itself.

[0064] In some embodiments, see Figures 2a to 2c , Figures 2a to 2c Another method for manufacturing a memory 10 is shown, wherein, when manufacturing a memory array device 110, after forming a memory channel hole Q extending into a substrate 111 in a stacked layer 112, a memory channel structure 113 is directly filled in the memory channel hole Q. At this time, the memory channel structure 113 includes a second end q2 having a larger critical dimension (equivalent to a larger diameter) and a first end q1 having a smaller critical dimension (equivalent to a smaller diameter). Then, the memory array device 110 is bonded to the peripheral circuit device 120 from the side of the stacked layer 112 close to the second end q2. Afterwards, the substrate 111 is removed, for example, by CMP (Chemical Mechanical Processing). The substrate 111 is thinned by a chemical mechanical polishing (CMP) process, and then the remaining substrate 111 and the storage functional layer in the first end portion q1 (not numbered in the figure) are removed by a wet etching process to facilitate the subsequent generation of a semiconductor layer used as a common source (not shown in the figure). However, since the heights of the first end portion q1 in the substrate 111 vary, it is not easy to control the grinding thickness during the CMP process. For example, if the grinding thickness is too large, it is easy to damage the first end portion q1 that extends deeper, while if the grinding thickness is too small, it is difficult to achieve the thinning purpose. That is, when manufacturing the memory 10 using this method, not only is there an extremely high control requirement for the digging depth of the storage channel hole Q, but it is also easy to damage the storage channel structure 113.

[0065] See Figures 3a to 31 , Figures 3a to 31 yes Figure 1 The cross-sectional structure diagram of the memory 20 at different process steps in the manufacturing method provided is shown, and the memory 20 includes a memory array device 210. Figures 3a to 31 , further describing the above steps S101-S106, wherein:

[0066] In step S101 , a stacked layer 212 is formed on a substrate 211 . The stacked layer 212 has a first side A1 close to the substrate 211 and a second side A2 away from the substrate 211 .

[0067] Among them, Figure 3a In the embodiment, the material of the substrate 211 may include at least one of single crystal silicon (Si), single crystal germanium (Ge), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0068] In some embodiments, the stacked layer 212 includes alternating gate spacer layers 2121 and sacrificial layers 2122, and the number of layers may be 8, 32, 64, or 128. The gate spacer layers 2121 and the sacrificial layers 2122 may be formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate spacer layers 2121 may be made of silicon oxide or other insulating materials, and the sacrificial layers 2122 may be made of silicon nitride, etc., which may be used for subsequent replacement to form a gate structure.

[0069] Step S102 : forming a storage channel hole Q penetrating the stacked layer 212 and extending into the substrate 211 .

[0070] Among them, Figure 3b In the embodiment of the present invention, a storage channel hole Q can be formed in the stacked layer 212 by dry etching. It should be noted that, due to the limitations of the etching process, the cross-sectional shape of the storage channel hole Q is not a rectangle, but an inverted trapezoid with a wide top and a narrow bottom. That is, the end of the storage channel hole Q close to the second side A2 has a larger aperture, and the end close to the first side A1 has a smaller aperture. Moreover, when the number of stacked layers 212 is large, the etching resistance becomes greater as it approaches the bottom of the stacked layer 212. Therefore, it is easy for the etched storage channel hole Q to have different depths in the substrate 211, for example Figure 3b It can be clearly seen from the figure that the end portions of the storage channel holes Q close to the first side A1 have different extension depths in the substrate 211 .

[0071] Step S103: removing the substrate 211.

[0072] The substrate 211 can be removed by a CMP (Chemical Mechanical Polishing) process. During the CMP process, the portion of the storage channel hole Q extending into the substrate 211 (i.e., the portion with different depths) is also removed, so that both ends of the storage channel hole Q can maintain a uniform height (see details). Figure 3f ).

[0073] It is easy to understand that in order to avoid directly removing the substrate 211 and causing deformation of the stacked layer 212, another substrate for carrying the stacked layer 212 can be bonded before removal, that is, see Figures 3b to 3e Before the above step S103, the manufacturing method of the memory 20 may further include:

[0074] The memory array device 210 is bonded to the sacrificial substrate 213 from the second side A2 of the stacked layer 212 .

[0075] The material of the sacrificial substrate 213 may be the same as or different from that of the substrate 211 , as long as it can support the stacked layer 212 .

[0076] In some embodiments, in order to increase the adhesion between the sacrificial substrate 213 and the stacked layer 212, so as to facilitate better bonding between the sacrificial substrate 213 and the memory array device 210, some intermediate film layers that are conducive to bonding can be formed between the sacrificial substrate 213 and the stacked layer 212, for example, see Figures 3c to 3e Before the above step of “bonding the memory array device 210 to the sacrificial substrate 213 from the second side A2 of the stacked layer 212 ”, the manufacturing method of the memory 20 may further include:

[0077] forming a spacer layer 2141 on the second side A2 of the stacked layer 212;

[0078] An interconnection layer 2142 is formed on the spacer layer 2141 .

[0079] At this time, the above step of “bonding the memory array device 210 to the sacrificial substrate 213 from the second side A2 of the stacked layer 212 ” may specifically include: bonding the interconnection layer 2142 to the sacrificial substrate 213 .

[0080] The material of the spacer layer 2141 may include silicon oxide, etc., and the material of the interconnection layer 2142 may include silicon nitride. When the material of the subsequently fabricated sacrificial channel structure 215 includes carbon, the interconnection layer 2142 may be doped with carbon to further improve the adhesion between the stacked layer 212 and the sacrificial substrate 213. Prior to bonding, the surfaces of the interconnection layer 2142 and the sacrificial substrate 213 may be cleaned and activated, and then the two are bonded together through van der Waals forces, molecular forces, or even atomic forces.

[0081] It should be noted that before removing the substrate 211, in order to avoid damage to the stacked layer 212 in which the storage channel hole Q is formed due to grinding, for example, uneven stress may cause the stacked layer 212 around the storage channel hole Q to be misaligned or bent, so it is necessary to first fill the storage channel hole Q. In some embodiments, a storage channel structure can be directly formed in the storage channel hole Q for filling. However, since the substrate 211 needs to be removed by grinding later, this process will damage the storage channel structure (part of the storage channel structure located in the substrate 211 will be removed), affecting the performance of the storage channel structure. Therefore, in this embodiment, a sacrificial channel structure 215 can be first formed in the storage channel hole Q, and then the sacrificial channel structure 215 can be removed if a storage channel structure is to be formed later.

[0082] For details, see Figure 3b and Figure 3c Before the above step S103, the manufacturing method of the memory 20 may further include:

[0083] A sacrificial channel structure 215 is formed in the storage channel hole Q from the second side A2 , and the sacrificial channel structure 215 fills the storage channel hole Q.

[0084] In which, a sacrificial channel structure 215 can be formed in the storage channel hole Q by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The material of the sacrificial channel structure 215 can be some materials that do not affect the formation of subsequent storage channel structures and are easy to remove. For example, the material of the sacrificial channel structure 215 can include carbide, which includes carbon.

[0085] It is easy to understand that if the sacrificial channel structure 215 is formed before the above-mentioned step S103, then not only the substrate 211 needs to be removed subsequently, but also the sacrificial channel structure 215 needs to be removed, that is, the manufacturing method of the memory 20 also includes: removing the sacrificial channel structure 215 from the first side A1. The substrate 211 can be removed by a CMP process, and the sacrificial channel structure 215 can be removed by an ashing Asher process. When the material of the sacrificial channel structure 215 is carbon, the solid carbon can be oxidized into a gas by an oxygen plasma process in the ashing process. It should be pointed out that in the above-mentioned step S103, when the substrate 211 is removed by the CMP process, the storage channel hole Q and the sacrificial channel structure 215 in the substrate 211 are removed at the same time, so that the two ends of the final storage channel hole Q can maintain a high degree of uniformity.

[0086] Step S104 : forming a storage channel structure 216 in the storage channel hole Q from the first side A1 . The storage channel structure 216 includes a storage function layer 2161 and a channel layer 2162 , and has a second end portion q2 close to the second side A2 .

[0087] Among them, see Figure 3g The storage function layer 2161 may include a blocking layer, a charge capture layer and a tunneling layer (not shown in the figure), wherein the materials of the blocking layer, the charge capture layer and the tunneling layer may be silicon oxide, silicon nitride and silicon oxide respectively, and the material of the channel layer 2162 may be polysilicon, thereby forming a storage channel structure 216 of an "ONOP" structure.

[0088] It should be noted that because the aforementioned storage channel hole Q has highly uniform wide and narrow ends, the storage channel structure 216 formed in the storage channel hole Q also has highly uniform wide and narrow ends. The second end q2 of the storage channel structure 216, located near the second side A2, is the wide end with a larger critical dimension, while the first end q1, located near the first side A1, is the narrow end with a smaller critical dimension. The critical dimension refers to the cross-sectional width along the thickness direction of the stacked layer 212. This method of fabricating a highly uniform storage channel structure 216 eliminates the need for strict control of the hole depth, reduces the difficulty of the etching process, and prevents damage to the storage channel structure 216, thereby improving device performance.

[0089] In some embodiments, after the storage channel structure 216 is fabricated, the memory array device 210 can be bonded to the peripheral circuit device from the first side A1 of the stacked layer 212, thereby achieving electrical connection between the storage channel structure 216 and the peripheral circuit device. Figure 3g to Figure 3iAfter the above step S104 , the manufacturing method of the memory 20 may further include: bonding the memory array device 210 and the peripheral circuit device 220 from the first side A1 of the stacked layer 212 .

[0090] At the same time, in order to facilitate the electrical connection between the storage channel structure 216 and the peripheral circuit device 220, before the peripheral circuit device 220 is bonded, a plug structure M needs to be formed at the first end q1. Figure 3g After the above step S104, the manufacturing method of the memory 20 may further include:

[0091] forming a dielectric layer 217 on the first side A1 of the stacked layer 212;

[0092] A plug structure M is formed in the dielectric layer 217 . The plug structure M penetrates the dielectric layer 217 and connects to the channel layer 2162 in the first end portion q1 .

[0093] The material of the dielectric layer 217 may include silicon oxide, and the material of the plug structure M may include a conductive material, such as tungsten.

[0094] In addition, after the storage channel structure 216 is fabricated and before the peripheral circuit device 220 is attached, the sacrificial layer 2122 needs to be replaced with a gate. Specifically, a gate gap can be formed, the sacrificial layer 2122 is removed through the gate gap, and then a conductive material is filled to form a gate. At this time, the stacked layer 212 becomes a stacked structure 212', wherein the conductive material can be any one or a combination of tungsten, cobalt, copper, aluminum, doped crystalline silicon or silicide. For example, see Figure 3g and Figure 3h After the above step S104, the manufacturing method of the memory 20 may further include:

[0095] A gate gap (not numbered in the figure) is formed in the stacked layer 212 from the first side A1;

[0096] The sacrificial layer 2122 is removed through the gate gap to form a filling gap;

[0097] A gate layer 2124 is formed in the filled gap, and a gate gap structure N is formed in the gate gap.

[0098] Among them, when the above-mentioned dielectric layer 217 is formed after the storage channel structure 216 is formed, the gate gap formed at this time will also penetrate the dielectric layer 217. Specifically, the sacrificial layer 2122 can be removed by a wet etching process through the gate gap, and then a conductive material such as metal or polysilicon is filled to form a gate layer 2124. The material of the gate gap structure N can also include a conductive material, such as tungsten. In this case, the gate gap structure N can be used to realize the subsequent production of a common source (i.e., a semiconductor layer). The material of the gate gap structure N can also include an insulating material, such as silicon oxide. In this case, the gate gap structure N mainly plays a supporting role in the future. Of course, when the material of the gate gap structure N includes a conductive material, in order to prevent the conductive material from leaking out, a layer of insulating material, such as oxide, can be first deposited on the inner wall of the gate gap, and then a conductive material can be deposited on the insulating material layer.

[0099] Step S105 , removing the storage function layer 2161 in the second end portion q2 and exposing the channel layer 2162 in the second end portion q2 .

[0100] Among them, see Figures 3i to 3k , the storage function layer 2161 in the second end portion q2 and the stacked layer 212 wrapping the second end portion q2 can be removed by a selective etching process, so that the channel layer 2162 in the second end portion q2 protrudes from the surface of the second side A2 of the stacked layer 212. Specifically, the material ratio can be controlled to ensure that only oxides and nitrides are etched, and the channel layer 2162 is not etched, and the etching time can be controlled to ensure that the required etching depth is reached. It is easy to understand that when the memory 20 includes the above-mentioned interconnection layer 2142 and the sacrificial substrate 213, before the above-mentioned step S105, the manufacturing method of the memory 20 also includes: removing the sacrificial substrate 213 and the interconnection layer 2142, and exposing the spacer layer 2141 (see Figures 3i to 3j At this time, when the storage function layer 2161 in the second end portion q2 is removed by a selective etching process, the spacer layer 2141 can be removed at the same time.

[0101] In some embodiments, in order to more accurately control the etching depth of the selective etching, a stop layer 2123 may be provided in the stacked layer 212. For example, please continue to refer to Figures 3a to 3k The stacked layer 212 includes a stop layer 2123 near the second end q2. The stop layer 2123 may be located between the gate spacer layer 2121 and the sacrificial layer 2122. In this case, the above step S105 may specifically include:

[0102] The exposed spacer layer 2141 is selectively etched, and the etching stops at the stop layer 2123 .

[0103] The material of the stop layer 2123 may include polysilicon, or it may be other materials that do not affect the removal of the storage functional layer 2161 during the etching process while preserving some of the channel layer 2162. When the stop layer 2123 is present, precise control of the etching target and etching depth can be achieved by directly controlling the selective material ratio, thereby reducing the difficulty of controlling the etching process. It should be noted that since the gate slot structure N also includes an oxide material, in order to avoid the aforementioned selective etching process affecting the gate slot structure N, such as possibly etching away the oxide material at the end of the gate slot structure N, thereby causing the conductive material in the gate slot structure N to directly connect to the subsequently formed semiconductor layer, the extension depth of the gate slot structure N in the stacked layer 212 can be controlled. Generally, the end of the gate slot structure N can be made to not extend beyond the stop layer 2123. That is, in the aforementioned step of "forming a gate slot in the stacked layer 212 from the first side A1," the gate slot can be simultaneously extended into the stop layer 2123, without extending beyond the stop layer 2123.

[0104] It is easy to understand that when the stop layer 2123 is provided in the stacked layer 212 and the gate gap extends into the stop layer 2123, when the gate is replaced by the sacrificial layer 2122 in the stacked layer 212 through the gate gap, not all of the sacrificial layer 2122 may be replaced, and some of the sacrificial layers 2122, such as the sacrificial layer 2122 located below the stop layer 2123 (i.e., Figure 3h The sacrificial layer 2122 between the middle stop layer 2123 and the sacrificial substrate 213 cannot be replaced by the gate gap, but it will be removed in the above-mentioned selective etching process.

[0105] Step S106 : forming a semiconductor layer 218 on the second side A2 of the stacked layer 212 , wherein the semiconductor layer 218 covers the exposed channel layer 2162 .

[0106] Among them, see Figure 3l The material of the semiconductor layer 218 may include polycrystalline silicon, and a silicon material layer may be formed on the second side A2 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The silicon material layer is then doped and processed by, for example, a laser annealing process to form polycrystalline silicon, thereby obtaining the semiconductor layer 218.

[0107] In some embodiments, in order to improve the electrical connection between the storage channel structure 216 and the external circuit, the second end portion q2 may be ion doped before covering the semiconductor layer 218 to improve the conductivity of the storage channel structure 216. Since the semiconductor layer 218 covers the second end portion q2 having a larger critical dimension and a high degree of uniformity, during ion doping, not only can the uniformity of the doping concentration be ensured, but also, relative to the solution of doping the first end portion q1 with the semiconductor layer 218 covering the first end portion q1, the doping area can be increased, thereby improving the conductivity of the storage channel structure 216 and improving the performance of the memory 20.

[0108] Furthermore, in some embodiments, an insulating layer and a metal interconnect layer (not shown) may be sequentially formed on a side of the semiconductor layer 218 facing away from the stacked layer 212. The insulating layer may be made of an oxide, and the metal interconnect layer may be made of a conductive material such as tungsten, cobalt, copper, or aluminum. A contact structure may be formed in the insulating layer, penetrating the insulating layer, to connect an external circuit to the channel layer 2162 at the second end q2.

[0109] Based on the manufacturing method of the memory 20 described above, the embodiment of the present application further provides a memory 20, see Figure 3l , Figure 3l 2 is a schematic diagram of the structure of a memory 20 provided in an embodiment of the present application. The memory 20 includes a memory array device 210, a stacked structure 212', a memory channel structure 216, and a semiconductor layer 218. The memory channel structure 216 is located within and extends through the stacked structure 212'. The memory channel structure 216 includes a storage functional layer 2161 and a channel layer 2162. The memory channel structure 216 has a second end q2 with a larger critical dimension and a first end q1 with a smaller critical dimension. The critical dimension refers to the cross-sectional width in the thickness direction of the stacked structure 212'. The semiconductor layer 218 is located on a side of the stacked structure 212' close to the second end q2, and the channel layer 2162 in the second end q2 extends into the semiconductor layer 218.

[0110] In some embodiments, the memory 20 further includes a peripheral circuit device 220 , which is bonded to a side of the memory array device 210 close to the first end q1 .

[0111] In some embodiments, the memory 20 further includes a dielectric layer 217 and a plug structure M located in the dielectric layer 217. The dielectric layer 217 is located between the stacked structure 212' and the peripheral circuit device 220. The plug structure M penetrates the dielectric layer 217 and is connected to the channel layer 2162 in the first end portion q1.

[0112] In some embodiments, the stacked structure 212 ′ includes a stop layer 2123 near the second end portion q2 , and gate spacer layers 2121 and gate layers 2124 that are alternately stacked.

[0113] In some embodiments, the memory array device 210 further includes a gate gap structure N. The gate gap structure N is located in the stack structure 212 ′ and extends from a side of the stack structure 212 ′ close to the first end q1 to the inside of the stop layer 2123 .

[0114] It should be understood that the structures and manufacturing processes of the various components of the memory 20 in the embodiment of the present application can refer to the above-mentioned embodiment of the manufacturing method of the memory 20, and will not be repeated here.

[0115] In summary, the memory 20 and the manufacturing method thereof provided in the embodiment of the present application are as follows: a stacked layer 212 is formed on a substrate 211, wherein the stacked layer 212 has a first side A1 close to the substrate 211 and a second side A2 away from the substrate 211; a storage channel hole Q is then formed through the stacked layer 212 and extending into the substrate 211; the substrate 211 is then removed, and a storage channel structure 216 is formed in the storage channel hole Q from the first side A1; the storage channel structure 216 includes a storage function layer 2161 and a channel layer 2162; And it has a second end q2 close to the second side A2, then, the storage function layer 2161 in the second end q2 is removed, and the channel layer 2162 in the second end q2 is exposed, and finally, a semiconductor layer 218 is formed on the second side A2 of the stacked layer 212, and the semiconductor layer 218 covers the exposed channel layer 2162, so that a highly unified storage channel structure 216 can be produced without damaging the storage channel structure 216, thereby improving the performance of the memory 20, and helping to reduce the production requirements of the channel hole and reduce the process difficulty.

[0116] In addition, the present application also provides a memory system. Figure 4 , Figure 4 1 is a schematic diagram of the structure of a memory system 100 provided in an embodiment of the present application. The memory system 100 includes at least one of the aforementioned memories 20, and a controller 30 electrically connected to the memory 20. The controller 30 is also connected to an external host, which can transmit user commands and stored data to the controller 30. User commands may include write commands, erase commands, and read commands, etc. The controller 30 can determine which storage location in the memory 20 to write, erase, and read based on these commands.

[0117] In the examples of the present application, the memory 20 is not limited to a three-dimensional NAND memory. Without violating the disclosure or teaching of the present application, the memory 20 can be implemented as various other types of non-volatile memories that can retain stored data when power is disconnected.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a memory, characterized in that: The memory includes a memory array device, and the manufacturing method includes: forming a stacked layer on a substrate, wherein the stacked layer has a first side close to the substrate and a second side facing away from the substrate; forming a storage channel hole penetrating the stacked layers and extending into the substrate; removing the substrate; forming a storage channel structure in the storage channel hole from the first side, the storage channel structure including a storage function layer and a channel layer, and having a second end portion close to the second side; removing the storage functional layer in the second end portion and exposing the channel layer in the second end portion; A semiconductor layer is formed on the second side of the stacked layer, where the semiconductor layer covers the exposed channel layer, so as to obtain the memory array device.

2. The method for manufacturing a memory according to claim 1, wherein: The memory further includes a peripheral circuit device, and after the step of forming a storage channel structure in the storage channel hole from the first side, further includes: The memory array device is bonded to the peripheral circuit device from the first side of the stacked layer.

3. The method for manufacturing a memory according to claim 2, wherein: The storage channel structure further includes a first end portion close to the first side, and before the step of bonding the storage array device to the peripheral circuit device from the first side of the stacked layer, further includes: forming a dielectric layer on the first side of the stack; A plug structure is formed in the dielectric layer, wherein the plug structure penetrates the dielectric layer and connects the channel layer in the first end portion.

4. The method for manufacturing a memory according to claim 1, wherein: Before the step of removing the substrate, the method further comprises: forming a sacrificial channel structure in the storage channel hole from the second side, the sacrificial channel structure filling the storage channel hole; and After removing the substrate, the method further includes removing the sacrificial channel structure from the first side.

5. The method for manufacturing a memory according to claim 4, wherein: The material of the sacrificial channel structure includes carbide.

6. The method for manufacturing a memory according to claim 1, wherein: Before the step of removing the substrate, the method further comprises: The memory array device is bonded to a sacrificial substrate from the second side of the stacked layer.

7. The method for manufacturing a memory according to claim 6, wherein: Before the step of bonding the memory array device to a sacrificial substrate from the second side of the stacked layer, the method further includes: forming a spacer layer on the second side of the stack; forming an interconnection layer on the spacer layer; The step of bonding the memory array device to a sacrificial substrate from the second side of the stacked layer includes bonding the interconnect layer to a sacrificial substrate.

8. The method for manufacturing a memory according to claim 7, wherein: The stacked layer includes a stop layer near the second end portion, and the step of removing the storage function layer in the second end portion includes: removing the sacrificial substrate and the interconnect layer to expose the spacer layer; The exposed spacer layer is selectively etched, and the etching is stopped at the stop layer.

9. The method for manufacturing a memory according to claim 8, wherein: The stacked layers further include gate spacer layers and sacrificial layers alternately stacked, the stop layer is located between the gate spacer layers and the sacrificial layers, and after the step of forming a storage channel structure in the storage channel hole from the first side, the method further includes: forming a gate slit in the stacked layer from the first side, the gate slit extending into the stop layer; Removing the corresponding sacrificial layer through the gate gap to form a filling gap; A gate layer is formed in the filling gap, and a gate gap structure is formed in the gate gap.

10. A memory, characterized in that: A storage array device is provided, wherein the storage array device comprises: stacked structure; a storage channel structure, the storage channel structure being located in the stacked structure and penetrating the stacked structure, the storage channel structure comprising a storage function layer and a channel layer, and having a second end portion having a larger critical dimension and a first end portion having a smaller critical dimension, wherein the critical dimension of the second end portion is larger than the critical dimension of the first end portion; A semiconductor layer is located on a side of the stack structure close to the second end portion and covers the channel layer, and the channel layer in the second end portion extends into the semiconductor layer.

11. The memory according to claim 10, wherein: The memory further includes a peripheral circuit device bonded to a side of the memory array device close to the first end.

12. The memory according to claim 11, wherein: The memory array device further includes a dielectric layer and a plug structure located in the dielectric layer. The dielectric layer is located between the stacked structure and the peripheral circuit device. The plug structure penetrates the dielectric layer and is connected to the channel layer in the first end portion.

13. The memory according to claim 11, wherein: The stack structure includes a stop layer close to the second end, and gate spacer layers and gate layers that are alternately stacked.

14. The memory according to claim 13, wherein: The memory array device further includes a gate gap structure, which is located in the stack structure and extends from a side of the stack structure close to the first end to the stop layer.

15. A memory system, characterized in that: The method comprises at least one memory according to any one of claims 10 to 14, and a controller coupled to the memory, wherein the controller is used to control the memory to perform data writing and reading operations.

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