IGBT device and manufacturing method thereof

Abstract

The present invention provides an IGBT device and a method for manufacturing the same. A trench is formed above the drift region and extends through the well and source regions. First and second polysilicon layers are located within the trench. The first polysilicon layer is connected to a gate electrode, while the second polysilicon layer is located below the source region and is isolated from the first polysilicon layer, the well, and the drift region. The IGBT device of the present invention has low gate capacitance, resulting in fast turn-on and turn-off speeds and low losses.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBTs, and in particular to an IGBT device and a method for manufacturing the IGBT device. Background Art

[0002] IGBTs (Insulated Gate Bipolar Transistors) combine the advantages of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and GTRs (Giant Transistors), offering fast switching speeds, low on-state voltage drop, large capacity, and flexible control. They are currently the primary power switching device in inverter welding machines. The primary factor affecting IGBT switching speed is the charging and discharging of gate capacitance by the gate control circuit. Therefore, to increase IGBT switching speed, gate capacitance must be minimized. Reducing gate capacitance has become a pressing issue. Summary of the Invention

[0003] In order to solve the above technical problems, the present invention provides an IGBT device and a manufacturing method thereof. The IGBT device has a small gate capacitance, thus having a fast turn-on and turn-off speed and low loss.

[0004] The technical solution adopted in the present invention is as follows:

[0005] An IGBT device, wherein a trench of the IGBT device is formed in the upper portion of a drift region and passes through a well region and a source region, wherein first polysilicon and second polysilicon are provided in the trench, wherein the first polysilicon is connected to a gate electrode, and the second polysilicon is located in a space below the source region, and the second polysilicon is isolated from the first polysilicon, the well region, and the drift region.

[0006] The second polysilicon is rectangular and is embedded in the rectangular notch of the first polysilicon. The second polysilicon is isolated from the rectangular notch of the first polysilicon by a gate oxide layer.

[0007] The second polysilicon and the well region, as well as the second polysilicon and the drift region are isolated by a gate oxide layer.

[0008] The well region is a P-type well region, and the source region is an N+ source region.

[0009] A method for manufacturing the above-mentioned IGBT device includes the following steps: forming the trench; growing an oxide layer in the trench to form a first gate oxide layer; depositing a layer of polysilicon on the first gate oxide layer to fill the trench, and forming a second polysilicon by photolithography and etching, wherein the size of the second polysilicon is smaller than the trench; removing the first gate oxide layer outside the second polysilicon; growing an oxide layer again in the remaining space in the trench to form a second gate oxide layer; depositing a layer of polysilicon on the second gate oxide layer to fill the trench, and forming the first polysilicon by photolithography and etching; and forming other structures of the IGBT device.

[0010] Other structures of the IGBT device include a P-region, an N+region, a dielectric layer, a hole, a P+region, and a metal layer.

[0011] Beneficial effects of the present invention:

[0012] The IGBT device of the present invention has a small gate capacitance, and thus has a fast turn-on and turn-off speed and low loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic cross-sectional view of an IGBT device according to an embodiment of the present invention, vertically cut at the location of the first polysilicon;

[0014] Figure 2 A schematic diagram of a cross-section and a three-dimensional structure of an IGBT device according to an embodiment of the present invention, taken vertically at the location of the first polysilicon;

[0015] Figure 3 A schematic diagram of a cross-section and a three-dimensional structure of an IGBT device according to an embodiment of the present invention, taken vertically at the location of the second polysilicon;

[0016] Figure 4 This is a schematic diagram of the three-dimensional structure of an IGBT device according to an embodiment of the present invention, cut along the side surface of the trench. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] like Figures 1 to 4As shown, the trench 1 of the IGBT device of the embodiment of the present invention is formed on the upper part of the drift region 2 and passes through the well region 3 and the source region 4. A first polysilicon 5 and a second polysilicon 6 are provided in the trench 1. The first polysilicon 5 is connected to the gate electrode, and the second polysilicon 6 is located in the space below the source region 4. The second polysilicon 6 is isolated from the first polysilicon 5, the well region 3, and the drift region 2.

[0019] In one embodiment of the present invention, the first polysilicon 5 may be connected to the gate metal through a through hole opened at the edge of the device.

[0020] In one embodiment of the present invention, the second polysilicon 6 is rectangular and is embedded in the rectangular notch of the first polysilicon 5. The second polysilicon 6 and the rectangular notch of the first polysilicon 5 can be isolated by a gate oxide layer. The second polysilicon 6 and the well region 3, as well as the second polysilicon 6 and the drift region 2, are both isolated by a gate oxide layer.

[0021] Specifically, if Figures 1 to 4 As shown, the top and both end surfaces of the second polysilicon 6 are isolated from the corresponding interlocking surfaces of the rectangular notch of the first polysilicon 5 by a gate oxide layer; the bottom surface of the second polysilicon 6 is isolated from the drift region 2 by a gate oxide layer; and the two side surfaces of the second polysilicon 6 are isolated from the well region 3 by a gate oxide layer. In other words, the second polysilicon 6 is in a floating state relative to the surrounding structures.

[0022] In one embodiment of the present invention, the well region 3 is a P-type well region, the well region forming the trench 1 is a P- region, and the source region is an N+ source region.

[0023] Based on the above structure, the polysilicon gate in the normal source area is complete polysilicon, while in the non-source area, the polysilicon is separated into floating polysilicon and polysilicon connected to the gate. In this way, since the polysilicon connected to the gate removes the P-region part connected to the source, the gate-source capacitance is reduced. The gate-drain capacitance is also reduced due to the thickening of the gate oxide layer between the floating polysilicon and the drain.

[0024] The IGBT device according to the embodiment of the present invention has a small gate capacitance, and thus has a fast turn-on and turn-off speed and low loss.

[0025] Corresponding to the IGBT device of the above embodiment, the present invention further provides a method for manufacturing the IGBT device.

[0026] The method for manufacturing an IGBT device according to an embodiment of the present invention includes the following steps: forming the trench; growing an oxide layer in the trench to form a first gate oxide layer; depositing a layer of polysilicon on the first gate oxide layer to fill the trench, and photolithographically etching to form a second polysilicon layer, wherein the second polysilicon is smaller than the trench; removing the first gate oxide layer outside the second polysilicon; growing another oxide layer in the remaining space in the trench to form a second gate oxide layer; depositing a layer of polysilicon on the second gate oxide layer to fill the trench, and photolithographically etching to form the first polysilicon layer; and forming other structures of the IGBT device. The other structures of the IGBT device include a P- region, an N+ region, a dielectric layer, a hole, a P+ region, a metal layer, etc.

[0027] In a specific embodiment of the present invention, a method for manufacturing an IGBT device includes:

[0028] 1. Trench lithography and etching

[0029] The trench area is defined by photolithography, and the Si in the area is etched into a trench of the required depth.

[0030] 2. Gate Oxide 1

[0031] An oxide layer is grown on the silicon surface using thermal oxidation to form a first gate oxide layer.

[0032] 3. Second polysilicon deposition

[0033] A layer of polysilicon is deposited on the first gate oxide layer to fill the trench and form a second polysilicon layer.

[0034] 4. Second polysilicon photolithography and etching

[0035] The second polysilicon region is defined by photolithography, and unnecessary second polysilicon is etched away.

[0036] 5. Etch the second polysilicon.

[0037] The second polysilicon on the surface is etched to make the upper surface of the second polysilicon lower than the Si surface, leaving space for the first polysilicon.

[0038] 6. First gate oxide layer corrosion

[0039] The first gate oxide layer exposed outside the second polysilicon is etched away.

[0040] 7. Gate Oxide 2

[0041] An oxide layer is grown on the silicon surface using thermal oxidation to form a second gate oxide layer.

[0042] 8. First polysilicon deposition

[0043] A layer of polysilicon is deposited on the second gate oxide layer to fill the trench and form a first polysilicon.

[0044] 9. First polysilicon lithography and etching

[0045] The first polysilicon region is defined by photolithography, and unnecessary first polysilicon is etched away.

[0046] 10. P-area lithography and implantation

[0047] Photolithography defines the area where implantation is required, and boron ions are implanted into the corresponding area to form a P-layer.

[0048] 11. N+ region lithography and implantation

[0049] Photolithography defines the area where injection is required, and arsenic ions or phosphorus ions are injected into the corresponding area to form an N+ layer.

[0050] 12. Dielectric layer deposition

[0051] An insulating dielectric layer is deposited on the surface to serve as electrical isolation between the polysilicon and the metal.

[0052] 13. Hole lithography and etching

[0053] The active layer hole layer and the hole layer on different polysilicon gates are defined by photolithography, and the unnecessary layer dielectric layer is etched away.

[0054] 14. P+ region lithography and implantation

[0055] Photolithography defines the area where injection is required, and boron ions are injected into the corresponding area to form a P+ layer.

[0056] 15. Metal layer deposition

[0057] A layer of metal is deposited on the insulating dielectric layer.

[0058] 16. Metal layer lithography and etching

[0059] The active metal layer domain and the gate metal layer domain are defined by photolithography, and etching is performed to form the active area electrode and gate electrode of the device.

[0060] According to the method for manufacturing an IGBT device in an embodiment of the present invention, the gate capacitance of the manufactured IGBT device is small, so the turn-on and turn-off speeds are fast and the loss is low.

[0061] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. "Multiple" means two or more, unless otherwise specifically defined.

[0062] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0063] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0064] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0065] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0066] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0067] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0068] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0069] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing module, or each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

[0070] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and are not to be construed as limiting the present invention. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. An IGBT device, characterized in that: The trench of the IGBT device is formed at the upper part of the drift region and passes through the well region and the source region. A first polysilicon and a second polysilicon are provided in the trench. The first polysilicon is connected to the gate electrode. The second polysilicon is located in the space below the source region, and the second polysilicon is isolated from the first polysilicon, the well region, and the drift region. The second polysilicon is rectangular and embedded in the rectangular notch of the first polysilicon. The second polysilicon is isolated from the rectangular notch of the first polysilicon by a gate oxide layer. The rectangular notch of the first polysilicon corresponds to the well region between the two source regions, so that the polysilicon gates at the two source regions are the two side parts of the first polysilicon on both sides of the rectangular notch, and the polysilicon gate at the position between the two source regions includes the upper part of the first polysilicon in the rectangular notch and the floating second polysilicon.

2. The IGBT device according to claim 1, wherein: The second polysilicon and the well region, as well as the second polysilicon and the drift region are isolated by a gate oxide layer.

3. The IGBT device according to claim 1, wherein: The well region is a P-type well region, and the source region is an N+ source region.

4. A method for manufacturing an IGBT device according to any one of claims 1 to 3, characterized in that: The following steps are involved: forming the groove; growing an oxide layer in the trench to form a first gate oxide layer; Depositing a layer of polysilicon on the first gate oxide layer to fill the trench, and forming the second polysilicon by photolithography and etching, wherein the size of the second polysilicon is smaller than the trench; removing the first gate oxide layer outside the second polysilicon; growing another oxide layer in the remaining space of the trench to form a second gate oxide layer; Depositing a layer of polysilicon on the second gate oxide layer to fill the trench, and etching the layer by photolithography to form the first polysilicon; Other structures of the IGBT device are formed.

5. The method for manufacturing an IGBT device according to claim 4, wherein: Other structures of the IGBT device include a P-region, an N+region, a dielectric layer, a hole, a P+region, and a metal layer.

Images