Multi-phase switching converter, integrated circuit controller device and control method thereof

Abstract

Disclosed are a multiphase switching converter, an integrated circuit control device and a control method thereof. The multiphase switching converter comprises a master switching circuit having a first power switch and a plurality of slave switching circuits, and the control method comprises: receiving a slave temperature signal representing a slave power switch temperature of each slave switching circuit and a first temperature signal representing a first power switch temperature; proportionally integrating a difference between the slave temperature signal and the first temperature signal to provide a corresponding gain; multiplying a slave current signal representing a corresponding slave switching circuit current by the gain to provide a corresponding current feedback signal; proportionally integrating a difference between the current feedback signal and a first current signal representing a master switching circuit current to provide a corresponding bias; providing a corresponding bias on duration signal based on the bias; and superimposing the bias on duration signal and a first on duration signal to generate an on duration signal corresponding to the slave power switch, respectively.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic circuits, and more particularly to multiphase switching converters with thermal equalization functions, and their integrated circuit controllers and control methods. Background Technology

[0002] Multiphase switching converters are widely used in high-performance CPU power supply solutions due to their superior performance. The operating temperature of each phase switching circuit in a multiphase switching converter must be equal. Overheating of any single phase switching circuit will cause instability in the switching converter's operation, and may even lead to the shutdown of the entire switching converter.

[0003] Generally, multiphase switching converters achieve temperature equalization by balancing the output current of each phase's switching circuit. Ideally, when the output current of each phase's switching circuit is equal, its power loss and temperature rise should also be equal. However, in today's application environments, CPU application systems and their peripherals are becoming increasingly complex, and their power delivery requirements are also becoming more complex. To meet these higher requirements, multiphase switching converters, under the control of the control circuit, can not only operate in all phases but also in phase-switching mode. For example, when the load changes, phases 1 to M (Phase M) are in power operation, while phases M+1 to N (Phase N) are in a low-power, non-power operation state, where M ≥ 1 and N ≥ M+1. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a multiphase switching converter, its controller and control method, so as to control the thermal balance under the free switching between full-phase operation and phase-cut operation.

[0005] According to an embodiment of the present invention, an integrated circuit controller for a multiphase switching converter includes a first switching circuit having a first power switch and a second switching circuit having a second power switch, providing an output voltage to a load. The integrated circuit controller includes a first pin for receiving a first temperature signal representing the temperature of the first power switch and a second temperature signal representing the temperature of the second power switch; a second pin for receiving a first current signal representing the current flowing through the first power switch; a third pin for receiving a second current signal representing the current flowing through the second power switch; and a comparator circuit for comparing a feedback signal representing the output voltage of the multiphase switching converter with a reference voltage. The circuit provides a comparison signal; a first conduction duration generation circuit provides a first conduction duration signal to control the conduction duration of the first power switch; a second conduction duration generation circuit provides a second conduction duration signal at its output terminal to control the conduction duration of the second power switch based on the first temperature signal, the second temperature signal, the first current signal, the second current signal, and the first conduction duration signal; and a switch control circuit coupled to the comparison circuit, the first conduction duration generation circuit, and the second conduction duration generation circuit, which, based on the comparison signal, the first conduction duration signal, and the second conduction duration signal, respectively generate a first control signal to control the first power switch and a second control signal to control the second power switch.

[0006] According to another embodiment of the present invention, a multiphase switching converter includes a first integrated circuit switching device having a first pin, a second pin, and a first power switch, wherein the first power switch couples the first pin to the second pin when the first integrated circuit switching device is enabled; a second integrated circuit switching device having a first pin, a second pin, and a second power switch, wherein the second power switch is used to couple the first pin of the second integrated circuit switching device to the second pin of the second integrated circuit switching device when the second integrated circuit switching device is enabled; and an integrated circuit control device as described above.

[0007] According to another embodiment of the present invention, an integrated circuit controller for a multiphase switching converter includes a main switching circuit having a first power switch and a plurality of slave switching circuits coupled in parallel, each slave switching circuit having a slave power switch. The integrated circuit controller includes: a plurality of closed-loop gain circuits, wherein each closed-loop gain circuit receives a slave temperature signal representing the temperature of a corresponding slave power switch and a first temperature signal representing the temperature of the first power switch, and performs proportional integration on the difference between the first temperature signal and the corresponding slave temperature signal to provide a corresponding gain; and a plurality of multiplication circuits, each multiplication circuit multiplying the value of the corresponding slave switch... The circuit current is multiplied by the corresponding gain to provide a corresponding current feedback signal at the output; multiple bias circuits, each bias circuit proportionally integrating the difference between the first current signal representing the main switch circuit current and the corresponding current feedback signal to provide a corresponding bias; multiple bias conduction duration generation circuits, each bias conduction duration generation circuit providing a corresponding bias conduction duration signal based on the corresponding bias; and multiple adder circuits, each adder circuit superimposing the first conduction duration signal and the corresponding bias conduction duration signal to generate a corresponding conduction duration signal to control the conduction duration of the corresponding slave power switch.

[0008] According to another embodiment of the present invention, a control method for a multiphase switching converter includes a main switching circuit having a first power switch and a plurality of parallel-coupled slave switching circuits, each slave switching circuit having a slave power switch. The control method includes: receiving a slave temperature signal representing the temperature of a corresponding slave power switch and a first temperature signal representing the temperature of the first power switch; performing proportional integration on the difference between the slave temperature signal and the first temperature signal to provide a corresponding gain; multiplying a slave current signal representing the current of a corresponding slave switching circuit with the gain to provide a corresponding current feedback signal; performing proportional integration on the difference between the current feedback signal and the first current signal to provide a corresponding bias; providing a corresponding bias conduction duration signal based on the bias; and superimposing the bias conduction duration signal and the first conduction duration signal to generate a conduction duration signal corresponding to the slave power switch.

[0009] According to an embodiment of the present invention, there are multiple conduction duration generation circuits, each providing an independent conduction duration for each switching circuit. In addition to the first conduction duration generation circuit, which serves as the reference for conduction duration, each of the other conduction duration generation circuits can provide a temperature closed loop as the outer loop of the current regulation inner loop. The temperature closed loop adjusts the current feedback signal of the current regulation inner loop by changing the gain provided by the closed loop gain circuit. This allows the temperature outer loop to selectively affect the current regulation inner loop during full-phase or phase-cut operation, thereby satisfying the different power requirements of the multiphase switching converter while accurately achieving thermal balance of the switching circuit under free switching between power operation and non-power operation. Attached Figure Description

[0010] Figure 1 This is a block diagram of a multiphase switching converter 100 according to an embodiment of the present invention;

[0011] Figure 2 This is a circuit schematic diagram of a multiphase switching converter 100A according to an embodiment of the present invention;

[0012] Figure 3 This is a circuit schematic diagram of a switch control circuit 109A according to an embodiment of the present invention;

[0013] Figure 4 This is a circuit schematic diagram of an integrated circuit controller 102B according to an embodiment of the present invention;

[0014] Figure 5 This is a circuit schematic diagram of the second closed-loop gain circuit 202B according to an embodiment of the present invention;

[0015] Figure 6 This is a circuit schematic diagram of a second bias circuit 204B according to an embodiment of the present invention;

[0016] Figure 7 This is a circuit schematic diagram of a hold signal generation circuit 218 according to an embodiment of the present invention;

[0017] Figure 8 This is a circuit schematic diagram of an integrated circuit controller 102C for controlling a multiphase switching converter according to an embodiment of the present invention;

[0018] Figure 9 According to an embodiment of the present invention Figure 8 The circuit diagram of the limiting circuit 217 shown is shown.

[0019] Figure 10 This is a flowchart of a control method 900 for a multiphase switching converter according to an embodiment of the present invention. Detailed Implementation

[0020] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0021] Throughout this specification, references to “an embodiment,” “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Figure 1 This is a block diagram of a multiphase switching converter 100 according to an embodiment of the present invention. The multiphase switching converter 100 includes a multiphase power conversion circuit 101 and an integrated circuit controller 102. The multiphase power conversion circuit 101 may include N+1 switching circuits, where N is an integer greater than or equal to 1. In one embodiment, the multiphase power conversion circuit 101 includes a master switching circuit and N slave switching circuits. The input terminals of the N+1 switching circuits receive an input voltage Vin, and their output terminals are coupled together to provide an output voltage Vout to the load. The switching circuits in the multiphase power conversion circuit 101 can employ any DC / DC or AC / DC conversion topology, such as synchronous or asynchronous boost / buck converters, forward / flyback converters, etc.

[0023] exist Figure 1 In the illustrated embodiment, the multiphase power conversion circuit 101 includes a first integrated circuit switching device 101-1 serving as a main switching circuit and a second integrated circuit switching device 101-2 and a third integrated circuit switching device 101-3 serving as slave switching circuits. Each integrated circuit switching device is a single integrated circuit chip. Figure 1 The multiphase power conversion circuit 101 includes three integrated circuit switching devices 101-1 to 101-3 to form a three-phase switching converter. It is understood that the multiphase power conversion circuit 101 may also include integrated circuit switching devices with any other number to form a multiphase switching converter with any other number of phases.

[0024] Each integrated circuit switching device (e.g., 101-1) has multiple pins, including a pin VIN for receiving an input voltage Vin, a pin VOUT for providing an output voltage Vout, a pin CS for reporting current information, a pin VTEMP for reporting junction temperature information, and a PWM pin for receiving power switch control signals. Each integrated circuit switching device includes a power switch having a first terminal coupled to the VIN pin and a second terminal coupled to the VOUT pin via an energy storage element, wherein the power switch connects the VIN pin to the VOUT pin via the energy storage element when the first integrated circuit switching device is enabled. The CS pin is used to report current information, such as the current flowing through the energy storage element in the integrated circuit switching device or the current flowing through the power switch. The VTEMP pin is used to report junction temperature information, such as the chip temperature of the integrated circuit switching device or the temperature of the power switch.

[0025] exist Figure 1 In the illustrated embodiment, the integrated circuit controller 102 has multiple pins, including a TSENS pin for receiving junction temperature information, CS1~CS3 pins for receiving current information, PWM1~PWM3 pins, and an output voltage detection pin VOSEN. The TSENS pin is coupled to the VTEMP pin of each integrated circuit switching device to receive junction temperature information from multiple integrated circuit switching devices in a time-division multiplexing manner. Based on this junction temperature information, it provides a temperature signal representing the temperature of the power device in each switching circuit, and determines whether to disable the corresponding integrated circuit switching device and whether to report fault information, etc. The CS1~CS3 pins of the integrated circuit controller 102 are respectively coupled to the CS pins of integrated circuit switching devices 101-1~101-3 to receive current signals representing the current flowing through the energy storage element in the integrated circuit switching device or the current flowing through the power switch.

[0026] Figure 2 This is a circuit schematic diagram of a multiphase switching converter 100A according to an embodiment of the present invention. Figure 2 As shown, the multiphase switching converter 100A includes a multiphase power conversion circuit 101A and an integrated circuit controller 102A. In Figure 2 In the illustrated embodiment, the multiphase power conversion circuit 101A includes a first integrated circuit switching device 101A-1 as a master switching circuit and a second integrated circuit switching device 101A-2 and a third integrated circuit switching device 101A-3 as slave switching circuits. It will be understood that in other embodiments, the slave switching circuit may include more integrated circuit switching devices to form a multiphase power conversion circuit with any number of phases.

[0027] Each of the multiple integrated circuit switching devices has the same circuit structure. In one embodiment, each integrated circuit switching device (e.g., 101A-1) has a VIN pin, a VOUT pin, a CS pin for output current information, a VTEMP pin for output junction temperature information, and a PWM pin for receiving control signals. It also includes at least one power switch (e.g., a high-side power switch HS and a low-side power switch LS), a drive circuit for driving the power switch, and a temperature detection unit for detecting the temperature of the power switch. The drive circuit controllably controls the on / off state of the power switch. In one embodiment, when the integrated circuit switching device is enabled, the high-side power switch HS is connected to the input power supply of the VIN pin, and through the inductor L, is connected to the load connected to the VOUT pin. The temperature detection unit detects the junction temperature of the integrated circuit switching device (e.g., the temperature of the power switch) and outputs the corresponding junction temperature information on the VTEMP pin. In one embodiment, this junction temperature information is a voltage signal proportional to the junction temperature of the integrated circuit switching device (e.g., 10 mV / ℃). In another embodiment, the junction temperature information is the sum of a voltage signal proportional to the junction temperature of the integrated circuit switching device and a junction temperature detection bias voltage.

[0028] exist Figure 2 In the illustrated embodiment, the integrated circuit controller 102A has at least pins CS1~CS3 for receiving current information from the integrated circuit switching device 101A, pin TSENS for receiving junction temperature information, pin VOSEN for receiving output voltage Vout information, and pins PWM1~PWM3 for output control signals. It also includes a current information unit 103, a temperature information unit 104, a comparison circuit 105, a first conduction duration generation circuit 106, a second conduction duration generation circuit 107, a third conduction duration generation circuit 108, and a switch control circuit 109.

[0029] The CS1~CS3 pins of the integrated circuit controller 102A are respectively coupled to the CS pins of the integrated circuit switching devices 101A-1~101A-3 to receive current information from the integrated circuit switching devices. Based on this current information, the current information unit 103 provides current signals i1~i3 representing the current flowing through the corresponding power switch and a load current signal ISEN representing the load current at its output terminal. In one embodiment, the current information unit 103 sums, filters, and amplifies / downscales the current signals i1~i3 to obtain the load current signal ISEN.

[0030] The TSENS pin of integrated circuit controller 102A is coupled to the VTEMP pin of each integrated circuit switch to receive junction temperature information from integrated circuit switches 101A-1 to 101A-3 in a time-division multiplexing manner. Based on the received junction temperature information, temperature information unit 104 provides temperature signals t1 to t3 representing the temperature of each power switch, and determines whether to disable the corresponding integrated circuit switch and whether to report fault information, etc., according to this junction temperature information.

[0031] exist Figure 2 In the illustrated embodiment, comparator circuit 105 is coupled to pin VOSEN to receive a feedback signal representing the output voltage Vout of multiphase switching converter 101A, and compares the feedback signal with a reference voltage Vref to generate a comparator signal SET. First on-time generation circuit 106 generates a first on-time signal ton1 to control the first on-time of the first power switch inside the first integrated circuit switching device 101A-1 during power operation. The first on-time signal ton1 can set the first on-time to a constant value or a variable value related to the input voltage Vin and / or the output voltage Vout.

[0032] The second conduction duration generation circuit 107 provides a second conduction duration signal ton2 at its output terminal based on the first temperature signal t1, the second temperature signal t2, the first current signal i1, the second current signal i2, and the first conduction duration signal ton1, to control the second conduction duration of the second power switch inside the second integrated circuit switching device 101A-2 during power operation. Similarly, the third conduction duration generation circuit 108 provides a third conduction duration signal ton3 at its output terminal based on the first temperature signal t1, the third temperature signal t3, the first current signal i1, the third current signal i3, and the first conduction duration signal ton1, to control the third conduction duration of the third power switch inside the third integrated circuit switching device 101A-3 during power operation. The switch control circuit 109 is coupled to the comparator circuit 105, the first on-time generation circuit 106, the second on-time generation circuit 107, and the third on-time generation circuit 108. Based on the comparator signal SET, the first on-time signal ton1, the second on-time signal ton2, and the third on-time signal ton3, the circuit generates the first control signal PWM1 for controlling the first power switch, the second control signal PWM2 for controlling the second power switch, and the control signal PWM3 for controlling the third power switch, respectively.

[0033] It should be noted that, although Figure 2 The embodiment shown employs a synchronous buck topology for the switching circuit, but this is not intended to limit the invention; other suitable DC-DC converter topologies are also applicable.

[0034] Figure 3 This is a circuit schematic diagram of a switch control circuit 109A according to an embodiment of the present invention. Figure 3 As shown, the switch control circuit 109A includes a frequency divider unit 191 composed of switches S1 to S3, and sub-control units (e.g., 192_1, 192_2, and 192_3). The first terminals of switches S1 to S3 are connected together to receive a comparison signal SET. Each sub-control unit (192_1 to 192_3) has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the second terminal of the corresponding switch among switches S1 to S3 to receive signals SET1 to SET3. The second input terminal is coupled to conduction time generation circuits 105 to 108 to receive conduction long signals ton1 to ton3. The output terminal is coupled to the corresponding integrated circuit switching element (e.g., 101A-1 to 101A-3) to provide control signals PWM1 to PWM3. The on and off states of switches S1 to S3 are determined by the number and timing of the switching circuits currently operating at power. When a switch is turned on, the comparison signal SET is sent to the corresponding sub-control unit to control the corresponding switching circuit. The pulses of the comparison signal SET are sequentially supplied to the integrated circuit switching devices (101A-1~101A-3) that are operating in power mode, to turn on the corresponding power switches (e.g., HS). The power switches will turn off after their on-time reaches its corresponding on-duration.

[0035] Continue as Figure 2 As shown, under the control of control signals PWM1~PWM3, each switching circuit that enters power operation will operate in a staggered phase, and its operating phase angle is 360 degrees divided by the number of switching circuits currently in power operation (i.e., 3).

[0036] Figure 2 The multiphase converter 100A includes three integrated circuit converters 101A-1 to 101A-3 to form a three-phase switching converter. It is understood that the multiphase converter 100A may also include integrated circuit switching devices of any other number to form a multiphase switching converter with any other number of phases.

[0037] In one embodiment, the multiphase converter includes N+1 switching circuits—a master switching circuit (e.g., 101A-1) and N slave switching circuits (e.g., 101A-2 to 101A-N). In one embodiment, when the multiphase switching converter 100A operates in phase-cut mode, the number of switching circuits currently operating at power is determined based on the load current signal ISEN, allowing the N slave switching circuits to operate at power only partially, with the remaining portion operating in non-power mode, depending on the magnitude of the load current. If the load current transiently increases, the multiphase switching converter will exit phase-cut mode, and the integrated circuit controller 102A will cause all N+1 switching circuits to enter full-phase power operation.

[0038] Figure 4 This is a circuit schematic diagram of an integrated circuit controller 102B according to an embodiment of the present invention. Figure 4 As shown, the second conduction duration generation circuit 107B includes a second closed-loop gain circuit 202, a second multiplication circuit 203, a second bias circuit 204, a second bias conduction duration generation circuit 205, and a second adder circuit 206.

[0039] like Figure 2 As shown, the second closed-loop gain circuit 202 performs proportional integration on the difference between the first temperature signal t1 and the second temperature signal t2 to provide a second gain i2_gain. The second multiplication circuit 203 multiplies the second current signal i2 with the second gain i2_gain to provide a second current feedback signal i2_tune. The second bias circuit 204 performs proportional integration on the difference between the first current signal i1 and the second current feedback signal i2_tune to provide a second bias Tune2. The second bias conduction duration generation circuit 205 provides a second bias conduction duration signal Δton2 based on the second bias Tune2. The second adder circuit 206 superimposes the first conduction duration signal ton1 and the second bias conduction duration signal Δton2 provided by the first conduction duration generation circuit 106 to provide a second conduction duration signal ton2.

[0040] Similarly, continuing as Figure 4 As shown, the third conduction duration generation circuit 108B includes a third closed-loop gain circuit 302, a third multiplication circuit 303, a third bias circuit 304, a third bias conduction duration generation circuit 305, and a third adder circuit 306. The third closed-loop gain circuit 302 performs proportional integration on the difference between the first temperature signal t1 and the third temperature signal t3 to provide a third gain i3_gain. The third multiplication circuit 303 multiplies the third current signal i3 with the third gain i3_gain to provide a third current feedback signal i3_tune. The third bias circuit 304 performs proportional integration on the difference between the first current signal i1 and the third current feedback signal i3_tune to provide a third bias Tune3. The third bias conduction duration generation circuit 305 provides a third bias conduction duration signal Δton3 based on the third bias Tune3. The third adder circuit 306 superimposes the first conduction duration signal ton1 provided by the first conduction duration generation circuit 106 and the third bias conduction duration signal Δton3 to provide the third conduction duration signal ton3.

[0041] In other embodiments, the integrated circuit controller 102A may further include more conduction duration generation circuits. Each conduction duration generation circuit from the switching circuit can provide a temperature closed loop as an outer loop of the current regulation inner loop. The temperature closed loop adjusts the current feedback signal of the current regulation inner loop by changing the gain provided by the closed loop gain circuit, so that the temperature outer loop can selectively act on the current regulation inner loop during full-phase or phase-cut operation, and finally realize the uniform temperature control of the power operation switching circuit under the free switching of full-phase or phase-cut operation.

[0042] Figure 5 This is a circuit schematic diagram of a second closed-loop gain circuit 202B according to an embodiment of the present invention. Figure 5 As shown, the second closed-loop gain circuit 202B includes a subtractor and a proportional-integral (PI) regulator. The first input of the subtractor receives a second temperature signal t2, and the second input receives a temperature reference signal tref, providing a temperature difference at the output. The PI regulator performs proportional-integral operation on this temperature difference under the control of a first clock signal CLK to generate a second gain data stored in the second gain storage unit. In one embodiment, the temperature reference signal tref is a first temperature signal t1. The proportional coefficient KP and integral coefficient KI to be set for the PI regulator can receive different selectable values ​​under different operating modes via multiplexers MUX1 and MUX2. In one embodiment, when the mode signal MS is high, it indicates that the second integrated circuit switching device 101A-2 is operating in the first operating mode, and Kp1 and KI1 are selected to set the PI regulator. When the mode signal MS is low, it indicates that the second integrated circuit switching device 101A-2 is operating in the second operating mode, and Kp2 and KI2 are selected to set the PI regulator.

[0043] In extreme conditions, when the load is suddenly removed, if the integrated circuit controller 102A continues to adjust the current loop according to the temperature of each switching circuit, current mismatch will occur, resulting in unnecessary power loss. Therefore, when the multiphase switching converter 100A operates in phase-cutting mode and the second integrated circuit switching device 101A-2 is phase-cut, switching from power operation to non-power operation, the reset signal RST2 becomes active (e.g., the reset signal RST2 goes high), and the second gain data stored in the second gain storage unit is reset to its initial value. In an embodiment of the invention, the initial value of the second gain i2_gain is 1.

[0044] Figure 6 This is a circuit schematic diagram of a second bias circuit 204B according to an embodiment of the present invention. Figure 6As shown, the second bias circuit 204B includes a subtractor and a proportional-integral (PI) regulator. The first input of the subtractor receives a second current signal i2, and the second input receives a current reference signal iref, providing a current difference at the output. In one embodiment, the current reference signal iref is a first current signal i1. Under the control of a second clock signal CLK1, the PI regulator performs a proportional-integral operation on this current difference to generate a second bias data stored in a second bias storage unit. In one embodiment, the frequency of the first clock signal CLK is less than the frequency of the second clock signal CLK1. The proportional coefficient KP and integral coefficient KI to be set for the PI regulator can be selected using multiplexers MUX1 and MUX2, receiving different selectable values ​​for different operating modes. In one embodiment, when the mode signal MS is high, it indicates that the second integrated circuit switching device 101A-2 is operating in the first operating mode, and Kp3 and KI3 are selected to set the PI regulator. When the mode signal MS is low, it indicates that the second integrated circuit switching device 101A-2 is operating in the second operating mode, and Kp4 and KI4 are selected to set the PI regulator. Furthermore, when the multiphase switch converter 100A operates in phase-cutting mode and the second integrated circuit switching device 101A-2 is phase-cut, switching from power operation to non-power operation, the reset signal RST2 becomes active (e.g., the reset signal RST2 goes high), and the second bias data stored in the second bias memory cell is reset to its initial value. In an embodiment of the present invention, the initial value of the second bias Tune2 is 0.

[0045] Furthermore, the second bias circuit 204B also receives a hold signal HOLD. When a valid hold signal HOLD is received, the second bias memory cell retains the second bias data from the previous clock cycle unchanged.

[0046] In one embodiment, when Figure 2 When the integrated circuit controller 102A detected a sudden change in load current, a dynamic change in voltage identification code, or a change in the number of switching circuits operating at power, it kept the HOLD signal valid, and the second bias memory cell retained the second bias data from the previous clock cycle. In one embodiment, Figure 2 The integrated circuit controller 102A shown further includes a hold signal generation circuit 218. Figure 7 This is a circuit schematic diagram of a hold signal generation circuit 218 according to an embodiment of the present invention. Figure 7 In the embodiment shown, the hold signal generation circuit 218 includes a load current comparison circuit 110, a phase number change judgment circuit 111, a DVID detection circuit 112, a load transient detection circuit 113, an OR gate circuit OR1, and a single trigger circuit 114.

[0047] The load current comparison circuit 110 is coupled to the current information unit 103, receives the load current signal ISEN, and compares it with multiple threshold voltages (e.g., threshold voltages Vth_1ph, Vth_2ph, Vth_3ph) to generate current comparison signals (LIS1, LIS2, and LIS3). Figure 7 In the illustrated embodiment, the load current comparison circuit 110 includes hysteresis comparators CMP1 to CMP3, whose connections are shown in the figure. The hysteresis comparators CMP1 to CMP3 compare the load current signal ISEN with the threshold voltages Vth_1ph, Vth_2ph, and Vth_3ph, respectively, to determine the number of switching circuits in which the three-phase converter 100A operates in power mode. The specific operating conditions are as follows: when Vth_3ph + VHYS < ISEN, all integrated circuit switching devices 101A-1 to 101A-3 operate in continuous current mode; when Vth_2ph + VHYS < ISEN ≤ Vth_3ph, two phases of integrated circuit switching devices 101A~1 to 101A-2 operate in continuous current mode; when Vth_1ph + VHYS < ISEN ≤ Vth_2ph, one phase of integrated circuit switching devices 101A~1 to 101A-2 operates in continuous current mode; when ISEN ≤ Vth_1ph, one phase of integrated circuit switching devices 101A~1 to 101A-2 operates in discontinuous current mode. Here, VHYS is the hysteresis voltage.

[0048] The phase number change judgment circuit 111 determines the number of switching circuits currently operating at power based on the current comparison signals LIS1~LIS3, and determines whether the number has changed, and outputs the phase number adjustment signal Ph_Num at the output terminal.

[0049] In an embodiment of the present invention, the multiphase converter 100A can adjust its provided reference voltage Vref according to the voltage identification code (VID) sent by the CPU or GPU. When the DVID detection circuit 112 detects a change in the voltage identification code, it generates a high-level dynamic voltage identification code signal DVID.

[0050] The load transient detection circuit 113 is coupled to the output of the comparator circuit 105 to receive the comparison signal SET. The period length of each cycle of the comparison signal SET is compared with a preset time threshold. If the period of the comparison signal SET is less than the lower time threshold or the period of the comparison signal SET is greater than the upper time threshold for multiple consecutive cycles, the transient indication signal LTD goes high, indicating that a load transient situation has occurred.

[0051] OR gate circuit OR1 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is coupled to the output terminal of phase number change judgment circuit 111 to receive the phase number adjustment signal Ph_Num. The second input terminal is coupled to the output terminal of DVID detection circuit 112 to receive the dynamic voltage identification code signal DVID. The third input terminal is coupled to load transient detection circuit 113 to receive the transient indication signal LTD. In an embodiment of the present invention, when the number of power-operated switching circuits changes, the voltage identification code changes, or a load transient occurs, the single-trigger circuit 114 is triggered, outputting a single-pulse HOLD signal, so that... Figure 6 The second bias memory cell shown retains the second bias data from the previous clock cycle.

[0052] Although the aforementioned multiphase converters are described using 3-phase switching converters as examples, those skilled in the art should understand that the present invention can be applied to switching converters with any number of phases and their integrated circuit controllers.

[0053] Figure 8 This is a circuit schematic diagram of an integrated circuit controller 102C for controlling a multiphase switching converter according to an embodiment of the present invention. In addition to the aforementioned current information unit 103, temperature information unit 104, comparator circuit 105, and first conduction duration generation circuit 106, the integrated circuit controller 102C also includes N closed-loop gain circuits 212, N multiplication circuits 213, N bias circuits 214, N bias conduction duration generation circuits 215, N adder circuits 216, and a switch control circuit. In the following description, i is an integer less than or equal to N and greater than or equal to 2.

[0054] exist Figure 8 In the illustrated embodiment, each of the N closed-loop gain circuits 212 has a first input terminal and a second input terminal, wherein the first input terminal receives a received temperature reference signal t_ref, and the second input terminal receives a temperature signal ti from the corresponding switching circuit. Each closed-loop gain circuit performs proportional integration on the difference between the temperature signal ti and the temperature reference signal tref, providing a gain ii_gain at the output terminal. In one embodiment, the temperature reference signal tref is a first temperature signal t1. In one embodiment, at least one of the plurality of closed-loop gain circuits 212 performs proportional integration under the control of a first clock signal CLK to generate corresponding gain data stored in a gain storage unit. In another embodiment, when the i-th switching circuit switches from power operation to non-power operation, the reset signal RSTi corresponding to the i-th switching circuit is active high, and the gain storage unit of the i-th closed-loop gain circuit performs a reset, resetting its gain data to a first value, such as 1.

[0055] Each of the plurality of multiplication circuits 213 multiplies the corresponding current signal ii with the corresponding gain ii_gain, providing a corresponding current feedback signal ii_tune at the output. Each of the plurality of bias circuits 214 receives the current feedback signal ii_tune and the current reference signal iref, and performs proportional integration on the difference between the current feedback signal and the current reference signal to provide a corresponding bias Tunei. In one embodiment, at least one of the plurality of bias circuits 214 performs proportional integration under the control of a second clock signal CLK2 to generate corresponding bias data stored in a bias memory cell. In one embodiment, the frequency of the first clock signal CLK is less than the frequency of the second clock signal CLK1. In another embodiment, when the i-th switching circuit switches from power operation to non-power operation, the reset signal RSTi corresponding to the i-th switching circuit is active high, and the bias memory cell of the i-th bias circuit is reset, resetting its bias data to a second value, such as 0. In one embodiment, when a sudden change in load current, a dynamic change in voltage identification code, or a change in the number of power-operated switching circuits is detected, the hold signal HOLD is valid, and the bias memory cell performs the bias data hold function to keep the bias data of the previous clock cycle unchanged.

[0056] Each of the multiple bias on-time generation circuits 215 provides a corresponding bias on-time signal Δtoni based on a corresponding bias Tunei. Each of the multiple adder circuits 216 superimposes the first on-time signal ton1 onto the bias on-time signal Δtoni to generate multiple on-time signals toni to control the on-time of multiple slave power switches respectively.

[0057] Furthermore, the switch control circuit is coupled to the comparator circuit, the first conduction duration generation circuit, and multiple adder circuits. Based on the comparator signal SET, the first conduction duration signal ton1, and multiple conduction duration signals ton2~tonN, it generates the first control signal PWM1 and multiple control signals PWM2~PWMN for the slave power switches, so as to control the main switch circuit and multiple slave switch circuits to conduct sequentially.

[0058] If the load current of the 100A multiphase converter changes frequently, and the conduction time of the power switches in different switching circuits becomes unpredictably too short or too long, it can cause overheating in a certain switching circuit, leading to thermal imbalance of the multiphase converter. Therefore, in Figure 8 In the illustrated embodiment, the integrated circuit controller 102C further includes a limiting circuit 217.

[0059] Limiting circuit 217 is coupled to current information unit 103 to receive current information related to load current ISEN. Specifically, limiting circuit 217 receives the per-unit value of load current Istd, the maximum value of load current Imax, gain coefficient A0, and bias coefficient B0, and outputs the range LIMT generated by limiting circuit 217 to bias conduction duration generation circuit 215, so that the absolute value of the bias conduction duration signal generated by bias conduction duration generation circuit 215 is not greater than the range LIMT generated by limiting circuit, thereby realizing the limitation and regulation of the conduction duration of the switching circuit by load current, and ultimately optimizing the thermal balance control of each switching circuit.

[0060] Figure 9 According to an embodiment of the present invention Figure 8 The circuit diagram of the limiting circuit 217 is shown. The range LIMT generated by the limiting circuit 217 can be expressed as: LIMT = Istd / Imax * A0 + B0. Figure 9 In the illustrated embodiment, the limiting circuit 217 is implemented by a multiplier 271 and an adder 272. The multiplier 271 receives the per-unit value of the load current Istd, the reciprocal of the maximum load current Imax, and the gain coefficient A0, and provides the product of these three at its output. The adder 272 superimposes the product of the multiplier 271's output with the bias coefficient B0, providing a range LIMT at its output and supplying it to the bias conduction duration generation circuit 215 to limit the absolute value of the bias conduction duration provided by the bias conduction duration generation circuit 215 to no greater than the range LIMT generated by the limiting circuit 217. In one embodiment, the range LIMT is at least not less than the bias coefficient B0 and at most not greater than the sum of the gain coefficient A0 and the bias coefficient B0.

[0061] Figure 10 The flowchart below shows a control method 900 for a multiphase switch converter according to an embodiment of the present invention. The multiphase switch converter includes a main switch circuit having a first power switch and a plurality of parallel-coupled slave switch circuits, each slave switch circuit having a slave power switch. The control method includes steps 901 to 905.

[0062] In step 901, a slave temperature signal representing the corresponding slave power switch temperature and a first temperature signal representing the first power switch temperature are received. The difference between the slave temperature signal and the first temperature signal is calculated using a proportional-integral method to provide a corresponding gain. In one embodiment, the difference between the slave temperature signal and the first temperature signal is calculated using a proportional-integral method under the control of a first clock signal to generate a corresponding gain data which is stored in a gain storage unit.

[0063] In step 902, the slave current signal, representing the corresponding slave switch circuit current, is multiplied by the gain to provide a corresponding current feedback signal. In one embodiment, the difference between the current feedback signal and the first current signal is proportional to integral under the control of a second clock signal to generate a corresponding bias data stored in a bias memory cell, wherein the frequency of the first clock signal is less than the frequency of the second clock signal.

[0064] In step 903, the difference between the current feedback signal and the first current signal is proportionally integrated to provide a corresponding bias.

[0065] In step 904, a corresponding bias conduction duration signal is provided based on the bias.

[0066] In step 905, the bias conduction duration signal is superimposed on the first conduction duration signal to generate a conduction duration signal corresponding to the power switch. In one embodiment, the control method further includes: resetting the gain data corresponding to the slave switch circuit in non-power operation to a first value; and resetting the bias data corresponding to the slave switch circuit in non-power operation to a second value. In one embodiment, the first value is 1 and the second value is 0.

[0067] In another embodiment, the control method further includes maintaining the bias data of the previous clock cycle unchanged when a sudden change in load current, a dynamic change in voltage identification code, or a change in the number of power-operated switching circuits is detected.

[0068] In another embodiment, a first range is provided based on the per-unit value of the load current, the maximum value of the load current, the gain coefficient, and the bias coefficient, such that the absolute value of the bias conduction time is not greater than the first range.

[0069] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. An integrated circuit controller for a multiphase switching converter, the multiphase switching converter including a first switching circuit having a first power switch and a second switching circuit having a second power switch, providing an output voltage to a load, the integrated circuit controller comprising: The first pin receives a first temperature signal representing the temperature of the first power switch and a second temperature signal representing the temperature of the second power switch. The second pin receives a first current signal representing the current flowing through the first power switch. The third pin receives a second current signal representing the current flowing through the second power switch. The comparator circuit compares the feedback signal, representing the output voltage of the multiphase switching converter, with the reference voltage to provide a comparison signal; The first conduction duration generation circuit provides a first conduction duration signal to control the conduction duration of the first power switch; The second conduction duration generation circuit provides a second conduction duration signal at the output terminal to control the conduction duration of the second power switch, based on the first temperature signal, the second temperature signal, the first current signal, the second current signal, and the first conduction duration signal. as well as The second conduction duration generation circuit includes: The second closed-loop gain circuit performs proportional integration on the difference between the first temperature signal and the second temperature signal to provide a second gain. The second multiplication circuit multiplies the second current signal with the second gain to provide a second current feedback signal; The second bias circuit performs proportional integration on the difference between the first current signal and the second current feedback signal to provide a second bias. The second bias conduction duration generation circuit provides a second bias conduction duration signal based on the second bias; and The second adder circuit superimposes the first conduction duration signal and the second bias conduction duration signal to provide the second conduction duration signal.

2. The control device as claimed in claim 1, wherein the second closed-loop gain circuit performs proportional-integral operation under the control of the first clock signal to generate second gain data stored in the second gain storage unit, and the second bias circuit performs proportional-integral operation under the control of the second clock signal to generate second bias data stored in the second bias storage unit, wherein the frequency of the first clock signal is less than the frequency of the second clock signal.

3. The control device as claimed in claim 2, wherein when the second switching circuit switches from power operation to non-power operation, the second gain storage unit resets the second gain data to the first value, and the second bias storage unit resets the second bias data to the second value.

4. The control device of claim 3, wherein when a sudden change in load current, a dynamic change in voltage identification code, or a change in the number of power-operated switching circuits is detected, the second bias storage unit retains the second bias data of the previous clock cycle unchanged.

5. The control device as claimed in claim 1, further comprising a limiting circuit, the limiting circuit outputting the generated range to a second bias conduction duration generating circuit, such that the absolute value of the second bias conduction duration signal generated by the second bias conduction duration generating circuit is not greater than the range generated by the limiting circuit.

6. The control device as claimed in claim 5, wherein the maximum value of the range generated by the limiting circuit does not exceed the sum of the gain coefficient and the bias coefficient, and the minimum value does not exceed the bias coefficient.

7. A multiphase switching converter, comprising: A first integrated circuit switching device has a first pin, a second pin, and a first power switch, wherein the first power switch couples the first pin to the second pin when the first integrated circuit switching device is enabled. A second integrated circuit switching device has a first pin, a second pin, and a second power switch, wherein the second power switch is used to couple the first pin of the second integrated circuit switching device to the second pin of the second integrated circuit switching device when the second integrated circuit switching device is enabled; and The integrated circuit controller as described in any one of claims 1 to 6.

8. The multiphase switching converter of claim 7, further comprising: A third integrated circuit switching device has a first pin, a second pin, and a third power switch, wherein the third power switch is used to couple the first pin of the third integrated circuit switching device to the second pin of the third integrated circuit switching device when the third integrated circuit switching device is enabled; and The first pin of the integrated circuit controller further receives a third temperature signal representing the temperature of the third power switch, and the integrated circuit controller also includes: The fourth pin receives a third current signal representing the current flowing through the third power switch; and The third conduction duration generation circuit provides a third conduction duration signal at the output terminal to control the conduction duration of the third power switch, based on the first temperature signal, the third temperature signal, the first current signal, the third current signal, and the first conduction duration signal.

9. An integrated circuit controller for a multiphase switching converter, the multiphase switching converter comprising a main switching circuit having a first power switch and a plurality of slave switching circuits coupled in parallel, each slave switching circuit having a slave power switch, the integrated circuit controller comprising: Multiple closed-loop gain circuits, wherein each closed-loop gain circuit receives a slave temperature signal representing the corresponding slave power switch temperature and a first temperature signal representing the first power switch temperature, and performs proportional integration on the difference between the first temperature signal and the corresponding slave temperature signal to provide corresponding gain respectively. Multiple multiplication circuits, each multiplying the slave current signal representing the corresponding slave switch circuit current with the corresponding gain, provide the corresponding current feedback signal at the output. Multiple bias circuits, each bias circuit proportionally integrates the difference between the first current signal representing the main switching circuit current and the corresponding current feedback signal to provide a corresponding bias. Multiple bias conduction duration generation circuits, each bias conduction duration generation circuit provides a corresponding bias conduction duration signal based on a corresponding bias; as well as Multiple adder circuits, each adding the first conduction duration signal and the corresponding bias conduction duration signal to generate a corresponding conduction duration signal to control the conduction duration of the corresponding slave power switch.

10. The control device of claim 9, further comprising: The comparator circuit compares the feedback signal, representing the output voltage of the multiphase switching converter, with the reference voltage to provide a comparison signal; A first conduction duration generation circuit provides the first conduction duration signal; as well as The switch control circuit is coupled to a comparator circuit, a first conduction duration generation circuit, and multiple adder circuits. Based on the comparison signal, the first conduction duration signal, and multiple conduction duration signals, it generates a first control signal and multiple slave control signals for the power switches to control the main switch circuit and multiple slave switch circuits to conduct sequentially.

11. The control device as claimed in claim 9, wherein Each closed-loop gain circuit performs a proportional-integral operation under the control of a first clock signal to generate corresponding gain data stored in a gain storage unit. Each bias circuit performs a proportional-integral operation under the control of a second clock signal to generate corresponding bias data stored in a bias storage unit. The frequency of the first clock signal is less than the frequency of the second clock signal.

12. The controller of claim 11, wherein when a sudden change in load current, a dynamic change in voltage identification code, or a change in the number of switching circuits operating at power is detected, the bias memory cell retains the bias data from the previous clock cycle.

13. The control device as described in claim 11, wherein the gain storage unit that receives the effective phase shielding signal resets the corresponding gain data to a first value, and the bias storage unit that receives the effective phase shielding signal resets the corresponding bias data to a second value.

14. The control device of claim 9, further comprising a limiting circuit that outputs the generated range to a bias conduction duration generation circuit, such that the absolute value of the bias conduction duration signal is not greater than the range generated by the limiting circuit.

15. A control method for a multiphase switching converter, the multiphase switching converter comprising a main switching circuit having a first power switch and a plurality of parallel-coupled slave switching circuits, each slave switching circuit having a slave power switch, the control method comprising: Receive a slave temperature signal representing the temperature of the corresponding slave power switch and a first temperature signal representing the temperature of the first power switch, and perform proportional integration on the difference between the slave temperature signal and the first temperature signal to provide a corresponding gain; The slave current signal, representing the corresponding slave switch circuit current, is multiplied by the gain to provide the corresponding current feedback signal; The difference between the current feedback signal and the first current signal is proportionally integrated to provide a corresponding bias. Based on the bias, a corresponding bias conduction duration signal is provided; as well as The bias conduction duration signal is superimposed with the first conduction duration signal to generate the corresponding conduction duration signal of the power switch.

16. The control method as described in claim 15, wherein: Under the control of the first clock signal, the difference between the temperature signal and the first temperature signal is calculated by proportional integration to generate the corresponding gain data, which is then stored in the gain storage unit. as well as Under the control of the second clock signal, the difference between the current feedback signal and the first current signal is subjected to proportional-integral operation to generate corresponding bias data which is stored in the bias storage unit, wherein the frequency of the first clock signal is less than the frequency of the second clock signal.

17. The control method of claim 16, further comprising: Reset the gain data from the switching circuit corresponding to non-power operation to the first value; as well as The bias data corresponding to non-power operation from the switching circuit is reset to the second value.

18. The control method of claim 16, wherein when a sudden change in load current, a dynamic change in voltage identification code, or a change in the number of switching circuits operating at power is detected, the bias data of the previous clock cycle is kept unchanged.

19. The control method of claim 15, further comprising: The first range is provided based on the per-unit value of the load current, the maximum value of the load current, the gain coefficient, and the bias coefficient, so that the absolute value of the bias conduction time signal is not greater than the first range.

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