Storage device and method of operating a storage device

Abstract

A method of operating a storage device including a non-volatile memory and a multi-core processor having at least two cores and a storage device are disclosed. The method includes the steps of receiving, by a host interface of the storage device, a first memory command from a host for requesting the non-volatile memory to perform a predetermined memory operation; generating, by a task scheduler of the storage device, a first task and a second task from the first memory command; selecting, by the task scheduler, a first core from among the at least two cores based on execution time of the at least two cores; assigning, by the task scheduler, the first task and the second task to the first core; and after the first core processes the assigned first task, loading, by the first core, code for processing the second task while the first core requests a subsequent task from the task scheduler.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0185982, filed with the Korean Intellectual Property Office on December 29, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a storage device and a method of operating the storage device. More specifically, this disclosure relates to a storage device with increased operating speed and a method of operating the storage device. Background Technology

[0004] Storage devices are used in electronic devices to store data. They can include volatile and / or non-volatile memory technologies. Volatile memory loses the information it contains once the system loses power, while non-volatile memory retains information even after power is lost. A common example of non-volatile memory is flash memory. Flash memory is typically implemented using floating-gate transistors, which are capable of storing data that can be read quickly.

[0005] The operating environment for storage devices, including non-volatile memory, has changed rapidly. For example, many storage devices are components in larger electronic systems such as personal computers, where they interact with other components, such as multi-core processors. For these multi-core processor storage devices, increasing the utilization of each of the multiple cores helps to achieve increased operating speeds within the storage device. Therefore, new research has been conducted on storage devices capable of utilizing multi-core processors. Summary of the Invention

[0006] Embodiments of this disclosure include a method of operating a storage device that can increase operating speed.

[0007] Embodiments of this disclosure also include a storage device with increased operating speed.

[0008] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description given below.

[0009] Some embodiments of this disclosure provide a method for operating a storage device including non-volatile memory and a multi-core processor having at least two cores, wherein the method includes: receiving from a host via a host interface of the storage device a first memory command for requesting the non-volatile memory to perform a predetermined memory operation; generating a first task and a second task by a task scheduler of the storage device based on the first memory command; selecting a first core from at least two cores by the task scheduler based on the execution time of the at least two cores; assigning the first task and the second task to the first core by the task scheduler; and loading code for processing the second task by the first core while the first core requests a subsequent task from the task scheduler after the first core processes the assigned first task.

[0010] Some embodiments of this disclosure provide a method for operating a storage device including non-volatile memory and a multi-core processor having at least two cores, wherein the method includes: receiving from a host via a host interface of the storage device a first memory command for requesting the non-volatile memory to perform a predetermined memory operation; generating a first task by a task scheduler of the storage device based on the first memory command; checking the execution time of the first task by the task scheduler; selecting a first core from at least two cores as the core to be assigned the first task by the task scheduler based on the execution time of the at least two cores, wherein the execution time of the at least two cores is based on the execution time of the first task; updating the execution time of the first core by the task scheduler considering the execution time of the first task; issuing the first task to the first core by the task scheduler; and providing a second memory command, generated by a storage controller after processing the first task and at least partially based on the first memory command, to the non-volatile memory via the memory interface.

[0011] Some embodiments of this disclosure provide a storage device comprising: a non-volatile memory including a plurality of non-volatile memory cells; a host interface receiving from a host a first memory command for requesting the non-volatile memory to perform a predetermined memory operation; a multi-core processor including a plurality of cores; a task scheduler generating a plurality of tasks according to the first memory command and selecting a core to process the plurality of tasks using a task execution schedule storing the processing time of each of the plurality of tasks and an execution timestamp table storing the execution time of each of the plurality of cores; and a memory interface outputting a second memory command corresponding to the first memory command generated based on the plurality of tasks processed by the plurality of cores to the non-volatile memory.

[0012] Other features and embodiments will become apparent from the following detailed description, accompanying drawings, and claims. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram illustrating a host storage system according to some embodiments;

[0015] Figure 2 yes Figure 1 A diagram showing the reconfiguration of the storage controller, memory interface, and non-volatile memory;

[0016] Figure 3 It is shown Figure 1 A diagram illustrating a multi-core processor;

[0017] Figure 4 It is shown Figure 1 A screenshot of the task list;

[0018] Figure 5 It is shown Figure 1 A diagram of the ETS (Execution Timestamp) table;

[0019] Figure 6 It is shown Figure 1 A diagram of the TDT (Task Duration) table;

[0020] Figure 7 This is a flowchart illustrating the operation of a storage device according to some embodiments;

[0021] Figures 8 to 15 It is a diagram illustrating the operation of a storage device according to some embodiments;

[0022] Figure 16 This is a diagram illustrating a TDT (Task Duration) table according to some embodiments. Detailed Implementation

[0023] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Similar reference numerals in the drawings may denote similar elements, and to the extent that descriptions of elements have been omitted, it can be understood that the element is at least similar to a corresponding element described elsewhere in the specification.

[0024] Figure 1 This is a block diagram illustrating a host storage system according to some embodiments.

[0025] The host storage system 10 may include a host 100 and a storage device 200. The storage device 200 may also include a storage controller 210 and a non-volatile memory (NVM) 220. The host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer for temporarily storing data to be sent to or from the storage device 200.

[0026] Storage device 200 may include a storage medium for storing data in response to a request from host 100. For example, storage device 200 may include at least one of SSD (Solid State Drive), embedded memory, and removable external memory. If storage device 200 is an SSD, then storage device 200 may be a device compliant with the NVMe (Non-Volatile Memory High Speed) standard.

[0027] If storage device 200 is embedded memory or external memory, it can be a device conforming to UFS (Universal Flash Memory) or eMMC (Embedded Multimedia Card) standards. Host 100 and storage device 200 can each generate and send packets according to their respective standard protocols.

[0028] When the non-volatile memory 220 of storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may also include various other types of non-volatile memory. For example, storage device 200 may include MRAM (magnetic RAM), STT-MRAM (spin-transfer torque MRAM), conductive bridged RAM (CBRAM), FeRAM (ferroelectric RAM), PRAM (phase RAM), resistive memory (resistive RAM), and / or other various types of memory.

[0029] In some embodiments, the host controller 110 and the host memory 120 may be implemented as different semiconductor chips. In some embodiments, the host controller 110 and the host memory 120 may be integrated on the same semiconductor chip. As an example, the host controller 110 may be one of multiple modules disposed in an application processor, and such application processor may be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 120 may be embedded memory disposed in the application processor, or non-volatile memory, or a memory module located outside the application processor.

[0030] The host controller 110 can manage operations including storing data from the buffer area (e.g., writing data) in the non-volatile memory 220 and / or storing data from the non-volatile memory 220 (e.g., reading data) in the buffer area.

[0031] The storage controller 210 may include a host interface (I / F) 211, a memory interface (I / F) 212, and a multi-core processor 213. The storage controller 210 may also include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an ECC (Error Correction Code) engine 217, an AES (Advanced Encryption Standard) engine 218, and a task scheduler 219.

[0032] The storage controller 210 may also include working memory loaded with a flash translation layer (FTL) 214, and when the multi-core processor 213 executes the flash translation layer 214, it can control data write and read operations to the non-volatile memory.

[0033] Host interface 211 can send packets to host 100 and receive packets from host 100. Packets sent from host 100 to host interface 211 may include commands and / or data to be written to non-volatile memory 220, and packets sent from host interface 211 to host 100 may include responses to commands and / or data read from non-volatile memory 220, etc.

[0034] The memory interface 212 can send data to be written to the non-volatile memory 220, and / or receive data from the non-volatile memory 220. This memory interface 212 can be implemented in accordance with standard conventions such as Toggle or ONFI.

[0035] The flash translation layer 214 can perform various functions such as address mapping, wear leveling, and garbage collection. Address mapping operations may include changing a logical address received from the host to a physical address used to actually store data in the non-volatile memory 220. Wear leveling may include ensuring that blocks in the non-volatile memory 220 are used evenly to prevent excessive degradation of specific blocks, and may be implemented, for example, by firmware capable of balancing the erase counts of physical blocks. Garbage collection may include ensuring available capacity in the non-volatile memory 220 by copying valid data from a block to a new block and then erasing the existing block.

[0036] The packet manager 215 can generate packets according to the protocol of the interface negotiated with the host 100, and / or can parse various types of information based on packets received from the host 100. Furthermore, in some embodiments, the packet manager 215 can manage packets provided from the task scheduler 219 to the multi-core processor 213 or packets provided from the multi-core processor 213 to the task scheduler 219. However, embodiments are not necessarily limited to this.

[0037] The buffer memory 216 can temporarily store data to be recorded on or read from the non-volatile memory 220. The buffer memory 216 can be located inside the storage controller 210 or outside the storage controller 210.

[0038] ECC engine 217 performs error detection and correction functions on data read from non-volatile memory 220. More specifically, ECC engine 217 generates parity bits for the data to be written to non-volatile memory 220, and the parity bits generated in this way are stored in non-volatile memory 220 along with the data to be written. When reading data from non-volatile memory 220, ECC engine 217 uses the parity bits read from non-volatile memory 220 along with the read data to correct errors in the read data and outputs the corrected read data.

[0039] The AES engine 218 can, for example, use a symmetric key algorithm to perform encryption and / or decryption operations on data input to the storage controller 210.

[0040] Figure 2 yes Figure 1 A diagram showing the reconfiguration of the storage controller, memory interface, and non-volatile memory. Figure 1 The memory interface 212 may include Figure 2 The controller interface circuit 212a and the memory interface circuit 212b.

[0041] The non-volatile memory 220 may include first pins P11 to eighth pins P18, memory interface circuitry 212b, control logic circuitry 510, and memory cell array 520.

[0042] The memory interface circuit 212b can receive a chip enable signal nCE from the memory controller 210 via a first pin P11. The memory interface circuit 212b can send signals to and receive signals from the memory controller 210 via second pins P12 to eighth pins P18, at least in part, based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 212b can send signals to and receive signals from the memory controller 210 via second pins P12 to eighth pins P18.

[0043] The memory interface circuit 212b can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 210 via pins P12 to P14, respectively. The memory interface circuit 212b can receive or send the data signal DQ to the memory controller 210 via pin P17. Command CMD, address ADDR, and data DATA can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to multiple data signals.

[0044] The memory interface circuit 212b can acquire the command CMD from the data signal DQ received in the enable segment (e.g., high state) of the command latch enable signal CLE based on the switching timing of the write enable signal nWE. The memory interface circuit 212b can also acquire the address ADDR from the data signal DQ received in the enable segment (e.g., high state) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0045] In some embodiments, the write enable signal nWE may remain static (e.g., high or low) and then toggle between high and low. For example, the write enable signal nWE may toggle during the transmission of command CMD or address ADDR. Therefore, the memory interface circuit 212b may acquire command CMD or address ADDR based on the toggle timing of the write enable signal nWE.

[0046] The memory interface circuit 212b can receive the read enable signal nRE from the memory controller 210 via its fifth pin P15. The memory interface circuit 212b can receive the data strobe signal DQS from the memory controller 210 via its sixth pin P16, or it can send the data strobe signal DQS to the memory controller 210.

[0047] In the data DATA output operation of the non-volatile memory 220, the memory interface circuit 212b can receive a switched read enable signal nRE via pin 5 P15 before outputting the data DATA. The memory interface circuit 212b can generate a switched data strobe signal DQS based on the switching of the read enable signal nRE. For example, the memory interface circuit 212b can generate a data strobe signal DQS that starts switching after a predetermined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The memory interface circuit 212b can transmit a data signal DQ including the data DATA based on the switching timing of the data strobe signal DQS. As a result, the data DATA can be aligned with the switching timing of the data strobe signal DQS and sent to the memory controller 210.

[0048] In the data input operation of the non-volatile memory 220, if a data signal DQ including data DATA is received from the memory controller 210, the memory interface circuit 212b can receive a switched data strobe signal DQS from the memory controller 210 along with the data DATA. The memory interface circuit 212b can acquire the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 212b can acquire the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0049] The memory interface circuit 212b can send a ready / busy output signal nR / B to the memory controller 210 via pin 8 P18. The memory interface circuit 212b can also send status information of the non-volatile memory 220 to the memory controller 210 via the ready / busy output signal nR / B. If the non-volatile memory 220 is in a busy state (e.g., when internal operations of the non-volatile memory 220 are being performed), the memory interface circuit 212b can send a ready / busy output signal nR / B indicating the busy state to the memory controller 210. If the non-volatile memory 220 is in a ready state (e.g., internal operations of the non-volatile memory 220 have not been performed or have completed), the memory interface circuit 212b can send a ready / busy output signal nR / B indicating the ready state to the memory controller 210.

[0050] For example, while the non-volatile memory 220 reads data DATA from the memory cell array 520 in response to a page read command, the memory interface circuit 212b may send a ready / busy output signal nR / B (e.g., low level) indicating a busy state to the memory controller 210. For example, while the non-volatile memory 220 programs data DATA into the memory cell array 520 in response to a programming instruction, the memory interface circuit 212b may send a ready / busy output signal nR / B indicating a busy state to the memory controller 210.

[0051] Control logic circuit 510 can control various operations of non-volatile memory 220. Control logic circuit 510 can receive commands CMD / address / ADDR obtained from memory interface circuit 212b. Control logic circuit 510 can generate control signals for controlling other components of non-volatile memory 220, at least in part, based on the received commands CMD / address / ADDR. For example, control logic circuit 510 can generate various control signals for programming data DATA into or reading data DATA from memory cell array 520.

[0052] The memory cell array 520 can store data DATA acquired from the memory interface circuit 212b, at least in part, under the control of the control logic circuit 510. The memory cell array 520 can also output the stored data DATA to the memory interface circuit 212b, at least in part, under the control of the control logic circuit 510.

[0053] The memory cell array 520 may include a plurality of memory cells. In one embodiment, the plurality of memory cells may be flash memory cells. However, this disclosure is not limited thereto, and the memory cells may be RRAM (resistive random access memory) cells, FRAM (ferroelectric random access memory) cells, PRAM (phase change random access memory) cells, TRAM (thyristor random access memory) cells, and / or MRAM (magnetic random access memory) cells. Hereinafter, embodiments of the present disclosure will be described with reference to an example where the memory cells are NAND flash memory cells.

[0054] The memory controller 210 may include first pins P21 to eighth pins P28 and controller interface circuitry 212a. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the non-volatile memory 220. For example, first pins P21 to eighth pins P28 of the memory controller 210 may be connected to first pins P11 to eighth pins P18 of the non-volatile memory 220, respectively.

[0055] The controller interface circuit 212a can send a chip enable signal nCE to the non-volatile memory 220 via the first pin P21. The controller interface circuit 212a can send signals to and receive signals from the non-volatile memory 220 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0056] The controller interface circuit 212a can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory 220 through pins P22 to P24, respectively. The controller interface circuit 212a can send the data signal DQ to or receive the data signal DQ from the non-volatile memory 220 through pin P27.

[0057] The controller interface circuit 212a can send the data signal DQ, including the command CMD or address ADDR, along with the switching enable signal nWE to the non-volatile memory 220. The controller interface circuit 212a can send the data signal DQ, including the command CMD, to the non-volatile memory 220 by sending the command latch enable signal CLE in the enabled state, and can also send the data signal DQ, including the address ADDR, to the non-volatile memory 220 by sending the address latch enable signal ALE in the enabled state.

[0058] The controller interface circuit 212a can send a read enable signal nRE to the non-volatile memory 220 via its fifth pin P25. The controller interface circuit 212a can receive a data strobe signal DQS from the non-volatile memory 220 via its sixth pin P26, and / or can send a data strobe signal DQS to the non-volatile memory 220.

[0059] In the data DATA output operation of the non-volatile memory 220, the controller interface circuit 212a can generate a switching read enable signal nRE and send the read enable signal nRE to the non-volatile memory 220. For example, the controller interface circuit 212a can generate a read enable signal nRE that changes from a static state (e.g., high or low level) to a switching state before outputting the data DATA. As a result, a switching data strobe signal DQS can be generated in the non-volatile memory 220 based on the read enable signal nRE. The controller interface circuit 212a can receive a data signal DA including the data DATA along with the switching data strobe signal DQS from the non-volatile memory 220. The controller interface circuit 212a can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0060] During the data input operation of the non-volatile memory 220, the controller interface circuit 212a can generate a switching data strobe signal DQS. For example, the controller interface circuit 212a can generate the data strobe signal DQS, which changes from a static state (e.g., high or low level), to a switching state before transmitting the data DATA. The controller interface circuit 212a can then transmit a data signal DQ including the data DATA to the non-volatile memory 220 based on the switching timing of the data strobe signal DQS.

[0061] The controller interface circuit 212a can receive the ready / busy output signal nR / B from the non-volatile memory 220 via pin 8 P28. The controller interface circuit 212a can determine the status information of the non-volatile memory 220 based on the ready / busy output signal nR / B.

[0062] Figure 3 It is shown Figure 1 A diagram illustrating a multi-core processor. Figure 4 It is shown Figure 1 A diagram showing the task list. Figure 5 It is shown Figure 1 A diagram of the ETS (Execution Timestamp) table. Figure 6 It is shown Figure 1 A diagram of the TDT (Task Duration) table.

[0063] Reference Figure 1 and Figure 3 A multi-core processor 213 may include n cores, where n is a natural number greater than or equal to 2.

[0064] Each core may include an compute unit (ALU) 2131a, an SRAM 2131b, and an ITCM (intended-closely coupled memory) 2131c. In some embodiments, each core may also include a code loader 2131d, a packet receiver 2131e, and a task requester 2131f.

[0065] The computing unit 2131a can perform calculations at least in part based on the code loaded into the ITCM 2131c. The SRAM 2131b can store the data required to perform such calculations.

[0066] Code loader 2131d can receive the code for a task to be executed by the core from an external source and load the code into ITCM 2131c. Packet receiver 2131e can receive packets related to core operations from an external source. When the processing of a task assigned to the core is complete, task requester 2131f can send a signal requesting subsequent tasks.

[0067] although Figure 3 Each core is shown to include a code loader 2131d, a packet receiver 2131e, and a task requester 2131f, but this disclosure is not limited thereto. In some embodiments, the embodiment may be implemented such that the code loader 2131d, packet receiver 2131e, and task requester 2131f are implemented, for example, in software to control each core. Additionally, in some embodiments, the code loader 2131d, packet receiver 2131e, and task requester 2131f may be implemented separately from the core.

[0068] Refer again Figure 1 The task scheduler 219 can generate tasks required to provide to the non-volatile memory 220 in response to commands received via the host interface 211, and can be operated such that the generated tasks are processed by the multi-core processor 213.

[0069] Specifically, the task scheduler 219 can generate multiple tasks based on commands received through the host interface 211, and select the core for processing the multiple tasks using the Execution Timestamp (ETS) table 219b and the Task Execution Time (TDT) table 219c, thereby allowing the tasks to be processed by the multi-core processor 213. The commands generated by processing multiple tasks can be referenced above. Figure 2 The described method is provided to the non-volatile memory 220.

[0070] The task scheduler 219 can operate using the task list 219a, the execution timestamp (ETS) table 219b, and the task execution time (TDT) table 219c.

[0071] Reference Figure 1 and Figure 4 Task list 219a may include m tasks required to generate commands to be provided to nonvolatile memory 220 in response to commands received from host 100 via host interface 211, where m is a natural number. Here, each task can be distinguished from the others by an ID (TID) and may depend on the others.

[0072] For example, Task 2 (TID 2) is a task that can be processed when Task 1 (TID 1) is completed, and Task 4 (TID 4) can be a task that can be processed when all Tasks 1 to 3 (TID 1 to TID 3) are completed.

[0073] Reference Figure 1 and Figure 5 ETS table 219b may include the execution times E1 to EN of each core included in the multi-core processor 213 at a specific point in time. The task scheduler 219 may check the execution times E1 to EN of each core included in the multi-core processor 213 at a specific point in time by referring to ETS table 219b.

[0074] Reference Figure 1 and Figure 6 The TDT table 219c may include the required time to complete each of the tasks TID 1 to TIDM stored in the task list 219a. Figure 6 In the diagram, Task 1 (TID 1) indicates the time T1 required to complete the processing, and Task 2 (TID 2) requires time T2 to complete the processing.

[0075] In some embodiments, the task scheduler 219 may be implemented, for example, in software, to schedule tasks in each core included in the multi-core processor 213. In this case, the task list 219a, ETS table 219b, and TDT table 219c described above may be stored in Figure 1 The buffer memory 216 shown, the internal memory of the storage controller 210, or the external memory of the storage controller 210.

[0076] The following will refer to Figures 7 to 15 The operation of a storage device according to some embodiments is described.

[0077] Figure 7 This is a flowchart illustrating the operation of a storage device according to some embodiments. Figures 8 to 15 This is a diagram illustrating the operation of a storage device according to some embodiments.

[0078] Reference Figure 7 The memory command is provided from the host 100 to the memory controller 210 (S100).

[0079] Specifically, refer to Figure 1 and Figure 8 The host interface 211 can receive memory commands that require memory operations to be performed on the non-volatile memory 220.

[0080] For example, memory operations may include operations to read data stored in non-volatile memory cells of non-volatile memory 220 addressed to a logical address, write operations to write data to non-volatile memory cells of non-volatile memory 220 addressed to a logical address, and / or erase operations to erase specific blocks of non-volatile memory 220 addressed to a logical address. However, embodiments are not limited thereto, and examples of memory operations on non-volatile memory 220 may be modified in various ways.

[0081] The following will illustrate, as an example, a read command requesting to read data stored in a non-volatile memory cell of non-volatile memory 220 addressed to a logical address. However, it will be understood that the embodiments are not limited to this example.

[0082] Next, a task corresponding to the provided read command is generated (S110).

[0083] Specifically, refer to Figure 1 and Figure 8 The task scheduler 219 of the storage controller 210 can generate tasks required to send to the non-volatile memory 220 in response to a read command provided from the host 100.

[0084] As an example, the first task (task 1) may include an address mapping (L2P) task that maps a logical address LA provided by the host 100 to a physical address (PA) used in the nonvolatile memory 220, and the second task (task 2) may include determining the level of the read voltage applied to the nonvolatile memory cell of the nonvolatile memory 220.

[0085] However, this is just an example. Task scheduler 219 can generate Q (Q is a natural number) tasks required to generate a read command to be sent to nonvolatile memory 220 in response to a read command provided from host 100.

[0086] Next, refer to Figure 7 Receive task request (S120).

[0087] Specifically, refer to Figure 1 The task scheduler 219 of the storage controller 210 can receive a test request from the core of the multi-core processor 213 in which the assigned task is processed.

[0088] Next, refer to Figure 7 Search task execution time (S130).

[0089] Specifically, refer to Figure 1 and Figure 9 The task scheduler 219 of the storage controller 210 can take into account the dependencies between individual tasks from the task list ( Figure 4 219a) Extracting the tasks to be assigned. The following description, as an example, illustrates the extraction of task 1 (TID 1) and task 2 (TID 2) by task scheduler 219. However, the embodiments are not limited thereto, and various tasks may be extracted depending on different embodiments and / or operations.

[0090] Task scheduler 219 checks the execution times of task 1 (TID 1) and task 2 (TID 2) in TDT table 219c. Figure 9 In the example shown, task scheduler 219 checks that the execution time of task 1 (TID 1) and task 2 (TID 2) is 40.

[0091] Next, refer to Figure 7 The kernel is selected by considering the task execution schedule and execution timestamp table (S140).

[0092] Specifically, refer to Figure 1 and Figure 10 Task scheduler 219 checks ETS table 219b and checks if core 1 has the shortest execution time at the current time. For example, if task 2 (TID 2) depends on task 1 (TID 1), task scheduler 219 can assign both task 1 (TID 1) and task 2 (TID 2) to core 1, which has the shortest execution time at the current time.

[0093] For example, if there is no dependency between task 2 (TID 2) and task 1 (TID 1), the task scheduler 219 recalculates the execution time of each core, assuming that task 1 (TID 1) is assigned to core 1, which has the shortest execution time at the current time. Task 2 (TID 2) can also be assigned to the core with the shortest execution time. For example, task 2 can be assigned to core 1 or another core other than core 1.

[0094] In this example, after task 1 (TID 1) is assigned to core 1, the execution time of core 1 becomes 30, which is the minimum execution time among the other cores. Therefore, task scheduler 219 can assign both task 1 (TID 1) and task 2 (TID 2) to core 1.

[0095] Next, refer to Figure 7 Update the ETS table (S 150).

[0096] It will be understood that the various components described herein (e.g., task scheduler 219, group manager 215, group receiver 2131e, task requester 2131f, and code loader 2131d) may be implemented as separate circuits. Additionally or alternatively, one or more components may be implemented within one or more processors configured to perform the functions described herein.

[0097] Specifically, refer to Figure 1 and Figure 11 The task scheduler 219 will update the execution time of core 1, which has been assigned to task 1 (TID 1) and task 2 (TID 2), to 60.

[0098] Next, refer to Figure 7 Task 1 and Task 2 are issued to Core 1 (S160).

[0099] Specifically, refer to Figure 1 and Figure 12 Task scheduler 219 provides task 1 (TID 1) and task 2 (TID 2) to packet receiver 2131e of core 1 to publish task 1 (TID 1) and task 2 (TID 2) to core 1.

[0100] Next, refer to Figure 7 Load the code required to process task 1 (TID 1) (S170).

[0101] Specifically, refer to Figure 1 and Figure 13The code loader 2131d of core 1 receives the code for task 1 (TID 1) to be processed by core 1 from an external component and can load the code into ITCM 2131c. In some embodiments, although the code required to process the task may be stored, for example, in the buffer memory 216 described above, the embodiments are not limited to this.

[0102] When the code for Task 1 (TID 1) is loaded into ITCM 2131c, Core 1 uses compute unit 2131a and SRAM 2131b to process Task 1 (TID 1).

[0103] Next, refer to Figure 7 When task 1 (TID 1) is completed, a request for subsequent tasks is sent (S180). Additionally, the code required to process task 2 (TID 2) is loaded (S190).

[0104] Specifically, refer to Figure 1 and Figure 14 When task 1 (TID 1) is completed, the task requester 2131f of core 1 requests the task scheduler 219 to assign a subsequent task (e.g., a task other than task 1 or task 2 that is yet to be determined). Furthermore, while the task requester 2131f requests the task scheduler 219 to assign a subsequent task, for example, the code loader 2131d of core 1 receives the code for task 2 (TID 2) to be processed by core 1 from buffer memory 216 and loads the code into ITCM 2131c. For example, the code loader 2131d of core 1 may not load the code required to execute the task after a timeout for issuing a new task, but may load the code for the scheduled task at the same time as the task requester 2131f requests the task scheduler 219 to assign a subsequent task. Therefore, the operating speed of the storage device can be improved.

[0105] Next, refer to Figure 7 Process Task 2 (TID 2) (S200).

[0106] Specifically, refer to Figure 1 and Figure 14 When the code for Task 2 (TID 2) is loaded into ITCM 2131c, Core 1 uses compute unit 2131a and SRAM 2131b to process Task 2 (TID 2).

[0107] Next, refer to Figure 7 Based on the processing results of the task, a read command to be provided to the non-volatile memory is generated (S210).

[0108] Specifically, refer to Figure 1 and Figure 15The storage controller 210 can check the physical address corresponding to the logical address provided by the slave host 100 based on the processing result of task 1 (TID 1), determine the read voltage level based on the processing result of task 2 (TID 2), and generate a read command to be provided to the non-volatile memory 220. At this time, unlike the read command provided by the slave host 100 to the storage controller 210, the read command provided by the storage controller 210 to the non-volatile memory 220 may include physical address and read voltage level information.

[0109] However, the above description is for an example embodiment, and the storage controller 210 may generate read commands from the storage controller 210 to the non-volatile memory 220 based on the processing results of Q tasks.

[0110] Next, refer to Figure 7 The generated read command is sent to the non-volatile memory (S220).

[0111] The storage controller 210 can be referenced above. Figure 2 The described method provides the generated read command to the non-volatile memory 220. Specifically, the memory controller 210 can provide a data signal including the generated read command and the generated physical address. Figure 2 The DQ) along with the switched write enable signal ( Figure 2 The nWE) are sent together to the non-volatile memory 220.

[0112] In the storage device 200 according to the above embodiment, each time the task scheduler 219 assigns a task, it considers the execution time of each core, and the task is assigned to the core that can process the task most efficiently. Furthermore, each core does not remain idle after processing the assigned task until the next task is assigned; instead, the code for the planned task is loaded simultaneously at the core when requesting the task scheduler 219 to execute the subsequent task. Therefore, core utilization efficiency can be significantly increased, and the operating speed of the storage device can be improved.

[0113] Although embodiments of the inventive concept according to this disclosure have been described by way of example, the operation of the scheduling memory controller 210 in response to a command received from the host 100 to generate m tasks required to provide to the nonvolatile memory 220 is described, the embodiments are not limited to these examples.

[0114] In some embodiments, the storage controller 210 may utilize the method described above when scheduling k tasks corresponding to multiple commands received from the host 100. For example, when the storage controller 210 schedules a first task for a first read command received from the host 100 and a second task for a second read command received from the host 100, the method described above may be used to schedule the first task and the second task.

[0115] Figure 16 This is a diagram illustrating a TDT (Task Duration) table according to some embodiments.

[0116] Reference Figure 1 , Figure 2 and Figure 16 The first task TID 1 is used to process the first read command received from the host 100, the second task TID 2 is used to process the second read command received from the host 100, and the kth task TID k is used to process the second read command received from the host 100.

[0117] The time required to complete the processing of the first task TID 1 is T1, the time required to complete the processing of the second task TID 2 is T2, and the time required to complete the processing of the kth task TID k is Tk.

[0118] When a first read command received from host 100 is used to read data stored in a first memory cell of memory cell array 520, and a second read command received from host 100 is used to read data stored in a second memory cell of memory cell array 520, the time T2 required to complete the processing of the second task TID 2 can be changed according to the location of the first memory cell and the second memory cell.

[0119] For example, due to locality, the time T2 required to complete the processing of the second task TID 2 when the first memory cell and the second memory cell in the memory cell array 520 are adjacent to each other can be less than the time T2 required to complete the processing of the second task TID 2 when the first memory cell and the second memory cell are not adjacent to each other.

[0120] For example, considering whether to perform internal operations of the non-volatile memory 220, the state of the non-volatile memory 220, the state of the memory interface 212, and the relationship between commands received from the host 100, the processing completion time T1 to Tk of the tasks included in the task execution schedule 219d can be changed.

[0121] Furthermore, although the tasks generated based on different commands received from host 100 are described as examples, the above references... Figure 6 The processing completion time T1 to Tm of the task generated according to a command may also be changed depending on whether internal operations of the non-volatile memory 220 are performed, the state of the non-volatile memory 220, the state of the memory interface 212, or other considerations.

[0122] Therefore, due to the increased utilization of the multi-core processor connected to the storage device, the storage device and its operating method according to this disclosure can operate with increased speed and efficiency. The above-described processing are some examples of how multi-core processors can be used efficiently according to embodiments of the present invention.

[0123] In summary, those skilled in the art will understand that variations and modifications can be made to the disclosed embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A method of operating a storage device, the storage device comprising non-volatile memory and a multi-core processor including at least two cores, the method comprising: The host interface of the storage device receives a first memory command from the host for requesting the non-volatile memory to perform a predetermined memory operation; The task scheduler of the storage device generates a first task and a second task based on the first memory command; The task scheduler selects a first core from the at least two cores based on the execution time of the at least two cores; The task scheduler assigns the first task and the second task to the first core; as well as After the first core processes the assigned first task, while the first core requests subsequent tasks from the task scheduler, the first core loads code for processing the second task.

2. The method of operating a storage device according to claim 1, wherein, The storage device also includes a memory interface connected to the non-volatile memory. Furthermore, a second memory command, generated after the processing of the first task and the second task is completed, and which is at least partially based on the first memory command, is provided to the non-volatile memory through the memory interface.

3. The method of operating a storage device according to claim 1, wherein, The first memory command includes a read command for reading data from a non-volatile memory cell addressed to a first logical address. The first task includes searching for the first physical address corresponding to the first logical address, and The second task includes determining the read voltage for reading data stored in a non-volatile memory cell addressed to the first physical address.

4. The method of operating a storage device according to claim 1, wherein, The host interface receives from the host a second memory command, different from the first memory command, for requesting the non-volatile memory to perform a predetermined memory operation. The task scheduler generates a third task based on the second memory command. The task scheduler checks the execution time of the third task and, based on the execution time of the third task, examines the execution times of the first core and the second core to select one of the first core and the second core as the core to be assigned the third task. The first memory command includes a first read command for reading data from a first memory cell among a plurality of non-volatile memory cells. The second memory command includes a second read command for reading data from a second memory cell among the plurality of non-volatile memory cells, and The execution time of the third task varies depending on the location of the first memory unit and the second memory unit.

5. The method of operating a storage device according to claim 1, wherein, The operation of selecting the first core from the at least two cores includes: The task scheduler checks the execution time operations of the first task and the second task, and The task scheduler checks the execution times of the first core and the second core based on the execution times of the checked first task and the second task, and checks the execution times of the first core and the second core when assigning the first task to the first core to further assign the second task to the first core.

6. The method of operating a storage device according to claim 5, further comprising: The task scheduler updates the execution time of the first core by taking into account the execution times of the first task and the second task.

7. A method for operating a storage device, the storage device comprising non-volatile memory and a multi-core processor including at least two cores, the method comprising: The host interface of the storage device receives a first memory command from the host for requesting the non-volatile memory to perform a predetermined memory operation; The task scheduler of the storage device generates a first task and a second task based on the first memory command; The task scheduler checks the execution time of the first task; The task scheduler selects the first core with the shortest execution time from the at least two cores based on the execution time of the at least two cores; The task scheduler adds the execution time of the first task to the execution time of the first core to update the execution time of the at least two cores; The task scheduler issues the first task to the first core; The task scheduler selects the second core with the shortest execution time from the at least two cores based on the updated execution times of the at least two cores; as well as The task scheduler publishes the second task to the first core when the second task depends on the first task, and otherwise publishes the second task to the second core.

8. The method of operating a storage device according to claim 7, further comprising: Once the first core has finished processing the first task it issued, it requests the task scheduler to assign subsequent tasks and simultaneously requests the code for processing the second task to be loaded into the first core.

9. The method of operating a storage device according to claim 8, further comprising: The second memory command, generated based on the processing of the first and second tasks, is provided to the non-volatile memory through the memory interface.

10. The method of operating a storage device according to claim 7, wherein, The first memory command includes a read command for reading data from a non-volatile memory cell addressed to a first logical address. The first task includes searching for the first physical address corresponding to the first logical address, and A second memory command is sent to the non-volatile memory, wherein the second memory command includes a read command for reading data from a non-volatile memory cell addressed to the first physical address.

11. A storage device, comprising: Non-volatile memory, which includes multiple non-volatile memory cells; A host interface configured to receive from a host a first memory command for requesting the non-volatile memory to perform a predetermined memory operation; A multi-core processor, which includes multiple cores; A task scheduler is configured to: generate a first task and a second task based on the first memory command; check the execution time of the first task; select a first core with the shortest execution time from the plurality of cores based on the execution time of the plurality of cores; add the execution time of the first task to the execution time of the first core to update the execution time of the plurality of cores; issue the first task to the first core; select a second core with the shortest execution time from the plurality of cores based on the updated execution time of the plurality of cores; and issue the second task to the first core if the second task depends on the first task, otherwise issue the second task to the second core.

12. The storage device according to claim 11, further comprising: A memory interface configured to send a switch write enable signal and a data signal including a second memory command to the non-volatile memory, wherein the second memory command is generated based on the completion of the first task and the second task.

13. The storage device according to claim 11, wherein, While the first core requests the task scheduler to assign subsequent tasks, the code for processing the second task is loaded into the first core.

14. The storage device according to claim 13, further comprising: A buffer memory, configured to temporarily store data to be read from the non-volatile memory. The code used to process the second task is stored in the buffer memory.

15. The storage device according to claim 13, wherein, The first memory command includes a read command that reads data from a non-volatile memory cell addressed to a first logical address. The first task includes the task of searching for the first physical address corresponding to the first logical address. The second task includes determining the read voltage for reading data stored in a non-volatile memory cell addressed to the first physical address, and A second memory command is sent to the non-volatile memory, wherein the second memory command includes a read command for reading data from a non-volatile memory cell addressed to the first physical address.

16. The storage device according to claim 15, further comprising: A memory interface configured to send a switch write enable signal and a data signal including a second memory command to the non-volatile memory, wherein the second memory command is generated based on the completion of the first task and the second task.

17. The storage device according to claim 11, wherein, The first memory command includes a read command that reads data from a non-volatile memory cell addressed to a first logical address. The first task includes searching for the first physical address corresponding to the first logical address, and A second memory command is sent to the non-volatile memory, wherein the second memory command includes a read command for reading data from a non-volatile memory cell addressed to the first physical address.

18. The storage device according to claim 17, further comprising: A memory interface configured to send a switch write enable signal and a data signal including a second memory command to the non-volatile memory.

19. The storage device according to claim 11, wherein, Updating the execution time of the multiple cores includes updating the execution timestamp table using the task execution schedule.

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