Low capacitance transient voltage suppressor with high holding voltage

Abstract

A transient voltage suppressor (TVS) device includes a silicon controlled rectifier (SCR) as a clamping device between a high-side steering diode and a low-side steering diode. The SCR includes alternating emitter and base regions interleaved along a major surface of a semiconductor layer and in a direction orthogonal to a current path of the SCR. The TVS device achieves low capacitance and high holding voltage at a protected node.

Description

TECHNICAL FIELD

[0001] The present invention relates to a low capacitance transient voltage suppressor with high holding voltage. BACKGROUND

[0002] Voltage and current transients are a major cause of integrated circuit failure in electronic systems. Transients are generated by a variety of sources both internal and external to the system. For example, common transient sources include normal switching operation of power supplies, AC line fluctuations, lightning strikes, and electrostatic discharge (ESD).

[0003] Transient voltage suppressors (TVS) are commonly used to protect integrated circuits from damage due to transients or overvoltage events occurring in the integrated circuit. Overvoltage protection is important for consumer or internet of things devices, as these electronic devices are exposed to frequent human handling and can therefore be susceptible to ESD or transient voltage events that can damage the device.

[0004] Specifically, both the power pins and data pins of an electronic device need protection from overvoltage conditions due to ESD events or switching and lightning transient events. Typically, power pins require high surge protection, but can tolerate protection devices with higher capacitance. At the same time, data pins, which can operate at high data speeds, require protection devices that provide surge protection with low capacitance to not interfere with the data speed of the protected data pins.

[0005] Existing TVS protection solutions are applied to input / output (I / O) terminals in high speed applications, and exist in both vertical and lateral type semiconductor circuit structures. In a unidirectional TVS, I / O current during an ESD event is diverted through a low capacitance high voltage side turning diode into a large reverse blocking junction, or the current is diverted through a low capacitance low voltage side turning diode to ground. In the case of bidirectional TVS protection, low capacitance is achieved by blocking through a series connection of a low capacitance forward biased diode and a large reverse biased junction.

[0006] HDMI (High Definition Multimedia Interface) is a high speed digital audio / video interface used to transfer digital audio / video data between HDMI compatible devices. HDMI connectors in electronic devices are equipped with overvoltage transient protection devices to prevent overvoltage events, such as ESD, due to frequent human handling. SUMMARY

[0007] To achieve the above object, the present application provides a transient voltage suppression (TVS) device, comprising: a semiconductor layer including a first epitaxial layer of a first conductivity type; a plurality of active regions formed in the semiconductor layer, the active regions being separated from each other by isolation structures; a high-side turn diode formed in a first active region, the high-side turn diode having an anode terminal coupled to a first protected node and a cathode terminal; and a clamping device formed in a second active region of the plurality of active regions, the clamping device including a silicon controlled rectifier (SCR) including an anode terminal coupled to the cathode terminal of the high-side turn diode and a cathode terminal, the silicon controlled rectifier including: a first well of the first conductivity type formed in the first epitaxial layer; a second well of a second conductivity type formed in the first epitaxial layer on a major surface of the semiconductor layer, the second well being adjacent to and spaced apart from the first well in a first direction, the second conductivity type being opposite to the first conductivity type; a first region of the first conductivity type and a second region of the second conductivity type formed in the first well and heavily doped, the first and second regions being electrically connected and forming the anode terminal of the SCR; and a third region of the first conductivity type and a fourth region of the second conductivity type formed in the second well and heavily doped, the third and fourth regions being electrically connected and forming the cathode terminal of the SCR, wherein the first and second regions are arranged as alternating doped regions in the first well in a second direction orthogonal to the first direction on the major surface of the semiconductor layer, and the third and fourth regions are arranged as alternating doped regions in the second well in the second direction, the third region being arranged co-planar with the second region in the second direction, and the fourth region being arranged co-planar with the first region in the second direction.

[0008] Preferably, the TVS device further includes a low-side turn diode formed in a third active region of the plurality of active regions, the low-side turn diode having a cathode terminal coupled to the first protected node and an anode terminal coupled to the cathode terminal of the SCR.

[0009] Preferably, the high-side turn diode includes a PN junction diode, and the low-side turn diode includes a punch-through SCR.

[0010] Preferably, the TVS device further includes a fifth region of the first conductivity type formed in the first epitaxial layer and overlapping the second well, the fifth region being heavily doped.

[0011] Preferably, the first and second regions in the first well are electrically connected by a first junction, and the third and fourth regions in the second well are electrically connected by a second junction.

[0012] Preferably, the semiconductor layer further comprises a second epitaxial layer of the second conductivity type formed on the second epitaxial layer and a first buried layer of the first conductivity type, wherein the first epitaxial layer is formed on the first buried layer.

[0013] Preferably, the isolation structure comprises a plurality of trench isolation structures isolating the active regions, each trench isolation structure extending from the first epitaxial layer to the second epitaxial layer.

[0014] Preferably, the high-side diode comprises a PN junction diode comprising: a sixth region of the second conductivity type formed in the first active region of the first epitaxial layer; and a seventh region of the first conductivity type formed in the first epitaxial layer spaced apart from the sixth region.

[0015] Preferably, the first conductivity type comprises N-type conduction and the second conductivity type comprises P-type conduction.

[0016] Preferably, the TVS device further comprises: eighth and ninth regions of the first conductivity type formed in the first well and extending adjacent to the alternating first and second regions in the second direction, the second region being surrounded in the first and second directions by the first region, the eighth region and the ninth region; and tenth and eleventh regions of the second conductivity type formed in the second well and extending adjacent to the alternating third and fourth regions in the second direction, the third region being surrounded in the first and second directions by the fourth region, the tenth region and the eleventh region.

[0017] Preferably, the cathode terminal of the SCR is conductively connected to a ground voltage.

[0018] Preferably, the second region has a length in the first direction that is shorter than a length of the first region, and the third region has a length in the first direction that is shorter than a length of the fourth region.

[0019] The present application also provides a transient voltage suppression (TVS) device, comprising: a semiconductor layer comprising a first epitaxial layer of a first conductivity type; a plurality of active regions formed in the semiconductor layer, the active regions being separated from each other by isolation structures; a combined diode / clamp device formed in a first active region of the plurality of active regions, the combined diode / clamp device comprising a high-side turn-on diode integrated with a silicon controlled rectifier (SCR), the combined diode / clamp device comprising: a first region of a second conductivity type opposite the first conductivity type formed in the first epitaxial layer, the first region forming an anode terminal of the high-side turn-on diode coupled to a first protected node; a first well of the first conductivity type formed in the first epitaxial layer and separated from the first region in a first direction on a major surface of the semiconductor layer; a second well of the second conductivity type formed in the first well; a second region of the first conductivity type; and a third region of the second conductivity type formed in the second well and heavily doped, the second and third regions being conductively connected and forming a cathode terminal of the SCR, wherein the second and third regions are arranged as alternating doped regions in the second well in a second direction on the major surface of the semiconductor layer and orthogonal to the first direction.

[0020] Preferably, the TVS device further comprises a low-side turn-on diode formed in a second active region of the plurality of active regions, the low-side turn-on diode having an anode terminal coupled to the cathode terminal of the SCR and a cathode terminal coupled to the first protected node.

[0021] Preferably, the low-side turn-on diode comprises a punch through SCR.

[0022] Preferably, the TVS device further comprises a fourth region of the first conductivity type formed in the first epitaxial layer adjacent to the second well, the fourth region being heavily doped.

[0023] Preferably, the first region is coupled to a first contact and the second and third regions in the second well are conductively connected by a second contact.

[0024] Preferably, the semiconductor layer further comprises a second epitaxial layer of the second conductivity type formed on the second epitaxial layer and a first buried layer of the first conductivity type, wherein the first epitaxial layer is formed on the first buried layer.

[0025] Preferably, the isolation structures comprise a plurality of trench isolation structures isolating the active regions, each trench isolation structure extending from the first epitaxial layer to the second epitaxial layer.

[0026] Preferably, the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

[0027] Preferably, the TVS device further comprises fifth and sixth regions of the second conductivity type formed in the second well and extending adjacent the alternating second and third regions in the second direction, the second region being surrounded by the third region, the fifth region and the sixth region in the first and second directions.

[0028] Preferably, the first region comprises a plurality of regions of the second conductivity type formed in the second direction, each region of the second conductivity type being coupled to a respective contact.

[0029] In summary, the present application provides a transient voltage suppression (TVS) device and apparatus that achieves low capacitance and high holding voltage at a protected node as compared to the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 Including Figure 1 (a) through Figure 1 (c) illustrate circuit diagrams of a SCR based TVS protection device in embodiments of the present application.

[0031] Figure 2 Illustrate current-voltage performance of a TVS protection device in embodiments of the present application.

[0032] Figure 3 Illustrate cross-sectional views of a TVS protection device in embodiments of the present application.

[0033] Figure 4 Illustrate, in some embodiments, Figure 3 the layout of the SCR device in the illustrated TVS protection device.

[0034] Figure 5 Illustrate, in embodiments of the present application, Figure 3 and Figure 4 cross-sectional views of the TVS protection device in along the A-A' line.

[0035] Figure 6 Illustrate, in embodiments of the present application, Figure 3 and Figure 4 cross-sectional views of the TVS protection device in along the B-B' line.

[0036] Figure 7 Including Figure 7 (a) through Figure 7 (b) illustrate physical diagrams and equivalent circuit diagrams of a SCR clamp device in embodiments of the present application.

[0037] Figure 8 Illustrate, in alternative embodiments of the present application, the layout of the SCR device in the TVS protection device.

[0038] Figure 9 shows a cross-sectional view of a TVS protection device along line C-C' in an embodiment of the application. Figure 8

[0039] Figure 10 shows a circuit diagram and a cross-sectional view of a TVS protection device in an alternative embodiment of the application.

[0040] Figure 11 shows a cross-sectional view of a TVS protection device along line D-D' in an embodiment of the application. Figure 10

[0041] Figure 12 shows a cross-sectional view of a TVS protection device along line E-E' in an embodiment of the application. Figure 11

[0042] Figure 13 shows a cross-sectional view of a TVS protection device along line F-F' in an embodiment of the application. Figure 11

[0043] Figure 14 shows a layout diagram of an integrated HS diode / SCR device in a TVS protection device in an alternative embodiment of the application.

[0044] Figure 15 shows a cross-sectional view of a TVS protection device along line F-F' in an embodiment of the application. Figure 14

[0045] Figure 16 shows a layout diagram of an SCR device in a TVS protection device in an alternative embodiment of the application. Figure 10 DETAILED DESCRIPTION

[0046] The following will be described in detail with reference to the accompanying drawings of the embodiments of the application. Figure 1 Figure 16 The technical solutions, structural features, achieved objects and effects of the embodiments of the application will be described in detail.

[0047] ​​​​​​​In embodiments of the invention, a transient voltage suppressor (TVS) device includes a silicon controlled rectifier (SCR) as a clamping device between a high voltage side turn-on diode and a low voltage side turn-on diode. The SCR includes alternating emitter and base regions staggered in a direction orthogonal to a current path of the SCR along a major surface of a semiconductor layer. In some embodiments, the SCR includes alternating emitter and base regions forming PNP and NPN bipolar transistors of a PNPN structure of the SCR. The TVS device of the invention achieves low capacitance at a protected node in a blocking mode while providing a high holding voltage in a conducting mode. For example, the TVS device of the invention can achieve a holding voltage greater than an operating voltage associated with the protected node.

[0048] HDMI applications require transient voltage protection devices to have low capacitance so as not to interfere with data speed of a protected pin. HDMI applications also require a holding voltage (DC) of the protection device to exceed a maximum operating voltage of an HDMI coupled device. A conventional solution to these requirements includes using a non-back-to-back TVS diode for I / O protection. Conventional thyristor-based TVS protection has a deep snapback characteristic that disallows use in HDMI applications because the holding voltage after snapback is typically lower than the maximum operating voltage of the HDMI coupled device.

[0049] The TVS device of the invention is particularly suitable for providing transient voltage protection in HDMI applications, where the TVS device provides low capacitance at a protected node in a blocking mode and provides a high holding voltage after snapback in a conducting mode. In embodiments of the invention, the TVS device is a SCR-based TVS protection device. The SCR-based TVS device achieves a low capacitance value, for example less than 0.2 pF, at the protected node while providing a high holding voltage that exceeds a maximum operating voltage of an HDMI coupled device. The TVS device of the invention can be advantageously applied to protect a high speed data pin or input output (I / O) terminal in high speed electronic applications, such as a data port or connector implementing the HDMI 2.1 specification.

[0050] In this specification, a transient voltage suppressor (TVS) protection device refers to a protection device for protecting a protected node from overvoltage transient conditions, such as voltage surges or voltage spikes. When a surge voltage exceeding a trigger voltage of the TVS device is applied to the protected node, the TVS protection device (“TVS device”) operates by shunting excess current away from the protected node. The TVS device can include a clamping device for clamping voltage at the protected node at a clamping voltage that is much lower than a voltage value of the voltage surge while safely conducting the surge current.

[0051] TVS devices can be unidirectional or bidirectional. Unidirectional TVS devices have asymmetric current-voltage characteristics and are typically used to protect circuit nodes whose signals are unidirectional, i.e., the signal is always above or below some reference voltage, such as ground voltage. For example, a unidirectional TVS device can be used to protect a circuit node whose normal signal is a positive voltage from 0V to 5V. On the other hand, bidirectional TVS devices have symmetric current-voltage characteristics and are typically used to protect circuit nodes whose signals are bidirectional or whose voltage levels can be above or below a reference voltage (e.g., ground). For example, a bidirectional TVS device can be used to protect a circuit node whose normal signal varies symmetrically above and below the ground voltage (e.g., from -12V to 12V). In this case, the bidirectional TVS device protects the circuit node from surge voltages below -12V or above 12V.

[0052] In operation, the TVS device is in a blocking mode and is non-conductive except for possible leakage current when the voltage at the protected node is below the trigger voltage of the TVS device. That is, when the voltage at the protected node is within the normal voltage range of the protected node, the TVS device is non-conductive and is in a blocking mode. However, in the blocking mode, the TVS device presents a capacitance to the protected node. When the protected node is associated with a high-speed data pin, the capacitance of the TVS device in the blocking or non-conductive mode should be low so as not to impede the high-speed operation of the data pin. In some embodiments, the TVS device of the present invention achieves a low capacitance value of less than 0.2 pf in the blocking mode. On the other hand, in response to the voltage at the protected node being equal to or above the trigger voltage of the TVS device, the TVS device enters a conductive mode and quickly recovers to the hold voltage such that the TVS device conducts excessive current at the hold voltage that is well below the voltage surge at the protected node.

[0053] Figure 1 Comprising Figure 1 (a) to Figure 1 (c), represent circuit diagrams of SCR-based TVS protection devices in embodiments of the present invention. Figure 1 (a) to 1(c) represent various configurations of SCR-based TVS devices constructed in accordance with embodiments of the present invention.

[0054] Figure 1 (a) represents a circuit diagram of a bidirectional TVS protection device in embodiments of the present invention. Reference is made to Figure 1(a), the TVS protection device 10 ("TVS device 10") includes two sets of coupled steering diodes to provide surge protection for two input-output (I / O) terminals I / O1 and I / O2. Each set of steering diodes includes a high-side steering diode and a low-side steering diode. More specifically, a high-side steering diode DH1 and a low-side steering diode DL1 are coupled to the I / O terminal I / O1 (node 12) as a protected node. At the same time, a high-side steering diode DH2 and a low-side steering diode DL2 are coupled to the I / O terminal I / O2 (node 14) as a protected node. The I / O terminal I / O1 is connected to the anode of the high-side steering diode DH1 and the cathode of the low-side steering diode DL1. Similarly, the I / O terminal I / O2 is connected to the anode of the high-side steering diode DH2 and the cathode of the low-side steering diode DL2. The cathode terminal of the high-side steering diode DH1 is connected to node N1 (node 13), which is also connected to the cathode of the high-side steering diode DH2. The anode terminal of the low-side steering diode DL1 is connected to node N2 (node 15), which is also the anode of the low-side steering diode DL2.

[0055] The TVS device 10 also includes a clamping device implemented as a silicon controlled rectifier (SCR). The anode of the SCR clamping device is connected to node N1 (node 13), while the cathode of the SCR clamping device is connected to node N2 (node 15). The SCR clamping device of the TVS device 10 clamps the voltage at the protected node I / O1 or I / O2 to a hold voltage while the TVS device safely conducts current out of the protected node.

[0056] In embodiments of the present application, the high-side steering diodes DH1 and DH2 are each configured as a PN junction diode with low capacitance at the anode terminal during the latching mode. In embodiments of the present application, the low-side steering diodes DL1 and DL2 of the TVS device 10 are each configured as a PN junction diode with low capacitance at the cathode terminal during the latching mode. In alternative embodiments, as shown in Figure 1 (b), the low-side steering diodes DL1 and DL2 of the TVS device 20 are each configured using a punch-through silicon controlled rectifier structure (referred to herein as a "PT-SCR"). The PT-SCR structure that can be used to implement the low-side steering diodes in the TVS devices of the present application is set forth in U.S. Patent No. 10825805, entitled "Low Capacitance Transient Voltage Suppressor Containing a Punch-Through Silicon Controlled Rectifier as a Low-Side Steering Diode," issued November 3, 2020, which is hereby incorporated by reference in its entirety. The low-side steering diodes DL1 and DL2 in the TVS devices of the present application can also be constructed using other suitable device structures that are presently known or will be developed in the future.

[0057] In this specification, an SCR is a current-controlled device containing four layers or regions of alternating P-type and N-type semiconductor material, forming an NPNP or PNPN structure. The anode of an SCR is the outermost p-type layer of the NPNP or PNPN structure, and the cathode is the outermost n-type layer of the NPNP or PNPN structure. A typical SCR includes a gate terminal connected to the p-type layer closest to the cathode. A thyristor can be represented as a PN junction diode with the gate terminal located at the cathode terminal. In an equivalent circuit diagram, the PNPN structure of an SCR forms cross-coupled PNP and NPN bipolar transistors. The emitter of the PNP transistor is the anode of the SCR, and the emitter of the NPN transistor is the cathode of the SCR.

[0058] In embodiments of the present application, the SCR is configured as a two-terminal device, where the gate terminal is electrically connected to the cathode terminal. When the voltage applied between the anode or cathode terminals is below the breakdown voltage of the junction between the internal P and N regions (“internal PN junction”), the SCR is in the latched mode (forward or reverse). In the latched mode, only a leakage current can flow into the SCR. On the other hand, when the voltage applied between the anode and cathode terminals exceeds the forward or reverse breakdown voltage of the thyristor, the thyristor conducts current. In this case, the internal PN junction breaks down, and the charge carriers (holes or electrons) produced by the avalanche breakdown flow to the base contact next to the emitter (the N+ cathode and P+ anode of the SCR). The avalanche current increases to a sufficient level, and the NPN bipolar transistor turns on (or the PNP bipolar transistor turns on). The PNP bipolar transistor turns on due to the positive feedback of the NPN bipolar transistor, and vice versa. When both the NPN and PNP transistors are on, the SCR is in the on state. When the SCR turns on, the SCR voltage quickly recovers to conduct current at a holding voltage below the breakdown voltage.

[0059] As used herein, a punch-through thyristor refers to an SCR in which the n-type region between the two p-type regions is substantially depleted at zero volts of bias voltage. That is, the two p-type regions separated by the n-type region are electrically shorted together at zero volts of bias voltage due to the depletion of the n-type region. The PT-SCR structure ensures low capacitance at the protected node.

[0060] As Figure 1The operation of the bidirectional TVS device of the present application shown in (a) and (b) is described as follows. When a positive surge is applied to I / O terminal I / Oi with respect to I / O terminal I / O2, current flows from terminal I / Oi through diode DHi and the SCR clamp, diode DL2 (which can be a PT-SCR device), and into terminal I / O2. Similarly, when a negative surge is applied to I / O terminal I / Oi with respect to I / O terminal I / O2 (equivalent to a positive surge being applied to terminal I / O2 with respect to I / Oi), current flows from terminal I / O2 through diode DH2 and the SCR clamp, diode DLi (which can be a PT-SCR), and into terminal I / Oi.

[0061] In other words, a positive surge voltage applied to either I / O terminal will forward bias the high voltage side of the impacted I / O terminal toward the diode (DHi or DH2), and when the surge voltage reaches or exceeds the breakdown voltage (BV) of the SCR clamp, the surge current triggers the SCR, which conducts current. The surge current exits through the other I / O terminal. A negative surge voltage applied to either I / O terminal will result in the same current conduction operation as a positive surge voltage applied to the other I / O terminal.

[0062] Figure 1 (c) represents a circuit diagram of a unidirectional TVS protection device in an embodiment of the present application. Referring to Figure 1 (c), unidirectional TVS protection device 30 ("TVS device 30") can be constructed from Figure 1 (a) by grounding node N2 (node 15) or the cathode terminal of the SCR clamp. That is, node N2 is connected to ground voltage. With such a configuration, the surge current from an overvoltage transient event applied to either I / O terminal will flow to the ground node.

[0063] In particular, a positive surge voltage applied to either I / O terminal will forward bias the high voltage side of the impacted I / O terminal toward the diode (DHi or DH2), and when the surge voltage reaches or exceeds the breakdown voltage of the SCR clamp, the surge current triggers the SCR, which conducts current. The surge current exits through ground node 15. A negative surge voltage applied to either I / O terminal will result in the same current conduction operation as a positive surge voltage applied to the other I / O terminal.

[0064] Figure 1TVS protection devices connected to two I / O or channels in a bi-directional mode or a unidirectional mode. In other embodiments, the TVS devices of the present application can be configured for multiple channels, such as four or more channels. In one embodiment of the present application, a TVS device is configured for four I / O terminals or four channels, where one pair of channels can be coupled to one pair of differential signals and another pair of channels can be coupled to another pair of differential signals. A TVS device with four channels is advantageous for use in an HDMI connector to protect the differential signal pairs in the HDMI connector. In the case of an HDMI application, the TVS device is typically configured in a unidirectional configuration, where the cathode of the SCR clamp device is connected to a ground voltage, such as Figure 2 TVS device 30 shown in (c).

[0065] Figure 2 represents the current-voltage characteristics of a TVS protection device in an embodiment of the present application. Referring to Figure 2 , curve 50 depicts the relationship between the current conducted by the TVS device and the voltage applied at the protected node. In this specification, only the forward conduction mode of the TVS device is represented. It is noted that Figure 3 the current-voltage characteristics of the TVS device shown in (c) represent the current-voltage characteristics of the SCR clamp device contained in the TVS device.

[0066] During normal operation, the voltage at the protected node should be within the operating voltage range (below V Op ). The TVS device is in the latched mode and does not conduct any current except for the leakage current. If the voltage at the protected node exceeds the trigger voltage (V Tri ) of the TVS device, the TVS device turns on so as to conduct current - that is, the TVS device is in the conduction mode. When the voltage at the protected node exceeds the trigger voltage, the SCR clamp device in the TVS device fires and enters into a snapback. Thus, the SCR of the TVS device clamps the voltage at the protected node at the holding voltage (V Hold ) and the TVS device safely conducts current out of the protected node. In this specification, the trigger voltage V Tri of the TVS device refers to the voltage level at which the internal PN junction of the SCR enters into breakdown due to the voltage at the protected node and one of the NPN and PNP bipolar transistors in the SCR of the TVS device turns on. When both bipolar transistors in the SCR are turned on, the TVS device is in the fully on mode and enters into a snapback to clamp the voltage at the protected node.

[0067] In an embodiment of the present application, the TVS device is designed to have a holding voltage V Op that is greater than the maximum operating voltage VHold For example, the operating voltage at the protected node can be 3.3V, and the TVS device of the present application has a holding voltage of 3.6V. In another example, the operating voltage at the protected node can be 5V, and the TVS device has a holding voltage of 5.5V. In particular, the TVS device preferably has a holding voltage greater than the operating voltage, such that even if the TVS device is triggered, the TVS device remains at a voltage higher than the operating voltage and does not divert current from the protected node.

[0068] In embodiments of the present application, the TVS device includes a structure that adjusts or tunes the trigger voltage V Tri of the TVS device to a desired voltage level, while maintaining the low parasitic capacitance and high holding voltage characteristics of the TVS device. For example, in some cases, the trigger voltage V Tri of the TVS device can be adjusted so as to make the TVS device more sensitive to voltage surges. The structure for adjusting the trigger voltage of the TVS device will be described in more detail below.

[0069] In accordance with embodiments of the present application, the low capacitance and high holding voltage SCR-based TVS device uses an alternating emitter and base region configuration that is staggered along a direction orthogonal to the current flow of the SCR. The TVS device thus formed can be configured in a bidirectional mode by floating the cathode terminal of the SCR, or in a unidirectional mode by connecting the cathode terminal of the SCR to ground voltage. The bidirectional or unidirectional configuration of the TVS device is not critical to the implementation of the TVS device of the present application. In the cross-sectional diagrams of the various embodiments of the TVS device described below, the specific connection of the cathode terminal of the SCR is not represented. It will be understood that the cathode terminal of the SCR can be connected in a manner required to form a bidirectional or unidirectional TVS device. Furthermore, in the cross-sectional diagrams of the various embodiments of the TVS device described below, the low voltage side turn-on diode is not represented. It will be understood that the TVS device includes a low voltage side turn-on diode, which can be implemented as a low capacitance PN junction diode or a PT-SCR, as described above.

[0070] Figure 3 A cross-sectional diagram of a TVS protection device is shown in accordance with embodiments of the present application. In particular, Figure 3 A cross-sectional diagram of the high voltage side turn-on diode ("HS diode") and SCR clamp device of the TVS protection device is shown. For example, Figure 1 The high voltage side turn-on diode and SCR clamp device of Figure 3 can be used to form the TVS protection device of Figure 3 In this figure, the low voltage side turn-on diode is omitted to simplify the discussion. It will be understood that Figure 3other elements not represented in the cross-sectional view.

[0071] Referring to Figure 3 A TVS protection device 100 ("TVS device 100") is fabricated on a P+ substrate 102. In the present embodiment, a P-type epitaxial layer 104 is formed on the P+ substrate 102. An N-type buried layer (NBL) 106 is then formed on the P-type epitaxial layer 104. An N-type epitaxial layer (N-Epi layer) 108 is formed on the N-type buried layer 106. The semiconductor structure is thereby constructed for forming a TVS device.

[0072] In the present embodiment, trench isolation structures 140 are used to define and isolate regions of the semiconductor structure for forming separate circuit elements. In particular, the trench isolation structures 140 divide the semiconductor structure into a number of active regions. In the present embodiment, the trench isolation structures 140 are formed as oxide-lined trenches filled with a polysilicon layer 142, and the trenches extend to the P+ substrate 102. In other embodiments, the trench isolation structures 140 can be formed as oxide-filled trenches.

[0073] With the trench isolation structures 140 thus formed, active regions in the semiconductor structure are defined for forming a high-side turn-off diode 150 and an SCR clamp 155. For example, the high-side turn-off diode 150 can be formed in a first active region, and the SCR clamp 155 can be formed in a second active region. In the present embodiment, the high-side turn-off diode (HS diode) 150 is formed as a PN junction diode with an anode formed by a heavily doped P+ region 110 and a cathode formed by a heavily doped N+ region 112, both formed in the N-type epitaxial layer 108 with an intervening N-type epitaxial layer 108, the TVS device 100 presenting a low capacitance to an I / O terminal connected to the P+ region 110 because the N-type epitaxial layer 108 is lightly doped.

[0074] A metal contact 132 is formed in the dielectric layer 138 so as to contact the P+ region 110, forming an anode terminal of the high-side turn-off diode 150. At the same time, another metal contact 134 is formed in the dielectric layer 138 to contact the N+ region 112, thereby forming a cathode terminal of the high-side turn-off diode 150. For the high-side turn-off diode 150, the anode terminal 132 is connected to the I / O terminal as a protected node, and the cathode terminal 134 is connected to a node N1, which is subsequently connected to an anode of the SCR clamp 155.

[0075] In embodiments of the application, the SCR clamp 155 (SCR or SCR device) is formed as a PNPN structure including a heavily doped P+ region 124 formed in an N-well 115 and a heavily doped N+ region 128 formed in a P-well 120. The N-well 115 and the P-well 120 are formed in an N-type epitaxial layer 108 and are spaced apart from each other in a first direction (e.g., the X direction) on a major surface of the semiconductor structure. The first direction (X direction) is also the current flow direction (or current path) of the SCR clamp 155. The SCR clamp 155 also includes a heavily doped N+ region 122 formed in the N-well 115 and a heavily doped P+ region 130 formed in the P-well 120.

[0076] In embodiments of the application, the SCR device 155 forms a PNPN structure by interleaving the emitter and base regions of the PNP and NPN bipolar transistors. Specifically, the emitter and base regions of each bipolar transistor are arranged to be interleaved in a second direction (e.g., the Z direction) on the major surface of the semiconductor structure and alternating doped regions in the respective well regions that are orthogonal to the first direction (X direction). In other words, the SCR device 155 includes emitter-base regions that are interleaved in a direction that is orthogonal to the current path of the SCR, or orthogonal to the current flow direction of the SCR. In Figure 4 In the drawings, black ink and gray ink are used to represent the emitter and base regions of each bipolar transistor in order to illustrate the alternating doped regions in the Z direction. For example, the N+ region 128 and the P+ region 130 are depicted as alternating doped regions in the Z direction in a cross-sectional view of the X-Y plane using black ink and gray ink. In this illustration, the gray ink represents a doped region that is formed behind the doped region of the black ink in the second (Z) direction. Further, the interleaved arrangement is such that the P+ emitter region of the PNP bipolar transistor is co-planar with the N+ emitter region of the NPN bipolar transistor in the second direction (Z direction), and further, the N+ base contact region of the PNP bipolar transistor is co-planar with the P+ base contact region of the NPN bipolar transistor in the second direction (Z direction). The SCR clamp 155 achieves a high holding voltage by using interleaved emitter-base regions in a direction that is orthogonal to the current path of the SCR.

[0077] A metal contact 146 is formed in the dielectric layer 138 to contact the P+ region 124 and the N+ region 122, forming an anode terminal of the SCR 155. Meanwhile, another metal contact 148 is formed in the dielectric layer 138 to contact the N+ region 128 and the P+ region 130, forming a cathode terminal of the SCR 155. The anode terminal 146 of the SCR is connected to the cathode of the high-voltage side diode 150, and the cathode terminal 136 of the SCR is connected to the anode terminal diode of the low-voltage side steering device (not shown in the figure). In order to form a unidirectional TVS device, the cathode terminal 136 of the SCR 155 can be further connected to a ground voltage.

[0078] With such a configuration, the P+ region 124 in the N-well 115 is the cathode of the SCR, the N+ region 128 in the P-well 120 is the anode of the SCR, the N+ region 122 in the N-well 115 is the body contact of the N-well, and the P+ region 130 in the P-well 120 is the body contact of the P-well. The PNPN structure of the SCR device 155 is formed by the P+ region 124, the N-well 115, the P-well 120, and the N+ region 128. More specifically, the SCR device 155 includes a PNP bipolar transistor and an NPN bipolar transistor forming the PNPN structure. In the SCR 155, the PNP bipolar transistor is formed by the P+ region 124 as the emitter, the N-well 115 / N+ region 122 as the base (the N+ region 122 as the body contact of the base), and the P-well 120 as the collector. Meanwhile, the NPN bipolar transistor is formed by the N+ region 128 as the emitter, the P-well 120 / P+ region 130 as the base (the P+ region 130 as the body contact of the base), and the N-well 115 as the collector.

[0079] Figure 3 It is shown that in some embodiments, Figure 3 The layout of the SCR device in the illustrated TVS protection device is shown. For simplicity of discussion, Figure 4 and Figure 4 Similar elements in the layout views of FIGS. 10A-10C are labeled with similar reference numbers. In particular, the layout views show the SCR device as seen from a third direction (e.g., the Y direction) that is orthogonal to the first and second directions. Figure 4 The layout view of FIG. 10A shows the structure of the SCR formed in the X-Z plane, and more specifically, the layout of the alternating emitter and base regions in the SCR device. Notably, Figure 4 The layout view of FIG. 10B shows the layout of certain regions and structures of the TVS device, with other regions or structures of the TVS device omitted for simplicity. For example, Figure 4 The isolation structures are omitted in the layout view of FIG. 10C. Figure 4 are for explanation only and are not limiting.

[0080] Reference is made to Figure 5The SCR device 155 is formed in an active region of the N-type epitaxial layer 108, isolated from other active regions by isolation structures (not shown). The P-well 120 and the N-well 115 are arranged as adjacent regions in the X direction (first direction). In the P-well 120, the P+ regions 130 forming base body contacts and the N+ regions 128 forming emitters of NPN bipolar transistors are formed as stripe doped regions alternating or interleaved in the Z direction (second direction). In the N-well 115, the N+ regions 122 forming base body contacts and the P+ regions 124 forming emitters of PNP bipolar transistors are formed as stripe doped regions alternating or interleaved in the Z direction (second direction).

[0081] Furthermore, the interleaved arrangement is such that the N+ regions 122 in the N-well 115 are co-planar with the P+ regions 130 in the P-well 120 in the second direction (Z direction). Similarly, the P+ regions 124 in the N-well 115 are co-planar with the N+ regions 128 in the P-well 120 in the second direction (Z direction). In this specification, as shown in Figure 6 and Figure 5 two regions are co-planar in the second direction when the two regions are aligned in the second (Z) direction and spaced apart in the first (X) direction.

[0082] Figure 3 shows a cross-sectional view along line A-A' of the TVS protection device in Figure 4 and Figure 6 in an embodiment of the present application. Figure 3 shows a cross-sectional view along line B-B' of the TVS protection device in Figure 4 and Figure 5 in an embodiment of the present application. First referring to Figure 6 along line A-A', the SCR device 155 includes the P+ regions 124 in the N-well 115 and the N+ regions 128 in the P-well 120 forming the PNPN structure of the SCR 155. The P+ regions 124 and the N+ regions 128 are aligned in the Z direction and thus co-planar in the Z direction. Now referring to Figure 7 along line B-B', the SCR device 155 includes the N+ regions 122 in the N-well 115 and the P+ regions 130 in the P-well 120 forming the base body contacts of the PNPN structure of the SCR 155. The N+ regions 122 and the P+ regions 130 are aligned in the Z direction and thus co-planar in the Z direction. With such a configuration, the SCR device 155 is formed of alternating emitter regions and base regions interleaved in the Z direction orthogonal to the current path of the SCR in the X direction.

[0083] The NPN and PNP bipolar transistors in the SCR device 155 are further explained in order to explain the alternating emitter and base regions.Figure 7 includes Figure 7 (a) and Figure 7 (b) represent the physical layout and equivalent circuit schematic of the SCR clamp device in embodiments of the present application. Referring to Figure 7 (a), the PNPN structure of the SCR device 155 includes a PNP bipolar transistor and an NPN bipolar transistor. The PNP bipolar transistor is formed by the P+ region 124 as the emitter, the N-well 115 / N+ region 122 as the base and the body contact, and the P-well 120 / P+ region 130 as the collector. At the same time, the NPN bipolar transistor is formed by the N+ region 128 as the emitter, the P-well 120 / P+ region 130 as the base and the body contact, and the N-well 115 / N+ region 122 as the collector. The NPN and PNP bipolar transistors share the N-well 115 / N+ region 122 and the P-well 120 / P+ region 130. In addition, the gate terminal (P-well 120) of the SCR is electrically connected with the cathode (N+ 128) to form a two-terminal SCR device. The composite circuit diagram of the cross-connected NPN and PNP bipolar transistors is shown in Figure 3 (b). The base of the PNP bipolar transistor is the collector of the NPN bipolar transistor, and the collector of the PNP bipolar transistor is the base of the NPN bipolar transistor.

[0084] In embodiments of the present application, the SCR device is constructed by interleaving the emitter (P+ region 124) and the base (N+ region 122) in the PNP bipolar transistor and interleaving the emitter (N+ region 128) and the base (P+ region 130) in the NPN bipolar transistor.

[0085] In embodiments of the present application, the TVS device includes a structure that enables the triggering voltage of the TVS device to be tuned to a desired voltage level while maintaining the low parasitic capacitance and high holding voltage characteristics of the TVS device. Returning to Figure 4 When the voltage applied to the protected node exceeds the triggering voltage, the N-well 115 to P-well 120 junction fails, and avalanche current flow causes one of the NPN or PNP bipolar transistors of the SCR device to turn on. In embodiments of the present application, the TVS device 100 includes a triggering voltage adjustment structure for adjusting or tuning the triggering voltage. More specifically, the TVS device 100 includes a heavily doped N+ region 126 formed in the current conduction region between the adjacent P-well 120 and N-well 115 as the triggering voltage adjustment structure. In the present embodiment, the N+ doped region 126 partially overlaps with the P-well 120 and extends into the N-type epitaxial layer 108 in the current conduction region between the P-well 120 and the N-well 115.

[0086] With the provided N+ doped region 126, the N- to P-well junction is broken at a lower voltage due to the N+ region 126 abutting the P-well 120. Thus, by providing the N+ doped region 126, the trigger voltage of the TVS device 100 can be reduced. In some embodiments, the trigger voltage of the TVS device can be tuned to a desired level by adjusting the doping levels of the N+ region 126 and the P-well 120.

[0087] In the present embodiment, as shown in the layout diagram in Figure 4 The N+ doped region 126 is configured as a rectangle in the present embodiment. In alternative embodiments, the N+ doped region 126 can be configured in other shapes suitable for tuning the trigger voltage of the TVS device. In other embodiments, two or more N+ doped regions 126 can be provided along the current conduction region (i.e. in the Z direction in Figure 8 The N+ doped region 126 is optional and can be omitted in other embodiments of the present application.

[0088] Figure 9 A layout diagram of an SCR device in a TVS protection device in an alternative embodiment of the present application is shown. Figure 8 A cross-sectional view of the TVS protection device along line C-C' in an embodiment of the present application is shown. Figure 8 A cross-sectional view of the TVS protection device along line C-C' in an embodiment of the present application is shown. Figure 9 Similar elements and reference numbers are given in Figure 8 and previous figures. Reference is made to Figure 9 and Figure 9 The TVS device 200 is formed using an SCR clamp device 255 with a modified base body contact region in the present embodiment. The SCR clamp device 255 includes a heavily doped P+ region 270 formed in the P-well 120, which is configured to interleave and surround N+ regions 228 also formed in the P-well 120 in the present embodiment. As shown in Figure 9 The P+ region 270 includes portions 230 interleaved with the N+ regions 228 in the second (Z) direction. The P+ region 270 also includes portions 231a and 231b formed in the second (Z) direction extending along two opposite sides of the N+ regions 228 without contacting the P+ portions 230. With such a configuration, the P+ region 270 is formed along the perimeter of the N+ regions 228 and surrounds all of the N+ regions 228.

[0089] A corresponding structure of N+ regions in the N-well 115 is formed. The SCR clamp device 255 includes a heavily doped N+ region 280 formed in the N-well 115, which is configured to interleave and surround P+ regions 224 also formed in the N-well 115 in the present embodiment. As shown in Figure 9As shown, the N+ region 280 includes portions 222 interleaved with the P+ regions 224 in the second (Z) direction. The N+ region 280 also includes portions 223a and 223b formed in the second (Z) direction and along two opposite sides of the P+ regions 224 that are not in contact with the N+ portions 222. With such a configuration, the N+ region 280 is formed along the perimeter of the P+ regions 224 and encloses all of the P+ regions 224.

[0090] Figure 9 A cross-sectional view of the SCR 255 shows the P+ regions 270 and the N+ regions 280 along the C-C' line. As shown, the N+ regions 228 in the P-well 120 are adjacent to the P+ portions 231a and 231b. Meanwhile, the P+ regions 224 in the N-well 115 are adjacent to the N+ portions 223a and 223b. With such a configuration, the P+ regions 270 and the N+ regions 280 are used to enclose the respective emitter regions of the SCR device, making it more difficult to turn on the SCR device, thereby increasing the holding voltage of the SCR. Figure 3

[0091] Returning to Figure 4 and Figure 4 , the SCR device in the TVS device constructed in accordance with the present invention can achieve a higher holding voltage than a conventional SCR device. Specifically, by adjusting various parameters of the SCR device, the holding voltage in the SCR device of the present invention can be tuned to any desired voltage.

[0092] First, the holding voltage of the SCR device can be adjusted by adjusting the length and width of the emitter regions and the base body contact regions. That is, the length and / or width of the interleaved emitter / base body contact regions can be adjusted to achieve a desired holding voltage. Referring to Figure 8 In some embodiments, the width of the N+ regions 128, 122 or the width of the P+ regions 130, 124 measured in the second (Z) direction can be adjusted to tune the holding voltage. In another embodiment, the length of the N+ regions 128, 122 or the length of the P+ regions 130, 124 measured in the first (X) direction can be adjusted to tune the holding voltage.

[0093] Specifically, in some embodiments, the length of the emitter regions (N+ regions 128 and P+ regions 124) can be shorter than the length of the base body contact regions (P+ regions 130 and N+ regions 122) to tune the holding voltage. Such a configuration will increase the holding voltage with a decrease in the emitter area. Figure 8 An example embodiment is shown in which the emitter regions (N+ regions 228 and P+ regions 224) are configured to have a shorter length (in the X direction) than the base contact regions (P+ portions 230 and N+ portions 222).​

[0094] Finally, as shown in Figure 10 by forming a base body contact region ring around the emitter region, the base current of the NPN / PNP bipolar transistor in the SCR is interrupted, which also increases the holding voltage of the thyristor.

[0095] In the above embodiment, the P-well 120 and N-well 115 in the SCR device are formed spaced apart in the N-type epitaxial layer 108 in the first (X) direction. Separating the P-well and N-well has the advantage of reducing the capacitance of the SCR device, thereby reducing the capacitance of the TVS device in the blocking mode. In another embodiment of the present application, the N-well 115 and P-well 120 in the SCR device can be formed abutting or close to each other, since the SCR device is in series with a low capacitance high-side turn-off diode, so the capacitance is not as important.

[0096] Figure 10 comprising Figure 10 (a) and 10(b) represent a circuit diagram and a cross-sectional view of a TVS protection device in an alternative embodiment of the present application. In particular, Figure 10 represent a cross-sectional view of a high-side turn-off diode ("HS diode") and SCR clamp device incorporated in a TVS protection device in an embodiment of the present application. In this figure, the low-side turn-off diode is omitted for simplicity of discussion. It should be understood that, Figure 10 only a portion of the TVS protection device is shown, and the TVS protection device includes other elements not shown in the cross-sectional view of Figure 10 .

[0097] In the above embodiment, the high-side turn-off diode and the SCR clamp device are formed as separate devices in separate active regions. In this embodiment, the high-side turn-off diode and the SCR clamp device are integrated together and formed in a single active region, so as to achieve a compact device layout and allow the TVS device to fit into a small package footprint. Figure 10 (a) represents a circuit diagram of a TVS protection device containing an integrated high-side diode and SCR clamp device in an embodiment of the present application. Reference is made to Figure 10(a), the TVS protection device 300 ("TVS device 300") includes two sets of coupled steering diodes to provide surge protection for two input-output (I / O) terminals I / O1 and I / O2. Each set of steering diodes includes a low-side steering diode and an integrated high-side diode and SCR clamp device. More specifically, low-side steering diode DL1 and integrated high-side diode / SCR MDH1 are connected in parallel between I / O terminal I / O1 (node 352) (the protected node) and node 355, and low-side steering diode DL2 and integrated high-side diode / SCR MDH2 are connected in parallel between I / O terminal I / O2 (node 354) (the protected node) and node 355. In this embodiment, node 355 is connected to ground voltage, and the TVS device 300 is a unidirectional TVS device. In other embodiments, node 355 can be left floating to form a bidirectional TVS device.

[0098] More specifically, I / O terminal I / O1 is connected to the anode of integrated high-side diode / SCR MDH1 and the cathode of low-side steering diode DL1. Similarly, I / O terminal I / O2 is connected to the anode of integrated high-side diode / SCR MDH2 and the cathode of low-side steering diode DL2. The cathode terminal of integrated high-side diode / SCR MDH1 is connected to node 355, which is also connected to the cathode of integrated high-side diode / SCR MDH2. The anode terminals of low-side steering diodes DL1 and DL2 are both connected to node 355.

[0099] Reference is made to Figure 10 An integrated high-side diode and SCR clamp device 360 ("integrated HS diode / SCR device") is formed in an active region of the semiconductor structure formed by P+ substrate 302, P-type epitaxial layer 304, N-type buried layer 306, and N-type epitaxial layer 308. The active region is isolated from other active regions on the semiconductor structure by isolation structure 340. In this embodiment, isolation structure 340 is formed as an oxide-lined trench filled with a polysilicon layer 342, and the trench extends to P+ substrate 302. In other embodiments, trench isolation structure 340 can be formed as an oxide-filled trench.

[0100] The integrated HS diode / SCR device 360 ​​includes a heavily doped P+ region 310 formed in an N-type epitaxial layer 308. The P+ region 310 forms the anode of the high-voltage side-biased diode and also serves as the anode of the SCR device. The integrated HS diode / SCR device 360 ​​includes a P-well 320 formed in a deep N-well (DNW) 370, both spaced apart from the P+ region 310 in the semiconductor structure in a first direction (X direction). Heavily doped N+ regions 328 and heavily doped P+ regions 330 are formed in the P-well 320. Specifically, the N+ regions 328 and P+ regions 330 are arranged as alternating doped regions in a second direction (Z direction) on the main surface of the semiconductor structure. Figure 11 In the diagram, N+ region 328 and P+ region 330 are represented by alternating doped regions in the Z direction of a cross-sectional view of the XY plane using black and gray ink. In the integrated structure, the SCR only includes the alternating emitter and base regions of the NPN bipolar transistor with a PNPN structure.

[0101] In the integrated HS diode / SCR device 360, the NPN bipolar transistor of the SCR device is formed by an N+ region 328 as the emitter, a P-well, and a base (with a P+ region 330 as the base body contact), and an N-type epitaxial layer 308 as the collector. The PNP bipolar transistor of the SCR device is formed by a P+ region 310 as the emitter, an N-type epitaxial layer 308 as the base, and a P-well 320 as the collector. In the integrated HS diode / SCR device 360, a deep N-well 370 is provided to prevent the PNP bipolar transistor of the SCR device from punching through. Specifically, because the N-type epitaxial layer 308 is lightly doped, during operation, the depletion region at the junction of the P+ region 310 and the N-type epitaxial layer 308 will extend to the lightly doped side, i.e., the N-Epi layer. If the depletion region is allowed to extend all the way to the P-well 320, punch-through of the PNP bipolar transistor will occur, and the PNP transistor will no longer be able to provide blocking functionality. In this embodiment, a deep N-well 370 is formed at the same location as the P-well 320. The deep N-well 370 extends out of the P-well 320 into the N-type epitaxial layer 308, thereby surrounding the P-well 320. The deep N-well 370 functions as a depletion stop region originating from the junction at the P+ region 310 and N-Epi 308. In one embodiment, the deep N-well 370 is more heavily doped than the N-type epitaxial layer 308, and the P-well 320 is more heavily doped than the deep N-well 370.

[0102] In the present embodiment, the integrated HS diode / SCR device 360 also includes a heavily doped N+ region 326 as a trigger voltage adjustment structure for tuning the trigger voltage of the TVS device. In some embodiments, the N+ region 326 is placed near the P well 320 and can overlap the P well 320. In the present embodiment, the N+ region 326 is formed at least partially in the deep N well 370. The N+ doped region 326 is optional and can be omitted in other embodiments of the present application.

[0103] Figure 10 illustrates that in some embodiments, Figure 11 a layout view of an integrated HS diode / SCR device in a TVS protection device. Figure 10 illustrates the integrated HS diode / SCR device from a third perspective and illustrates the structure in the X-Z plane. For simplicity of discussion, Figure 11 and Figure 12 similar elements in Figure 11 illustrates that in embodiments of the present application, Figure 13 a cross-sectional view of the TVS protection device along line D-D'. Figure 11 illustrates that in embodiments of the present application, Figure 11 a cross-sectional view of the TVS protection device along line E-E'.

[0104] Reference is first made to Figure 12 The integrated HS diode / SCR device 360 includes a P+ region 310 as the anode of the high voltage side steering diode and the SCR device. Alternating P+ regions 330 and N+ regions 328 are formed in a P well 320, which is formed in a deep N well 370. As Figure 13 illustrated along line D-D', the integrated HS diode / SCR device 360 includes N+ regions 328 formed in the P well 320. As Figure 14 illustrated along line E-E', the integrated HS diode / SCR device 360 includes P+ regions 330 formed in the P well 320. With such a configuration, a compact layout of the integrated HS diode / SCR device 360 is achieved.

[0105] Figure 15 illustrates a layout view of an integrated HS diode / SCR device in a TVS protection device in an optional embodiment of the present application. Figure 14 illustrates that in embodiments of the present application, Figure 14 a cross-sectional view of the TVS protection device along line F-F'. Reference is made to Figure 15 and Figure 8 The integrated HS diode / SCR device 460 is similar to Figure 14The SCR device in the middle is constructed in a similar way, using an improved base body contact region, in which the base body contact region surrounds the emitter region to form an alternating emitter region and base region.

[0106] In this embodiment, the integrated HS diode / SCR device 460 includes a heavily doped P+ region 475 formed in a P-well 320, which is configured to interleave and surround N+ regions 428, which are also formed in the P-well 320. Figure 15 As shown, the P+ region 475 includes a portion 430 that intersects with the N+ region 428 in the second (Z) direction. The P+ region 475 also includes portions 431a and 431b that extend in the second (Z) direction and are formed along two opposite sides of the N+ region 428 that do not contact the P+ portion 430. With this configuration, the P+ region 475 is formed along the perimeter of the N+ region 428 and surrounds all of the N+ regions 428.

[0107] Figure 15 The cross-sectional view of the integrated HS diode / SCR device 460 shown indicates the P+ region 475 and N+ region 428 along the F-F' line. (As shown...) Figure 11 As shown, the N+ region 428 in the P-well 320 is adjacent to the P+ portions 431a and 431b. By using the P+ region 475 to surround the emitter region (N+ region 428) of the SCR device, the holding voltage of the SCR is increased by making the SCR device more difficult to turn on.

[0108] exist Figure 16 and 14 In the illustrated embodiment, the P+ region 310 is formed as a single doped region extending in the Z direction, that is, extending to the entire width of the integrated HS diode / SCR device. In other embodiments, the P+ region 310 may be configured in other ways. Figure 10 In an optional embodiment of the present invention, Figure 14 The diagram shows the layout of the SCR device within a TVS protection system. For the sake of simplicity, Figure 16 and Figure 16 Similar elements in the reference list are given similar reference numbers. Figure 16 The integrated HS diode / SCR device 560 includes a heavily doped P+ region 510 formed from a plurality of P+ regions 511 formed along a second (Z) direction. Each P+ region 511 has a contact 546 formed thereon for electrical contact with the P+ region. A conductive layer, such as a metal wire 547, can be used to electrically connect the contacts 546 of all the P+ regions 511 together. In some embodiments, Figure 11 The configuration of P+ region 511 in the text can also be applied to ​ The example shown.

[0109] The application can be implemented in numerous ways, including as a process, an apparatus, a system, and / or a composition of matter. Generally, the application(s) described herein can be implemented as a process, an apparatus, a system, a composition of matter, a computer program product, or a processor, among other possibilities. It is contemplated that the application(s) can be implemented in a variety of ways, including as an apparatus (which can be further divided into sub-apparatuses), a method (which can be further divided into sub-methods), or a computer program product (which can be further divided into computer program sub-products). Furthermore, the application(s) can take the form of a computer program product on a computer- readable storage medium having computer readable program code embodied in the medium.

[0110] A detailed description of one or more embodiments of the application is provided below along with accompanying figures that illustrate the principles of the application. The application is described in connection with such embodiments, but the application is not limited to any embodiment. The scope of the application is limited only by the claims and the application encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the application. These details are provided for the purpose of example and the application can be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the application has not been described in detail so that the application is not unnecessarily obscured.

[0111] The detailed description provided above is for the purpose of illustrating the application, but not for the purpose of limiting the same. Many modifications and variations of the application can be apparent to those of ordinary skill in the art without departing from the scope of the application. The scope of the application is defined by the appended claims.

Claims

1. A transient voltage suppression (TVS) device, characterized by, comprises: a semiconductor layer comprising a first epitaxial layer of a first conductivity type; a plurality of active regions formed in the semiconductor layer, the active regions being separated from each other by isolation structures; a high-side turn-off diode formed in a first active region, the high-side turn-off diode having an anode terminal coupled to a first protected node and a cathode terminal; and a clamping device formed in a second active region of the plurality of active regions, the clamping device comprising a silicon controlled rectifier (SCR) comprising an anode terminal coupled to the cathode terminal of the high-side turn-off diode and a cathode terminal, the silicon controlled rectifier comprising: a first well of the first conductivity type formed in the first epitaxial layer; a second well of a second conductivity type formed in the first epitaxial layer on a main surface of the semiconductor layer, the second well being adjacent and spaced apart from the first well in a first direction, the second conductivity type being opposite to the first conductivity type, for reducing a capacitance of the SCR device; a first region of the first conductivity type and a second region of the second conductivity type formed in the first well and being heavily doped, the first and second regions being electrically connected and forming the anode terminal of the SCR; and a third region of the first conductivity type and a fourth region of the second conductivity type formed in the second well and being heavily doped, the third and fourth regions being electrically connected and forming the cathode terminal of the SCR, wherein the first and second regions are arranged as alternating doped regions in the first well along a second direction orthogonal to the first direction on the main surface of the semiconductor layer, and the third and fourth regions are arranged as alternating doped regions in the second well along the second direction, the third region being arranged co-planar with the second region in the second direction, and the fourth region being arranged co-planar with the first region in the second direction; wherein the second region and the third region are emitter regions, the first region and the fourth region are base body contact regions, the alternating emitter and base body contact regions form PNP and NPN bipolar transistors of a PNPN structure of the SCR, and a ring of the base body contact regions is formed around the emitter regions, such that a base current of the NPN / PNP bipolar transistors in the SCR is interrupted.

2. The TVS device of claim 1, wherein, further comprising a low-side turn-off diode formed in a third active region of the plurality of active regions, the low-side turn-off diode having a cathode terminal coupled to the first protected node and an anode terminal coupled to the cathode terminal of the SCR.

3. The TVS device of claim 2, wherein, the high-side turn-off diode comprises a PN junction diode, and the low-side turn-off diode comprises a punch-through silicon controlled rectifier.

4. The TVS device of claim 1, wherein, further comprising a fifth region of the first conductivity type formed in the first epitaxial layer and overlapping the second well, the fifth region being heavily doped.

5. The TVS device of claim 1, wherein, the first and second regions in the first well are electrically connected by a first junction, and the third and fourth regions in the second well are electrically connected by a second junction.

6. The TVS device of claim 1, wherein, the semiconductor layer further comprises a second epitaxial layer of a second conductivity type formed on a second epitaxial layer, and a first buried layer of the first conductivity type, wherein the first epitaxial layer is formed on the first buried layer.

7. The TVS device of claim 6, wherein, The isolation structures include a plurality of trench isolation structures isolating the first active regions, each trench isolation structure extending from the first epitaxial layer to the second epitaxial layer.

8. The TVS device of claim 1, wherein, The high-side turn-off diode includes a PN junction diode including: a sixth region of a second conductivity type formed in the first active region of the first epitaxial layer; and a seventh region of a first conductivity type formed in the first epitaxial layer spaced apart from the sixth region.

9. The TVS device of claim 1, wherein, The first conductivity type includes N-type conduction and the second conductivity type includes P-type conduction.

10. The TVS device of claim 1, wherein, Further comprising: eighth and ninth regions of the first conductivity type formed in the first well and extending adjacent to alternating first and second regions in the second direction, the second regions being surrounded in the first and second directions by the first regions, the eighth region, and the ninth region; and tenth and eleventh regions of the second conductivity type formed in the second well and extending adjacent to alternating third and fourth regions in the second direction, the third regions being surrounded in the first and second directions by the fourth regions, the tenth region, and the eleventh region.

11. The TVS device as claimed in claim 1, characterized in that, The cathode terminal of the SCR is conductively coupled to a ground voltage.

12. The TVS device of claim 1, wherein, The second regions have a length in the first direction that is shorter than a length of the first regions, and the third regions have a length in the first direction that is shorter than a length of the fourth regions.

13. The TVS device of claim 1, wherein, The first regions and the third regions can have widths in the second direction that are adjusted to adjust a holding voltage, or the second regions and the fourth regions can have widths in the second direction that are adjusted to adjust a holding voltage.

14. A transient voltage suppression (TVS) device comprising: Comprising: a semiconductor layer including a first epitaxial layer of a first conductivity type; a plurality of active regions formed in the semiconductor layer, the active regions being isolated from one another by isolation structures; a merged diode / clamp device formed in a first active region of the plurality of active regions, the merged diode / clamp device including a high-side turn-off diode integrated with a silicon controlled rectifier (SCR), the merged diode / clamp device including: a first region of a second conductivity type opposite the first conductivity type, the first region being formed in the first epitaxial layer and being heavily doped, the first region constituting an anode terminal of the high-side turn-off diode and an anode terminal of the SCR, the first region being coupled to a first protected node; a first well of the first conductivity type formed in the first epitaxial layer and spaced apart from the first region in a first direction along a major surface of the semiconductor layer; a second well of the second conductivity type formed in the first well; a second region of the first conductivity type, and a third region of the second conductivity type formed in the second well and being heavily doped, the second and third regions being conductively coupled and forming a cathode terminal of the SCR, wherein the second and third regions are arranged as alternating doped regions in the second direction along the major surface of the semiconductor layer and in the second well orthogonal to the first direction.

15. The TVS device of claim 14, wherein, Further comprising a low-side turn-off diode formed in a second active region of the plurality of active regions, the low-side turn-off diode having a cathode terminal coupled to the first protected node and an anode terminal coupled to the cathode terminal of the SCR.

16. The TVS device of claim 15, wherein, The low-side turn-off diode includes a punch-through thyristor.

17. The TVS device of claim 14, wherein, A fourth region of the first conductivity type is also included formed in the first epitaxial layer and adjacent the second well, the fourth region being heavily doped.

18. The TVS device of claim 14, wherein, The first region is coupled to a first contact, and the second and third regions in the second well are electrically connected by a second contact.

19. The TVS device of claim 14, wherein, The semiconductor layer further includes a second epitaxial layer of a second conductivity type formed on a second epitaxial layer and a first buried layer of the first conductivity type, wherein the first epitaxial layer is formed on the first buried layer.

20. The TVS device of claim 14, wherein, The isolation structure includes a plurality of trench isolation structures isolating the first active region, each trench isolation structure extending from the first epitaxial layer to the second epitaxial layer.

21. The TVS device of claim 14, wherein, The first conductivity type includes N-type conduction, and the second conductivity type includes P-type conduction.

22. The TVS device of claim 14, wherein, A fifth and sixth region of the second conductivity type are also included, the fifth and sixth regions being formed in the second well and extending adjacent the alternating second and third regions in the second direction, the second region being surrounded in the first and second directions by the third region, the fifth region, and the sixth region.

23. The TVS device of claim 14, wherein, The first region includes a plurality of regions of the second conductivity type formed along the second direction, each region of the second conductivity type being coupled to a respective contact.

24. The TVS device of claim 14, wherein, The first region is a single doped region of the second conductivity type extending along the second direction, the first region extending to an entire width of the merged diode / clamp device.

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