Array substrate, preparation method of array substrate and display panel
By employing an NPN or PNP semiconductor structure driving transistor layer in the array substrate, combined with solution processing methods, the problems of high power consumption and high leakage current of thin-film driving transistors are solved, achieving low power consumption and high display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2022-03-22
- Publication Date
- 2026-07-03
Smart Images
Figure CN114695392B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display, and more particularly to an array substrate, a method for fabricating the array substrate, and a display panel. Background Technology
[0002] Thin-film transistors (TFTs), as semiconductor switching devices, can control the conduction and cutoff of the active layer by inputting different electrical signals to the gate, and are therefore widely used in the semiconductor display field. The structure of a TFT includes: a gate, a gate insulating layer, an active layer, source and drain electrodes, and a protective layer. Currently, most TFTs are driven by unipolar N-type or P-type semiconductors. N-type semiconductor materials mainly include inorganic semiconductor materials such as amorphous silicon, oxides, and low-temperature polycrystalline silicon. Metal oxide TFTs are typically N-type semiconductors and rarely exhibit P-type performance. Compared to inorganic semiconductor materials, organic semiconductor materials often exhibit better P-type performance and poorer N-type performance. Unipolar N-type or P-type semiconductor drives have higher power consumption, more complex manufacturing processes, and higher off-state leakage current. Summary of the Invention
[0003] In view of this, this application provides an array substrate and display panel that can reduce the power consumption and off-state leakage current of the driving transistors.
[0004] This application also provides a method for preparing an array substrate that can optimize the array substrate fabrication process.
[0005] To solve the above problems, the technical solution provided in this application is as follows:
[0006] In a first aspect, this application provides an array substrate, including a substrate and a driving transistor layer formed on the substrate; the driving transistor layer includes at least one driving transistor, each of the driving transistors comprising:
[0007] Gate;
[0008] An active layer, located opposite the gate, comprises a first semiconductor and two second semiconductors, the two second semiconductors being formed on the first semiconductor.
[0009] Two second semiconductors are formed at opposite ends of the first semiconductor and are respectively in contact with the first semiconductor to form a first PN junction and a second PN junction, wherein the first PN junction and the second PN junction have opposite conduction directions; and
[0010] The source-drain layer is located opposite to the active layer. The source-drain layer includes a source and a drain. The source is connected to a second semiconductor at the location of the first PN junction, and the drain is connected to a second semiconductor at the location of the second PN junction.
[0011] In an optional embodiment of this application, the active layer is an NPN semiconductor, the second semiconductor is an N-type semiconductor, and the first semiconductor is a P-type semiconductor.
[0012] In an optional embodiment of this application, the active layer is a PNP type semiconductor, the first semiconductor is an N type semiconductor, and the second semiconductor is a P type semiconductor.
[0013] In an optional embodiment of this application, the material of the N-type semiconductor is an N-type inorganic semiconductor material, and the material of the P-type semiconductor is a P-type organic semiconductor material.
[0014] In an optional embodiment of this application, the first semiconductor includes a channel region, and the orthographic projections of the two second semiconductors on the substrate are located on both sides of the orthographic projection of the channel region on the substrate.
[0015] In an optional embodiment of this application, the first semiconductor includes two end faces and a first surface connected to the end faces. The first surface is away from the substrate. The two end faces are located at opposite ends of the first surface. A second semiconductor is attached to a corresponding end face and / or the first surface.
[0016] In an optional embodiment of this application, the driving transistor further includes a gate insulating layer, a first protective layer, and a second protective layer. The gate insulating layer is formed on the substrate and covers the gate, the active layer is formed on the gate insulating layer, the first protective layer covers the active layer and is formed on the gate insulating layer, and the second protective layer covers the source and drain layers.
[0017] A second aspect of this application provides a method for fabricating an array substrate, comprising:
[0018] Provide a substrate; and
[0019] A gate is formed on the substrate, and a gate insulating layer is formed on the gate and the substrate.
[0020] A first semiconductor is formed on the gate insulating layer;
[0021] A second semiconductor is formed at each of the opposite ends of the first semiconductor, and the two second semiconductors are respectively in contact with the two ends of the first semiconductor to form an active layer; the first semiconductor layer is one of N-type and P-type semiconductors, and the second semiconductor layer is the other of P-type and N-type semiconductors;
[0022] A first protective layer is formed on the active layer and the gate insulating layer;
[0023] A source-drain layer is formed on the first protective layer, the source-drain layer including a source and a drain, and the source and the drain are respectively electrically connected to two second semiconductors; and
[0024] A second protective layer is formed on the source / drain layer and the first protective layer.
[0025] In an optional embodiment of this application, the first semiconductor and / or the second semiconductor are formed by vapor deposition or solution coating.
[0026] A third aspect of this application provides a display panel, including an array substrate and a pair of opposing substrates as described above, wherein the array substrate and the array substrate are disposed at a distance from each other.
[0027] The array substrate and display panel provided in this application include an active layer of driving transistors in the array substrate comprising a first semiconductor and two second semiconductors. The two second semiconductors are formed at one end of the first semiconductor and are in contact with the first semiconductor. The two second semiconductors are electrically connected to the source and the drain, respectively. A first PN junction and a second PN junction with opposite conduction directions are formed between the two second semiconductors and the first semiconductor, respectively. The first PN junction corresponds to the source, and the second PN junction corresponds to the drain.
[0028] When the active layer is an NPN structure (the first semiconductor is a P-type semiconductor, and the second semiconductor is an N-type semiconductor), after a positive voltage is applied to the gate, the first PN junction near the source opens. Because the electron concentration in the first semiconductor (P-type semiconductor) continuously increases, it overcomes the potential barrier formed by the second PN junction near the drain, resulting in a stable on-state current. When a negative voltage is applied to the gate, the hole concentration in the first semiconductor (P-type semiconductor) increases, and the electron concentration decreases. The first PN junction near the source opens, and the second PN junction near the drain, due to its high potential barrier, prevents electrons from passing through. No current is transmitted in the channel region, and the source and drain are disconnected. This essentially eliminates leakage current, improving the display effect of the display panel and reducing the power consumption of the driving transistors.
[0029] When the active layer is a PNP type structure (the first semiconductor is an N-type semiconductor, and the second semiconductor is a P-type semiconductor), after a positive voltage is applied to the gate, the first PN junction near the source is initially in a closed state. However, after a certain current is applied to the source, electrons continuously accumulate towards the second semiconductor (P-type semiconductor) corresponding to the source, and the electron concentration continuously increases. Overcoming the potential barrier formed by the second PN junction, they migrate into the second semiconductor (N-type semiconductor). At this time, the second PN junction opens, forming a stable on-state current. When a negative voltage is applied to the gate, the reverse electric field hinders the current applied to the source from entering the second semiconductor (P-type semiconductor). The hole concentration in the second semiconductor (P-type semiconductor) increases, and the electron concentration is low, making it more difficult for electrons to jump across the first PN junction near the source. No current is transmitted in the channel, and the driving transistor is in a closed state. This reduces leakage current formation, improves the display effect of the display device, and reduces the power consumption of the driving transistor.
[0030] In addition, the array substrate fabrication method provided in this application can be used to prepare both the second semiconductor and the first semiconductor of the active layer by solution processing. Compared with particle doping methods or physical vapor deposition or chemical vapor deposition film formation processes, the fabrication method is simple and can optimize the fabrication process of the array substrate. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of a display panel provided in a preferred embodiment of this application.
[0033] Figure 2 This is a top view of an array substrate provided in the first embodiment of this application.
[0034] Figure 3 For along Figure 2 A sectional view showing the section lines.
[0035] Figure 4 This is a cross-sectional view of the array substrate provided in the second embodiment of this application.
[0036] Figure 5 This is a cross-sectional view of the array substrate provided in the third embodiment of this application.
[0037] Figure 6 This is a flowchart of a method for fabricating an array substrate according to a preferred embodiment of the present application. Detailed Implementation
[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0039] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0040] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.
[0041] The array substrate, the method for fabricating the array substrate, and the display panel provided in this application will be described in detail below with reference to specific embodiments and accompanying drawings.
[0042] Please see Figure 1-2 This application provides a display panel 1000, which can be a liquid crystal display panel, OLED display panel, Micro-LED display panel, mini-LED display panel, electronic paper, etc. The display panel 1000 includes an array substrate and a counter substrate, the array substrate being disposed opposite to each other at a distance. When the display panel 1000 is a liquid crystal display panel or electronic paper, the counter substrate is a color filter substrate; when the display panel 1000 is an OLED display panel, Micro-LED display panel, mini-LED display panel, etc., the counter substrate can be a cover plate.
[0043] Specifically, please refer to Figure 1In an optional embodiment of this application, the display panel 1000 is a liquid crystal display panel. The display panel 1000 includes an array substrate 100, a liquid crystal 300, and a color filter substrate 200. The array substrate 100 and the color filter substrate 200 are disposed opposite to each other, and the liquid crystal 300 is located between the array substrate 100 and the color filter substrate 200. Since the liquid crystal 300 and the color filter substrate 200 are both well-known structures in the industry, they will not be described in detail here. That is, the array substrate 100 can be used in a liquid crystal display panel.
[0044] Specifically, in other embodiments, the display panel 1000 can also be an OLED display panel, a Micro-LED display panel, a mini-LED display panel, electronic paper, etc. The display panel 1000 includes an array substrate 100, light-emitting units (not shown), and an encapsulation layer (not shown). The light-emitting units are formed on and electrically connected to the array substrate 100, and the encapsulation layer covers the light-emitting units. Since the light-emitting units and encapsulation layer are well-known structures in the industry, they will not be described in detail here. That is, the array substrate 100 can be applied to display devices such as OLED display panels, Micro-LED display panels, mini-LED display panels, and electronic paper.
[0045] In an optional embodiment of this application, the array substrate 100 can also be used in driving solar cells, etc.
[0046] For details, please continue to refer to Figures 2-6 This is to illustrate the specific structure of the array substrate 100 provided in this application.
[0047] Please continue to refer to this. Figures 2-3 The array substrate 100 includes a substrate 110 and a driving transistor layer 120 formed on the substrate 110. The driving transistor layer 120 includes at least one driving transistor 130. Each driving transistor 130 includes a gate 20, an active layer 30, and a source-drain layer 40. The active layer 30 is positioned opposite to the gate 20, and the source-drain layer 40 is positioned opposite to the active layer 30. The source-drain layer 40 includes a source 42 and a drain 41.
[0048] In an optional embodiment of this application, the driving transistor 130 further includes a first protective layer 60 and a second protective layer 70, wherein the first protective layer 60 covers the active layer 30 and the second protective layer 70 covers the source-drain layer 40. The first protective layer 60 is also formed on the gate insulating layer 50.
[0049] The first protective layer 60 is used to protect the active layer 30, and the second protective layer 70 is used to protect the source-drain layer 40. The first protective layer 60 may be an interlayer insulating layer, and the second protective layer may be a passivation layer and / or a planarization layer.
[0050] Specifically, please refer to Figure 2 In this embodiment, the driving transistor 130 has a bottom gate structure, the gate 20 is formed on the substrate 110, and the active layer 30 is located on the side of the gate 20 away from the substrate 110 and between the gate 20 and the source-drain layer 40.
[0051] In another optional embodiment of this application, the driving transistor 130 may also be a top-gate structure, with the active layer 30 formed above the substrate 110, and the gate 20 formed between the active layer 30 and the source-drain layer 40 and located on the side of the second semiconductor 32 of the active layer 30. Specifically, the gate 20 may be formed above the first protective layer 60, and the gate insulating layer 50 may be formed between the gate 20 and the source-drain layer 40.
[0052] In another optional embodiment of this application, the driving transistor 130 may further be a dual-gate structure, comprising two opposing first gates and a second gate. In one scenario, the active layer 30 is formed above the substrate 110, and the first gate and the second gate may be formed between the active layer 30 and the source / drain layer 40, and located on the side of the second semiconductor 32 of the active layer 30. Specifically, the first gate may be located on the side of the second semiconductor 32 of the active layer 30, and the second gate may be disposed adjacent to the source / drain layer 40. In another scenario, the first gate and... Figure 2 The second gate is located in the same position as the gate 20 in the active layer 30 and the source / drain layer 40, and is located on the side of the second semiconductor 32 in the active layer 30.
[0053] The active layer 30 includes a first semiconductor 31 and two second semiconductors 32. The two second semiconductors 32 are formed at opposite ends of the first semiconductor 31 and are in contact with the first semiconductor 31 to form a first PN junction 34 and a second PN junction 33, respectively. The conduction directions of the first PN junction 34 and the second PN junction 33 are opposite. Between the two second semiconductors 32 and the first semiconductor 31, the first PN junction 34 corresponds to the source 42, and the second PN junction 33 corresponds to the drain 41. The source 42 is connected to the second semiconductor 32 located at the location of the first PN junction 34, and the drain 41 is connected to the second semiconductor 32 located at the location of the second PN junction 33.
[0054] In an optional embodiment of this application, the first semiconductor 31 includes a channel region 311, and the orthographic projections of the two second semiconductors 32 on the substrate 110 are located on both sides of the orthographic projection of the channel region 311 on the substrate 110.
[0055] The first semiconductor 31 further includes two end faces 312 and a first surface 313. The first surface 313 is connected to the two end faces 312. The two end faces 312 are located at opposite ends of the first surface 313. The first surface 313 is away from the substrate 110.
[0056] In an optional embodiment of this application, a second semiconductor 32 is attached to a corresponding end face 312 and a portion of the first surface 313.
[0057] In an optional embodiment of this application, the active layer 30 is an NPN type structure, the second semiconductor 32 is an N-type semiconductor, and the first semiconductor 31 is a P-type semiconductor.
[0058] In another embodiment of this application, the active layer 30 is a PNP type structure, the second semiconductor 32 is a P-type semiconductor, and the first semiconductor 31 is an N-type semiconductor.
[0059] In an optional embodiment of this application, the material of the N-type semiconductor is an N-type inorganic semiconductor material, and the material of the P-type semiconductor layer is a P-type organic semiconductor material.
[0060] The N-type inorganic semiconductor material can be an oxide semiconductor material such as zinc oxide, zinc tin oxide, titanium oxide, molybdenum oxide, or nickel oxide, or at least one of cadmium selenide, graphene, fullerene, or substituted fullerene. In this embodiment, the N-type inorganic semiconductor material is a semiconductor material composed of a mixture of indium oxide, gallium oxide, and zinc oxide in a specific ratio.
[0061] Among them, the P-type organic semiconductor material is at least one of conjugated aryl compounds, conjugated heteroaryl compounds, etc.
[0062] When the active layer is an NPN structure, after a positive voltage is applied to the gate 20, the first PN junction 34 near the source 42 opens. Because the electron concentration in the first semiconductor 31 (P-type semiconductor) continuously increases, it overcomes the potential barrier formed by the second PN junction 33 near the drain 41, resulting in a stable on-state current. After a negative voltage is applied to the gate 20, the hole concentration in the first semiconductor 31 (P-type semiconductor) increases, and the electron concentration decreases. The first PN junction 34 near the source 42 opens, and the second PN junction 33 near the drain 41, due to its high potential barrier, prevents electrons from passing through. No current is transmitted in the channel region 311, and the driving transistor 130 is in the off state. This essentially eliminates leakage current, improving the display effect of the display panel 1000 and reducing the power consumption of the driving transistor 130.
[0063] When the active layer 30 is a PNP type structure, after a positive voltage is applied to the gate 20, the first PN junction 34 near the source 42 is originally in a closed state. However, after a certain current is applied to the source 42, electrons continuously accumulate in the second semiconductor 32 (P-type semiconductor) corresponding to the source 42, and the electron concentration continuously increases. They overcome the potential barrier formed by the second PN junction 33 near the drain 41 and migrate in the second semiconductor 32 (N-type semiconductor). At this time, the second PN junction 33 opens, forming a stable on-state current. When a negative voltage is applied to the gate 20, the reverse electric field hinders the current applied to the source 42 from entering the second semiconductor 32 (P-type semiconductor). The hole concentration in the second semiconductor 32 (P-type semiconductor) increases, and the electron concentration is low, making it more difficult for electrons to jump over the first PN junction 34 near the source 42. No current is transmitted in the channel region 311, and the driving transistor 130 is in a closed state. This reduces leakage current formation, improves the display effect of the display panel 1000, and reduces the power consumption of the driving transistor 130.
[0064] The second semiconductor 32 and the first semiconductor 31 of the active layer 30 can both be prepared by solution processing. Compared with particle doping methods or physical vapor deposition or chemical vapor deposition film formation processes, the preparation method is simple and can optimize the preparation process of the array substrate.
[0065] Wherein, when the first semiconductor 31 and / or the second semiconductor 32 are N-type semiconductors, the first semiconductor 31 or the second semiconductor 32 can be formed by vapor deposition or solution coating method; when the first semiconductor 31 and / or the second semiconductor 32 are P-type semiconductors, the first semiconductor 31 or the second semiconductor 32 can be formed by solution coating method; wherein, the solution coating method refers to making a solution from the material for making the first semiconductor 31 or the material for making the second semiconductor 32, and then coating the prepared solution onto the gate insulating layer 50 or the first semiconductor 31 to form the first semiconductor 31 or the second semiconductor 32.
[0066] In an optional embodiment of this application, the driving transistor 130 has a bottom-gate structure. The driving transistor 130 further includes a gate insulating layer 50, which is formed on the substrate 110 and covers the gate 20. The active layer 30 is formed on the gate insulating layer 50. The gate insulating layer 50 is used to insulate the gate 20 and the active layer 30.
[0067] The source electrode 42 is electrically connected to a second semiconductor 32 through a first via 44, and the drain electrode 41 is electrically connected to a second semiconductor 32 through a second via 43.
[0068] The driving transistor 130 further includes a scan line 21 and a data line 45. The scan line 21 extends along a first direction, and the data line 45 extends along a second direction, with the first direction perpendicular to the second direction. The scan line 21 is connected to the gate 20, and the data line 45 is electrically connected to the source 42.
[0069] Please see Figure 4 The second embodiment of this application also provides an array substrate 300, the structure of which is similar to that of the array substrate 100, except that two second semiconductors 32 of the array substrate 300 are formed at both ends of the first semiconductor 31 and are in contact with the two end faces 312. That is, one second semiconductor 32 of the array substrate 300 is only in contact with one corresponding end face 312 of the first surface 313.
[0070] In an optional embodiment of this application, the second semiconductor 32 protrudes from the first semiconductor 31.
[0071] Please see Figure 5The third embodiment of this application also provides an array substrate 400, the structure of which is similar to that of the array substrate 100, except that one of the second semiconductors 32 of the array substrate 400 is formed on the first surface 313, that is, one of the second semiconductors 32 of the array substrate 400 is only in contact with the first surface 313.
[0072] Please see Figure 2 and Figure 6 This application also provides a method for fabricating an array substrate, comprising the following steps:
[0073] S1: Provide a substrate 110; and
[0074] S2: A gate 20, a gate insulating layer 50, and a first semiconductor 31 are formed on the substrate 110; wherein, the gate insulating layer 50 covers the gate 20 and is located between the gate 20 and the first semiconductor 31;
[0075] S3: A second semiconductor 32 is formed at each of the opposite ends of the first semiconductor 31, and the two second semiconductors 32 are respectively in contact with the two ends of the first semiconductor 31 to form an active layer 30; the first semiconductor layer 31 is one of an N-type and a P-type semiconductor, and the second semiconductor layer 32 is the other of a P-type and an N-type semiconductor; and
[0076] S4: A source-drain layer 40 is formed on the active layer 30, and the source 42 and drain 41 of the source-drain layer 40 are electrically connected to the two second semiconductors 32 respectively.
[0077] Since the two second semiconductors 32 are in contact with the first semiconductor 31, a first PN junction 34 and a second PN junction 33 are formed between the two second semiconductors 32 and the first semiconductor 31, respectively. The first PN junction 34 corresponds to the source 42, and the second PN junction 33 corresponds to the drain 41. The conduction directions of the first PN junction 34 and the second PN junction 33 are opposite.
[0078] Wherein, when the first semiconductor 31 and / or the second semiconductor 32 are N-type semiconductors, the first semiconductor 31 or the second semiconductor 32 can be formed by vapor deposition or solution coating method; when the first semiconductor 31 and / or the second semiconductor 32 are P-type semiconductors, the first semiconductor 31 or the second semiconductor 32 can be formed by solution coating method; wherein, the solution coating method refers to making a solution from the material for making the first semiconductor 31 or the material for making the second semiconductor 32, and then coating the prepared solution onto the gate insulating layer 50 or the first semiconductor 31 to form the first semiconductor 31 or the second semiconductor 32.
[0079] The specific steps of S3 will be explained below, taking the driving transistor 130 as an example of a bottom-gate structure.
[0080] Specifically, S3 includes the following steps: First, the gate 20 is formed on the substrate 110; second, a gate insulating layer 50 covering the gate 20 is formed on the gate 20; third, a first semiconductor 31 is formed on the gate insulating layer 50 by solution coating, and a second semiconductor layer 32 is formed at each end of the first semiconductor 31 away from the gate insulating layer 50 by solution coating to obtain an active layer 30; then, a first protective layer 60 covering the active layer 30 is formed on the active layer 30, a source-drain layer 40 is formed on the first protective layer 60, and a second protective layer 70 is formed on the source-drain layer 40.
[0081] The array substrate and display panel provided in this application include an active layer of driving transistors in the array substrate comprising a first semiconductor and two second semiconductors. The two second semiconductors are formed at one end of the first semiconductor and are in contact with the first semiconductor. The two second semiconductors are electrically connected to the source and the drain, respectively. A first PN junction and a second PN junction with opposite conduction directions are formed between the two second semiconductors and the first semiconductor, respectively. The first PN junction corresponds to the source, and the second PN junction corresponds to the drain.
[0082] When the active layer is an NPN structure (the first semiconductor is a P-type semiconductor, and the second semiconductor is an N-type semiconductor), after a positive voltage is applied to the gate, the first PN junction near the source opens. Because the electron concentration in the first semiconductor (P-type semiconductor) continuously increases, it overcomes the potential barrier formed by the second PN junction near the drain, resulting in a stable on-state current. When a negative voltage is applied to the gate, the hole concentration in the first semiconductor (P-type semiconductor) increases, and the electron concentration decreases. The first PN junction near the source opens, and the second PN junction near the drain, due to its high potential barrier, prevents electrons from passing through. No current is transmitted in the channel region, and the source and drain are disconnected. This essentially eliminates leakage current, improving the display effect of the display panel and reducing the power consumption of the driving transistors.
[0083] When the active layer is a PNP type structure (the first semiconductor is an N-type semiconductor, and the second semiconductor is a P-type semiconductor), after a positive voltage is applied to the gate, the first PN junction near the source is initially in a closed state. However, after a certain current is applied to the source, electrons continuously accumulate towards the second semiconductor (P-type semiconductor) corresponding to the source, and the electron concentration continuously increases. Overcoming the potential barrier formed by the second PN junction, they migrate into the second semiconductor (N-type semiconductor). At this time, the second PN junction opens, forming a stable on-state current. When a negative voltage is applied to the gate, the reverse electric field hinders the current applied to the source from entering the second semiconductor (P-type semiconductor). The hole concentration in the second semiconductor (P-type semiconductor) increases, and the electron concentration is low, making it more difficult for electrons to jump across the first PN junction near the source. No current is transmitted in the channel, and the driving transistor is in a closed state. This reduces leakage current formation, improves the display effect of the display device, and reduces the power consumption of the driving transistor.
[0084] In addition, the array substrate fabrication method provided in this application can be used to prepare both the second semiconductor and the first semiconductor of the active layer by solution coating. Compared with particle doping or physical vapor deposition or chemical vapor deposition film formation processes, the fabrication method is simple, can optimize the array substrate fabrication process, and is suitable for large-area and flexible device fabrication.
[0085] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.
Claims
1. An array substrate, comprising a substrate and a driving transistor layer formed on the substrate; characterized in that, The driving transistor layer includes at least one driving transistor, each driving transistor comprising: Gate; An active layer, located opposite to the gate, includes a first semiconductor and two second semiconductors. The two second semiconductors are formed at opposite ends of the first semiconductor and are respectively in contact with the first semiconductor to form a first PN junction and a second PN junction. The conduction directions of the first PN junction and the second PN junction are opposite. A source-drain layer is positioned opposite to the active layer. The source-drain layer includes a source and a drain. The source is connected to a second semiconductor at the location of the first PN junction, and the drain is connected to a second semiconductor at the location of the second PN junction. When the active layer is an NPN semiconductor, the first semiconductor is a P-type semiconductor layer, the second semiconductor is an N-type semiconductor layer, and the second PN junction is configured such that when a negative voltage is applied to the gate, the second PN junction forms a barrier to block the migration of electrons from the source to the drain. When the active layer is a PNP semiconductor, the first semiconductor is an N-type semiconductor layer, the second semiconductor is a P-type semiconductor layer, and the first PN junction is configured such that when a negative voltage is applied to the gate and the driving transistor is turned off, the first PN junction forms a barrier to block the migration of electrons from the drain to the source. The material of the N-type semiconductor layer is an N-type inorganic semiconductor material, and the material of the P-type semiconductor layer is a P-type organic semiconductor material.
2. The array substrate as described in claim 1, characterized in that, The first semiconductor includes a channel region, and the orthographic projections of the two second semiconductors on the substrate are located on either side of the orthographic projection of the channel region on the substrate.
3. The array substrate as described in claim 1, characterized in that, The first semiconductor includes two end faces and a first surface connected to the end faces. The first surface is away from the substrate. The two end faces are located at opposite ends of the first surface. A second semiconductor is attached to a corresponding end face and / or the first surface.
4. The array substrate as described in claim 1, characterized in that, The driving transistor layer further includes a gate insulating layer, a first protective layer, and a second protective layer. The gate insulating layer is formed on the substrate and covers the gate. The active layer is formed on the gate insulating layer. The first protective layer covers the active layer and is formed on the gate insulating layer. The second protective layer covers the source and drain layers.
5. A method for fabricating an array substrate, characterized in that, include: Provide a substrate; A gate, a gate insulating layer, and a first semiconductor are formed on the substrate; wherein the gate insulating layer covers the gate and is located between the gate and the first semiconductor; A second semiconductor is formed at each of the opposite ends of the first semiconductor, and the two second semiconductors are respectively in contact with the two ends of the first semiconductor to form a first PN junction and a second PN junction, thereby forming an active layer; A source-drain layer is formed on the active layer, and the source and drain are electrically connected to two second semiconductors respectively; the source-drain layer and the active layer are separated by a first protective layer; the source-drain layer includes a source and a drain. When the active layer is an NPN semiconductor, the first semiconductor is a P-type semiconductor layer, the second semiconductor is an N-type semiconductor layer, and the second PN junction is configured such that when a negative voltage is applied to the gate, the second PN junction forms a barrier to block the migration of electrons from the source to the drain. When the active layer is a PNP semiconductor, the first semiconductor is an N-type semiconductor layer, the second semiconductor is a P-type semiconductor layer, and the first PN junction is configured such that when a negative voltage is applied to the gate and the driving transistor is turned off, the first PN junction forms a barrier to block the migration of electrons from the drain to the source. The material of the N-type semiconductor layer is an N-type inorganic semiconductor material, and the material of the P-type semiconductor layer is a P-type organic semiconductor material.
6. The method for fabricating an array substrate as described in claim 5, characterized in that, The first semiconductor and / or the second semiconductor are formed by vapor deposition or solution coating.
7. A display panel, characterized in that, The display panel includes an array substrate and a pair of opposing substrates as described in any one of claims 1-4, wherein the array substrate and the array substrate are disposed at a distance from each other.