Display panel and display device

Abstract

This disclosure relates to the field of display technology, and discloses a display panel and a display device. The display panel includes: a substrate, including a first display area and a second display area disposed adjacent to each other along a second direction; a fifth conductive layer located on one side of the substrate, the fifth conductive layer including: a plurality of data lines extending along the second direction and spaced apart in a first direction in the orthographic projection of the substrate, the first direction intersecting the second direction; a sixth conductive layer located on the side of the fifth conductive layer away from the substrate, the sixth conductive layer including: a plurality of adapter lines located in the first display area in the orthographic projection of the substrate, the adapter lines being connected to the data lines through vias; and a plurality of virtual signal lines extending along the first direction and spaced apart in the second direction in the orthographic projection of the substrate, and at least a portion of the virtual signal lines located in the second display area in the orthographic projection of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] FIAA, also known as Fout in AA, is a design solution to address the difficulties of border fanout routing in narrow and ultra-narrow bezel applications. Related technologies suffer from uneven film layer distribution, which can negatively impact optical display performance.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0005] According to one aspect of this disclosure, a display panel is provided, the display panel including a pixel driving circuit, the pixel driving circuit including a driving transistor and a fourth transistor, the first terminal of the fourth transistor being connected to a data line, and the second terminal being connected to the first terminal of the driving transistor; the display panel further includes: a substrate, including a first display area and a second display area disposed adjacent to each other along a second direction; a fifth conductive layer located on one side of the substrate, the fifth conductive layer including: a plurality of the data lines, which extend along the second direction and are spaced apart in a first direction when projected onto the substrate, the first direction intersecting the second direction; a sixth conductive layer located on the side of the fifth conductive layer away from the substrate, the sixth conductive layer including: a plurality of adapter lines, which are located in the first display area when projected onto the substrate, the adapter lines being connected to the data lines through vias; and a plurality of virtual signal lines, which extend along the first direction and are spaced apart in the second direction when projected onto the substrate, and at least a portion of the virtual signal lines are located in the second display area when projected onto the substrate.

[0006] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor, the second terminal of which is connected to a first power line and the second terminal of the fourth transistor; the fifth conductive layer further includes: the first power line, which extends along the second direction in the orthographic projection of the substrate; wherein the virtual signal line is connected to the first power line through a via.

[0007] In an exemplary embodiment of this disclosure, all virtual signal lines are located in the second display area; the adapter cable includes a first component and a second component, and the virtual signal lines include a third component and a fourth component. The orthographic projection of the first component onto the substrate and the orthographic projection of the second component onto the substrate both extend along the first direction. The first component and the third component are disposed opposite to each other in a second direction, and the second component and the fourth component are disposed opposite to each other in a second direction. Furthermore, the orthographic projection of any point of the adapter cable located in the first component onto the substrate and the orthographic projection of the adjacent adapter cable onto the substrate are... The distance in the second direction is L1. The distance in the second direction between the orthographic projection of any point in the third component of the virtual signal line on the substrate and the orthographic projection of the adjacent virtual signal line on the substrate is L2, L1 = L2. The distance in the second direction between the orthographic projection of any point in the second component of the adapter line on the substrate and the orthographic projection of the adjacent adapter line on the substrate is L3. The distance in the second direction between the orthographic projection of any point in the fourth component of the virtual signal line on the substrate and the orthographic projection of the adjacent virtual signal line on the substrate is L4, L3 = L4.

[0008] In an exemplary embodiment of this disclosure, in any two adjacent adapter lines, the first component and the second component are mirror images of each other in their orthographic projections on the substrate; the orthographic projection of any virtual signal line on the substrate is a mirror image of the orthographic projection of the adjacent virtual signal line on the substrate.

[0009] In an exemplary embodiment of this disclosure, the plurality of virtual signal lines include a plurality of first virtual signal lines and a plurality of second virtual signal lines. The first virtual signal lines are projected onto the first display area of ​​the substrate, and the second virtual signal lines are projected onto the second display area of ​​the substrate. A first virtual signal line is distributed between adjacent adapter lines.

[0010] In an exemplary embodiment of this disclosure, the adapter cable includes a first extension portion that extends along the first direction in the orthographic projection of the first extension portion onto the substrate; wherein, the orthographic projection of the first virtual signal line located between two adjacent adapter cables onto the substrate is a mirror image of the orthographic projection of the first extension portion of the adjacent adapter cable onto the substrate; and the orthographic projection of any second virtual signal line onto the substrate is a mirror image of the orthographic projection of the adjacent second virtual signal line onto the substrate.

[0011] In an exemplary embodiment of this disclosure, the first virtual signal line includes a first segment and a second segment, and the second virtual signal line includes a third segment and a fourth segment. The first segment and the third segment are disposed opposite to each other in the second direction, and the second segment and the fourth segment are disposed opposite to each other in the second direction. Specifically, the distance in the second direction between the orthographic projection of any point on the first segment of the first virtual signal line located between adjacent pixel rows onto the substrate and the orthographic projection of the transition line of the next pixel row onto the substrate is L5; the distance in the second direction between the orthographic projection of any point on the third segment of the second virtual signal line onto the substrate and the orthographic projection of the second virtual signal line of the next virtual pixel row onto the substrate is L6, where L5 = L6; the distance in the second direction between the orthographic projection of any point on the second segment of the first virtual signal line located between adjacent pixel rows onto the substrate and the orthographic projection of the transition line of the next pixel row onto the substrate is L7; and the distance in the second direction between the orthographic projection of any point on the fourth segment of the second virtual signal line onto the substrate and the orthographic projection of the second virtual signal line of the next virtual pixel row onto the substrate is L8, where L7 = L8.

[0012] In an exemplary embodiment of this disclosure, L5 < L7.

[0013] In an exemplary embodiment of this disclosure, the gate of the fifth transistor is connected to an enable signal line, the first terminal is connected to the first terminal of the driving transistor, and the gate of the fourth transistor is connected to a first gate line; the display panel further includes: a first active layer located between the substrate and the fifth conductive layer, the first active layer including: a fifth active portion for forming the channel region of the fifth transistor; a fourth active portion for forming the channel region of the fourth transistor; and a first conductive layer located between the first active layer and the fifth conductive layer, the first conductive layer including: the enable signal line extending along the first direction in the orthographic projection of the substrate, the enable signal line covering the fifth active portion in the orthographic projection of the substrate, and the enable signal line portion... A substructure is used to form the gate of the fifth transistor; a third conductive layer is located between the first conductive layer and the fifth conductive layer, the third conductive layer including: a first gate line extending along the first direction in the orthographic projection of the substrate, the orthographic projection of the first gate line on the substrate covering the orthographic projection of the fourth active portion on the substrate, a portion of the structure of the first gate line being used to form the gate of the fourth transistor; the fifth conductive layer further includes: a first power line extending along the second direction in the orthographic projection of the substrate; wherein, in the same pixel driving circuit, the first extension of the adapter line is located between the orthographic projection of the first gate line substrate and the orthographic projection of the enable signal line substrate in the orthographic projection of the substrate.

[0014] In an exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuits, the plurality of pixel driving circuits being arrayed in the first direction and the second direction; the pixel driving circuit further includes a first transistor, the first electrode of the first transistor being connected to the gate of the driving transistor via an eighth transistor, the gate being connected to a reset signal line; the first active layer further includes: a first active portion for forming a channel region of the first transistor; the first conductive layer further includes: the reset signal line, extending along the first direction in the orthographic projection of the substrate, the orthographic projection of the reset signal line on the substrate covering the orthographic projection of the first active portion on the substrate, a portion of the structure of the reset signal line being used to form the gate of the first transistor; wherein, the orthographic projection of the first virtual signal line on the substrate overlaps with the orthographic projection portion of the reset signal line on the substrate.

[0015] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a storage capacitor, a sixth transistor, and a seventh transistor. The first terminal of the storage capacitor is connected to the gate of the driving transistor, and the second terminal is connected to the first power supply line. The first terminal of the sixth transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the first terminal of the seventh transistor. The gate of the sixth transistor is connected to the enable signal line. The second terminal of the seventh transistor is connected to the second initial signal line, and the gate of the seventh transistor is connected to the reset signal line. The second terminal of the first transistor is connected to the first initial signal line. The first active layer further includes a third active portion for forming the channel region of the driving transistor. The first conductive layer further includes a first conductive portion on the substrate. The orthographic projection of the plate covers the orthographic projection of the third active portion on the substrate. The first conductive portion is used to form the gate of the driving transistor and the first electrode of the storage capacitor. The third conductive layer further includes: a first initial signal line extending along the first direction in the orthographic projection of the substrate. The display panel further includes a fourth conductive layer located between the fifth conductive layer and the third conductive layer. The fourth conductive layer includes: a second initial signal line extending along the first direction in the orthographic projection of the substrate. The orthographic projections of the first gate line and the first enable signal line on the substrate are located on both sides of the orthographic projection of the first conductive portion on the substrate.

[0016] In an exemplary embodiment of this disclosure, the first direction is a row direction and the second direction is a column direction; wherein, the orthographic projection of the reset signal line in the previous row onto the substrate covers the orthographic projection of the first active portion in the current row onto the substrate, a portion of the structure of the reset signal line in the previous row is used to form the gate of the first transistor in the current row, and the orthographic projection of the reset signal line in the previous row onto the substrate is located on the side of the orthographic projection of the first gate line in the current row onto the substrate that is away from the orthographic projection of the first conductive portion in the current row onto the substrate.

[0017] In an exemplary embodiment of this disclosure, the display panel further includes: a second conductive layer located between the first conductive layer and the third conductive layer; the second conductive layer includes: a second conductive portion overlapping the orthographic projection of the first conductive portion on the substrate with the orthographic projection of the first conductive portion on the substrate; the second conductive portion is used to form a second electrode of the storage capacitor; and the second conductive portion is connected to the first power line through a via.

[0018] In an exemplary embodiment of this disclosure, the first direction is a row direction and the second direction is a column direction; the display panel includes a plurality of repeating units distributed along the row and column directions, the repeating unit includes two adjacent pixel driving circuits in the row direction, and each column of pixel driving circuits is provided with a first power line and a second conductive part; in the same repeating unit, the two first power lines are connected and the two second conductive parts are connected; in repeating units adjacent in the row direction, adjacent second conductive parts are connected.

[0019] In an exemplary embodiment of this disclosure, two pixel driving circuits that are adjacent in the row direction within the same repeating unit are mirror images of each other.

[0020] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor, a seventh transistor, and a storage capacitor. The first terminal of the fifth transistor is connected to the first terminal of the driving transistor, and the second terminal is connected to a first power line. The first terminal of the seventh transistor is connected to the second terminal of the driving transistor via a sixth transistor, and the second terminal is connected to a second initial signal line. The first terminal of the storage capacitor is connected to the gate of the driving transistor, and the second terminal is connected to the first power line. The display panel further includes: a first active layer located between the substrate and the fifth conductive layer. The first active layer includes: a third active portion for forming the channel region of the driving transistor; a fifth active portion for forming the channel region of the fifth transistor; a seventh active portion for forming the channel region of the seventh transistor; a ninth active portion connected to one end of the seventh active portion for forming the second terminal of the seventh transistor; and a fourteenth active portion connected to one side of the fifth active portion for forming the second terminal of the fifth transistor. The first conductive layer is located between the substrate and the first active layer. Between the layers, the first conductive layer includes: a first conductive portion, the orthographic projection of which overlaps the orthographic projection of the third active portion on the substrate, the first conductive portion being used to form the gate of the driving transistor and the first electrode of the storage capacitor; a second conductive layer, located between the first active layer and the fifth conductive layer, the second conductive layer including: a second conductive portion, the orthographic projection of which overlaps with the orthographic projection of the first conductive portion on the substrate, the second conductive portion being used to form the second electrode of the storage capacitor, the second conductive portion being connected to the first power line through a via; a fourth conductive layer, located between the fifth conductive layer and the second conductive layer, the fourth conductive layer including: a second initial signal line, the orthographic projection of which extends along the first direction, the second initial signal line being connected to the ninth active portion through a first via; a first bridging portion, the first bridging portion being connected to the fourteenth active portion and the second conductive portion through a second via and a third via, respectively, and connected to the first power line through another via.

[0021] In an exemplary embodiment of this disclosure, the first direction is a row direction and the second direction is a column direction; the display panel includes a plurality of repeating units distributed along the row and column directions, the repeating unit including two adjacent pixel driving circuits in the row direction; two ninth active portions in the same repeating unit are connected and share the first via; in the repeating units adjacent in the row direction, adjacent first bridging portions are connected and share the second via and the third via.

[0022] In an exemplary embodiment of this disclosure, in repeating units that are adjacent in the row direction, adjacent first bridging portions are mirror images of each other.

[0023] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, a second transistor, and an eighth transistor. The first terminal of the first transistor is connected to the second terminal of the second transistor, and the second terminal is connected to a first initial signal line. The first terminal of the second transistor is connected to the second terminal of the driving transistor, and its gate is connected to a first gate line. The first terminal of the eighth transistor is connected to the gate of the driving transistor, its second terminal is connected to the first terminal of the first transistor, and its gate is connected to a third gate line. The display panel further includes a second active layer located between the second conductive layer and the fourth conductive layer. The second active layer includes an eighth active portion for forming the channel region of the eighth transistor; and an eleventh active portion connected to the first... One side of the eighth active portion is used to form the first electrode of the eighth transistor; the twelfth active portion is connected to the other side of the eighth active portion and is used to form the second electrode of the eighth transistor; a third conductive layer is located between the second active layer and the fourth conductive layer, the third conductive layer including: a second gate line extending along the first direction in the orthographic projection of the substrate, the orthographic projection of the second gate line on the substrate covering the orthographic projection of the eighth active portion on the substrate, a portion of the structure of the second gate line being used to form the top gate of the eighth transistor; a first initial signal line extending along the first direction in the orthographic projection of the substrate; the second conductive layer further includes: a third gate line extending along the first direction in the orthographic projection of the substrate. The projection extends along the first direction, and the orthographic projection of the third gate line on the substrate covers the orthographic projection of the eighth active portion on the substrate. A portion of the structure of the third gate line is used to form the bottom gate of the eighth transistor. The first active layer further includes: a first active portion for forming the channel region of the first transistor; a seventeenth active portion connected to one side of the first active portion for forming the first electrode of the first transistor; an eighteenth active portion connected to the other side of the first active portion for forming the second electrode of the first transistor; a fourth active portion for forming the channel region of the fourth transistor; and a fifteenth active portion connected to one side of the fourth active portion for forming the first electrode of the fourth transistor. The second active portion is used to form the channel region of the second transistor; the nineteenth active portion is connected between the second active portion and the third active portion and is used to form the first electrode of the second transistor; the twentieth active portion is connected between the second active portion and the seventeenth active portion and is used to form the second electrode of the second transistor; the fourth conductive layer further includes: a second bridging portion, one end of which is connected to the eleventh active portion through a via, and the other end of which is connected to the first conductive portion through a via; a third bridging portion, one end of which is connected to the seventeenth active portion through a via, and the other end of which is connected to the twelfth active portion through a via; a fourth bridging portion, one end of which is connected to the eighteenth active portion through a via, and the other end of which is connected to the first initial signal line through a via;The third conductive part connects the fifteenth active part and the data line via a via.

[0024] In an exemplary embodiment of this disclosure, the display panel further includes: a fourth conductive layer located between the substrate and the fifth conductive layer, the fourth conductive layer including: a first transition portion connected to the tenth active portion via a via; the fifth conductive layer further including: a second transition portion connected to the first transition portion via a via; the sixth conductive layer further including: a third transition portion connected to the second transition portion via a via; the display panel further includes: a pixel defining layer located on the side of the sixth conductive layer opposite to the substrate, including a plurality of pixel openings, wherein at least a portion of the pixel openings located in the first display area are projected onto the substrate in the orthographic projection of the transition line on the substrate and the first virtual signal line on the substrate, and at least a portion of the pixel openings located in the second display area are projected onto the substrate in the orthographic projection of two adjacent second virtual signal lines on the substrate.

[0025] According to another aspect of this disclosure, a display device is also provided, including the display panel described in any embodiment of this disclosure.

[0026] The display panel provided in this disclosure improves the uniformity of the wiring in the display area by setting multiple virtual signal lines in the sixth conductive layer, with at least some of the virtual signal lines located in the second display area. Since the first display area is provided with adapter lines, setting virtual signal lines in the second display area can improve the flatness of the anode and solve the display defects caused by the difference in the flatness of the anode due to uneven wiring.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1 This is a schematic diagram of the circuit structure of a pixel driving circuit in a display panel according to one embodiment of the present disclosure;

[0030] Figure 2 for Figure 1 Timing diagram of each node in a driving method of a mid-pixel driving circuit;

[0031] Figure 3 This is a structural layout diagram of a display panel according to one embodiment of the present disclosure;

[0032] Figure 4 for Figure 3 The structural layout of the fifth conductive layer;

[0033] Figure 5 for Figure 3 Structural layout of the sixth conductive layer;

[0034] Figure 6 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure;

[0035] Figure 7 for Figure 6 The diagram shows the structural layout of the sixth conductive layer in the display panel.

[0036] Figure 8 This is a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure;

[0037] Figure 9 for Figure 3 Structural layout of the first active layer;

[0038] Figure 10 for Figure 3 Structural layout of the first conductive layer;

[0039] Figure 11 for Figure 3 Structural layout of the second conductive layer;

[0040] Figure 12 for Figure 3 Structural layout of the second active layer;

[0041] Figure 13 for Figure 3 Structural layout of the third conductive layer;

[0042] Figure 14 for Figure 3 Structural layout of the fourth conductive layer;

[0043] Figure 15 for Figure 3 The structural layout of the mid-pixel boundary layer;

[0044] Figure 16 for Figure 3 The stacked layout of the first and second active layers;

[0045] Figure 17 for Figure 3The bottom layer structure layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer;

[0046] Figure 18 This is a layout of the stacked structure of the second and fifth conductive layers in three repeating units;

[0047] Figure 19 This is the structural layout of the ILD layer;

[0048] Figure 20 The structural layout of the PVX layer and PLN1 layer;

[0049] Figure 21 The structural layout of PLN2 and PLN3 layers;

[0050] Figure 22 for Figure 3 A partial sectional view along the dashed line AA. Detailed Implementation

[0051] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0052] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0053] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0054] Figure 1This is a schematic diagram of the circuit structure of a pixel driving circuit in a display panel according to one embodiment of the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor C. In this configuration, the first transistor T1 has its first terminal connected to the fifth node N5, its second terminal connected to the first initial signal terminal Vinit1, and its gate connected to the reset signal terminal Re. The second transistor T2 has its first terminal connected to the second terminal of the driving transistor T3, and its second terminal connected to the fifth node N5; its gate connected to the first gate drive signal terminal Gate1. The gate of the driving transistor T3 is connected to the first node N1. The fourth transistor T4 has its first terminal connected to the data signal terminal Da, its second terminal connected to the first terminal of the driving transistor T3, and its gate connected to the first gate drive signal terminal Gate1. The fifth transistor T5 has its first terminal connected to the first power supply terminal VDD, its second terminal connected to the first terminal of the driving transistor T3, and its gate connected to the enable signal terminal EM. The sixth transistor T6 has its first terminal connected to the second terminal of the driving transistor T3, and its gate connected to the enable signal terminal EM. The seventh transistor T7 has its first terminal connected to the second terminal of the sixth transistor T6, its second terminal connected to the second initial signal terminal Vinit2, and its gate connected to the reset signal terminal Re. The eighth transistor T8 has its first terminal connected to the first node N1, its second terminal connected to the fifth node N5, and its gate connected to the second gate line Gate2. The storage capacitor C is connected between the gate of the driving transistor T3 and the first power supply terminal VDD. This pixel driving circuit can be connected to an OLED (OLED light-emitting unit) to drive the OLED to emit light. The OLED can be connected between the second terminal of the sixth transistor T6 and the second power supply terminal VSS. Transistors T1-T7 can all be P-type transistors, and the eighth transistor T8 can be an N-type transistor.

[0055] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode.

[0056] Figure 2 for Figure 1This diagram illustrates the timing of nodes in a pixel driving circuit using a specific driving method. Gate1 represents the timing of the first gate driving signal terminal Gate1, Gate2 represents the timing of the second gate driving signal terminal Gate2, Re represents the timing of the reset signal terminal Re, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of this pixel driving circuit may include a reset phase t1, a compensation phase t2, and an emission phase t3. In the reset phase t1: the reset signal terminal Re outputs a low-level signal, the second gate driving signal terminal Gate2 outputs a high-level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Init1 inputs an initial signal to the first node N1, the seventh transistor T7 is turned on, and the second initial signal terminal INIT2 inputs an initial signal to the second terminal of the sixth transistor T6. During the compensation phase t2: Both the first gate drive signal terminal Gate1 and the second gate drive signal terminal Gate2 output high-level signals, turning on the fourth transistor T4 and the second transistor T2. Simultaneously, the data signal terminal Data outputs a drive signal to write a voltage Vdata + Vth (i.e., the sum of voltages Vdata and Vth) to the second node N2, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. During the light emission phase t3: The enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. The drive transistor T3 emits light under the action of the voltage Vdata + Vth stored in capacitor C.

[0057] According to the formula for the output current of the driving transistor, I = (μWCox / 2L)(Vgs-Vth) 2 Where μ is the carrier mobility; Cox is the gate storage capacity per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of this disclosure, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0058] This exemplary embodiment provides a display panel that may include a pixel driving circuit. The pixel driving circuit may include a driving transistor T3 and a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to a data line Vdata, and the second terminal is connected to the first terminal of the driving transistor T3. The pixel driving circuit can be configured as follows: Figure 1 As shown, in other exemplary embodiments, the pixel driving circuit in the display panel may also be of other structures, such as 7T1C, 9T1C, etc. Figure 3 This is a structural layout diagram of a display panel according to one embodiment of the present disclosure. Figure 4 for Figure 3 Schematic diagram of the fifth conductive layer. Figure 5 for Figure 3 The structural layout of the sixth conductive layer, as shown below. Figure 3-5 As shown, the display panel may include: a substrate, a fifth conductive layer 8, and a sixth conductive layer 9. The substrate may include a first display area A1 and a second display area A2 disposed adjacent to each other along a second direction Y. The fifth conductive layer 8 is located on one side of the substrate and may include multiple data lines Vdata. The orthographic projection of the multiple data lines Vdata on the substrate extends along the second direction Y and is spaced apart in a first direction X, where the first direction X intersects the second direction Y. The sixth conductive layer 9 is located on the side of the fifth conductive layer 8 away from the substrate and may include multiple adapter lines D1 and multiple dummy signal lines. The orthographic projection of the multiple adapter lines D1 on the substrate is located in the first display area A1, and the adapter lines D1 are connected to the data lines Vdata through vias. The orthographic projection of the multiple dummy signal lines on the substrate extends along the first direction X and is spaced apart in the second direction Y, and at least some of the dummy signal lines are located in the second display area A2.

[0059] The display panel provided in this exemplary embodiment provides multiple dummy signal lines in the sixth conductive layer 9, with at least some of the dummy signal lines located in the second display area A2. Since the first display area A1 is provided with the adapter line D1, the dummy signal lines in the second display area A2 can improve the uniformity of the wiring in the display area, thereby improving the anode flatness and solving the display defects caused by the difference in the anode flatness due to uneven wiring.

[0060] Figure 6 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure, as shown below. Figure 6 As shown in this exemplary embodiment, the first display area A1 can be a sub-display area on the side of the display area closer to the source driving circuit S-IC, and the second display area A2 can be a sub-display area on the side of the display area farther away from the source driving circuit S-IC, wherein the source driving circuit S-IC is used to provide data signals to each sub-pixel.

[0061] like Figure 3As shown in this exemplary embodiment, the first direction X can be the row direction, and the second direction Y can be the column direction. It is understood that sub-pixels located in the same column use the same data line D to connect to the source driver circuit S-IC. That is, the source driver circuit S-IC transmits data signals to the sub-pixels in the same column through the data line D extending in the column direction. The number of adapter lines D1 corresponds one-to-one with the number of pixel columns. One adapter line D1 connects to one data line D. Specifically, one adapter line D1 connects to one column of data lines D, so that the data signal of the fifth conductive layer 8 can be output through the sixth conductive layer 9 via the adapter line D1. This frees up the fanout traces on the bottom bezel, which is beneficial for narrow bezel design.

[0062] like Figure 6 As shown in this exemplary embodiment, the virtual signal line dummy can be laid only in the second display area A2. In this case, the wiring density of the virtual signal line dummy can be the same as the wiring density of the adapter cable D1. The wiring density can be understood as the spacing between two adjacent virtual signal lines dummy or two adapter cables D1 in the row direction. For example, Figure 7 for Figure 6 The structural layout of the sixth conductive layer in the display panel shown is as follows: Figure 7As shown, the adapter cable D1 may include a first component 111 and a first component 112, and the dummy signal line dummy may include a third component 113 and a fourth component 114. The first component 111 and the third component 113 are arranged opposite to each other in the second direction Y, and the first component 112 and the fourth component 114 are arranged opposite to each other in the second direction Y. The distance between the orthographic projection of any point in the first component 111 of the adapter cable D1 onto the substrate and the orthographic projection of the adjacent adapter cable D1 onto the substrate in the second direction Y is L1. The distance between the first component 111 and the fourth component 114 of the dummy signal line dummy is L1. The distance between the orthographic projection of any point in component 113 onto the substrate and the orthographic projection of an adjacent virtual signal line dummy onto the substrate in the second direction Y is L2, L1 = L2; the distance between the orthographic projection of any point in the first component 112 of the adapter line D1 onto the substrate and the orthographic projection of an adjacent adapter line D1 onto the substrate in the second direction Y is L3; the distance between the orthographic projection of any point in the fourth component 114 of the virtual signal line dummy onto the substrate and the orthographic projection of an adjacent virtual signal line dummy onto the substrate in the second direction Y is L4, L3 = L4. This is equivalent to the spacing between two adjacent adapter lines D1 in the first display area A1 at the same position in the column direction being the same as the spacing between two adjacent virtual signal lines dummy in the second display area A2. This makes the wiring density of the virtual signal lines dummy in the second display area A2 the same or comparable to the wiring density of the adapter lines D1 in the first display area A1, thereby improving the uniformity of the wiring in the display area. Based on this, the adapter cable D1 can be configured as a mirror-symmetrical structure in the column direction, and the dummy signal line can also be configured as a mirror-symmetrical structure in the column direction. This improves the flatness below the anode and ensures that the height difference between the two areas below the anode is consistent, resulting in a more uniform optical display. Of course, in other exemplary embodiments, the adapter cable D1 and the dummy signal line can also extend along a straight line in the first direction, i.e., there is no protruding structure in the second direction.

[0063] In this exemplary embodiment, the arrangement of two signal lines opposite each other in the second direction Y can be understood as follows: the first endpoint of one signal line extends infinitely along the second direction Y and coincides with one endpoint of the other signal line, and the second endpoint of the signal line extends infinitely along the second direction Y and coincides with the other endpoint of the other signal line.

[0064] Figure 8 This is a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure, as shown below. Figure 8 As shown in this exemplary embodiment, virtual signal lines (dummy) can also be simultaneously deployed in the first display area A1 and the second display area A2. For example... Figure 5 , 8As shown, multiple virtual signal lines (dummy lines) can include multiple first virtual signal lines (dummy 1) and multiple second virtual signal lines (dummy 2). The orthographic projection of the first virtual signal line (dummy 1) onto the substrate is located in the first display area A1, and the orthographic projection of the second virtual signal line (dummy 2) onto the substrate is located in the second display area A2. A first virtual signal line (dummy 1) is distributed between adjacent adapter lines (D1), meaning that in the first display area A1, a first virtual signal line (dummy 1) is inserted between two adjacent adapter lines (D1). Furthermore, the first virtual signal line (dummy 1) and the adjacent adapter line (D1) can be mirror images of each other, and the second virtual signal lines (dummy 2) can also be mirror images of each other. The mirror symmetry arrangement of the first virtual signal line (dummy 1) and the adapter line (D1) ensures a consistent height difference in the area below the anode, resulting in a more uniform optical display. Similarly, the second virtual signal line (dummy 2) in the second display area A2 is also mirror symmetrically arranged, achieving the same effect. For example, as shown... Figure 5 As shown, the adapter cable D1 may include a first extension D11, the orthographic projection of which onto the substrate extends along a first direction X. The orthographic projection of a first virtual signal line dummy1 located between two adjacent adapter cables D1 onto the substrate is a mirror image of the orthographic projection of the first extension D11 of the adjacent adapter cable D1 onto the substrate. Similarly, the orthographic projection of any second virtual signal line dummy2 onto the substrate is a mirror image of the orthographic projection of the adjacent second virtual signal line dummy2 onto the substrate. It is understood that the adapter cable D1 may also include a second extension D12, the orthographic projection of which onto the substrate extends along a second direction Y. The adapter cable D1 connects the corresponding column of data lines to the source driver circuit S-IC through the second extension D12.

[0065] like Figure 5As shown in this exemplary embodiment, the first virtual signal line dummy1 may include a first segment D111 and a second segment D112, and the second virtual signal line dummy2 may include a third segment DM113 and a fourth segment DM114. The first segment D111 and the third segment DM113 are arranged opposite to each other in the second direction Y, and the second segment D112 and the fourth segment DM114 are arranged opposite to each other in the second direction Y. The distance between the orthographic projection of any point on the first segment D111 of the first virtual signal line dummy1 located between adjacent pixel rows and the orthographic projection of the transition line D1 of the next pixel row on the substrate in the second direction Y is L5. The third segment of the second virtual signal line dummy2... The distance between the orthographic projection of any point in DM113 onto the substrate and the orthographic projection of the second virtual signal line dummy2 of the next virtual pixel row onto the substrate in the second direction Y is L6, L5 = L6; the distance between the orthographic projection of any point on the second segment D112 of the first virtual signal line dummy1 located between adjacent pixel rows and the orthographic projection of the transition line D1 of the next pixel row onto the substrate in the second direction Y is L7; the distance between the orthographic projection of any point on the fourth segment DM114 of the second virtual signal line dummy2 onto the substrate and the orthographic projection of the second virtual signal line dummy2 of the next virtual pixel row onto the substrate in the second direction Y is L8, L7 = L8. Essentially, at the same position in the column direction, the spacing between the transition line D1 in the first display area A1 and the adjacent first virtual signal line dummy1 is the same as the spacing between two adjacent second virtual signal lines dummy2 in the second display area A2, making the display panel uniformly spaced throughout, further improving the wiring uniformity of the display panel and enhancing the display effect. In this exemplary embodiment, L5 can be set to be greater than L7. Of course, in other exemplary embodiments, L5, L6, L7, and L8 can also be set to be the same, that is, the first virtual signal line dummy1 and the second virtual signal line dummy2 extend along a straight line in the row direction.

[0066] like Figure 3As shown in this exemplary embodiment, the display panel may further include a light-shielding layer, a first active layer 2, a first conductive layer 3, a second conductive layer 4, a second active layer 5, a third conductive layer 6, a fourth conductive layer 7, a fifth conductive layer 8, a sixth conductive layer 9, and a pixel defining layer. The substrate, light-shielding layer, first active layer 2, first conductive layer 3, second conductive layer 4, second active layer 5, third conductive layer 6, fourth conductive layer 7, fifth conductive layer 8, sixth conductive layer 9, and pixel defining layer are sequentially stacked. Insulating layers may be disposed between the functional layers. The first conductive layer 3 may be a first gate metal layer (Gate1 layer), the second conductive layer 4 may be a second gate metal layer (Gate2 layer), the third conductive layer 6 may be a third gate metal layer (Gate3 layer), the fourth conductive layer 7 may be a first metal trace layer (SD1 layer), the fifth conductive layer 8 may be a second metal trace layer (SD2 layer), and the sixth conductive layer 9 may be a third metal trace layer (SD3 layer). The light-shielding layer may include multiple light-shielding portions distributed in the row direction X and column direction Y, and adjacent light-shielding portions may be interconnected. The light-shielding layer may be a conductive structure; for example, the light-shielding layer may be a light-shielding metal layer.

[0067] Figure 9 for Figure 3 The structural layout of the first active layer in the middle, Figure 10 for Figure 3 The structural layout of the first conductive layer in the middle, Figure 11 for Figure 3 Layout of the second conductive layer. Figure 12 for Figure 3 The structural layout of the second active layer in the middle. Figure 13 for Figure 3 The structural layout of the third conductive layer in the middle. Figure 14 for Figure 3 The structural layout of the fourth conductive layer in the middle. Figure 15 for Figure 3 The structural layout of the mid-pixel boundary layer. Figure 16 for Figure 3 The stacked layout of the first and second active layers in the middle. Figure 17 for Figure 3 The bottom layer structure layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer. Figure 18 This is a layout of the stacked structure of the second and fifth conductive layers in three repeating units.

[0068] like Figure 3 , 9As shown in this exemplary embodiment, the first active layer 2 may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 can be used to form the channel region of the first transistor T1, the second active portion 72 can be used to form the channel region of the second transistor T2, the third active portion 73 can be used to form the channel region of the driving transistor T3, the fourth active portion 74 can be used to form the channel region of the fourth transistor T4, the fifth active portion 75 can be used to form the channel region of the fifth transistor T5, the sixth active portion 76 can be used to form the channel region of the sixth transistor T6, and the seventh active portion 77 can be used to form the channel region of the seventh transistor T7. The first active layer 2 may further include a ninth active section 79, a tenth active section 710, and thirteenth active sections 713 to twentieth active sections 720. The ninth active section 79 and the tenth active section 710 are connected to both sides of the seventh active section 77 and are used to form the second electrode and the first electrode of the seventh transistor T7, respectively. The ninth active section 79 can be connected to the second initial signal line Vinit2 located in the fourth conductive layer 7 through the first via H1, connecting the second electrode of the seventh transistor T7 to the second initial signal line Vinit2. The tenth active section 710 is also connected to the sixth active section 76. At the same time, the tenth active section 710 can be connected to the anode located in the pixel defining layer through the via, so that the first electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6 are connected to the anode of the light-emitting unit. The thirteenth active portion 713 and the fourteenth active portion 714 are connected to both sides of the fifth active portion 75, and are used to form the first and second electrodes of the fifth transistor T5, respectively. The thirteenth active portion 713 can be connected to the first bridging portion 41 located on the fourth conductive layer 7 through a via, thereby connecting to the first power line Vdd located on the fifth conductive layer 8 through the first bridging portion 41. The fourteenth active portion 714 is connected to one side of the third active portion 73, forming... Figure 1The second node N2 in the first active part 71. The seventeenth active part 717 and the eighteenth active part 718 are connected to both sides of the first active part 71 and are used to form the first and second electrodes of the first transistor T1, respectively. The seventeenth active part 717 can be connected to the third bridging part 43 located in the fourth conductive layer 7 through the via H7, and connected to the twelfth active part 712 located in the second active layer 5 through the third bridging part 43, connecting the first electrode of the first transistor T1 to the second electrode of the eighth transistor T8. The eighteenth active part 718 can be connected to the fourth bridging part 44 located in the fourth conductive layer 7 through the via H10, connecting the second electrode of the first transistor T1 to the first initial signal line Vinit1 through the fourth bridging part 44. The fifteenth active part 715 is connected to one side of the fourth active part 74 and is used to form the first electrode of the fourth transistor T4. The fifteenth active part 715 can be connected to the third conductive part 45 located on the fourth conductive layer 7 through the via H11. Through the third conductive part 45, the first electrode of the fourth transistor T4 is connected to the data line Vdata located on the fifth conductive layer 8. In addition, the thirteenth active part 713 is also connected to the side of the fourth active part 74 away from the fifteenth active part 715, which means that the thirteenth active part 713 also forms the second electrode of the fourth transistor T4. The nineteenth active part 719 and the twentieth active part 720 are respectively connected to both sides of the second active part 72 and are used to form the first electrode and the second electrode of the second transistor T2, respectively. The nineteenth active part 719 is also connected to the third active part 73 and the sixth active part 76, that is, the nineteenth active part 719 is also used to form Figure 1 The third node N3 and the second terminal of driving transistor T3, the first terminal of sixth transistor T6, the twentieth active part 720 is also connected to the seventeenth active part 717, and in addition, as Figure 19 As shown, the twentieth active portion 720 and the seventeenth active portion 717 can be connected to the twelfth active portion 712 located in the second active layer 5 via via H8, so that the first electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the eighth transistor T8 are connected. The first active layer 2 can be formed of polycrystalline silicon semiconductor material, and correspondingly, the transistors in the display panel of this disclosure can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0069] like Figure 3 , 10 As shown in Figure 17, in this exemplary embodiment, the first conductive layer 3 may include a first conductive portion 11. The orthographic projection of the first conductive portion 11 onto the substrate may cover the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the storage capacitor C. The first conductive layer 3 may also include an enable signal line EM, a reset signal line Re, and a first gate line G1, wherein the enable signal line EM can be used to provide... Figure 1The enable signal terminal EM in the substrate has its orthographic projection onto the substrate extending along the first direction X and covering the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM is used to form the gate of the fifth transistor T5, and a portion is used to form the gate of the sixth transistor T6. The first gate line G1 can be used to provide... Figure 1 The first gate drive signal terminal Gate1 in the circuit has a first gate line G1 whose orthogonal projection onto the substrate extends along the first direction X and covers the orthogonal projections of the second active portion 72 and the fourth active portion 74 onto the substrate. A portion of the first gate line G1 is used to form the gate of the second transistor T2, and a portion is used to form the gate of the fourth transistor T4, providing the first gate drive signal to the gates of the second transistor T2 and the fourth transistor T4, respectively. The reset signal line Re can be used to provide... Figure 1 The reset signal terminal Re in the substrate can be extended along the first direction X and cover the seventh active part 77. A part of the structure of the reset signal line Re is used to form the gate of the seventh transistor T7 and to provide a reset signal to the gate of the seventh transistor T7.

[0070] In this exemplary embodiment, the display panel can use the first conductive layer 3 as a mask to perform conductor processing on the active layer, that is, the active layer covered by the first conductive layer 3 forms the channel region of the transistor, and the area not covered by the first conductive layer 3 forms a conductor structure.

[0071] It should be understood that, in this exemplary embodiment, the orthographic projection of one structure A onto the substrate covering the orthographic projection of another structure B onto the substrate can be understood as the outline of the projection of B onto the plane of the substrate being completely inside the outline of the projection of A onto the same plane.

[0072] It should be understood that, in this exemplary embodiment, for a structure A to extend along the direction B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along the direction B, and the length of the main part extending along the direction B is greater than the length of the secondary part extending along other directions.

[0073] like Figure 3 , 11 As shown in Figure 17, in this exemplary embodiment, the second conductive layer 4 may include a second conductive portion 22, the orthographic projection of which overlaps with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 can be used to form the second electrode of the storage capacitor C. The second conductive portion 22 can be connected to the first power line Vdd located in the fifth conductive layer 8 through a via, so that the second electrode of the storage capacitor C is connected to the first power line Vdd. The second conductive layer 4 may also include a second gate line G2, which can be used to provide... Figure 1The second gate drive signal terminal Gate1 in the middle, the second gate line G2 can be extended along the first direction X and cover the eighth active part 78 on the substrate, and part of the structure of the second gate line G2 is used to form the bottom gate of the eighth transistor T8.

[0074] like Figure 3 , 12 As shown in Figure 17, in this exemplary embodiment, the second active layer 5 may include an eighth active portion 78, an eleventh active portion 711, and a twelfth active portion 712. The eighth active portion 78 can be used to form the channel region of the eighth transistor T8. The eleventh active portion 711 and the twelfth active portion 712 are connected to both sides of the eighth active portion 78 and are used to form the first electrode and the second electrode of the eighth transistor T8, respectively. The eleventh active portion 711 can be connected to the second bridging portion 42 located in the fourth conductive layer 7 through a via, and the first electrode of the eighth transistor T8 is connected to the gate of the driving transistor T3 through the second bridging portion 42. The twelfth active portion 712 can be connected to the third bridging portion 43 located in the fourth conductive layer 7 through a via, and the second electrode of the eighth transistor T8 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2 through the third bridging portion 43. The second active layer 5 may be formed of indium gallium zinc oxide, and correspondingly, the eighth transistor T8 may be an N-type metal oxide thin film transistor.

[0075] like Figure 3 , 13 As shown in Figure 17, in this exemplary embodiment, the third conductive layer 6 may include a third gate line G3 and a first initial signal line Vinit1. The orthographic projection of the first initial signal line Vinit1 onto the substrate may extend along a first direction X. The first initial signal line Vinit1 can be used to provide... Figure 1 The first initial signal terminal Vinit1 in the first active layer 7 is connected to the fourth bridging portion 44 located in the fourth conductive layer 7 via via H10. This fourth bridging portion 44 connects to the eighteenth active portion 718 located in the first active layer 2, thereby connecting the second terminal of the first transistor T1 to the first initial signal line Vinit1. The orthographic projection of the third gate line G3 onto the substrate extends along the first direction X and covers the orthographic projection of the eighth active portion 78 onto the substrate. A portion of the structure of the third gate line G3 is used to form the top gate of the eighth transistor T8. Furthermore, the display panel can utilize the third conductive layer 6 as a mask to conduct the second active layer 5, meaning that the area of ​​the second active layer 5 covered by the third conductive layer 6 can form the channel region of the transistor, while the area of ​​the second active layer 5 not covered by the third conductive layer 6 forms a conductive structure.

[0076] like Figure 3 , 14As shown in this exemplary embodiment, the fourth conductive layer 7 may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, and a third conductive portion 45. One end of the first bridging portion 41 can be connected to the fourteenth active portion 714 via a second via H2, and the other end can be connected to the second conductive portion 22 via a third via H3. Furthermore, the first bridging portion 41 can be connected to the first power line Vdd located on the fifth conductive layer 8 via a via H22 located on the first planarization layer PLN1, thereby connecting the second terminal of the fifth transistor T5 to the second terminal of the storage capacitor C and the first power line Vdd, respectively. The second bridging portion 42 can be connected to the eleventh active portion 711 via a via H5 located on the ILD layer, connecting to the first terminal of the eighth transistor T8. The second bridging portion 42 also connects to the first conductive portion 11 via a via H6 located on the ILD layer, thereby connecting the first terminal of the eighth transistor T8 to the gate of the driving transistor T3 via the second bridging portion 42. The third bridging portion 43 can be connected to the seventeenth active portion 717 via via H7 in the ILD layer to connect to the first terminal of the first transistor T1. The third bridging portion 43 can also be connected to the twelfth active portion 712 via via H8 in the ILD layer to connect to the second terminal of the eighth transistor T8, thereby connecting the second terminal of the eighth transistor T8 to the first terminal of the first transistor T1 through the third bridging portion 43. The fourth bridging portion 44 can be connected to the eighteenth active portion 718 via via H9 in the ILD layer to connect to the second terminal of the first transistor T1. The fourth bridging portion 44 can also be connected to the first initial signal line Vinit1 via via via H10 in the ILD layer, thereby connecting the second terminal of the first transistor T1 to the first initial signal line Vinit1 through the fourth bridging portion 44. The third conductive portion 45 can be connected to the fifteenth active portion 715 via via H11 in the ILD layer and to the data line Vdata via via via H23 in the PLN1 layer, thereby connecting the first terminal of the fourth transistor T4 to the data line Vdata. Furthermore, the fourth conductive layer 7 may also include a first transition portion 46, which can be connected to the tenth active portion 710 through a via H12 in the ILD layer to connect with the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7. Simultaneously, the first transition portion can be connected to the second transition portion 52 located in the fifth conductive layer 8 through a via H24 in the PLN1 layer. This second transition portion is used to connect to the anode. Additionally, the fourth conductive layer 7 may also include a second initial signal line Vinit2, the second initial signal line Vinit2's orthographic projection onto the substrate can extend along a first direction X. The second initial signal line Vinit2 can be used to provide... Figure 1The second initial signal terminal Vinit2 is located in the ILD layer. Vinit2 can be connected to the ninth active part 79 via a via H1 in the ILD layer, and thus connected to the second electrode of the seventh transistor T7. In this exemplary embodiment, the first initial signal line Vinit1 provides a first initialization signal, and the second initial signal line Vinit2 provides a second initialization signal. The first and second initialization signals may not be equal; therefore, the pixel driving circuit can provide different initialization signals to the first node N1 and the first electrode of the light-emitting device according to actual needs. For example, the effective voltage level of the first initialization signal can be set to -3V, and the effective voltage level of the second initialization signal can be set to -4V to ensure that the display screen has low brightness in a black state, improving the image display effect. Furthermore, it is understood that in this exemplary embodiment, vias are also formed at the opening positions of the passivation layer (PVX layer) corresponding to the PLN1 layer.

[0077] like Figure 3 , 4 As shown in this exemplary embodiment, the fifth conductive layer 8 may further include a second transition portion 52, which can be connected to a third transition portion 63 located in the sixth conductive layer 9 via a via H34 of PLN2, so as to connect to the anode through the third transition portion 63. Furthermore, the fifth conductive layer 8 may also include a first power line Vdd and a data line Vdata. The orthographic projection of the first power line Vdd onto the substrate and the orthographic projection of the data line Vdata onto the substrate can both extend along the second direction Y. The first power line Vdd can be used to provide... Figure 1 The first power supply terminal VDD and the first power line Vdd can be connected to the first bridging portion 41 located on the fourth conductive layer 7 through the via H22 of the PLN1 layer. This first bridging portion 41 connects the second terminal of the fifth transistor T5 and the second terminal of the storage capacitor C to the first power line Vdd. The data line Vdata can be used to provide... Figure 1 The data signal terminal Data and the data line Vdata can be connected to the third conductive part 45 of the fourth conductive layer 7 through the via H23 of the PLN1 layer, thereby connecting the first terminal of the fourth transistor T4 to the data line Vdata through the third conductive part 45.

[0078] In this exemplary embodiment, a structure A extending along direction B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending in other directions.

[0079] like Figure 3 , 5As shown in this exemplary embodiment, the sixth conductive layer 9 may include a third transition portion 63, which can be connected to the anode through a via H41 in the PLN3 layer. The sixth conductive layer 9 may also include a transition line D1 and a dummy signal line. The orthographic projection of the transition line D1 onto the substrate is located in the first display area A1. The dummy signal line may include a first dummy signal line 1 and a second dummy signal line 2. The orthographic projection of the first dummy signal line 1 onto the substrate may be located in the first display area A1, and the orthographic projection of the second dummy signal line 2 onto the substrate may be located in the second display area A2. This exemplary embodiment can improve the uniformity of the wiring in the display area by setting the first dummy signal line 1 and the second dummy signal line 2. For the specific structure of the dummy signal line, please refer to the description of the above embodiment, which will not be repeated here. Furthermore, it should be noted that in this exemplary embodiment, both the first virtual signal line dummy1 and the second virtual signal line dummy2 are connected to the first power line Vdd of the fifth conductive layer 8 through vias H35 located in the PLN2 layer. This provides a stable voltage signal to the first virtual signal line dummy1 and the second virtual signal line dummy2, preventing them from being suspended and interfered with by other signals. On the other hand, it reduces the RC loading of the first power line Vdd signal, thereby helping to reduce the voltage drop loss of the first power line Vdd and improve the light emission stability of the light-emitting unit.

[0080] like Figure 3 , 15As shown in this exemplary embodiment, the display panel may further include a pixel defining layer, which includes pixel openings. At least a portion of the pixel openings located in the first display area A1 are projected onto the orthographic projection of the adapter line D1 onto the substrate and the first dummy signal line dummy1 onto the substrate. At least a portion of the pixel openings located in the second display area A2 are projected onto the orthographic projection of two adjacent second dummy signal lines dummy2 onto the substrate. As described above, because the first extension of the adapter line D1 in the first display area A1 is mirror-symmetrically arranged with the adjacent first dummy signal line dummy1, and the two adjacent second dummy signal lines dummy2 in the second display area A2 are mirror-symmetrically arranged, the height difference between the two regions below the anode in the pixel defining layer can be made consistent, resulting in a more uniform optical display. For example, the pixel openings of the R and B sub-pixels in the first display area can be positioned on the orthogonal projection of the adapter line D1 on the substrate and the orthogonal projection of the first virtual signal line dummy1 on the substrate, and the pixel openings of the R and B sub-pixels in the second display area can be positioned on the orthogonal projection of the two adjacent second virtual signal lines dummy2 on the substrate. Of course, in other exemplary embodiments, the pixel opening of the G sub-pixel may also have the above features, and this disclosure does not limit this.

[0081] like Figure 3 , 18 As shown in this exemplary embodiment, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 that are adjacently distributed in the row direction X. The first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in a mirror-symmetric manner. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit Q. The display panel may include a plurality of repeating units Q arranged in an array in the row direction X and the column direction Y. Furthermore, in two adjacent repeating units Q in the row direction, the first pixel driving circuit P1 in one repeating unit Q is adjacent to the second pixel driving circuit P2 in the adjacent repeating unit Q, and the second pixel driving circuit P2 in one repeating unit Q is adjacent to the first pixel driving circuit P1 in the other repeating unit Q.

[0082] like Figure 3 , 18As shown in this exemplary embodiment, in a repeating unit Q, the first pixel driving circuit P1 and the second pixel driving circuit P2 are arranged in a mirror-symmetric manner, and the first power line Vdd in the first pixel driving circuit P1 and the first power line Vdd in the second pixel driving circuit P2 can be connected as a whole, while the second conductive part 2232 is connected as a whole. In two adjacent repeating units Q in the row direction, the first power line Vdd in the first pixel driving circuit P1 and the first power line Vdd in the second pixel driving circuit P2 in the adjacent repeating unit Q can be unconnected, and the second conductive part 2232 in the first pixel driving circuit P1 and the second conductive part 2232 in the second pixel driving circuit P2 in the adjacent repeating unit Q are connected, so that the power line Vdd and the second conductive part 2232 can form a grid structure, which can reduce the voltage drop of the power signal on the power line. In addition, as Figure 3 As shown, in the same repeating unit Q, the data line Vdata in the first pixel driving circuit P1 and the data line Vdata in the second pixel driving circuit P2 are not connected, and the two data lines Vdata are distributed on both sides of the two first power lines Vdd.

[0083] like Figure 3 , 18 As shown in this exemplary embodiment, in two adjacent repeating units Q in the row direction, the first bridging portion 41 in the first pixel driving circuit P1 and the first bridging portion 41 in the second pixel driving circuit of the adjacent repeating unit Q can be interconnected. Furthermore, the first pixel driving circuit P1 and the second pixel driving circuit P2 in the adjacent repeating unit Q can share a second via H2 and a third via H3. Since two sub-pixels share a second via H2 and a third via H3, the space occupied by the sub-pixels can be saved, which is beneficial to improving the space utilization of the display panel. In addition, in the same repeating unit Q, the first pixel driving circuit P1 and the second pixel driving circuit P2 share a first via H1. Similarly, since two sub-pixels share a first via H1, the space occupied by the sub-pixels can be saved, which improves the space utilization of the display panel.

[0084] like Figure 22 As shown, Figure 3A partial cross-sectional view along the dashed line AA. The display panel may include a first insulating layer 81, a second insulating layer 82, a third insulating layer 83, a fourth insulating layer 84, a fifth insulating layer 85, a first dielectric layer 86, and a first planarization layer 87, wherein the substrate 80, the light-shielding layer, the first insulating layer 81, the first active layer 2, the second insulating layer 82, the first conductive layer 3, the third insulating layer 83, the second conductive layer 4, the fourth insulating layer 84, the second active layer 5, the fifth insulating layer 85, the third conductive layer 6, the first dielectric layer 86, the fourth conductive layer 7, the first planarization layer 87, the fifth conductive layer 8, the second planarization layer 88, and the sixth conductive layer 9 are stacked sequentially. The first insulating layer 81 and the second insulating layer 82 may be silicon oxide layers, and the first dielectric layer 86 may be a silicon nitride layer. The substrate may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer may be an inorganic material. The materials of the first conductive layer 3 and the second conductive layer 4 can be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stack thereof. The materials of the third conductive layer 6 and the fourth conductive layer 7 can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stack thereof, or a titanium / aluminum / titanium stack thereof.

[0085] This disclosure also provides a display device, which may include the display panel described in any embodiment of this disclosure.

[0086] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A display panel, characterized by, The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor and a fourth transistor, the first electrode of the fourth transistor is connected with a data line, and the second electrode of the fourth transistor is connected with the first electrode of the driving transistor. The substrate substrate comprises a first display area and a second display area arranged adjacent along a second direction; The fifth conductive layer is located on one side of the substrate substrate, and the fifth conductive layer comprises: A plurality of data lines extend along the second direction in the orthographic projection of the substrate substrate and are distributed at intervals in the first direction intersecting the second direction; The sixth conductive layer is located on the side of the fifth conductive layer away from the substrate substrate, and the sixth conductive layer comprises: A plurality of adapter lines are located in the orthographic projection of the substrate substrate in the first display area, and the adapter lines are connected with the data lines through vias; A plurality of virtual signal lines extend along the first direction in the orthographic projection of the substrate substrate and are distributed at intervals in the second direction, and at least part of the virtual signal lines are located in the orthographic projection of the substrate substrate in the second display area; The display panel further comprises a plurality of repeating units arranged in the first direction and the second direction, and each repeating unit comprises two pixel driving circuits adjacent in the first direction, and the two pixel driving circuits in the same repeating unit are mirror images of each other.

2. The display panel of claim 1, wherein, The pixel driving circuit further comprises a fifth transistor, the second electrode of the fifth transistor is connected with a first power supply line, and the second electrode of the fifth transistor is connected with the second electrode of the fourth transistor; The fifth conductive layer further comprises: The first power supply line extends along the second direction in the orthographic projection of the substrate substrate; The virtual signal line is connected with the first power supply line through a via.

3. The display panel of claim 2, wherein, The virtual signal lines are all located in the second display area; the adapter lines comprise a first component and a second component, the virtual signal lines comprise a third component and a fourth component, the first component extends along the first direction in the orthographic projection of the substrate substrate, the second component extends along the first direction in the orthographic projection of the substrate substrate, the first component and the third component are oppositely arranged in the second direction, and the second component and the fourth component are oppositely arranged in the second direction; The distance between any point in the first component of the adapter line in the orthographic projection of the substrate substrate and the orthographic projection of the adjacent adapter line in the second direction is L1, the distance between any point in the third component of the virtual signal line in the orthographic projection of the substrate substrate and the orthographic projection of the adjacent virtual signal line in the second direction is L2, and L1=L2; The distance between any point in the second component of the adapter line in the orthographic projection of the substrate substrate and the orthographic projection of the adjacent adapter line in the second direction is L3, the distance between any point in the fourth component of the virtual signal line in the orthographic projection of the substrate substrate and the orthographic projection of the adjacent virtual signal line in the second direction is L4, and L3=L4.

4. The display panel of claim 3, wherein, Any two adjacent transition lines, the first component in the orthographic projection of the substrate substrate mirror each other and the second component in the orthographic projection of the substrate substrate mirror each other; Any of the virtual signal lines in the orthographic projection of the substrate substrate mirror each other with adjacent virtual signal lines in the orthographic projection of the substrate substrate.

5. The display panel of claim 2, wherein, The plurality of virtual signal lines includes a plurality of first virtual signal lines and a plurality of second virtual signal lines, the first virtual signal line in the orthographic projection of the substrate substrate is located in the first display area, the second virtual signal line in the orthographic projection of the substrate substrate is located in the second display area, and a first virtual signal line is distributed between adjacent transition lines.

6. The display panel of claim 5, wherein, The transition line includes a first extension, the first extension in the orthographic projection of the substrate substrate extends along the first direction; Wherein, the first virtual signal line between the two adjacent transition lines in the orthographic projection of the substrate substrate mirror each other with the first extension of the adjacent transition line in the orthographic projection of the substrate substrate. Any of the second virtual signal lines in the orthographic projection of the substrate substrate mirror each other with adjacent second virtual signal lines in the orthographic projection of the substrate substrate.

7. The display panel of claim 6, wherein, The first virtual signal line includes a first segment and a second segment, the second virtual signal line includes a third segment and a fourth segment, the first segment and the third segment are oppositely arranged in the second direction, and the second segment and the fourth segment are oppositely arranged in the second direction; Wherein, the distance between any point on the first segment of the first virtual signal line between adjacent pixel rows in the orthographic projection of the substrate substrate and the transition line of the next pixel row in the orthographic projection of the substrate substrate in the second direction is L5, the distance between any point on the third segment of the second virtual signal line and the second virtual signal line of the next virtual pixel row in the orthographic projection of the substrate substrate in the second direction is L6, L5=L6; The distance between any point on the second segment of the first virtual signal line between adjacent pixel rows in the orthographic projection of the substrate substrate and the transition line of the next pixel row in the orthographic projection of the substrate substrate in the second direction is L7, the distance between any point on the fourth segment of the second virtual signal line and the second virtual signal line of the next virtual pixel row in the orthographic projection of the substrate substrate in the second direction is L8, L7=L8.

8. The display panel of claim 7, wherein, L5 9. The display panel of claim 6, wherein, The gate of the fifth transistor is connected to an enable signal line, the first electrode of the fifth transistor is connected to the first electrode of the driving transistor, and the gate of the fourth transistor is connected to a first gate line; The display panel further comprises: A first active layer between the substrate substrate and the fifth conductive layer, the first active layer comprising: A fifth active part for forming a channel region of the fifth transistor; A fourth active part for forming a channel region of the fourth transistor; A first conductive layer between the first active layer and the fifth conductive layer, the first conductive layer comprising: The enable signal line, in the orthographic projection of the substrate substrate, extends along the first direction, the enable signal line in the orthographic projection of the substrate substrate covers the fifth active part, part of the structure of the enable signal line is used to form the gate of the fifth transistor; The third conductive layer is located between the first conductive layer and the fifth conductive layer, and the third conductive layer comprises: The first gate line, in the orthographic projection of the substrate substrate, extends along the first direction, the first gate line in the orthographic projection of the substrate substrate covers the fourth active part in the orthographic projection of the substrate substrate, part of the structure of the first gate line is used to form the gate of the fourth transistor; The fifth conductive layer further comprises: The first power supply line, in the orthographic projection of the substrate substrate, extends along the second direction; Among the same pixel driving circuit, the first extension part in the adapter line is located between the first gate line substrate substrate and the enable signal line substrate substrate in the orthographic projection of the substrate substrate.

10. The display panel of claim 9, wherein, The display panel comprises a plurality of pixel driving circuits, and a plurality of pixel driving circuits are arranged in the first direction and the second direction; The pixel driving circuit further comprises a first transistor, the first electrode of the first transistor is connected to the gate of the driving transistor through the eighth transistor, and the gate is connected to the reset signal line; The first active layer further comprises: A first active part is used to form a channel region of the first transistor; The first conductive layer further comprises: The reset signal line, in the orthographic projection of the substrate substrate, extends along the first direction, the reset signal line in the orthographic projection of the substrate substrate covers the first active part in the orthographic projection of the substrate substrate, part of the structure of the reset signal line is used to form the gate of the first transistor; Wherein, the first virtual signal line in the orthographic projection of the substrate substrate and the reset signal line in the orthographic projection of the substrate substrate partially overlap.

11. The display panel of claim 10, wherein, The pixel driving circuit further comprises a storage capacitor, a sixth transistor and a seventh transistor, the first electrode of the storage capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power supply line; The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the seventh transistor, and the gate is connected to the enable signal line; The second electrode of the seventh transistor is connected to the second initial signal line, and the gate is connected to the reset signal line; The second electrode of the first transistor is connected to the first initial signal line; The first active layer further comprises: A third active part is used to form a channel region of the driving transistor; The first conductive layer further comprises: A first conductive part, in the orthographic projection of the substrate substrate, covers the third active part in the orthographic projection of the substrate substrate, and the first conductive part is used to form the gate of the driving transistor and the first electrode of the storage capacitor; The third conductive layer further comprises: The first initial signal line, in the orthographic projection of the substrate substrate, extends along the first direction; The display panel further comprises a fourth conductive layer located between the fifth conductive layer and the third conductive layer, and the fourth conductive layer comprises: The second initial signal line, in the orthographic projection of the substrate substrate, extends along the first direction; The orthographic projection of the first gate line on the substrate substrate, the orthographic projection of the enable signal line on the substrate substrate are located on both sides of the orthographic projection of the first conductive part on the substrate substrate.

12. The display panel of claim 11, wherein, The first direction is a row direction, and the second direction is a column direction. The orthographic projection of the reset signal line of the previous row on the substrate substrate covers the orthographic projection of the first active part of the current row on the substrate substrate, part of the structure of the reset signal line of the previous row is used to form the gate of the first transistor of the current row, and the orthographic projection of the reset signal line of the previous row on the substrate substrate is located on the side of the orthographic projection of the first gate line of the current row on the substrate substrate away from the orthographic projection of the first conductive part of the current row on the substrate substrate.

13. The display panel of claim 11, wherein, The display panel further comprises: The second conductive layer is located between the first conductive layer and the third conductive layer, and the second conductive layer comprises: The second conductive part, in the orthographic projection of the substrate substrate, partially overlaps with the orthographic projection of the first conductive part on the substrate substrate, the second conductive part is used to form the second electrode of the storage capacitor, and the second conductive part is connected to the first power supply line through the via hole.

14. The display panel of claim 13, wherein, The first direction is a row direction, and the second direction is a column direction. The display panel comprises a plurality of repeating units distributed along the row and column directions, and each repeating unit comprises two pixel drive circuits adjacent in the row direction. In the same repeating unit, the two first power supply lines are connected and the two second conductive parts are connected. In the repeating units adjacent in the row direction, the adjacent second conductive parts are connected.

15. The display panel of claim 14, wherein, In the same repeating unit, the two pixel drive circuits adjacent in the row direction are mirror images of each other.

16. The display panel of claim 5, wherein, The pixel drive circuit further comprises a fifth transistor, a seventh transistor and a storage capacitor, the first electrode of the fifth transistor is connected to the first electrode of the drive transistor, and the second electrode is connected to the first power supply line; the first electrode of the seventh transistor is connected to the second electrode of the drive transistor through the sixth transistor, and the second electrode is connected to the second initial signal line; The first electrode of the storage capacitor is connected to the gate of the drive transistor, and the second electrode is connected to the first power supply line. The display panel further comprises: The first active layer is located between the substrate substrate and the fifth conductive layer, and the first active layer comprises: The third active part is used to form the channel region of the drive transistor. The fifth active part is used to form the channel region of the fifth transistor. The seventh active part is used to form the channel region of the seventh transistor. The ninth active part is connected to one end of the seventh active part and is used to form the second electrode of the seventh transistor. The tenth active part is located on one side of the seventh active part and is used to form the first electrode of the seventh transistor. The fourteenth active part is connected to one side of the fifth active part and is used to form the second electrode of the fifth transistor. The first conductive layer is located between the substrate substrate and the first active layer, and the first conductive layer comprises: A first conductive part, in a projection of the substrate substrate covering a projection of the third active part on the substrate substrate, the first conductive part is used to form a gate of the driving transistor and a first electrode of the storage capacitor; A second conductive layer between the first active layer and the fifth conductive layer, the second conductive layer comprises: A second conductive part, in a projection of the substrate substrate and a projection of the first conductive part on the substrate substrate, the second conductive part is used to form a second electrode of the storage capacitor, and the second conductive part is connected to the first power line through a via hole; A fourth conductive layer between the fifth conductive layer and the second conductive layer, the fourth conductive layer comprises: The second initial signal line, in the projection of the substrate substrate along the first direction, the second initial signal line is connected to the ninth active part through a first via hole; The first bridge part is connected to the fourteenth active part and the second conductive part through a second via hole and a third via hole respectively, and is connected to the first power line through another via hole.

17. The display panel of claim 16, wherein, The first direction is the row direction, and the second direction is the column direction; The display panel comprises a plurality of repeating units distributed along the row and column directions, and each repeating unit comprises two pixel driving circuits adjacent in the row direction; The two ninth active parts in the same repeating unit are connected and share the first via hole; In the repeating units adjacent in the row direction, the adjacent first bridge parts are connected and share the second via hole and the third via hole.

18. The display panel of claim 16, wherein, In the repeating units adjacent in the row direction, the adjacent first bridge parts are mirror images of each other.

19. The display panel of claim 15, wherein, The pixel driving circuit further comprises a first transistor, a second transistor and an eighth transistor, the first electrode of the first transistor is connected to the second electrode of the second transistor, and the second electrode is connected to a first initial signal line; the first electrode of the second transistor is connected to the second electrode of the driving transistor, and the gate is connected to a first gate line; The first electrode of the eighth transistor is connected to the gate of the driving transistor, the second electrode is connected to the first electrode of the first transistor, and the gate is connected to a third gate line; The display panel further comprises: A second active layer between the second conductive layer and the fourth conductive layer, the second active layer comprises: An eighth active part for forming a channel region of the eighth transistor; An eleventh active part connected to one side of the eighth active part for forming a first electrode of the eighth transistor; A twelfth active part connected to the other side of the eighth active part for forming a second electrode of the eighth transistor; A third conductive layer between the second active layer and the fourth conductive layer, the third conductive layer comprises: A second gate line, in the projection of the substrate substrate along the first direction, the second gate line covers the projection of the eighth active part on the substrate substrate, and part of the structure of the second gate line is used to form a top gate of the eighth transistor; The first initial signal line, in the projection of the substrate substrate along the first direction; The second conductive layer further comprises: A third gate line extending along a projection of the substrate substrate in the first direction, a portion of the third gate line covering a projection of the eighth active part on the substrate substrate, the portion of the third gate line being configured to form a bottom gate of the eighth transistor; The first active layer further includes: A first active part configured to form a channel region of the first transistor; A seventeenth active part connected to one side of the first active part and configured to form a first electrode of the first transistor; An eighteenth active part connected to another side of the first active part and configured to form a second electrode of the first transistor; A fourth active part configured to form a channel region of the fourth transistor; A fifteenth active part connected to one side of the fourth active part and configured to form a first electrode of the fourth transistor; A second active part configured to form a channel region of the second transistor; A nineteenth active part connected between the second active part and the third active part and configured to form a first electrode of the second transistor; A twentieth active part connected between the second active part and the seventeenth active part and configured to form a second electrode of the second transistor; The fourth conductive layer further includes: A second bridge part having one end connected to the eleventh active part through a via and the other end connected to the first conductive part through a via; A third bridge part having one end connected to the seventeenth active part through a via and the other end connected to the twelfth active part through a via; A fourth bridge part having one end connected to the eighteenth active part through a via and the other end connected to the first initial signal line through a via; A third conductive part connected to the fifteenth active part and the data line through vias.

20. The display panel of claim 16, wherein, The display panel further includes: A fourth conductive layer between the substrate substrate and the fifth conductive layer, the fourth conductive layer including: A first bridge part connected to the tenth active part through a via; The fifth conductive layer further includes: A second bridge part connected to the first bridge part through a via; The sixth conductive layer further includes: A third bridge part connected to the second bridge part through a via; The display panel further includes: A pixel definition layer on a side of the sixth conductive layer away from the substrate substrate and including a plurality of pixel openings, wherein a projection of at least some pixel openings in the first display area on the substrate substrate is located on a projection of the bridge line on the substrate substrate and a projection of the first dummy signal line on the substrate substrate, and a projection of at least some pixel openings in the second display area on the substrate substrate is located on a projection of two adjacent second dummy signal lines on the substrate substrate.

21. A display device comprising: The display panel of any one of claims 1-20.

Images