Counting circuit and operating system

Abstract

A counting circuit and operating system provide an output count value. A switching circuit provides one of first and second input signals as a first output signal and the other of the first and second input signals as a second output signal in response to a first select signal. A mode select circuit provides the first and second output signals as first and second channel signals or the first and second output signals as third and fourth channel signals in response to a second select signal. A first processing circuit adjusts a first count value when the first channel signal or the second channel signal changes from a first level to a second level. A second processing circuit adjusts a second count value when the third channel signal changes from the first level to the second level. An output circuit provides the first or second count value as the output count value.

Description

Technical Field

[0001] This invention relates to a counting circuit and an operating system, and more particularly to a counting circuit having multiple counting modes and an operating system having said counting circuit. Background Technology

[0002] With the advancement of technology, electronic devices are becoming increasingly diverse in type and function. Among common electronic devices, counting circuits are a particularly important component. However, existing counting circuits have a single counting mode and operate using fixed rules. Therefore, existing counting circuits have limited flexibility. Summary of the Invention

[0003] An embodiment of the present invention provides a counting circuit and operating system for providing an output count value to a central processing unit, and includes a switching circuit, a mode selection circuit, a first processing circuit, a second processing circuit, and an output circuit. The switching circuit receives a first input signal and a second input signal, and, according to a first selection signal, uses the first input signal and the second input signal as a first output signal and a second output signal, respectively, or uses the second input signal and the first input signal as a first output signal and a second output signal, respectively. The mode selection circuit is coupled to the switching circuit, and, according to a second selection signal, uses the first output signal and the second output signal as a first channel signal and a second channel signal, or uses the first output signal and the second output signal as a third channel signal and a fourth channel signal. When the first channel signal or the second channel signal changes from a first level to a second level, the first processing circuit adjusts a first count value. When the third channel signal changes from a first level to a second level, the second processing circuit adjusts a second count value. The output circuit uses the first count value or the second count value as the output count value.

[0004] The present invention also provides an operating system, including a counting circuit, a timer, and a central processing unit. The counting circuit provides an output count value and includes a switching circuit, a mode selection circuit, a first processing circuit, a second processing circuit, and an output circuit. The switching circuit receives a first input signal and a second input signal, and, according to a first selection signal, uses the first input signal and the second input signal as a first output signal and a second output signal, respectively, or uses the second input signal and the first input signal as a first output signal and a second output signal, respectively. The mode selection circuit is coupled to the switching circuit and, according to a second selection signal, uses the first output signal and the second output signal as a first channel signal and a second channel signal, or uses the first output signal and the second output signal as a third channel signal and a fourth channel signal. When the first channel signal or the second channel signal changes from a first level to a second level, the first processing circuit adjusts a first count value. When the third channel signal changes from a first level to a second level, the second processing circuit adjusts a second count value. The output circuit uses the first count value or the second count value as the output count value. The timer calculates the operating times of the first and second processing circuits to provide a time value. The central processing unit executes a specific action based on the output count value and the time value. Attached Figure Description

[0005] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 This is a schematic diagram of the counting circuit of the present invention.

[0007] Figure 2A This is a schematic diagram of the operation of the processing circuit of the present invention.

[0008] Figure 2B This is another schematic diagram of the processing circuit of the present invention.

[0009] Figures 3A-3C This is a schematic diagram illustrating other operations of the processing circuit of the present invention.

[0010] Figure 4 This is another schematic diagram of the counting circuit of the present invention.

[0011] Figure 5 This is a schematic diagram of an application of the counting circuit of the present invention.

[0012] [Icon Numbers]

[0013] 100, 400, 520: Counting circuit

[0014] 110, 410: Switching circuits

[0015] 120, 420: Mode selection circuit

[0016] 130, 140, 430, 440, 450: Processing circuits

[0017] 150, 460: Output circuit

[0018] INA, INB: Input signals

[0019] OCV: Output Count Value

[0020] SEL1~SEL5: Selection Signals

[0021] OTA, OTB: Output signals

[0022] 111, 112, 142, 151, 473, 474: Multitasking

[0023] CHA_0~CHA_2, CHB_0~CHB_2: Channel signals

[0024] MODE_0_En~MODE_2_En: Control signals

[0025] 121–124, 421–426: Logic gates

[0026] CV_0~CV_2: Count values

[0027] 131, 141, 441: Edge detection circuits

[0028] 132, 143, 442: Counters

[0029] UP_0, UP_1: Up-counting signals

[0030] DN_0, DN_1: count down signal

[0031] ST: Trigger signal

[0032] L0, L1: Default values

[0033] QA, QB, EXA, EXB: external signals

[0034] 470: Receiver circuit

[0035] 471, 472: Inverters

[0036] 500: Operating System

[0037] 510: External devices

[0038] 530: Timer

[0039] 540: Central Processing Unit

[0040] SEL: Select Data

[0041] TV: Time Value Detailed Implementation

[0042] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the components in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0043] Figure 1 This is a schematic diagram of the counting circuit of the present invention. As shown, the counting circuit 100 includes a swap circuit 110, a mode selection circuit 120, processing circuits 130 and 140, and an output circuit 150. In this embodiment, the counting circuit 100 has at least two counting modes. In different counting modes, the counting circuit 100 uses different rules to perform different counting operations on the input signals INA and INB, and after the counting operation is completed, provides an output count value OCV to an external circuit (not shown), such as a central processing unit. The external circuit performs a specific action based on the output count value OCV. In one possible embodiment, the external circuit infers the operating state of the device providing the input signals INA and INB based on the output count value OCV.

[0044] The switching circuit 110 receives input signals INA and INB, and, according to a selection signal SEL1, uses the input signals INA and INB as output signals OTA and OTB, or, according to the selection signal SEL1, uses the input signals INA and INB as output signals OTB and OTA. The selection signal SEL1 may be provided by an external device (not shown).

[0045] This invention does not limit the architecture of the switching circuit 110. In one possible embodiment, the switching circuit 110 includes multiplexers 111 and 112. Multiplexer 111 receives input signals INA and INB, and, according to selection signal SEL1, uses either input signal INA or INB as output signal OTA. Multiplexer 112 receives input signals INA and INB, and, according to selection signal SEL1, uses either input signal INA or INB as output signal OTB. In this embodiment, when multiplexer 111 uses input signal INA as output signal OTA, multiplexer 112 uses input signal INB as output signal OTB. When multiplexer 111 uses input signal INB as output signal OTA, multiplexer 112 uses input signal INA as output signal OTB.

[0046] The mode selection circuit 120 is coupled to the switching circuit 110 and, according to a selection signal SEL2, uses the output signals OTA and OTB as channel signals CHA_0 and CHB_0, respectively, or uses the output signals OTA and OTB as channel signals CHA_1 and CHB_1, respectively. In this embodiment, the selection signal SEL2 includes control signals MODE_0_En and MODE_1_En. When the control signal MODE_0_En is equal to a specific level (such as a low level) and the control signal MODE_1_En is not equal to the specific level, the mode selection circuit 120 enters a first mode. In the first mode, the mode selection circuit 120 uses the output signals OTA and OTB as channel signals CHA_1 and CHB_1. At this time, the channel signals CHA_0 and CHB_0 may be equal to the specific level. However, when the control signal MODE_0_En is not equal to the specific level and the control signal MODE_1_En is equal to the specific level, the mode selection circuit 120 enters a second mode. In the second mode, the mode selection circuit 120 uses the output signals OTA and OTB as channel signals CHA_0 and CHB_0. At this time, the channel signals CHA_1 and CHB_1 may be equal to a specific level.

[0047] In other embodiments, when the control signals MODE_0_En and MODE_1_En are not equal to a specific level, the mode selection circuit 120 enters a third mode. In the third mode, the mode selection circuit 120 uses not only the output signals OTA and OTB as channel signals CHA_0 and CHB_0, but also the output signals OTA and OTB as channel signals CHA_1 and CHB_1.

[0048] This invention does not limit the architecture of the mode selection circuit 120. In one possible embodiment, the mode selection circuit 120 includes logic gates 121 to 124. Logic gate 121 receives the output signal OTA and the control signal MODE_0_En, and generates the channel signal CHA_0. Logic gate 122 receives the output signal OTB and the control signal MODE_0_En, and generates the channel signal CHB_0. Logic gate 123 receives the output signal OTA and the control signal MODE_1_En, and generates the channel signal CHA_1. Logic gate 124 receives the output signal OTB and the control signal MODE_1_En, and generates the channel signal CHB_1.

[0049] This invention does not limit the types of logic gates 121 to 124. In one possible embodiment, logic gates 121 to 124 are all AND gates. Since the operation of logic gates 121 to 124 is similar, only logic gate 121 will be used as an example below. When the control signal MODE_0_En is equal to a specific level, regardless of the level of the output signal OTA (high or low), logic gate 121 sets the channel signal CHA_0 to a specific level, such as a low level. However, when the control signal MODE_0_En is not equal to a specific level, logic gate 121 adjusts the channel signal CHA_0 according to the output signal OTA. At this time, if the output signal OTA is a first level, logic gate 121 sets the channel signal CHA_0 to the first level. When the output signal OTA is a second level, logic gate 121 sets the channel signal CHA_0 to the second level.

[0050] Processing circuit 130 provides a count value CV_0 based on channel signals CHA_0 and CHB_0. In this embodiment, processing circuit 130 adjusts the count value CV_0 when the channel signal CHA_0 or CHB_0 changes from a first level to a second level. In other embodiments, processing circuit 130 also adjusts the count value CV_0 when the channel signal CHA_0 or CHB_0 returns from the second level to the first level. In other embodiments, processing circuit 130 increases the count value CV_0 when the channel signal CHA_0 leads the channel signal CHB_0. In this example, processing circuit 130 decreases the count value CV_0 when the channel signal CHA_0 lags the channel signal CHB_0.

[0051] Figure 2AThis is a schematic diagram of the operation of the processing circuit 130 of the present invention. When the channel signal CHB_0 changes from a first level (e.g., a low level) to a second level (e.g., a high level) and the channel signal CHA_0 is at the second level, it indicates that the channel signal CHA_0 leads the channel signal CHB_0. Therefore, the processing circuit 130 increments the count value CV_0. However, when the channel signal CHA_0 changes from the second level to the first level and the channel signal CHB_0 is at the first level, it indicates that the channel signal CHA_0 lags behind the channel signal CHB_0. Therefore, the processing circuit 130 decrements the count value CV_0.

[0052] In some embodiments, when channel signal CHB_0 returns from a second level (e.g., high level) to a first level (e.g., low level) and channel signal CHA_0 is at the first level, it indicates that channel signal CHA_0 leads channel signal CHB_0. Therefore, processing circuit 130 increments the count value CV_0. However, when channel signal CHB_0 returns from a second level to the first level, if channel signal CHA_0 is at the second level, it indicates that channel signal CHA_0 lags behind channel signal CHB_0. Therefore, processing circuit 130 decrements the count value CV_0.

[0053] In other embodiments, when the channel signal CHA_0 changes from a first level to a second level and the channel signal CHB_0 is at the second level, it indicates that the channel signal CHA_0 lags behind the channel signal CHB_0. Therefore, the processing circuit 130 decrements the count value CV_0. However, when the channel signal CHA_0 changes from the first level to the second level, if the channel signal CHB_0 is at the first level, it indicates that the channel signal CHA_0 leads the channel signal CHB_0. Therefore, the processing circuit 130 increments the count value CV_0.

[0054] Figure 2B This is another schematic diagram of the operation of the processing circuit 130 of the present invention. When the channel signal CHA_0 changes from a first level (e.g., low level) to a second level (e.g., high level), if the channel signal CHB_0 is at the second level, the processing circuit 130 increments the count value CV_0. However, when the channel signal CHB_0 changes from the first level to the second level, if the channel signal CHA_0 is at the second level, the processing circuit 130 decrements the count value CV_0.

[0055] In this embodiment, when the channel signal CHA_0 returns from the second level to the first level, the processing circuit 130 does not adjust the count value CV_0. In this example, when the channel signal CHB_0 returns from the second level to the first level, the processing circuit 130 does not adjust the count value CV_0. In other embodiments, when the channel signal CHA_0 returns from the second level to the first level, if the channel signal CHB_0 is at the second level, the processing circuit 130 increases the count value CV_0. In this example, when the channel signal CHB_0 returns from the second level to the first level, if the channel signal CHA_0 is at the second level, the processing circuit 130 decreases the count value CV_0.

[0056] This invention does not limit the architecture of the processing circuit 130. Figure 1 In the process circuit 130, an edge detection circuit 131 and a counter 132 are included. The edge detection circuit 131 enables an up-counting signal UP_0 or a down-counting signal DN_0 based on the levels of the channel signals CHA_0 and CHB_0. This invention does not limit the type of edge detection circuit 131. In one possible embodiment, the edge detection circuit 131 is a rising / falling detector.

[0057] When the channel signal CHA_0 changes from a first level (e.g., a low level) to a second level (e.g., a high level), if the channel signal CHB_0 is at the first level, the edge detection circuit 131 enables the up-counting signal UP_0. When the channel signal CHA_0 changes from the second level to the first level, if the channel signal CHB_0 is at the second level, the edge detection circuit 131 enables the down-counting signal DN_0. When the channel signal CHA_0 changes from the second level to the first level, if the channel signal CHB_0 is at the first level, the edge detection circuit 131 enables the down-counting signal DN_0.

[0058] Counter 132 adjusts the count value CV_0 based on the up count signal UP_0 and the down count signal DN_0. In one possible embodiment, counter 132 increments the count value CV_0 when the up count signal UP_0 is enabled. In this example, counter 132 decrements the count value CV_0 when the down count signal DN_0 is enabled.

[0059] Processing circuit 140 receives channel signals CHA_1 and CHB_1 and provides a count value CV_1. In one possible embodiment, when the channel signal CHA_1 changes from a first level (e.g., low level) to a second level (e.g., high level), processing circuit 140 adjusts the count value CV_1. In other embodiments, when the channel signal CHA_1 returns from the second level to the first level, processing circuit 140 adjusts the count value CV_1 again.

[0060] In this embodiment, the processing circuit 140 operates in a first mode, a second mode, and a third mode according to a selection signal SEL3. Figure 3A This is a schematic diagram of the processing circuit 140 of the present invention operating in a first mode. In the first mode, when the channel signal CHA_1 changes from a first level (e.g., a low level) to a second level (e.g., a high level), if the channel signal CHB_1 is at the second level, the processing circuit 140 increments the count value CV_1. However, when the channel signal CHA_1 changes from the first level to the second level, if the channel signal CHB_1 is at the first level, the processing circuit 140 decrements the count value CV_1.

[0061] In some embodiments, when the channel signal CHA_1 returns from the second level to the first level, if the channel signal CHB_1 is at the second level, the processing circuit 140 increments the count value CV_1. In this example, when the channel signal CHA_1 returns from the second level to the first level, if the channel signal CHB_1 is at the first level, the processing circuit 140 decrements the count value CV_1.

[0062] Figure 3B This is a schematic diagram of the processing circuit 140 of the present invention operating in a second mode. In the second mode, when the channel signal CHA_1 changes from a first level to a second level, the processing circuit 140 increments the count value CV_1. In the second mode, regardless of whether the channel signal CHB_1 is high or low, the processing circuit 140 increments the count value CV_1 only according to the change in the level of the channel signal CHA_1. In other words, in the second mode, the processing circuit 140 ignores the channel signal CHB_1.

[0063] Figure 3C This is a schematic diagram of the processing circuit 140 of the present invention operating in a third mode. In the third mode, when the channel signal CHA_1 changes from a first level to a second level, the processing circuit 140 decrements the count value CV_1. In this mode, regardless of the level of the channel signal CHB_1, the processing circuit 140 decrements the count value CV_1 only based on the level change of the channel signal CHA_1. In other words, in the third mode, the processing circuit 140 ignores the channel signal CHB_1.

[0064] This invention does not limit the architecture of the processing circuit 140. In one possible embodiment, the processing circuit 140 includes an edge detection circuit 141, a multiplexer 142, and a counter 143. The edge detection circuit 141 determines whether to enable a trigger signal ST based on the level of the channel signal CHA_1. For example, when the channel signal CHA_1 changes from a first level to a second level, the edge detection circuit 141 enables the trigger signal ST. In some embodiments, when the channel signal CHA_1 returns from the second level to the first level, the edge detection circuit 141 enables the trigger signal ST again.

[0065] The multiplexer 142 receives the channel signal CHB_1, the default value L1, and L0. In this embodiment, the multiplexer 142 outputs the channel signal CHB_1, the default value L1, or L0 according to the selection signal SEL3. In one possible embodiment, the default value L1 is a high level, and the default value L0 is a low level.

[0066] Counter 143 adjusts the count value CV_1 based on the trigger signal ST and the output of multiplexer 142. In one possible embodiment, when the trigger signal ST is enabled and multiplexer 142 outputs channel signal CHB_1, counter 143 adjusts the count value CV_1 according to the level of channel signal CHB_1. In this example, if channel signal CHB_1 is at the second level, counter 143 increments the count value CV_1. If channel signal CHB_1 is at the first level, counter 143 decrements the count value CV_1. In other embodiments, when the trigger signal ST is enabled and multiplexer 142 outputs a default value L1, counter 143 increments the count value CV_1. In some embodiments, when the trigger signal ST is enabled and multiplexer 142 outputs a default value L0, counter 143 decrements the count value CV_1.

[0067] Output circuit 150 receives count values ​​CV_0 and CV_1 and provides an output count value OCV. In one possible embodiment, output circuit 150 has a multiplexer 151. Multiplexer 151 selects either count value CV_0 or CV_1 as the output count value OCV according to a selection signal SEL4.

[0068] Figure 4 This is another schematic diagram of the counting circuit of the present invention. The counting circuit 400 includes a switching circuit 410, a mode selection circuit 420, processing circuits 430, 440, and 450, an output circuit 460, and a receiving circuit 470. In this embodiment, the counting circuit 400 has three counting modes. In different counting modes, the counting circuit 400 processes external signals QA and QB according to different counting rules to provide an output count value OCV.

[0069] The receiving circuit 470 receives external signals QA and QB, and provides input signals INA and INB according to a selection signal SEL5. In this embodiment, the receiving circuit 470 includes inverters 471 and 472, and multiplexers 473 and 474. Inverter 471 inverts the external signal QA to generate a first inverted signal and outputs the first inverted signal to multiplexer 473. Multiplexer 473 uses either the external signal QA or the first inverted signal as the input signal INA according to the selection signal SEL5. Inverter 472 inverts the external signal QB to generate a second inverted signal and outputs the second inverted signal to multiplexer 474. Multiplexer 474 uses either the external signal QB or the second inverted signal as the input signal INB according to the selection signal SEL5.

[0070] In one possible embodiment, when multiplexer 473 uses external signal QA as input signal INA, multiplexer 474 uses external signal QB as input signal INB. In this example, when multiplexer 473 uses the first inverted signal as input signal INA, multiplexer 474 uses the second inverted signal as input signal INB.

[0071] Switching circuit 410 receives input signals INA and INB, and according to a selection signal SEL1, uses input signals INA and INB as output signals OTA and OTB respectively, or uses input signals INB and INA as output signals OTA and OTB respectively. Because the characteristics of switching circuit 410 are similar to... Figure 1 The switching circuit 110 is described in detail, so it will not be elaborated further.

[0072] The mode selection circuit 420 is coupled to the switching circuit 420 and operates in a first mode, a second mode, or a third mode according to a selection signal SEL2. For example, when the control signal MODE_0_En is not at a specific level and the control signals MODE_1_En and MODE_2_En are at a specific level, the mode selection circuit 420 enters the first mode. In the first mode, the mode selection circuit 420 uses the output signals OTA and OTB as channel signals CHA_0 and CHB_0, and sets the channel signals CHA_1 and CHB_1, CHA_2 and CHB_2 to a specific level.

[0073] When the control signal MODE_1_En is not at a specific level and the control signals MODE_0_En and MODE_2_En are at a specific level, the mode selection circuit 420 enters the second mode. In the second mode, the mode selection circuit 420 uses the output signals OTA and OTB as channel signals CHA_1 and CHB_1, and sets the channel signals CHA_0 and CHB_0, CHA_2 and CHB_2 to a specific level.

[0074] When the control signal MODE_2_En is not at a specific level and the control signals MODE_0_En and MODE_1_En are at a specific level, the mode selection circuit 420 enters the third mode. In the third mode, the mode selection circuit 420 uses the output signals OTA and OTB as the channel signals CHA_2 and CHB_2, and sets the channel signals CHA_0 and CHB_0, CHA_1 and CHB_1 to a specific level.

[0075] In some embodiments, when the control signals MODE_0_En to MODE_2_En are not at a specific level, the mode selection circuit 420 enters a fourth mode. In the fourth mode, the mode selection circuit 420 treats the output signals OTA and OTB as channel signals CHA_0 and CHB_0, CHA_1 and CHB_1, and CHA_2 and CHB_2 at a specific level. In this example, channel signal CHA_0 is equal to channel signals CHA_1 and CHA_2, and channel signal CHB_0 is equal to channel signals CHB_1 and CHB_2.

[0076] In this embodiment, the mode selection circuit 420 includes logic gates 421 to 426. Since the characteristics of logic gates 421, 422, 425, and 426 are similar... Figure 1 The characteristics of logic gates 121-124 are not described in detail here. Logic gate 423 receives the output signal OTA and the control signal MODE_2_En, and generates the channel signal CHA_2. Logic gate 424 receives the output signal OTB and the control signal MODE_2_En, and generates the channel signal CHB_2. When the control signal MODE_2_En is not at a specific level, logic gates 423 and 424 adjust the levels of the channel signals CHA_2 and CHB_2 according to the levels of the output signals OTA and OTB, respectively. At this time, the levels of the channel signals CHA_2 and CHB_2 are the same as the levels of the output signals OTA and OTB. In this embodiment, logic gates 423 and 424 are both AND gates.

[0077] Processing circuit 430 receives channel signals CHA_0 and CHB_0 and generates a count value CV_0. Due to the characteristics of processing circuit 430 and... Figure 1 The characteristics of the processing circuit 130 are similar, so they will not be described again. In this embodiment, when the channel signal CHA_0 leads the channel signal CHB_0, the processing circuit 430 increases the count value CV_0. When the channel signal CHA_0 lags behind the channel signal CHB_0, the processing circuit 430 decreases the count value CV_0.

[0078] Processing circuit 440 receives channel signals CHA_2 and CHB_2 and generates a count value CV_2. In this embodiment, when channel signal CHA_2 or CHB_2 changes from a first level (e.g., low level) to a second level (e.g., high level), processing circuit 440 adjusts the count value CV_2. For example, when channel signal CHA_2 changes from the first level to the second level, if channel signal CHB_2 is at the second level, processing circuit 440 increases the count value CV_2. In this example, when channel signal CHB_2 changes from the first level to the second level, if channel signal CHA_2 is at the second level, processing circuit 440 decreases the count value CV_2. In other embodiments, processing circuit 440 is based on... Figure 2B It operates according to the control timing.

[0079] This invention does not limit the architecture of the processing circuit 440. In one possible embodiment, the processing circuit 440 includes an edge detection circuit 441 and a counter 442. The edge detection circuit 441 enables an up-counting signal UP_1 or a down-counting signal UP_2 based on the levels of the channel signals CHA_2 and CHB_2. For example, when the channel signal CHA_2 changes from a first level to a second level, if the channel signal CHB_2 is at the second level, the edge detection circuit 441 enables the up-counting signal UP_1. When the channel signal CHB_2 changes from a first level to a second level, if the channel signal CHA_2 is at the second level, the edge detection circuit 441 enables the down-counting signal DN_1.

[0080] Counter 442 adjusts the count value CV_2 based on the up count signal UP_1 and the down count signal DN_1. In one possible embodiment, counter 442 increments the count value CV_2 when the up count signal UP_1 is enabled. In this example, counter 442 decrements the count value CV_2 when the down count signal DN_1 is enabled.

[0081] Processing circuit 450 receives channel signals CHA_1 and CHB_1, and adjusts the count value CV_1 according to selection signal SEL3. Due to the characteristics of processing circuit 450 and... Figure 1 The characteristics of the processing circuit 140 are similar, so they will not be described in detail here.

[0082] The output circuit 460 selects one of the count values ​​CV_0 to CV_2 as the output count value OCV based on the selection signal SEL4. In this embodiment, the characteristics of the output circuit 460 are similar to... Figure 1 The characteristics of the output circuit 150 are similar, so they will not be described in detail here.

[0083] Figure 5This is a schematic diagram illustrating an application of the counting circuit of the present invention. As shown, the operating system 500 includes an external device 510, a counting circuit 520, a timer 530, and a central processing unit 540. The external device 510 provides external signals EXA and EXB. The present invention does not limit the type of external device 510. In one possible embodiment, the external device 510 is a motor.

[0084] The counting circuit 520 receives external signals EXA and EXB, and operates in different counting modes according to a selection data SEL. In different counting modes, the counting circuit 520 processes the external signals EXA and EXB according to different counting rules to provide an output count value OCV. In one possible embodiment, the architecture of the counting circuit 520 is the same as... Figure 1 The counting circuit 100. In this example, external signals EXA and EXB are used as... Figure 1 The input signals INA and INB. Additionally, the selection data SEL includes selection signals SEL1 to SEL4. In another possible embodiment, the architecture of the counting circuit 520 is the same as... Figure 4 The counting circuit 400. In this example, external signals EXA and EXB are used as... Figure 4 External signals QA and QB. Additionally, the selection data SEL includes selection signals SEL1 to SEL5.

[0085] Timer 530 performs a timing operation to provide a time value TV. Figure 1 For example, timer 530 is used to calculate the operating time of processing circuits 130 and 140, and provides the calculation result (i.e., time value TV) to the central processing unit 540. In other embodiments, timer 530 is used to calculate Figure 4 The processing circuits 430, 440 and 450 are used to calculate the operating time and provide the calculation result (i.e., the time value TV) to the central processing unit 540.

[0086] The central processing unit 540 executes a specific action based on the time value TV and the output count value OCV. In one possible embodiment, this specific action is to infer the operating state of the external device 510. For example, if the external device 510 is a motor, the central processing unit 540 can infer the motor's speed and direction of rotation based on the time value TV and the output count value OCV. In other embodiments, the central processing unit 540 executes program code (not shown) to generate selection data SEL.

[0087] Because the counting circuit 520 has a switching circuit (such as...) Figure 1 110 or Figure 4Therefore, when the external device 510 mistakenly reverses the output of external signals EXA and EXB, the central processing unit 540 can use the selection information SEL to command the switching circuit in the counting circuit 520 to reverse the external signals EXA and EXB. Thus, the processing circuits (such as 130, 140, 430, 440, and 450) in the counting circuit 520 can generate the correct counting value.

[0088] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various components, these components should not be limited by these terms. These terms are merely used to distinguish one component from another.

[0089] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in hardware, software, or combinations thereof. Therefore, the scope of protection of the present invention is determined by the claims.

Claims

1. A counting circuit for providing an output count value to a central processing unit, comprising: A switching circuit receives a first input signal and a second input signal, and according to a first selection signal, uses the first input signal and the second input signal as a first output signal and a second output signal, respectively, or uses the second input signal and the first input signal as the first output signal and the second output signal, respectively. A mode selection circuit is coupled to the switching circuit and, according to a second selection signal, uses the first output signal and the second output signal as a first channel signal and a second channel signal, or uses the first output signal and the second output signal as a third channel signal and a fourth channel signal. A first processing circuit adjusts a first count value when the first channel signal or the second channel signal changes from a first level to a second level; A second processing circuit adjusts a second counter value when the third channel signal changes from the first level to the second level; and An output circuit that uses either the first count value or the second count value as the output count value. in: The switching circuit includes a first multiplexer and a second multiplexer. When the first multiplexer uses the first input signal as the first output signal, the second multiplexer uses the second input signal as the second output signal. When the first multiplexer uses the second input signal as the first output signal, the second multiplexer uses the first input signal as the second output signal. The second selection signal includes a first control signal and a second control signal. When the first control signal and the second control signal are not equal to a specific level, the mode selection circuit not only uses the first output signal and the second output signal as the first channel signal and the second channel signal, but also uses the first output signal and the second output signal as the third channel signal and the fourth channel signal.

2. The counting circuit as described in claim 1, characterized in that, When the mode selection circuit uses the first output signal and the second output signal as the first channel signal and the second channel signal, the mode selection circuit sets the third channel signal and the fourth channel signal to be equal to the specific level.

3. The counting circuit as described in claim 1, characterized in that, When the first channel signal leads the second channel signal, the first processing circuit increases the first count value; when the first channel signal lags behind the second channel signal, the first processing circuit decreases the first count value.

4. The counting circuit as described in claim 1, characterized in that, When the first channel signal changes from the first level to the second level and the second channel signal is at the second level, the first processing circuit increases the first count value; when the second channel signal changes from the first level to the second level and the first channel signal is at the first level, the first processing circuit decreases the first count value.

5. The counting circuit as described in claim 1, characterized in that, The first processing circuit includes: A first edge detection circuit enables either a first upper-order signal or a first lower-order signal based on the levels of the first channel signal and the second channel signal; and A first counter increments the first count value when the first up-count signal is enabled, and decrements the first count value when the first down-count signal is enabled. in: When the first channel signal changes from the first level to the second level and the second channel signal is at the first level, the first edge detection circuit enables the first upper-level signal; When the first channel signal changes from the second level to the first level and the second channel signal is at the second level, the first edge detection circuit enables the first upper-level signal; When the first channel signal changes from the first level to the second level and the second channel signal is at the second level, the first edge detection circuit enables the first lower-level signal; When the first channel signal changes from the second level to the first level and the second channel signal is at the first level, the first edge detection circuit enables the first lower number signal.

6. The counting circuit as described in claim 5, characterized in that, The second processing circuit operates in a first mode, a second mode, or a third mode according to a third selection signal; In the first mode, when the third channel signal changes from the first level to the second level and the fourth channel signal is at the second level, the second processing circuit increases the second count value; when the third channel signal changes from the first level to the second level and the fourth channel signal is at the first level, the second processing circuit decreases the second count value. In the second mode, when the third channel signal changes from the first level to the second level, the second processing circuit increases the second count value; In the third mode, when the third channel signal changes from the first level to the second level, the second processing circuit reduces the second count value.

7. The counting circuit as described in claim 6, characterized in that, The second processing circuit includes: A second edge detection circuit enables a trigger signal when the third channel signal changes from the first level to the second level; and A third multiplexer outputs the fourth channel signal, a first default value, or a second default value based on the third selection signal; A second counter is used to adjust the second count value; in: When the trigger signal is enabled and the third multiplexer outputs the fourth channel signal, the second counter adjusts the second count value according to the level of the fourth channel signal; When the trigger signal is enabled and the third multiplexer outputs the first default value, the second counter increments the count value; When the trigger signal is enabled and the third multitasker outputs the second default value, the second counter decrements the count value.

8. The counting circuit as described in claim 7, characterized in that, Also includes: A third processing circuit adjusts a third count value when a fifth channel signal or a sixth channel signal changes from the first level to the second level; The mode selection circuit uses the first output signal and the second output signal as the fifth channel signal and the sixth channel signal according to the second selection signal, and the output circuit uses the first count value, the second count value or the third count value as the output count value.

9. An operating system, characterized in that, include: A counting circuit for providing an output count value, and includes: A switching circuit receives a first input signal and a second input signal, and according to a first selection signal, uses the first input signal and the second input signal as a first output signal and a second output signal, respectively, or uses the second input signal and the first input signal as the first output signal and the second output signal, respectively. A mode selection circuit is coupled to the switching circuit and, according to a second selection signal, uses the first output signal and the second output signal as a first channel signal and a second channel signal, or uses the first output signal and the second output signal as a third channel signal and a fourth channel signal. A first processing circuit adjusts a first count value when the first channel signal or the second channel signal changes from a first level to a second level; A second processing circuit adjusts a second counter value when the third channel signal changes from the first level to the second level; and An output circuit that uses either the first count value or the second count value as the output count value; A timer calculates the operating times of the first processing circuit and the second processing circuit to provide a time value; and A central processing unit executes a specific action based on the output count value and the time value. in: The switching circuit includes a first multiplexer and a second multiplexer. When the first multiplexer uses the first input signal as the first output signal, the second multiplexer uses the second input signal as the second output signal. When the first multiplexer uses the second input signal as the first output signal, the second multiplexer uses the first input signal as the second output signal. The second selection signal includes a first control signal and a second control signal. When the first control signal and the second control signal are not equal to a specific level, the mode selection circuit not only uses the first output signal and the second output signal as the first channel signal and the second channel signal, but also uses the first output signal and the second output signal as the third channel signal and the fourth channel signal.

10. The operating system as described in claim 9, characterized in that, Also includes: A first inverter inverts a first external signal to generate a first inverted signal; A third multiplexer, according to a fourth selection signal, uses either the first external signal or the first inverted signal as the first input signal; A second inverter inverts a second external signal to generate a second inverted signal; as well as A fourth multiplexer, based on the fourth selection signal, uses either the second external signal or the second inverted signal as the second input signal.

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