Intelligent replaceable modular unit for local cooling loops in data center cooling systems

Abstract

An intelligent replaceable modular unit for a local cooling loop in a data center cooling system. Systems and methods for cooling a data center are disclosed. In at least one embodiment, the modular unit is replaceable or hot-swappable and has a heat exchanger, a variable speed fan, and at least one flow controller that passes fluid through microchannels of a cold plate, such that fluid absorbs heat from at least one computing device and such that fluid passing through the heat exchanger is able to dissipate heat through forced air from the variable speed fan.

Description

TECHNICAL FIELD

[0001] At least one embodiment relates to cooling systems, including systems and methods for operating those cooling systems. In at least one embodiment, such cooling systems can be used in data centers containing one or more racks or computing servers. BACKGROUND

[0002] Data center cooling systems use fans to circulate air through server components. Certain supercomputers or other high-capacity computers can use water or other cooling systems instead of air cooling systems to draw heat away from server components or racks of a data center to an area outside of the data center. The cooling system can include a chiller within the data center area (which can include an area outside of the data center itself). Further, the area outside of the data center can include a cooling tower or other external heat exchanger that receives heated coolant from the data center and dissipates heat to the environment (or external cooling medium) through forced air or other means. The cooled coolant is recirculated back into the data center. The chiller and cooling tower together form a cooling plant. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 An example data center cooling system is shown that is improved over at least one embodiment;

[0004] Figure 2 Server-level features associated with intelligent replaceable modular units for data center cooling systems are shown according to at least one embodiment;

[0005] Figure 3 Rack-level features associated with intelligent replaceable modular units for data center cooling systems are shown according to at least one embodiment;

[0006] Figure 4 Data center-level features associated with intelligent replaceable modular units for data center cooling systems are shown according to at least one embodiment;

[0007] Figure 5 Methods associated with a data center cooling system according to at least one embodiment are shown; Figures 2-4

[0008] Figure 6 A distributed system is shown according to at least one embodiment;

[0009] Figure 7 An example data center is shown according to at least one embodiment;

[0010] Figure 8 ​A client-server network is shown in accordance with at least one embodiment;

[0011] Figure 9 A computer network is shown in accordance with at least one embodiment;

[0012] Figure 10A A networked computer system is shown in accordance with at least one embodiment;

[0013] Figure 10B A networked computer system is shown in accordance with at least one embodiment;

[0014] Figure 10C A networked computer system is shown in accordance with at least one embodiment;

[0015] Figure 11 One or more components of a system environment in which services can be offered as third party network services are shown in accordance with at least one embodiment;

[0016] Figure 12 A cloud computing environment is shown in accordance with at least one embodiment;

[0017] Figure 13 A set of functional abstraction layers offered by a cloud computing environment is shown in accordance with at least one embodiment;

[0018] Figure 14 A supercomputer at the chip level is shown in accordance with at least one embodiment;

[0019] Figure 15 A supercomputer at the rack module level is shown in accordance with at least one embodiment;

[0020] Figure 16 A supercomputer at the rack level is shown in accordance with at least one embodiment;

[0021] Figure 17 A supercomputer at the entire system level is shown in accordance with at least one embodiment;

[0022] Figure 18A Inference and / or training logic is shown in accordance with at least one embodiment;

[0023] Figure 18B Inference and / or training logic is shown in accordance with at least one embodiment;

[0024] Figure 19 Training and deployment of a neural network is shown in accordance with at least one embodiment;

[0025] Figure 20 An architecture of a network system is shown in accordance with at least one embodiment;

[0026] Figure 21 An architecture of a network system is shown in accordance with at least one embodiment;

[0027] Figure 22 A control plane protocol stack is shown in accordance with at least one embodiment;

[0028] Figure 23 A user plane protocol stack is shown in accordance with at least one embodiment;

[0029] Figure 24 Components of a core network are shown in accordance with at least one embodiment;

[0030] Figure 25 Components of a system that supports network function virtualization (NFV) are shown in accordance with at least one embodiment;

[0031] Figure 26 A processing system is shown in accordance with at least one embodiment;

[0032] Figure 27 A computer system is shown in accordance with at least one embodiment;

[0033] Figure 28 A system is shown in accordance with at least one embodiment;

[0034] Figure 29 An exemplary integrated circuit is shown in accordance with at least one embodiment;

[0035] Figure 30 A computing system is shown in accordance with at least one embodiment;

[0036] Figure 31 An APU is shown in accordance with at least one embodiment;

[0037] Figure 32 A CPU is shown in accordance with at least one embodiment;

[0038] Figure 33 An exemplary accelerator integration slice is shown in accordance with at least one embodiment;

[0039] Figures 34A-34B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0040] Figure 35A A graphics core is shown in accordance with at least one embodiment;

[0041] Figure 35B A GPGPU is shown in accordance with at least one embodiment;

[0042] Figure 36A A parallel processor is shown in accordance with at least one embodiment;

[0043] Figure 36B A processing cluster is shown in accordance with at least one embodiment;

[0044] Figure 36C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0045] Figure 37 A software stack of a programming platform is shown in accordance with at least one embodiment;

[0046] Figure 38 A CUDA implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0047] Figure 39 An ROCm implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0048] Figure 40 An OpenCL implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0049] Figure 41 Software supported by a programming platform is shown in accordance with at least one embodiment; and

[0050] Figure 42 Compiled code for execution on a programming platform of Figures 37-40 is shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0051] In at least one embodiment, an exemplary data center 100 as shown in Figure 1 can be used with the improved cooling systems described herein. In at least one embodiment, numerous specific details are set forth in order to provide a thorough understanding of the concepts herein but it can be practiced without one or more of these specific details in at least one embodiment. In at least one embodiment, a data center cooling system can respond to sudden high heat demands caused by varying computational loads in today’s computing components. In at least one embodiment, as these demands experience a range of varying or trending from a minimum to a maximum cooling demand, appropriate cooling systems must be used to meet these demands in an economical manner. In at least one embodiment, for moderate to high cooling demands, a liquid cooling system can be used. In at least one embodiment, high cooling demands are economically met by local immersion cooling. In at least one embodiment, these different cooling demands also reflect different thermal signatures of a data center. In at least one embodiment, heat generated from these components, servers, and racks is cumulatively referred to as a thermal signature or cooling demand, as the cooling demand must fully address the thermal signature.

[0052] In at least one embodiment, a data center liquid cooling system is disclosed. In at least one embodiment, the data center cooling system addresses thermal features in associated computing or data center equipment, such as a graphics processing unit (GPU), a switch, a dual in-line memory module (DIMM), or a central processing unit (CPU). In at least one embodiment, these components can be referred to herein as high heat density computing components. Further, in at least one embodiment, the associated computing or data center equipment can be a processing card having one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of the GPUs, switches, and CPUs can be heat generating features of the computing equipment. In at least one embodiment, the GPUs, CPUs, or switches can have one or more cores, and each core can be a heat generating feature.

[0053] In at least one embodiment, the intelligent replaceable modular unit enables redundancy for a liquid data center cooling system using a primary cooling loop to secondary cooling loop architecture. In at least one embodiment, redundancy can be achieved through a local cooling loop having a modular unit. In at least one embodiment, the modular unit is a replaceable, replaceable, or even hot-swappable unit having at least one heat exchanger, a variable speed fan, and at least one flow controller. In at least one embodiment, the modular unit can be adapted to be replaceable and fluidly coupled with a cold plate that can include microchannels. In at least one embodiment, the at least one flow controller of the modular unit can be adapted to cause fluid to pass through the microchannels of the cold plate to draw heat from at least one computing device. In at least one embodiment, the at least one flow controller of the modular unit can be adapted to cause fluid to pass through the heat exchanger to effectuate dissipation of heat from the at least one computing device through forced air action on the heat exchanger from the variable speed fan, the heat exchanger carrying the fluid having drawn heat therein.

[0054] In at least one embodiment, each modular unit can be associated with a server tray or server sled. In at least one embodiment, each modular unit can have one or more fans and can be associated with a heat exchanger. In at least one embodiment, the fan-heat exchanger combination of the modular unit effects efficient removal of heat from a working fluid running between a direct to chip (DC) cold plate of each server and the modular unit. In at least one embodiment, the variable speed fan of the modular unit is controllable such that fan speed control can be based in part on inlet and / or outlet fluid temperatures of the heat exchanger of the modular unit and components associated with the cold plate. In at least one embodiment, the component (data center component or computing component or device) can be a GPU, a switch, or a CPU.

[0055] In at least one embodiment, a junction temperature can be incorporated into each fan of a modular unit. In at least one embodiment, the junction temperature allows a server to adjust fan speed to best control fluid temperature of a modular unit. In at least one embodiment, the fluid can be coolant or other fluid. In at least one embodiment, the temperature of the fluid can be the temperature of fluid within a closed loop and forming a loop between cold plates and associated modular units. In at least one embodiment, a built-in micro quick disconnect is a flow controller or part of a flow controller that allows for replacement of modular units, including hot swap, and also allows for redundant piping design in a data center cooling system. In at least one embodiment, failure of an auxiliary cooling loop or any component of one or more modular units can be addressed by other modular units until corrected in place.

[0056] In at least one embodiment, solutions as disclosed herein address the problem of reliable cooling of high heat density GPUs, switches, CPUs, and other related computing components of data center servers or racks. In at least one embodiment, modular units as in herein are able to meet the requirements of core as well as edge data centers even without intervention of facility cooling systems, such as main cooling loops. In at least one embodiment, modular units as in herein address the problem of meeting high heat density requirements of such computing systems in current data centers. In at least one embodiment, modular units with fans and heat exchangers in a combined configuration enable meeting various cooling requirements through at least speed control of fans. In at least one embodiment, in core or edge data center applications, speed control of fans can be based in part on critical system temperatures to be maintained by removing heat from high heat generating components of servers and racks of servers. In at least one embodiment, solutions herein address the problem of reliable cooling of high heat density computing components of data centers in core as well as edge data center applications even without intervention of facility cooling systems from main cooling loops.

[0057] In at least one embodiment, a cold plate may have separate ports for coolant or other fluids from modular units that are part of a local cooling loop. In at least one embodiment, at least one flow controller may be activated when a flow or temperature problem is identified in the auxiliary cooling loop or in a primary cooling loop associated with the auxiliary cooling loop. In at least one embodiment, at least one flow controller enables fluid circulation through the cold plate and modular units. In at least one embodiment, the modular units enable efficient liquid-to-air heat exchangers. In at least one embodiment, the liquid-to-air heat exchanger can be located in a separate fluid path to allow heat to dissipate from the fluid to a hot aisle or the ambient environment within the data center. In at least one embodiment, the modular units can be associated with rack doors, and multiple modular units can be provided for a fan wall. In at least one embodiment, electrical coupling can be provided to enable the fans in the modular units to force air through the liquid-to-air heat exchanger. In at least one embodiment, the modular units enable local loops to address temporary issues in the data center's primary cooling loop. In at least one embodiment, the modular units can be sufficient to meet low-level heating or cooling needs of a data center and can be economically used during data center downtime.

[0058] In at least one embodiment, the Figure 1An exemplary data center 100 is shown, having a cooling system improved upon as described herein. In at least one embodiment, the data center 100 can be one or more rooms 102 having racks 110 for housing one or more servers on one or more server trays and ancillary equipment. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside of the data center 100. In at least one embodiment, the cooling tower 104 draws heat from within the data center 100 by acting on a primary cooling loop 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the primary cooling loop 106 and a secondary or auxiliary cooling loop 108 to enable heat to be extracted from the secondary or auxiliary cooling loop 108 to the primary cooling loop 106. In at least one embodiment, the auxiliary cooling loop 108 can access different conduits into the server trays as needed, in one aspect. In at least one embodiment, the loops 106, 108 are shown as line graphs, but one of ordinary skill will recognize that one or more conduit features can be used. In at least one embodiment, flexible polyvinyl chloride (PVC) tubing can be used with the associated conduit system to move fluid along each of the established loops 106, 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the coolant loops 106, 108 to enable the coolant to move according to temperature sensors in different locations, including in the room, in one or more racks 110, and / or in server cabinets or server trays within one or more racks 110.

[0059] In at least one embodiment, the coolant in the primary cooling loop 106 and the auxiliary cooling loop 108 can be at least water and an additive. In at least one embodiment, the additive can be ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the primary cooling loop and the auxiliary cooling loop can have their own coolant. In at least one embodiment, the coolant in the auxiliary cooling loop can be dedicated to the needs of the server trays or components in the associated racks 110. In at least one embodiment, the CDU 112 is capable of complex control of the coolant within the established coolant loops 106, 108 independently or simultaneously. In at least one embodiment, the CDU can be adapted to control the flow rate of the coolant such that the coolant is appropriately distributed to draw heat generated within the associated racks 110. In at least one embodiment, more flexible conduits 114 are provided from the auxiliary cooling loop 108 to enter each server tray to provide coolant to the electrical and / or computing components therein.

[0060] In at least one embodiment, tubing 118 forming part of secondary cooling loop 108 can be referred to as a room manifold. Separately, in at least one embodiment, additional tubing 116 can extend from row manifold tubing 118 and can also be part of secondary cooling loop 108, but can be referred to as a row manifold. In at least one embodiment, coolant tubing 114 enters a rack as part of secondary cooling loop 108, but can be referred to as a rack cooling manifold within one or more racks. In at least one embodiment, row manifold 116 extends along a row in data center 100 to all racks. In at least one embodiment, piping of secondary cooling loop 108 including coolant manifolds 118, 116, and 114 can be improved by at least one embodiment herein. In at least one embodiment, chillers 120 can be provided in a primary cooling loop within data center 102 to support cooling prior to a cooling tower. In at least one embodiment, there can be additional loops in a primary control loop that provide cooling outside of racks and outside of secondary cooling loops, which for the present disclosure can be grouped together with a primary cooling loop and distinct from a secondary cooling loop.

[0061] In at least one embodiment, in operation, heat generated within server trays of a set of racks 110 can be transferred via flexible tubing of row manifold 114 of secondary cooling loop 108 to coolant exiting one or more racks 110. In at least one embodiment, second coolant from CDU 112 for cooling a set of racks 110 (in secondary cooling loop 108) moves via tubing toward one or more racks 110. In at least one embodiment, second coolant from CDU 112 passes from one side of room manifold having tubing 118 via row manifold 116 to one side of racks 110 and via different tubing 114 through one side of server trays. In at least one embodiment, used or returning second coolant (or exiting second coolant taking heat away from computing components) exits from another side of server trays (such as into a left side of a rack for server trays and out a right side of the rack after circulating through server trays or through components on server trays). In at least one embodiment, used second coolant exiting server trays or racks 110 comes out of a different side (such as an exit side) of tubing 114 and moves to a parallel but also exit side of row manifold 116. In at least one embodiment, used second coolant moves from row manifold 116 in a parallel portion of room manifold 118 and travels in an opposite direction from entering second coolant (which can also be newer second coolant) and toward CDU 112.

[0062] In at least one embodiment, the spent secondary coolant exchanges its heat with the primary coolant in the primary cooling loop 106 via the CDU 112. In at least one embodiment, the spent secondary coolant can be refreshed (e.g., relatively cooled compared to the temperature of the spent secondary coolant stage) and ready to be circulated back through the auxiliary cooling loop 108 to one or more computing components. In at least one embodiment, various flow and temperature control features in the CDU 112 enable control of the exchange of heat from the spent secondary coolant or the flow of secondary coolant into and out of the CDU 112. In at least one embodiment, the CDU 112 can also be capable of controlling the flow of the primary coolant in the primary cooling loop 106.

[0063] In at least one embodiment, Figure 2 The illustrated server-level feature 200 can be associated with a smart replaceable modular unit for a data center cooling system. In at least one embodiment, the server-level feature 200 includes a server tray or box 202. In at least one embodiment, the server tray or box 202 includes a server manifold 204, which is intermediately coupled between cold plates 210A-D provided in the server tray or box 202 and a rack manifold of a rack hosting the server tray or box 202. In at least one embodiment, the server tray or box 202 includes one or more cold plates 210A-D associated with one or more computing or data center components or devices 220A-D. In at least one embodiment, one or more server-level cooling circuits 214A, 214B can be provided between the server manifold 204 and the one or more cold plates 210A-D. In at least one embodiment, each server-level cooling circuit 214A, 214B includes an inlet line 210 and an outlet line 212. In at least one embodiment, when the cold plates 210A, B are arranged in series, an intermediate line 216 can be provided. In at least one embodiment, one or more cold plates 210A-D can support various ports and channels for auxiliary coolant of an auxiliary cooling circuit or local coolant (or other fluid) of a modular unit. In at least one embodiment, a local cooling circuit can be used to cool and circulate auxiliary coolant, local coolant, or other fluid. In at least one embodiment, if the auxiliary coolant is transferred to the modular unit, the auxiliary coolant can be used as the fluid cooled by the modular unit. In at least one embodiment, the fluid for cooling can be provided to the server manifold 204 via the provided inlets and contours 206A, 206B.

[0064] In at least one embodiment, server tray 202 is an immersion cooling server tray that can be fluid-submerged. In at least one embodiment, a fluid used for an immersion cooling server tray can be a dielectric engineering fluid that can be used in an immersion cooling server. In at least one embodiment, an auxiliary coolant, a local coolant, or other fluid can be used to cool the engineering fluid. In at least one embodiment, a local coolant can be used to cool the engineering fluid when a primary cooling loop associated with an auxiliary cooling loop of a secondary cooling loop fails or is failing. In at least one embodiment, at least one cold plate therefore has ports for an auxiliary cooling loop and ports for a local cooling loop with modular units and is capable of supporting a local cooling loop that is activated when a primary cooling loop fails.

[0065] In at least one embodiment, at least one dual-cooling cold plate 210B; 250 can be configured to work with a conventional cold plate 210A, C, D. In at least one embodiment, a conventional cold plate can be used with a local cooling loop, which can divert or enable flow of an auxiliary coolant (or local coolant or other fluid) of an auxiliary cooling loop to modular units of a local cooling loop and be cooled with a liquid-to-air heat exchanger before circulating back to a conventional cold plate. In at least one embodiment, a conventional cold plate is suitable for an auxiliary coolant that is supported by both an auxiliary cooling loop and a local cooling loop.

[0066] In at least one embodiment, a three-dimensional (3D) zoomed-in view (cold plate 250) provides internal details of at least some features that can be included in a dual-cooling cold plate 210B. In at least one embodiment, dual-cooling cold plate 250 has different paths 264, 270 (each path also referred to as a microchannel) for an auxiliary coolant of an auxiliary cooling loop and for a local coolant (or other fluid) of a local cooling loop featuring modular units. In at least one embodiment, an auxiliary or local coolant (or other fluid) can not be dielectric in nature. In at least one embodiment, in a use case of an immersion cooling server, a fluid that can be a dielectric engineering fluid can be suitable for both cold plate applications and immersion cooling server tray applications.

[0067] In at least one embodiment, reference to a cold plate in connection with its dual cooling features means reference to a cold plate capable of supporting at least two types of cooling loops, unless otherwise specified. In at least one embodiment, both types of cold plates receive fluid for cooling from the same secondary cooling loop and can both support a local cooling loop. In at least one embodiment, a standard coolant, such as facility water, can be used for both the secondary cooling loop and the local cooling loop, such that during a failure of the primary cooling loop associated with the secondary cooling loop, the local cooling loop can temporarily cool the secondary coolant via a liquid-to-air heat exchanger. In at least one embodiment, the secondary coolant that has been within the cold plate is transferred to the modular unit and can be mixed with pre-loaded secondary coolant that has been within the modular unit. In at least one embodiment, this mixing can immediately cool the secondary coolant that is otherwise cooled by the liquid-to-air heat exchanger.

[0068] In at least one embodiment, the local coolant can therefore be the same or similar to the secondary coolant to avoid issues related to chemical differences and manufacturer requirements of the cold plates used in the data center cooling system. In at least one embodiment, the fluid can only support cold plate use and can not be usable for immersion cooling. In at least one embodiment, each type of cold plate receives a different fluid from a respective secondary or other cooling loop that interfaces with the primary cooling loop. In at least one embodiment, in the case of different fluids used with different coolant distribution units (CDUs) of different secondary loops, then the local cooling loop can be adapted for dual-cooled cold plates such that different passages can be used for each of the local coolant and the different secondary coolant.

[0069] In at least one embodiment, dual-cooled cold plate 250 is adapted to receive two types of fluids (e.g., secondary coolant and local coolant) and to keep the two types of fluids different from each other via their different ports 252, 272; 268, 262 and their different paths 264, 270. In at least one embodiment, each different path is a fluid path. In at least one embodiment, the fluid (e.g., local coolant) from a fluid source and the secondary coolant can have the same or similar composition and can be restocked from the same source in the data center cooling system.

[0070] In at least one embodiment, dual-cooled cold plate 250 includes ports 252, 272 to receive fluid into and out of cold plate 250. In at least one embodiment, dual-cooled cold plate 250 includes ports 268, 262 to receive secondary coolant into and out of cold plate 250. In at least one embodiment, ports 252, 272 can have valve caps 254, 260 that can be directional and pressure controlled. In at least one embodiment, valve caps can be associated with all ports provided. In at least one embodiment, valve caps 254, 260 provided are mechanical features of associated flow controllers that also have corresponding electronic features (e.g., at least one processor that executes instructions stored in associated memory and controls mechanical features of associated flow controllers).

[0071] In at least one embodiment, each valve can be actuated by an electronic feature of an associated flow controller. In at least one embodiment, electronic and mechanical features of a flow controller provided are integrated. In at least one embodiment, electronic and mechanical features of a flow controller provided are physically distinct. In at least one embodiment, a reference to a flow controller can refer to one or more of electronic and mechanical features provided or to a combination of them, but at least to features that enable control of coolant or fluid flow through each cold plate or immersion-cooled server tray or tank.

[0072] In at least one embodiment, an electronic feature of a flow controller provided receives a control signal and asserts control over a mechanical feature. In at least one embodiment, an electronic feature of a flow controller provided can be an actuator or other electronic component of other similar electromechanical feature. In at least one embodiment, a flow pump can be used as a flow controller. In at least one embodiment, an impeller, a piston, or a bellows can be a mechanical feature and an electronic motor and circuitry form an electronic feature of a flow controller provided.

[0073] In at least one embodiment, the circuitry of the flow controller can include a processor, memory, switches, sensors, and other components that collectively form the electronic features of the flow controller. In at least one embodiment, the ports 252, 262, 272, 268 of the flow controller can be adapted to allow entry of an immersion fluid or to allow exit of an immersion fluid. In at least one embodiment, the flow controller 280 can be associated with a fluid line 276 (also 256, 274) that enables fluid (e.g., local coolant) to enter and exit the cold plate 210B. In at least one embodiment, other flow controllers can be similarly associated with the coolant lines 210, 216, 212 (also 266, 258) to enable auxiliary coolant to enter and exit the cold plate 210B.

[0074] In at least one embodiment, a fluid (e.g., local coolant) enters the provided fluid lines 276 via dedicated fluid inlet and outlet lines 208A, 208B. In at least one embodiment, the server manifold 204 has channels therein (shown by dashed lines) to support different paths to the different fluid lines 276 (also 256, 274) and any remaining loops 214A, 214B associated with the auxiliary coolant inlet and outlet lines 206A, 206B. In at least one embodiment, there can be multiple manifolds to support the fluid (local coolant) and auxiliary coolant differently. In at least one embodiment, there can be multiple manifolds to support different entries and exits for each of the fluid and auxiliary coolant. In at least one embodiment, if the fluid is the same or similar to the auxiliary coolant, then at least two different flows can reach the fluid source (e.g., local coolant) via the same fluid path (at least within the cold plate or server tray). Figure 3 tank 332) and to the auxiliary coolant row manifold (e.g. Figure 3 row manifold 350 in the middle).

[0075] In at least one embodiment, a first flow can enable a fluid (e.g., a local coolant) to flow through one or more of the provided ports 252, 272 and associated pathways 270. In at least one embodiment, the dual-cooling cold plate 250 can have isolated plate portions filled with fluid and / or auxiliary coolant while being kept distinct from one another by gaskets or seals. In at least one embodiment, a second flow can enable an auxiliary coolant to flow through the provided ports 268, 262 and associated pathways 264.

[0076] In at least one embodiment, flow controllers 278 may be associated with the fluid inlet 276 and outlet sections at the server manifold 204, rather than flow controllers 280 provided at the corresponding cold plates. In at least one embodiment, the first flow utilizes only local coolant and may be implemented when a fault is determined in the auxiliary cooling loop or the primary cooling loop, such that the auxiliary coolant is unable to effectively extract heat from at least one computing device. In at least one embodiment, the fault may be that the auxiliary coolant is not being adequately cooled by the CDU, and therefore, it may not be able to extract sufficient heat from at least one computing device via its associated cold plate.

[0077] In at least one embodiment, before local coolant (or auxiliary coolant) from a fluid source of a local cooling circuit is used to temporarily address cooling of at least one computing component, the auxiliary coolant from the CDU can be shut down first. In at least one embodiment, the first flow provides redundancy for failures in the auxiliary cooling circuit. In at least one embodiment, when a failure is determined, there is no auxiliary coolant flow from the CDU. In at least one embodiment, auxiliary coolant from the local cooling circuit can be allowed to enter the cold plate 210B simultaneously with auxiliary coolant from the CDU until a shutdown of the CDU flow is performed to allow corrective action to be taken on the auxiliary cooling circuit or the main cooling circuit. In at least one embodiment, this represents the first flow and the second flow (the flow of auxiliary coolant and the flow of local coolant) occurring together. In at least one embodiment, a CDU may not be required because the modular unit is capable of dissipating all heat generated by one or more associated computing devices.

[0078] In at least one embodiment, Figure 3 The rack-level feature 300 shown can be associated with a smart replaceable modular unit for a data center cooling system. In at least one embodiment, the rack-level feature 300 includes a rack 302 having brackets 304, 306 for suspending cooling manifolds 314A, 314B. In at least one embodiment, although rack 330 is shown separate from rack 302, rack 330 may illustrate a rear perspective view of rack 302. In at least one embodiment, the brackets 334, 336 provided on rack 330 are similarly a perspective view of the brackets 304, 306 provided on rack 302. In at least one embodiment, the brackets 304, 306 provided for the rack are flat structures that rest against the inner wall of the rack. In at least one embodiment, the brackets 304, 306 provided for the rack extend from the inner wall of the rack. In at least one embodiment, the brackets 304, 306 provided for the rack are secured to the inner wall of the rack and have mounting points facing the rear of the rack. In at least one embodiment, cooling manifolds 314A, 314B may be provided to provide cooling at server level features 200 (and at Figure 3308) and a CDU (e.g., a secondary cooling loop) of a data center cooling system. Figure 4 The auxiliary coolant or local coolant is transferred between the CDU 406 of the rack or the fluid source 332 of the local cooling circuit. In at least one embodiment, different CDUs 362, 364 can serve different racks. In at least one embodiment, different rack cooling manifolds can be distinctly part of the auxiliary cooling circuit and the local cooling circuit.

[0079] In at least one embodiment, the rack level features 300 can include a local cooling circuit supported by a modular unit 340 that includes: at least one flow controller 356A; 356B; a liquid-to-air heat exchanger having a circulation tube or coil 344 and one or more fans or other forced air features 342; and inlet and outlet fluid paths 346A, 346B. In at least one embodiment, the modular unit is housed within a structure 340 having a coupling feature 358 to enable the modular unit 340 to couple with a rear door 338 of the rack 302. In at least one embodiment, the coupling feature 358 is a mating pin for a keyhole recess of a bracket 334; 336. In at least one embodiment, the flow controller 356A, 356B can be associated with the cold plate 326 (or, for example, at Figure 2 In at least one embodiment, such flow controllers 356A; 356B may be part of at least one flow controller supporting a local cooling circuit from modular unit 340. In at least one embodiment, from Figure 2 The flow controller description can be applied to Figure 3 Flow controllers 356A; 356B in rack-level features 300. In at least one embodiment, the described flow controllers can be adapted to different flow rates and flow rates, such that they can be used in cold plates or cooling manifolds, depending on the application.

[0080] In at least one embodiment, a local cooling loop from modular unit 340 can be associated with at least one computing device 324 and associated cold plate 326. In at least one embodiment, another fluid path can be implemented for a local cooling loop via entry and exit lines 320, 322 and path 354. In at least one embodiment, an auxiliary cooling loop has a different fluid path that can be implemented by entry and exit lines 316, 318. In at least one embodiment, a single fluid path is used with a splitter flow controller between modular unit 340 and manifold 350 associated with an auxiliary cooling loop. In at least one embodiment, an immersion server tray 352 has lines therein to pass auxiliary coolant or local coolant for cooling immersion fluid. In at least one embodiment, back door 338 can be separated from rack 330 at coupling area 332.

[0081] In at least one embodiment, a splitter flow controller can be able to pass local or auxiliary coolant from a single entry line to two exit lines. In at least one embodiment, auxiliary coolant from an auxiliary cooling loop supported by a CDU interfacing with a main cooling loop enters manifold 350 to be distributed to different racks, such as rack 302. In at least one embodiment, auxiliary coolant from manifold 350 is passed to flow controller 310C via rack entry line 310A. In at least one embodiment, by default, flow controller 310C passes auxiliary coolant to inlet rack manifold 314A via cooling manifold entry line 310. In at least one embodiment, auxiliary coolant enters one or more cold plates 326 and exits to exit rack manifold 314B via respective server exit lines 318. In at least one embodiment, auxiliary coolant travels via cooling manifold exit line 312, flow controller 312C, and rack exit line 312A. In at least one embodiment, auxiliary coolant enters the same manifold 350 to be circulated back to a CDU or a different manifold to be circulated back to a CDU.

[0082] In at least one embodiment, a local cooling loop replaces an auxiliary cooling loop to provide cooling for at least one computing component 324. In at least one embodiment, since an auxiliary cooling loop can be associated with a primary cooling loop and a cooling facility, a failure of any of auxiliary cooling loop, primary cooling loop, CDU, or cooling facility can require repair for those respective features. In at least one embodiment, a service level agreement (SLA) can describe allowed downtime for those respective features. In at least one embodiment, downtime for those respective features can be considered in determining a cooling capacity of modular unit 340. In at least one embodiment, a cooling capacity of modular unit 340 enables it to provide cooling for local coolant or auxiliary coolant, and enables it to support cooling during downtime of an auxiliary cooling loop or a primary cooling loop, including their components (e.g., CDU and cooling tower). In at least one embodiment, stands 334, 336 are provided to suspend wiring and electronics associated with connectors 348 (associated with modular unit) and associated with flow controllers 356A, 356B.

[0083] In at least one embodiment, flow controllers 356A, 356B can be associated with similar flow controllers of adjacent modular units in order to provide continuity of flow for a local cooling loop between one or more cold plates and multiple modular units 340. In at least one embodiment, flow controllers 356A, 356B can be associated with flow controllers of at least one cold plate in order to provide a local cooling loop directly between at least one cold plate and at least one modular unit 340. In at least one embodiment, flow controllers 356A, 356B can be associated with similar flow controllers of an immersion cooling server tray or tank 352 to allow fluid to receive heat from dielectric fluid and dissipate heat via at least one modular unit 340.

[0084] In at least one embodiment, flow controllers 356A, 356B disposed in modular unit 340 are push-to-couple to enable quick connection and disconnection between modular units or server trays or boxes, cold plates, or different manifolds disposed to couple multiple server trays 308 with one or more modular units. In at least one embodiment, one or more flow controllers 310C, 312C can be disposed as shunts to block auxiliary coolant from line manifold 350 and instead engage modular unit 340. In at least one embodiment, flow controllers 356A, 356B are coupled to flow controllers 310C, 312C to enable a local cooling loop between cooling manifolds 314A, 314B and modular unit 340. In at least one embodiment, electrical connectors 348 such as plugs or sockets can be disposed to power one or more fans 342 of module 340. In at least one embodiment, power can be provided from an adjacent modular unit that in turn receives power from a power distribution unit of rack 302.

[0085] In at least one embodiment, parameters such as flow, flow rate, and expected temperature of local coolant (or auxiliary coolant) can be used to determine capacity of fluid source 332 in the event of a failure of primary cooling loop, auxiliary cooling loop, or cooling facility. In at least one embodiment, SLA specified downtime can be compensated for by parameters enabled for local cooling loops such that local cooling loops can provide sufficient redundant cooling until a failure of any of primary cooling loop, auxiliary cooling loop, or related components can be repaired. In at least one embodiment, a local cooling loop with one or more modular units can be the only provided cooling feature of a data center cooling system without requiring a primary cooling loop, auxiliary cooling loop, and associated CDU.

[0086] In at least one embodiment, in the event of a failure of primary cooling loop, auxiliary cooling loop, or cooling facility, at least one processor can engage at least one of flow controllers 310C, 312C, 356A, 356B in a local cooling loop upon determining the failure while shutting down auxiliary cooling loop to at least one rack 302. In at least one embodiment, flow controllers 310C, 312C can enable shutting down auxiliary cooling loop by diverting auxiliary coolant flow via line 364 to a local cooling line manifold that is different from line manifold 350. In at least one embodiment, a completely different line and rack manifold can be used with an alternative cooling line manifold. In at least one embodiment, modular unit 340 can be directly associated with one or more racks 302 located in proximity to modular unit 340. In at least one embodiment, a local cooling line manifold can not be required and modular unit is directly coupled to a cold plate or server tray.

[0087] In at least one embodiment, a data center cooling system can include one or more modular units 340. In at least one embodiment, a modular unit 340 can include a heat exchanger 344, which can be copper tubes or plates or other heat transferable material to allow heat to escape from fluid flowing there through and be dissipated by forced air. In at least one embodiment, a variable speed fan 342 enables forced air to pass through heat exchanger 344. In at least one embodiment, a modular unit 340 includes at least one flow controller 356A; 356B. In at least one embodiment, a flow controller can be provided to enable circulation of fluid from a cold plate through a modular unit. In at least one embodiment, a flow controller can perform a push or pull action on fluid within heat exchanger 344. In at least one embodiment, a modular unit can be adapted to be replaceable or hot swappable. In at least one embodiment, an electrical connector 348 and fluid coupling (via one or more flow controllers 356A; 356B) can be disconnected to enable removal and replacement of a modular unit 340. In at least one embodiment, another modular unit 340 can be coupled via similar electrical coupling and push coupling by respective flow controllers 356A; 356B to perform cooling according to local cooling loop requirements.

[0088] In at least one embodiment, a modular unit 340 can be fluidly coupled with a cold plate having microchannels. In at least one embodiment, at least one flow controller 356A; 356B can be provided to cause fluid to pass through microchannels of a cold plate 326 to draw heat from at least one computing device 324. In at least one embodiment, at least one flow controller 356A; 356B can be provided to cause fluid to pass through a heat exchanger 344 to enable heat dissipation by forced air from a variable speed fan 342.

[0089] In at least one embodiment, at least one processor can be provided to determine a temperature associated with at least one computing device 324 or fluid of an auxiliary cooling loop or modular unit 340. In at least one embodiment, at least one processor can cause a change in speed of a variable speed fan 342. In at least one embodiment, a change in speed of a variable speed fan 342 can enable more or less heat to be removed from fluid in a heat exchanger 344 of a modular unit 340.

[0090] In at least one embodiment, a copper coil can be provided as heat exchanger 344. In at least one embodiment, coil heat exchanger 344 can enable use of different fluids in a modular unit. In at least one embodiment, a modular unit can have different coil configurations to enable different heat distribution through coil heat exchanger 344 and different heat loss through the action of forced air from variable speed fan 342 in modular unit 340. In at least one embodiment, a cold plate is provided with first ports for a first portion of microchannels to support a coolant (e.g., secondary coolant) differently than a second portion of microchannels that support a different fluid, e.g., a different chemically natured coolant. In at least one embodiment, this enables use of a secondary coolant of a secondary cooling loop that is different than a different coolant of a local cooling loop.

[0091] In at least one embodiment, at least one processor can receive sensor input from sensors associated with at least one computing device 324 or with fluid of cold plate 326, in line 354, through coil 344. In at least one embodiment, at least one processor is adapted to determine a change in coolant status based in part on sensor input. In at least one embodiment, a change in coolant status can reference a change in temperature of a secondary coolant that reflects a higher temperature than an operating temperature required to cool computing device 324. In at least one embodiment, a change in coolant status can reference a flow rate or flow volume that is insufficient to cool computing device 324. In at least one embodiment, a change in coolant status can reference an increased humidity determined in manifold 350 or one or more of lines 316, 318. In at least one embodiment, a coolant status can change due to a failure (e.g., a leak, a blockage, or an unintended shunt) in a secondary cooling loop or a modular unit. In at least one embodiment, a determination of a failure enables a modular unit to be shut down and replaced or used in place of a secondary cooling loop. In at least one embodiment, at least one processor can cause or enable one or more of at least one flow controller to stop or cause a change in flow of fluid therein. In at least one embodiment, at least one processor can cause a change in variable speed fan to enable a modular unit to be replaced or used. In at least one embodiment, one or more neural networks can be adapted to receive sensor input and infer a change in coolant status. In at least one embodiment, one or more neural networks can be trained to make such inferences.

[0092] In at least one embodiment, the at least one processor can implement electrical disconnection of the modular unit to enable replacement of the modular unit. In at least one embodiment, replacement of the modular unit can be temporary replacement of the auxiliary cooling loop or replacement of the auxiliary cooling loop to enable power economy when heat generated by the high density component is below cooling needs addressed by the auxiliary cooling loop. In at least one embodiment, the electrical disconnection can be my control of an electronic switch before removal of the physical electrical connector 348. In at least one embodiment, a magnetic feature can be used to pop the electrical connector 348 to replace the modular unit.

[0093] In at least one embodiment, the at least one processor includes one or more neural networks. In at least one embodiment, the one or more neural networks can be adapted to determine a failure of the primary cooling loop. In at least one embodiment, the at least one processor can cause the at least one flow controller 356A; 356B to implement cooling from the modular unit. In at least one embodiment, the modular unit faces a rear of the rack and toward a hot aisle in the data center.

[0094] In at least one embodiment, the cold plate 326 can be adapted to interface with the modular unit 340 and with an auxiliary cooling loop that includes at least the manifold 350, a coolant distribution unit (CDU), and which in turn interfaces with the primary cooling loop. In at least one embodiment, the auxiliary cooling loop can be associated with the primary cooling loop and with the cooling facility through the CDU. In at least one embodiment, the at least one flow controller 310C prevents auxiliary coolant of the CDU from reaching the cold plate 326. In at least one embodiment, this allows fluid associated with the modular unit 340, such as a similar or same auxiliary coolant or a different local coolant, to circulate between the cold plate and the heat exchanger 344.

[0095] In at least one embodiment, the at least one flow controller 356A; 356B; 310C; 312C can be set to engage the modular unit 340 based in part on a first threshold cooling need of the at least one computing device. In at least one embodiment, the at least one flow controller 310C; 312C can be set to engage the auxiliary cooling loop based in part on a second threshold cooling need of the at least one computing device. In at least one embodiment, the first threshold cooling need associated with the modular unit 340 can be less than or greater than the second cooling need associated with the auxiliary cooling loop. In at least one embodiment, the first threshold cooling need is less than the second cooling need and, therefore, the modular unit is engaged to provide economical cooling for lower heat generated by the at least one computing device. In at least one embodiment, the first threshold cooling need can be greater than the second cooling need, where the modular unit is used to supplement the auxiliary cooling loop when more heat is generated in the at least one computing device requiring more cooling.

[0096] In at least one embodiment, when the exit temperature of the secondary coolant is within a threshold of the entry temperature of the secondary coolant, at least one flow controller 310C, 312C (or bonnet of a flow controller associated with ports 268, 260, as described in Figure 2 In at least one embodiment, a threshold between the entry temperature and the exit temperature can indicate that the secondary coolant is not sufficiently cooled by the primary cooling loop or is not sufficiently cooled to remove heat from the at least one computing device. In at least one embodiment, the secondary coolant not being sufficiently cooled can indicate a failure in the secondary cooling loop, the primary cooling loop, or any associated cooling components of these respective cooling loops. In at least one embodiment, the entry temperature and the exit temperature can be associated with entry and exit of the secondary coolant with respect to the CDU. In at least one embodiment, the temperatures can be sensed at the rack 302 or the CDU. In at least one embodiment, a sensor can be associated with the rack or the CDU to monitor the temperature of the secondary coolant. In at least one embodiment, a sensor can be disposed to sense a temperature of the at least one computing component, and cooling can be provided from the secondary cooling loop or the modular unit based in part on such sensed temperature.

[0097] In at least one embodiment, the at least one processor can be to determine that the secondary cooling loop is operating outside of a threshold cooling requirement of the at least one computing device. In at least one embodiment, the threshold cooling requirement is a prescribed cooling required for the at least one computing device to operate normally. In at least one embodiment, the indication that the secondary cooling loop is operating outside of the threshold can result in the local cooling loop to satisfy the threshold cooling requirement of the at least one computing device instead. In at least one embodiment, the secondary coolant can be facility water and can include an additive. In at least one embodiment, heat from the secondary coolant from the secondary cooling loop or from the local coolant from the local cooling loop is dissipated into the environment through forced air or a passive environmental unit 362.

[0098] In at least one embodiment, a data center level feature 400 as shown in Figure 4 may be associated with an intelligent replaceable modular unit for a data center cooling system. In at least one embodiment, the data center level feature 400 within a data center 402 can include: a rack 404 to host one or more server trays or sleds; one or more CDUs 406 to exchange heat between a secondary cooling loop and a primary cooling loop 422; one or more row manifolds 410 to distribute coolant from the CDUs 406; and associated various flow controllers 424, as well as inlet and outlet lines 412, 414, 416, 418.

[0099] In at least one embodiment, a modular unit is provided on a back door of each rack 404. In at least one embodiment, a passageway behind the rack 404 is a hot passageway for exhausting heat from at least one computing device in at least one rack. In at least one embodiment, different manifold lines can be associated with different sleds. In at least one embodiment, different coolants can be locally coolant chemically matched or mismatched. In at least one embodiment, different fluid sources are provided to different CDUs as a redundancy feature according to a chemical composition of different secondary coolants used with each of the different provisioned CDUs. In at least one embodiment, a particular modular unit can be associated with a back door and engaged with a rack in the event of a failure of one of the available CDUs.

[0100] In at least one embodiment, associated plumbing (cooling manifolds, flow controllers, and fluid paths) can be used to provide local coolant previously received from an affected CDU. In at least one embodiment, at least one flow controller can be associated with a modular unit and with a corresponding CDU, such as a shunt flow controller. In at least one embodiment, at least one flow controller can be provisioned to divert secondary coolant from a CDU to a modular unit and back to cold plates so that a CDU can be repaired without downtime to at least one computing device that requires cooling provided by the CDU.

[0101] In at least one embodiment, when a failure is determined for a corresponding CDU, local coolant or secondary coolant previously preloaded in a modular unit can be first thermally and chemically validated to be consistent for one or more cold plates before being provided to the one or more cold plates in a manner described with respect to Figure 2 、 3 In at least one embodiment, a thermal and / or chemical validation is provided prior to associating a modular unit with a rack and can cause local coolant to be at an expected temperature (or temperature range) and / or an expected chemical composition (or within a range of chemical properties) intended to be provided from a corresponding CDU prior to its failure.

[0102] In at least one embodiment, a processor can include an input to receive sensor input from a sensor associated with at least one rack. In at least one embodiment, a sensor can be associated with a primary cooling loop, an auxiliary cooling loop, a CDU, a cooling tower, or any row cooling manifold associated with a primary cooling loop and an auxiliary cooling loop. In at least one embodiment, a processor can use sensor input to determine a change in coolant status and control one or more flow controllers to engage an auxiliary cooling loop or a local cooling loop. In at least one embodiment, sensor input can be at least one temperature of an auxiliary coolant of an auxiliary cooling loop. In at least one embodiment, when a sensed temperature is above an operating temperature of at least one computing device, then an auxiliary coolant can be determined to be ineffective at cooling at least one computing device. In at least one embodiment, this can be a problem because a primary cooling loop is not absorbing heat from an auxiliary cooling loop. In at least one embodiment, this can be a leak or CDU failure problem. In at least one embodiment, this can be a cooling facility failure problem. In at least one embodiment, a primary cooling loop can be sensed to be above an operating temperature and can not be effective at cooling an auxiliary cooling loop.

[0103] In at least one embodiment, one or more neural networks can be used to receive sensor input and infer a change in coolant status. In at least one embodiment, a change in coolant status can be a determination that an auxiliary coolant previously applied at a certain flow rate, flow volume, and / or entry temperature is ineffective at cooling at least one computing device. In at least one embodiment, such a determination can be identified based in part on previous ineffective cooling associated with previous flow rates, flow volumes, and / or entry temperatures of previous coolants (and their associated chemical compositions). In at least one embodiment, such prior information can be used to train a learning model to infer a current flow rate, flow volume, and / or temperature of an auxiliary coolant. In at least one embodiment, an inference can be that an auxiliary coolant is ineffective at providing coolant, which triggers a processor to cause a flow controller to stop a flow of an auxiliary coolant of an auxiliary cooling loop and engage an alternative cooling loop until the problem with the auxiliary cooling loop is resolved.

[0104] In at least one embodiment, an input of a processor can be adapted to receive sensor input from a sensor associated with at least one rack. In at least one embodiment, a processor can be capable of determining a change in coolant status based in part on a temperature of an auxiliary coolant in an auxiliary coolant loop from received sensor input. In at least one embodiment, a processor can be capable of controlling one or more flow controllers to implement a local cooling loop and disable an auxiliary cooling loop.

[0105] In at least one embodiment, a processor can include one or more circuits and can be associated with at least one modular unit having a heat exchanger, a variable speed fan, and at least one flow controller. In at least one embodiment, a modular unit can be adapted to be replaceable or hot-swappable and fluidly coupled with a cold plate having microchannels. In at least one embodiment, one or more circuits of a processor can be adapted to cause at least one flow controller to cause fluid to pass through microchannels of a cold plate to draw heat from at least one computing device. In at least one embodiment, at least one flow controller can be caused to cause fluid having heat absorbed from at least one computing device (via a cold plate) to pass through a heat exchanger of a modular unit. In at least one embodiment, this enables heat dissipation by forced air from a variable speed fan of a modular unit.

[0106] In at least one embodiment, a processor includes outputs that provide signals for one or more of different features of a modular unit. In at least one embodiment, signals can be provided for at least one flow controller or a variable speed fan. In at least one embodiment, signals to one or more flow controllers enable fluid to flow through a cold plate associated with a modular unit. In at least one embodiment, signals are issued to a variable speed fan to implement different speeds of forced air in a modular unit.

[0107] In at least one embodiment, a processor includes inputs for receiving sensor inputs from sensors associated with at least one computing device or sensors associated with fluid associated with cooling at least one computing device. In at least one embodiment, a processor executes instructions that can cause it to determine a change in coolant status based in part on received sensor inputs. In at least one embodiment, a processor can then cause or implement one or more functions. In at least one embodiment, functions caused or implemented by a processor include, for at least one flow controller, stopping or causing a change in fluid flow therein. In at least one embodiment, one or more circuits of a processor can cause a change in a variable speed fan or implement use of a modular unit instead of a secondary cooling loop or replacement of a modular unit.

[0108] In at least one embodiment, one or more neural networks of a processor can be adapted to receive sensor inputs and infer a change in coolant status. In at least one embodiment, one or more neural networks can be trained to make such inferences. In at least one embodiment, one or more neural networks can determine a failure of a primary cooling loop or a secondary cooling loop from sensor inputs. In at least one embodiment, one or more circuits of a processor can be adapted to cause at least one flow controller to implement cooling from a modular unit.

[0109] In at least one embodiment, one or more circuits of a processor can be used to train one or more neural networks to infer that a change in coolant status has occurred from sensor input from sensors associated with at least one computing device or fluid of an auxiliary cooling loop or modular unit. In at least one embodiment, a processor can be adapted to cause or enable one or more features to occur, such as at least one flow controller to stop or change flow of fluid, or change a variable speed fan, or replace a modular unit.

[0110] In at least one embodiment, one or more neural networks of a processor are capable of receiving sensor input from sensors discussed throughout this document and can be trained to infer a change in coolant status as part of an analysis of prior sensor input and prior coolant status. In at least one embodiment, an output of a process enables a signal to be provided for at least one flow controller to engage a modular unit based in part on a first threshold cooling requirement of at least one computing device and to engage an auxiliary cooling loop based in part on a second threshold cooling requirement of at least one computing device.

[0111] In at least one embodiment, a processor includes an input to receive sensor input, which can be associated with a temperature from at least one computing device or a temperature of fluid from an auxiliary cooling loop or modular unit. In at least one embodiment, a processor includes one or more circuits to load or pre-load one or more neural networks trained to infer that a change in coolant status has occurred based in part on a sensed temperature and a recorded prior temperature. In at least one embodiment, one or more circuits of a processor can cause a change in speed of a variable speed fan based in part on an inference by one or more neural networks trained.

[0112] In at least one embodiment, a processor can include one or more circuits with one or more neural networks to infer that a first change in coolant status has occurred from sensor input from sensors associated with at least one computing device or fluid. In at least one embodiment, a processor can include one or more circuits to cause one or more of at least one flow controller to stop or change flow of fluid, such as auxiliary coolant, local coolant, or other fluid. In at least one embodiment, a processor can include one or more circuits to cause a second change in a variable speed fan or to enable use of a modular unit.

[0113] In at least one embodiment, an output of processor can be adapted to provide a signal for one or more of at least one flow controller or a variable speed fan. In at least one embodiment, one or more flow controllers can enable fluid flow through a cold plate. In at least one embodiment, a variable speed fan can enable different speeds of forced air for a heat exchanger. In at least one embodiment, one or more neural networks can be adapted to receive sensor inputs and infer a change in coolant state as part of an analysis of prior sensor inputs and prior coolant state.

[0114] In at least one embodiment, an input of processor is adapted to receive sensor inputs associated with temperature from at least one computing device or fluid. In at least one embodiment, one or more neural networks are adapted to infer that a change in coolant state has occurred based in part on temperature and prior temperature, which can be from at least one computing device and / or at least fluid of an auxiliary cooling loop or local cooling loop. In at least one embodiment, one or more circuits of processor are adapted to cause a change in speed of a variable speed fan based in part on an inference made by one or more neural networks.

[0115] In at least one embodiment, Figures 1-4 Each of the at least one processor described in the preceding paragraphs can have inferencing and / or training logic 1815, which can include, without limitation, code and / or data storage 1801 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1801 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information can be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALUs). In at least one embodiment, code such as graph code loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network that is trained during training, or used during inferencing, with respect to one or more embodiments, during a forward propagation of input / output data and / or weight parameters. In at least one embodiment, any portion of code and / or data storage 1801 can be included with other on-chip or off-chip data storage, including a processor’s Ll, L2, or L3 cache or system memory.

[0116] In at least one embodiment, inference and / or training logic 1815 of at least one processor can be part of a building management system (BMS) for controlling flow controllers at one or more of a server level, a rack level, and a row level. In at least one embodiment, one or more neural networks of inference and / or training logic 1815 can be provided determinations for engaging flow controllers associated with local cooling loops, modular units, CDUs, cold plates, or cooling manifolds to cause one or more neural networks to infer which flow controllers can be normally engaged or disengaged with respect to coolant needs of one or more cold plates, servers, or racks for an auxiliary cooling loop or a local cooling loop. In at least one embodiment, an increase or decrease in fluid flow can be implemented by a flow controller controlled by inference and / or training logic 1815 of at least one processor associated with control logic associated with a local cooling loop. In at least one embodiment, one or more neural networks of inference and / or training logic 1815 can cause one or more neural networks to infer which variable speed fan is normally engaged, disengaged, or adjusted for coolant needs of one or more cold plates.

[0117] In at least one embodiment, at least one processor can be associated with a local cooling loop and an auxiliary cooling loop. In at least one embodiment, at least one processor includes control logic, such as inference and / or training logic 1815, and is associated with at least one flow controller. In at least one embodiment, at least one flow controller can have its own processor or microcontroller. In at least one embodiment, a processor or microcontroller executes instructions sent to it from control logic. In at least one embodiment, control logic can be determining a change in coolant status, such as a failure in an auxiliary cooling loop (e.g., CDU and cooling manifold) or a primary cooling loop (e.g., cooling plant, cooling manifold, and also associated CDUs). In at least one embodiment, a need for another modular unit as a replacement modular unit can also fail. In at least one embodiment, control logic can cause at least one flow controller to provide a coolant response, such as providing local coolant or auxiliary coolant for at least one computing device by engaging a local cooling loop having a fluid source and a liquid-to-air heat exchanger.

[0118] In at least one embodiment, control logic can cause a first signal to be sent to at least one flow controller to enable stopping of secondary coolant from a secondary cooling loop as part of a coolant response. In at least one embodiment, control logic can cause a second signal to be sent to at least one flow controller to enable starting of local coolant from a local cooling loop with a modular unit as part of a coolant response. In at least one embodiment, adjusting a variable speed fan in a modular unit can be a further coolant response. In at least one embodiment, control logic can receive sensor input from sensors associated with secondary coolant, local coolant, and / or at least one computing device of a CDU. In at least one embodiment, at least one processor can determine a change in coolant status based in part on sensor input. In at least one embodiment, one or more neural networks of inference and / or training logic 1815 can be adapted to receive sensor input and infer a change in coolant status.

[0119] In at least one embodiment, at least one processor can include one or more circuits for one or more neural networks, such as inference and / or training logic 1815. In at least one embodiment, inference and / or training logic 1815 can be adapted to infer a change in coolant status from sensor input associated with at least one server or at least one rack, such as coolant from a CDU being ineffective or retaining too much heat upon entering a rack. In at least one embodiment, one or more circuits can be adapted to cause at least one flow controller to provide a coolant response from a local cooling loop of a modular unit.

[0120] In at least one embodiment, control logic associated with one or more circuits can issue a first signal to at least one flow controller (along with any associated signals) to implement a coolant response. In at least one embodiment, a second signal sent to at least one variable speed fan can also implement a coolant response. In at least one embodiment, a distributed or integrated architecture is implemented by one or more circuits of at least one processor. In at least one embodiment, a distributed architecture can be supported by circuits in different locations in one or more circuits.

[0121] In at least one embodiment, one or more neural networks of inference and / or training logic 1815 can be adapted to infer an increase or decrease in cooling demand of at least one computing component of at least one server. In at least one embodiment, one or more circuits can be adapted to form a cooling loop through modular units having liquid-air heat exchangers to economically address a decreased cooling demand or supplement an increased cooling demand of at least one computing component. In at least one embodiment, implementing a cooling loop represents a coolant response from a local cooling loop to preempt a respective increase or respective decrease in cooling demand of at least one computing component of at least one server based in part on a workload sent to at least one computing component.

[0122] In at least one embodiment, at least one processor includes one or more circuits, such as inference and / or training logic 1815, to train one or more neural networks to infer from provided data. In at least one embodiment, inference and / or training logic 1815 can infer a change in coolant status from sensor inputs associated with at least one server or at least one rack. In at least one embodiment, inference can be used to enable one or more circuits to cause at least one flow controller of a local cooling loop to provide a coolant response or cause a speed change of a variable speed fan. In at least one embodiment, a coolant response can be to cause a coolant response from a local cooling loop to absorb heat into a local coolant of a modular unit and exchange absorbed heat from a liquid-air heat exchanger to an environment rather than an auxiliary cooling loop having a CDU.

[0123] In at least one embodiment, one or more circuits can be adapted to train one or more neural networks to infer an increase or decrease in cooling demand of at least one computing component of at least one server. In at least one embodiment, one or more circuits can be adapted to train one or more neural networks to infer that an increase or decrease in flow output from an auxiliary cooling loop is associated with an improper flow of auxiliary coolant due to a failed CDU or a respective increase or respective decrease in power demand of at least one computing component of at least one server.

[0124] In at least one embodiment, one or more neural networks can be trained to infer by prior associated thermal signatures or cooling demands from computing devices, servers, or racks and a cooling capacity or capability indicated by a fluid source of a local cooling loop. In at least one embodiment, prior cooling demands satisfied by a local cooling loop can be used to enable one or more neural networks to make similar inferences for similar cooling demands to be satisfied in future (allowing for minor variations there) by adjusting one or more flow controllers to engage a local cooling loop.

[0125] Figure 5 A method 500 associated with a data center cooling system of FIG. Figures 2-4 In at least one embodiment, method 500 includes step 502 for providing a modular unit including a heat exchanger, a variable speed fan, and at least one flow controller. In at least one embodiment, step 502 includes adapting the modular unit to be replaceable or hot-swappable. In at least one embodiment, step 504 enables fluid coupling between the modular unit and a cold plate that can include microchannels. In at least one embodiment, step 506 performs a determination of whether at least one computing device associated with the cold plate requires cooling. In at least one embodiment, upon determining that cooling is required in step 506, step 508 enables the at least one flow controller to cause fluid to pass through the microchannels of the cold plate.

[0126] In at least one embodiment, the required cooling can be based in part on sensors providing input such that such a determination can be made. In at least one embodiment, the required cooling can be a supplement to existing provided cooling that is deemed insufficient. In at least one embodiment, the required cooling can refer to more economical cooling than already exists and is already drawing heat from the at least one computing device. In at least one embodiment, the modular unit ensures efficient removal of high density heat with lower chance of leakage, but can be limited to addressing a threshold of cooling needs that can be less than cooling needs addressed by an auxiliary cooling loop. In at least one embodiment, step 510 enables fluid including heat drawn from the cold plate to pass through the heat exchanger. In at least one embodiment, fluid coupling can still be enabled as in step 504 if cooling is not required. In at least one embodiment, step 512 dissipates heat through forced air from the variable speed fan.

[0127] In at least one embodiment, method 500 includes steps or sub-steps for determining, by at least one processor, a temperature associated with at least one computing device or fluid and causing a change in speed of the variable speed fan as part of at least step 512. In at least one embodiment, method 500 includes steps or sub-steps for causing a copper coil or plate to be a heat exchanger.

[0128] In at least one embodiment, method 500 includes steps or substeps for enabling a cold plate to include a first port for a first portion of a microchannel to support a coolant differently than a second portion of a microchannel that supports a different fluid. In at least one embodiment, method 500 includes steps or substeps for enabling at least one processor to receive sensor input from sensors associated with at least one computing device or a fluid (e.g., secondary coolant, local coolant, or other fluid). In at least one embodiment, method 500 includes steps or substeps for determining, by at least one processor, a change in coolant status based in part on sensor input from sensors associated with a computing device, a modular unit, a secondary coolant, a local coolant, or other fluid. In at least one embodiment, method 500 includes steps or substeps for causing or effecting one or more of: at least one flow controller to stop or cause a change in flow of a fluid through a modular unit and / or a cold plate; at least one processor to cause a variable speed fan to change; or use of a modular unit. In at least one embodiment, stopping flow enables a quick disconnect flow controller to be disconnected and a modular unit to be removed and replaced.

[0129] Servers and Data Centers

[0130] The following figures illustrate, without limitation, example network server and data center based systems that can be used to implement at least one embodiment.

[0131] Figure 6 A distributed system 600 is shown in accordance with at least one embodiment. In at least one embodiment, distributed system 600 includes one or more client computing devices 602, 604, 606, and 608, which are configured to execute and operate a client application such as a web browser, a proprietary client, and / or variants thereof. In at least one embodiment, server 612 can be communicatively coupled with remote client computing devices 602, 604, 606, and 608 via network 610.

[0132] In at least one embodiment, server 612 can be adapted to run one or more services or software applications, such as services and applications that can manage session activity for single sign-on (SSO) access across multiple data centers. In at least one embodiment, server 612 can also provide other services, or software applications, which can include non-virtual and virtual environments. In at least one embodiment, these services can be provided as web-based services or cloud services or under a software as a service (SaaS) model to users of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating client computing devices 602, 604, 606, and / or 608 can in turn utilize one or more client applications to interact with server 612 to utilize services provided by these components.

[0133] In at least one embodiment, software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or services provided by these components can also be implemented by one or more of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating these client computing devices can then utilize one or more client applications to use services provided by these components. In at least one embodiment, these components can be implemented in hardware, firmware, software, or combinations thereof. It should be appreciated that various Figure 6 The illustrated embodiment is at least one embodiment of a distributed system for implementing an embodiment system and is not intended to be limiting.

[0134] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 can include different types of computing systems. In at least one embodiment, client computing devices can include portable handheld devices (e.g., an iPhone® by Apple Inc. of Cupertino, California, a cellular phone, a computing tablet, a personal digital assistant (PDA), or a wearable device (e.g., a Google head-mounted display) running software such as the Android® operating system (OS) by Google, Inc. of Mountain View, California, or the iOS® operating system (OS) by Apple Inc. of Cupertino, California. ) and / or various mobile operating systems such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS, and / or variations thereof. In at least one embodiment, the devices can support different applications such as different Internet-related applications, email, short message service (SMS) applications, and can use various other communications protocols. In at least one embodiment, client computing devices can also include general purpose personal computers including, by way of example, personal computers and / or laptops running various versions of Microsoft Windows, Apple MacOS, and / or Linux, and / or running proprietary operating systems. Client computing devices can also include tablet computers running variants of Windows, MacOS, Linux, and / or Android OS, and / or running proprietary operating systems. Client computing devices can include wearable devices running variants of Windows, MacOS, Linux, Android OS, and / or proprietary operating systems. Apple and / or Linux operating systems.

[0135] In at least one embodiment, client computing devices can be workstation computers running any of a variety of commercially-available UNIX, such as the various GNU / Linux operating systems such as Google Chrome OS. In at least one embodiment, client computing devices can also include devices running Microsoft Xbox using gesture input devices), and / or a personal messaging device, capable of communicating over one or more networks 610. Although Figure 6 Distributed system 600 is shown with four client computing devices, but any number of client computing devices can be supported. Other devices can interact with server 612, such as devices having sensors, etc.

[0136] In at least one embodiment, network 610 in distributed system 600 can be any type of network familiar to those skilled in the art that can support data communications using any of a variety of available protocols, including without limitation TCP / IP (transmission control protocol / Internet protocol), SNA (systems network architecture), IPX (Internet packet exchange), AppleTalk, and / or variations thereof. In at least one embodiment, network 610 can be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network, the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network, e.g., a network operating under any of the Institute of Electrical and Electronics (IEEE) 802.11 suite of protocols, Bluetooth®, and / or any other wireless protocol(s), and / or any combination thereof. and / or any other wireless protocol(s)), and / or any combination thereof.

[0137] In at least one embodiment, the server 612 may be comprised of one or more general purpose computers, dedicated server computers (including, in at least one embodiment, PC (personal computer) servers, The server 612 may be composed of a plurality of servers (e.g., servers, mid-range servers, mainframe computers, rack servers, etc.), a server farm, a server cluster, or any other suitable arrangement and / or combination. In at least one embodiment, the server 612 may include one or more virtual machines running virtual operating systems or other computing architectures involving virtualization. In at least one embodiment, one or more flexible logical storage device pools may be virtualized to maintain virtual storage devices for the server. In at least one embodiment, the virtual network may be controlled by the server 612 using software-defined networking. In at least one embodiment, the server 612 may be adapted to run one or more services or software applications.

[0138] In at least one embodiment, the server 612 can run any operating system, and any commercially available server operating system. In at least one embodiment, the server 612 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP (Hypertext Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, Server, database server and / or variants thereof.In at least one embodiment, exemplary database servers include, but are not limited to, those commercially available from Oracle, Microsoft, Sybase, IBM (International Business Machines), and / or variants thereof.

[0139] In at least one embodiment, server 612 may include one or more applications for analyzing and consolidating data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, data feeds and / or event updates may include, but are not limited to, data received from one or more third-party information sources and continuous data streams. feed, Updates or real-time updates, which may include real-time events related to sensor data applications, financial quoters, network performance measurement tools (e.g., network monitoring and business management applications), clickstream analysis tools, automobile traffic monitoring, and / or changes thereto. In at least one embodiment, server 612 may also include one or more applications for displaying data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0140] In at least one embodiment, distributed system 600 can also include one or more databases 614 and 616. In at least one embodiment, databases can provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 614 and 616 can reside in various locations. In at least one embodiment, one or more of databases 614 and 616 can reside on a non-transitory storage medium local to (and / or in) server 612. In at least one embodiment, databases 614 and 616 can be remote from server 612 and in communication with server 612 via a network-based or dedicated connection. In at least one embodiment, databases 614 and 616 can reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing functions attributed to server 612 can be appropriately either locally stored on server 612 and / or remotely stored. In at least one embodiment, databases 614 and 616 can comprise a relational database such as one adapted to store, update, and retrieve data in response to SQL-formatted commands.

[0141] Figure 7 An example data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, without limitation, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0142] In at least one embodiment, as shown in Figure 7 In at least one embodiment, data center infrastructure layer 710 can include a resource orchestrator 712, grouped computing resources 714, and node computing resources (“node C.R.”) 716(1)-716(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s 716(1)-716(N) can include, without limitation, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), graphics processors, etc.), memory devices (e.g., dynamic random access memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of node C.R.s 716(1)-716(N) can be a server having one or more of the above computing resources.

[0143] In at least one embodiment, grouped computing resources 714 can include individual groupings of nodes C.R. housed within one or more racks (not shown), or housed within a number of racks (also not shown) within various geographic locations. Individual groupings of nodes C.R. within grouped computing resources 714 can include grouped computing, network, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several nodes C.R. including CPUs or processors can be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches in any combination.

[0144] In at least one embodiment, resource orchestrator 712 can configure or otherwise control one or more nodes C.R. 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource orchestrator 712 can include a software design infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource orchestrator 712 can include hardware, software, or some combination thereof.

[0145] In at least one embodiment, as Figure 7As shown, framework layer 720 includes, without limitation, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, framework layer 720 can include a framework that supports software 752 of software layer 730 and / or one or more applications 742 of application layer 740. In at least one embodiment, software 752 or applications 742 can include, respectively, web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 can be, without limitation, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that can utilize distributed file system 738 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 732 can include a Spark driver to facilitate scheduling workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 734 can be capable of configuring different layers, such as software layer 730 and framework layer 720 including Spark and distributed file system 738 for supporting large-scale data processing. In at least one embodiment, resource manager 736 can be capable of managing clustered or grouped computing resources mapped to or allocated for supporting distributed file system 738 and job scheduler 732. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 714 on data center infrastructure layer 710. In at least one embodiment, resource manager 736 can coordinate with resource orchestrator 712 to manage these mapped or allocated computing resources.

[0146] In at least one embodiment, software 752 included in software layer 730 can include software used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of software can include, without limitation, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0147] In at least one embodiment, one or more applications 742 included in application layer 740 can include one or more types of applications used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of applications can include, without limitation, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.

[0148] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource orchestrator 712 can implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions can relieve data center operators of data center 700 from making possibly poor configuration decisions and can avoid underutilization and / or poor-performing portions of a data center.

[0149] Figure 8 A client-server network 804 formed of a plurality of network server computers 802 interconnected is shown, according to at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible by other network server computers 802 and client computers 806 and networks 808 linked to a wide area network 804. In at least one embodiment, a configuration of client-server network 804 can change over time as client computers 806 and one or more networks 808 connect and disconnect with network 804, and as one or more backbone server computers 802 are added to or removed from network 804. In at least one embodiment, a client-server network includes client computers 806 and networks 808 when they are connected with network server computers 802. In at least one embodiment, the term computer includes any device or machine that is capable of accepting data, applying prescribed processes to data, and providing results of processes.

[0150] In at least one embodiment, client-server network 804 stores information accessible to web server computers 802, remote network 808, and client computers 806. In at least one embodiment, web server computers 802 are formed from mainframe computers, minicomputers, and / or microcomputers each having one or more processors. In at least one embodiment, server computers 802 are linked together through wired and / or wireless transmission media, such as wire, fiber optic cable, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, client computers 806 access web server computers 802 through similar wired or wireless transmission media. In at least one embodiment, client computers 806 can link into client-server network 804 using modems and standard telephone communication networks. In at least one embodiment, alternative carrier systems, such as cable and satellite communication systems, can also be used to link into client-server network 804. In at least one embodiment, other private or time-shared carrier systems can be used. In at least one embodiment, network 804 is a global information network, such as the Internet. In at least one embodiment, network is a private intranet using similar protocols as the Internet but with added security measures and restricted access controls. In at least one embodiment, network 804 is a private or semi-private network using proprietary communication protocols.

[0151] In at least one embodiment, client computers 806 are any end-user computers, and can also be mainframe computers, minicomputers, or microcomputers having one or more microprocessors. In at least one embodiment, server computers 802 can sometimes act as client computers accessing another server computer 802. In at least one embodiment, remote network 808 can be a local area network, a network added to a wide area network through an independent service provider (ISP) for the Internet, or another group of computers interconnected by wired or wireless transmission media having a fixed or changing configuration over time. In at least one embodiment, client computers 806 can link into and access network 804 independently or through remote network 808.

[0152] Figure 9A computer network 908 connecting one or more computer machines is shown in accordance with at least one embodiment. In at least one embodiment, network 908 can be any type of electrically connected computer group, including, for example, the following networks: the Internet, an intranet, a local area network (LAN), a wide area network (WAN), or an interconnected combination of these network types. In at least one embodiment, connections within network 908 can be a remote modem, Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), Fiber Distributed Datalink Interface (FDDI), Asynchronous Transfer Mode (ATM), or any other communications protocol. In at least one embodiment, computing devices linked to network can be desktops, servers, portable, handheld, set-top, personal digital assistants (PDAs), terminals, or any other desired type or configuration. In at least one embodiment, network-connected devices can vary widely in processing power, internal memory, and other performance depending on their functionality.

[0153] In at least one embodiment, communications within network and to or from computing devices connected to network can be wired or wireless. In at least one embodiment, network 908 can include, at least in part, the world-wide public Internet, which typically connects multiple users according to a client-server model according to Transmission Control Protocol / Internet Protocol (TCP / IP) specifications. In at least one embodiment, a client-server network is a dominant model for communication between two computers. In at least one embodiment, a client computer (“client”) issues one or more commands to a server computer (“server”). In at least one embodiment, a server fulfills client commands by accessing available network resources and returning information to a client according to client commands. In at least one embodiment, client computer systems and network resources residing on network servers are assigned network addresses for identification during communications between elements of a network. In at least one embodiment, communications from other network-connected systems to a server will include a network address of a relevant server / network resource as part of a communication, so that an appropriate destination for data / requests is identified as a recipient. In at least one embodiment, when network 908 includes the global Internet, network addresses are IP addresses in TCP / IP format, which can route data, at least in part, to an email account, website, or other Internet tool residing on a server. In at least one embodiment, information and services residing on network servers can be available to web browsers of client computers through a domain name (e.g., www.site.com), which maps to an IP address of a network server.

[0154] In at least one embodiment, multiple clients 902, 904, and 906 connect to network 908 via corresponding communication links. In at least one embodiment, each of these clients can access network 908 via any desired form of communication, such as via a dial-up modem connection, cable link, digital subscriber line (DSL), wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine compatible with network 908 (e.g., a personal computer (PC), a workstation, a dedicated terminal, a personal data assistant (PDA), or other similar device). In at least one embodiment, clients 902, 904, and 906 can or can not be located in the same geographic region.

[0155] In at least one embodiment, multiple servers 910, 912, and 914 are connected to network 918 to serve clients in communication with network 918. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, servers include computer-readable data storage media, such as hard drive and RAM memory, that store program instructions and data. In at least one embodiment, servers 910, 912, 914 run application programs in response to client commands. In at least one embodiment, server 910 can run a web server application for responding to client requests for HTML pages, and can also run a mail server application for receiving and routing electronic mail. In at least one embodiment, other application programs can also run on server 910, such as an FTP server or media server for streaming audio / video data to clients. In at least one embodiment, different servers can be dedicated to performing different tasks. In at least one embodiment, server 910 can be a dedicated web server that manages resources related to a website for different users, while server 912 can be dedicated to providing electronic mail (email) management. In at least one embodiment, other servers can be dedicated to media (audio, video, etc.), file transfer protocol (FTP), or a combination of any two or more services typically available or provided over a network. In at least one embodiment, each server can be in the same or different location as other servers. In at least one embodiment, there can be multiple servers performing mirror tasks for users, thereby relieving congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, 914 are under the control of a web hosting provider that maintains and delivers third-party content over network 918.

[0156] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which can be referred to as a browser, requests content from servers 910, 912, 914, such as web pages, email messages, video clips, etc. In at least one embodiment, a second type, which can be referred to as a user, hires the web hosting provider to maintain a network resource, such as a website, and make it available to browsers. In at least one embodiment, a user contracts with a web hosting provider to make memory space, processor capacity, and communication bandwidth available to their desired network resource according to the amount of server resources the user desires to utilize.

[0157] In at least one embodiment, in order for the web hosting provider to provide services to both clients, the application programs that manage the network resources hosted by the servers must be properly configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application program’s response to browser requests, and also at least partially define the server resources available to a particular user.

[0158] In one embodiment, intranet server 916 communicates with network 908 via a communication link. In at least one embodiment, intranet server 916 communicates with server manager 918. In at least one embodiment, server manager 918 includes a database of application program configuration parameters used in servers 910, 912, 914. In at least one embodiment, a user modifies database 920 via intranet 916, and server manager 918 interacts with servers 910, 912, 914 to modify the application program parameters so that they match the contents of the database. In at least one embodiment, a user logs into intranet 916 by connecting to intranet 916 via computer 902 and entering authentication information such as a username and password.

[0159] In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that allows the user to access configuration parameters for a particular application. In at least one embodiment, the user is presented with a number of modifiable text boxes that describe aspects of the user's website or other network resource's configuration. In at least one embodiment, if the user desires to increase the amount of memory space reserved on the server for their website, the user is provided with a field in which the user specifies the desired amount of memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards this information to the appropriate server, and the new parameters are used during operation of the application. In at least one embodiment, the intranet server 916 is configured to provide the user with access to configuration parameters for a hosted network resource (e.g., web page, email, FTP site, media site, etc.) that the user has contracted with a web hosting service provider.

[0160] Figure 10A A networked computer system 1000A is shown in accordance with at least one embodiment. In at least one embodiment, the networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, the personal computers or nodes 1002 include a processor 1014, a memory 1016, a video camera 1004, a microphone 1006, a mouse 1008, a speaker 1010, and a monitor 1012. In at least one embodiment, the PCs 1002, 1018, 1020 can each run one or more desktop servers for an internal network within a given company, or can be servers for a general-purpose network that is not limited to a particular environment. In at least one embodiment, there is one server per PC node of the network, such that each PC node of the network represents a particular network server with a particular network URL address. In at least one embodiment, each server has a default web page for the user of that server by default, which default web page can itself contain embedded URLs pointing to further sub-pages of that user on that server, or to other servers on the network or pages on other servers.

[0161] In at least one embodiment, nodes 1002, 1018, 1020, and other nodes of network are interconnected by a medium 1022. In at least one embodiment, medium 1022 can be a communication channel such as an Integrated Services Digital Network (“ISDN”). In at least one embodiment, various nodes of a networked computer system can be connected by various communication media, including a Local Area Network (“LAN”), a Plain Old Telephone Line (“POTS”) (sometimes referred to as a Public Switched Telephone Network (“PSTN”)), and / or variations thereof. In at least one embodiment, various nodes of a network can also constitute computer system users interconnected via a network such as the Internet. In at least one embodiment, each server on a network (running from a particular node of a network at a given instance) has a unique address or identification within a network, which can be specified according to a URL.

[0162] In at least one embodiment, multiple Multipoint Conference Units (“MCUs”) can thus be used to transmit data to and from various nodes or “endpoints” of a conferencing system. In at least one embodiment, nodes and / or MCUs can be interconnected via ISDN links or through a Local Area Network (“LAN”), in addition to various other communication media, such as nodes connected through the Internet. In at least one embodiment, nodes of a conferencing system can typically be connected either directly to a communication medium such as a LAN or through an MCU, and a conferencing system can include other nodes or elements such as routers, servers, and / or variations thereof.

[0163] In at least one embodiment, processor 1014 is a general-purpose programmable processor. In at least one embodiment, a processor of a node of networked computer system 1000A can also be a special-purpose video processor. In at least one embodiment, different peripherals and components of a node, such as those of node 1002, can differ from those of other nodes. In at least one embodiment, node 1018 and node 1020 can be configured the same as or differently from node 1002. In at least one embodiment, nodes can be implemented on any suitable computer system in addition to a PC system.

[0164] Figure 10BA networked computer system 1000B is shown in accordance with at least one embodiment. In at least one embodiment, system 1000B shows a network, such as LAN 1024, which can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are a number of nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, nodes can also connect to the LAN via a web server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, including routers, servers, and nodes for at least one embodiment.

[0165] Figure 10C A networked computer system 1000C is shown in accordance with at least one embodiment. In at least one embodiment, system 1000C shows a WWW system with communication across a backbone communication network, such as Internet 1032, which can be used to interconnect various nodes of a network. In at least one embodiment, the WWW is a set of protocols that operate on top of the Internet, and allows graphical interface systems to operate on it in order to access information over the Internet. In at least one embodiment, attached to Internet 1032 in the WWW are a number of nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, nodes interface with other nodes of the WWW through WWW HTTP servers, such as servers 1034, 1036. In at least one embodiment, PC 1044 can be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although PC 1044 and server 1036 are shown separately in Figure 10C for purposes of illustration.

[0166] In at least one embodiment, the WWW is a distributed type of application, characterized by WWW HTTP, the protocol of the WWW, which operates on top of the Transmission Control Protocol / Internet Protocol (“TCP / IP”) of the Internet. In at least one embodiment, the WWW can thus be characterized by a set of protocols (i.e., HTTP) that operate on the Internet as its “backbone.”

[0167] In at least one embodiment, a web browser is an application running on a node of a network in a network system of the WWW type that allows a user of a particular server or node to view such information and thus allows the user to search through graphical and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understand HTTP. In at least one embodiment, when a user uses another server on a network such as the Internet to retrieve a given web page of a first server associated with a first node, the retrieved document can have different hypertext links embedded in it, and a local copy of the page is created locally at the retrieval user's machine. In at least one embodiment, when the user clicks on a hypertext link, the locally stored information related to the selected hypertext link is typically sufficient to allow the user's machine to open a connection through the Internet to the server indicated by the hypertext link.

[0168] In at least one embodiment, more than one user can be coupled to each HTTP server through a LAN such as LAN 1038, such as shown with respect to WWW HTTP server 1034. In at least one embodiment, system 1000C can also include other types of nodes or elements. In at least one embodiment, a WWW HTTP server is an application running on a machine such as a PC. In at least one embodiment, each user can be considered to have a unique "server" as shown with respect to PC 1044. In at least one embodiment, a server can be considered to be a server such as WWW HTTP server 1034 that provides access to a network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each with a desktop PC or node of a network, each desktop PC potentially setting up a server for its user. In at least one embodiment, each server is associated with a particular network address or URL that, when accessed, provides a default web page for that user. In at least one embodiment, the web page can contain further links (embedded URLs) that point to further sub-pages of that user on that server, or to other servers on the network or to pages on other servers on the network.

[0169] Cloud computing and services

[0170] The following figures set forth, but are not limited to, exemplary cloud-based systems that can be used to implement at least one embodiment.

[0171] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and often virtualized resources are provided as a service over the Internet. In at least one embodiment, users do not need to have knowledge, understanding or control over the technology infrastructure in the “cloud” that supports them, in at least one embodiment, cloud computing converges infrastructure as a service, platform as a service, software as a service, and other variants that have common themes of reliance on internet for delivery of common tasks to meet users’ computing needs. In at least one embodiment, a typical cloud deployment, such as in a private cloud (e.g., enterprise network) or data center (DC) in a public cloud (e.g., Internet), can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel or Fibre Channel over Ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, a cloud can also consist of network services infrastructure, such as IPsec VPN hubs, firewalls, load balancers, Wide Area Network (WAN) optimizers, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services by connecting via a VPN tunnel, such as an IPsec VPN tunnel.

[0172] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0173] In at least one embodiment, cloud computing is characterized by on-demand self-service, wherein consumers can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically (without requiring human interaction with each service provider). In at least one embodiment, cloud computing is characterized by broad network access, wherein capabilities are available over a network and accessed through standard mechanisms that promote the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, wherein the provider’s computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally have no control or knowledge over the exact location of the provided resources, but can be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0174] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, in which capability can be rapidly and elastically provisioned (in some cases automatically), in some cases with little or no management effort or interaction with provider. In at least one embodiment, cloud computing is characterized by pay-per-use billing in which users are only billed for the capacity that they actually use — contributing to what is often a substantial cost savings for users. In at least one embodiment, cloud computing is characterized by measured service, in which cloud systems automatically control and optimize resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage can be monitored, controlled, and reported providing transparency for both the provider and consumer of the service.

[0175] In at least one embodiment, cloud computing can be associated with various services. In at least one embodiment, cloud Software as a Service (SaaS) can refer to a paradigm in which the providing of an application is delivered to a consumer on a cloud infrastructure. In at least one embodiment, the application is accessible from various client devices through a thin client interface such as a web browser (e.g., web-based e-mail). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0176] In at least one embodiment, cloud Platform as a Service (PaaS) can refer to a paradigm in which the providing of a platform is delivered by the provider. The platform can be comprised of tools, libraries and infrastructure that support the development and execution of applications. In at least one embodiment, consumer developers can develop, test, deploy, and / or serve their created applications using programming languages and tools supported by the provider. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

[0177] In at least one embodiment, cloud Infrastructure as a Service (IaaS) can refer to a paradigm in which the providing of infrastructure is delivered by the provider. The infrastructure can be comprised of computer servers that a consumer can program or control. In at least one embodiment, the consumer does not manage or control or does not have direct control over the underlying cloud infrastructure including networks, servers, operating systems, storage, or even individual applications. In at least one embodiment, the consumer retains control over operating systems and storage, has control over deployed applications and possibly limited control of select networking components (e.g., host firewalls).

[0178] In at least one embodiment, cloud computing provides a convenient, on-demand network access to a shared pool of configurable computing resources. In at least one embodiment, such resources include networks, servers, storage, applications, and client data, which can be readily provisioned and released with reduced management effort or service provider interaction. In at least one embodiment, a cloud model can be Service Provider’s Infrastructure, Platforms, and / or Software as a Service (SaaS), or some combination thereof. In at least one embodiment, cloud computing resources can be hosted locally or by a third party.

[0179] Figure 11 One or more components of a system environment 1100, in accordance with one or more embodiments, are shown in which services can be provided as third party network services. In at least one embodiment, a third party network can be referred to as a cloud, a cloud network, a cloud computing network, and / or variations thereof. In at least one embodiment, system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which can be used by users to interact with a third party network infrastructure system 1102 that provides third party network services, which can be referred to as cloud computing services. In at least one embodiment, third party network infrastructure system 1102 can include one or more computers and / or servers.

[0180] It is to be appreciated that the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, an embodiment of a third party network infrastructure system is depicted. In at least one embodiment, third party network infrastructure system 1102 can have more or fewer components than depicted in FIG. 11, can have a different configuration or arrangement of components, or can have different names. In at least one embodiment, a user of a client computing device 1104, 1106, or 1108 can access the third party network infrastructure system 1102 through the network 1110. Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in

[0181] In at least one embodiment, client computing devices 1104, 1106, and 1108 can be configured to operate a client application such as a web browser that can be used by users of client computing devices to interact with third party network infrastructure system 1102 to use services provided by third party network infrastructure system 1102. Although example system environment 1100 is illustrated as having three client computing devices, any number of client computing devices can be supported. In at least one embodiment, other devices such as devices with sensors, etc. can interact with third party network infrastructure system 1102. In at least one embodiment, one or more networks 1110 can facilitate communications and exchange of data between client computing devices 1104, 1106, and 1108 and third party network infrastructure system 1102.

[0182] In at least one embodiment, services provided by third party network infrastructure system 1102 can include hosting of services available on demand to users of third party network infrastructure system. In at least one embodiment, various services can also be provided including, but not limited to, online data storage and backup solutions, Web-based electronic mail services, managed office suites and document collaboration services, database management and processing, managed technical support services, and / or variations thereof. In at least one embodiment, services provided by a third party network infrastructure system can dynamically scale to meet the needs of its users.

[0183] In at least one embodiment, a particular instantiation of a service provided by third party network infrastructure system 1102 can be referred to as a “service instance.” In at least one embodiment, generally, any service available to a user from a third party network service provider system via a communications network, such as the Internet, is referred to as a “third party network service.” In at least one embodiment, in a public third party network environment, servers and systems that make up the third party network service provider system are distinct from a customer’s on-premise servers and systems. In at least one embodiment, a third party network service provider system can host an application and users can order and utilize the application on-demand via a communications network, such as the Internet.

[0184] In at least one embodiment, a service in a computer network third party network infrastructure can include protected computer network access to storage, hosted databases, hosted network servers, software applications, or other services provided to a user by a third party network vendor. In at least one embodiment, a service can include password protected access to remote storage on a third party network over the Internet. In at least one embodiment, a service can include a network service based hosted relational database and scripting language middleware engine for private use by a networked developer. In at least one embodiment, a service can include access to an email software application hosted on a website of a third party network vendor.

[0185] In at least one embodiment, third party network infrastructure system 1102 can include a suite of applications, middleware, and database service offerings that are delivered to customers in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, third party network infrastructure system 1102 can also provide “big data” related computing and analytics services. In at least one embodiment, the term “big data” is commonly used to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by infrastructure system at many levels and at different scales. In at least one embodiment, tens, hundreds, or thousands of processors linked in parallel can act on such data to present the data or simulate an outside force on the data or what it represents. In at least one embodiment, these data sets can involve structured data (such as structured data in a database or otherwise organized according to a structured model) and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging capabilities of embodiments to relatively quickly focus more (or less) computing resources on a target, third party network infrastructure system can be better used to perform tasks on big data sets based on demand from businesses, government agencies, research organizations, private individuals, groups of like-minded individuals or organizations, or other entities.

[0186] In at least one embodiment, third party network infrastructure system 1102 can be adapted to automatically provide, manage and track customer subscriptions for services provided by third party network infrastructure system 1102. In at least one embodiment, third party network infrastructure system 1102 can provide third party network services via different deployment models. In at least one embodiment, services can be provided under a public third party network model in which third party network infrastructure system 1102 is owned by an organization that sells third party network services and makes services available to the general public or different industry enterprises. In at least one embodiment, services can be provided under a private third party network model in which third party network infrastructure system 1102 operates for a single organization and can provide services for one or more entities within the organization. In at least one embodiment, third party network services can also be provided under a community third party network model in which third party network infrastructure system 1102 and the services provided by third party network infrastructure system 1102 are shared by several organizations in a related community. In at least one embodiment, third party network services can also be provided under a hybrid third party network model, which is a combination of two or more different models.

[0187] In at least one embodiment, services provided by third party network infrastructure system 1102 can include one or more services provided under a Software as a Service (SaaS) category, a Platform as a Service (PaaS) category, an Infrastructure as a Service (IaaS) category, or other categories of services including hybrid services. In at least one embodiment, a customer can order one or more services provided by third party network infrastructure system 1102 via a subscription order. In at least one embodiment, third party network infrastructure system 1102 then performs processing to provide services in customer’s subscription order.

[0188] In at least one embodiment, services provided by third party network infrastructure systems 1102 can include, without limitation, application services, platform services, and infrastructure services. In at least one embodiment, application services can be provided by third party network infrastructure systems via a SaaS platform. In at least one embodiment, a SaaS platform can be configured to provide third party network services that fall into the SaaS category. In at least one embodiment, a SaaS platform can provide the capability for customers to use applications, running on third party network infrastructure systems, that are built using an integrated development and deployment platform. In at least one embodiment, a SaaS platform can manage and control underlying software and infrastructure for providing the SaaS services. In at least one embodiment, by utilizing the services provided by a SaaS platform, customers can no longer have to worry about acquiring and managing the underlying hardware and software. In at least one embodiment, customers can obtain an application service without the need for customers to purchase, install, and manage software or hardware. In at least one embodiment, various different SaaS services can be provided. In at least one embodiment, this can include, without limitation, services for sales performance management, enterprise integration, and business flexibility that provide solutions for managing sales, aligning sales with customers, and improving business responsiveness, respectively.

[0189] In at least one embodiment, platform services can be provided by third party network infrastructure systems 1102 via a PaaS platform. In at least one embodiment, a PaaS platform can be configured to provide third party network services that fall into the PaaS category. In at least one embodiment, platform services can include, without limitation, services enabling organizations to combine existing applications with new applications built using the shared services provided by the platform, as well as the ability to establish new applications that leverage the shared services provided by the platform. In at least one embodiment, a PaaS platform can manage and control the underlying software and infrastructure for providing the PaaS services. In at least one embodiment, customers can obtain PaaS services provided by third party network infrastructure systems 1102 without the need for customers to purchase, install, and manage the underlying hardware and software.

[0190] In at least one embodiment, by utilizing the services provided by a PaaS platform, customers can use programming languages and tools supported by the third party network infrastructure system and also control deployed services. In at least one embodiment, platform services provided by a third party network infrastructure system can include database third party network services, middleware third party network services, and third party network services. In at least one embodiment, database third party network services can support a shared services deployment model that enables organizations to pool database resources and offer customers database as a service in the form of a database third party network. In at least one embodiment, middleware third party network services can provide customers with a platform for developing and deploying various business applications, and third party network services can provide customers with a platform to deploy applications in a third party network infrastructure system.

[0191] In at least one embodiment, various different infrastructure services can be provided by an IaaS platform in third party network infrastructure system. In at least one embodiment, infrastructure services facilitate the management and control of underlying computing resources, such as storage, networks, and other fundamental computing resources for customers utilizing services provided by SaaS and PaaS platforms.

[0192] In at least one embodiment, third party network infrastructure system 1102 can also include infrastructure resources 1130 for providing resources used to offer various services of third party network infrastructure system to customers. In at least one embodiment, infrastructure resources 1130 can include pre-integrated and optimized combinations of hardware, such as, for example, servers, storage and networking resources to execute the services provided by PaaS and SaaS platforms and other resources.

[0193] In at least one embodiment, resources in third party network infrastructure system 1102 can be shared by multiple users and dynamically re-allocated per demand. In at least one embodiment, resources can be allocated to users in different time zones. In at least one embodiment, third party network infrastructure system 1102 can enable a first set of users in a first time zone to utilize resources of third party network infrastructure system for a specified number of hours and subsequently enable reallocation of same resources to another set of users located in a different time zone, thereby maximizing resource utilization.

[0194] In at least one embodiment, a number of internal shared services 1132 can be provided that are shared by different components or modules of third party network infrastructure system 1102 for implementing services offered by third party network infrastructure system 1102. In at least one embodiment, these internal shared services can include, but are not limited to, security and identity services, integration services, enterprise repository services, enterprise manager services, virus scanning and white list services, high availability, backup and recovery services, services for enabling third party network support, email services, notification services, file transfer services, and / or variations thereof.

[0195] In at least one embodiment, third party network infrastructure system 1102 can provide comprehensive management of third party network services (e.g., SaaS, PaaS, and IaaS services) in third party network infrastructure system. In at least one embodiment, third party network management functionality can include the ability to provision, manage and track subscriptions of customers received by third party network infrastructure system 1102 and / or variations thereof.

[0196] In at least one embodiment, as Figure 11As shown, the third party network management functionality can be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order provisioning module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules can include or use one or more computers and / or servers, which can be general purpose computers, special purpose server computers, server farms, server clusters, or any other appropriate arrangement and / or combination.

[0197] In at least one embodiment, at step 1134, a customer using a client device, such as client computing device 1104, 1106, or 1108, can interact with the third party network infrastructure system 1102 by requesting and placing an order for subscription to one or more services provided by the third party network infrastructure system 1102. In at least one embodiment, the customer can access third party network user interfaces (UIs), such as third party network UI 1112, third party network UI 1114, and / or third party network UI 1116, and place the order for subscription via these UIs. In at least one embodiment, order information received by the third party network infrastructure system 1102 in response to the customer placing the order can include information identifying the customer and one or more services provided by the third party network infrastructure system 1102 that the customer wants to subscribe to.

[0198] In at least one embodiment, at step 1136, the order information received from the customer can be stored in an order database 1118. In at least one embodiment, if this is a new order, a new record can be created for the order. In at least one embodiment, the order database 1118 can be one of several databases operated by the third party network infrastructure system 1118 and in conjunction with other system elements.

[0199] In at least one embodiment, at step 1138, the order information can be forwarded to an order management module 1120, which can be configured to perform billing and accounting functions related to the order, such as validating the order, and, upon validation, provisioning the order.

[0200] In at least one embodiment, at step 1140, information about the order can be transmitted to an order coordination module 1122 configured to coordinate the provisioning of services and resources for orders placed by customers. In at least one embodiment, order coordination module 1122 can use the services of an order provisioning module 1124 for provisioning. In at least one embodiment, order coordination module 1122 enables management of business processes associated with each order and applies business logic to determine whether an order should continue to be provisioned.

[0201] In at least one embodiment, at step 1142, upon receiving a new subscribed order, order coordination module 1122 sends a request to order provisioning module 1124 to allocate resources and configure resources needed to fulfill the subscribed order. In at least one embodiment, order provisioning module 1124 implements resource allocation for services ordered by customers. In at least one embodiment, order provisioning module 1124 provides a level of abstraction between third-party network infrastructure systems 1100 provided third-party network services and physical implementation layers used to provision resources for providing the requested services. In at least one embodiment, this enables order coordination module 1122 to be isolated from implementation details, such as whether services and resources are provisioned in real-time or pre-provisioned and only allocated / assigned upon request.

[0202] In at least one embodiment, at step 1144, once services and resources are provisioned, a notification can be sent to the subscribing customer indicating that the requested services are now ready for use. In at least one embodiment, information (e.g., a link) can be sent to the customer that enables the customer to begin using the requested services.

[0203] In at least one embodiment, at step 1146, orders for customers subscribing can be managed and tracked by an order management and monitoring module 1126. In at least one embodiment, order management and monitoring module 1126 can be configured to collect usage statistics about customer usage of subscribed services. In at least one embodiment, statistics can be collected for amount of storage used, amount of data transferred, number of users, and amount and / or changes in system up times and system down times.

[0204] In at least one embodiment, third party network infrastructure system 1100 can include an identity management module 1128 configured to provide identity services such as access management and authorization services in third party network infrastructure system 1100. In at least one embodiment, identity management module 1128 can control information about customers who wish to utilize services provided by third party network infrastructure system 1102. In at least one embodiment, such information can include information to authenticate identities of such customers and information describing what actions those customers are authorized to perform with respect to various system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, identity management module 1128 can also include managing descriptive information about each customer and descriptive information about how and by whom the descriptive information can be accessed and modified.

[0205] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, cloud computing environment 1202 includes one or more computer systems / server 1204 that are in communication with one or more computing devices, such as personal digital assistant (PDA) or cellular telephone 1206A, desktop computer 1206B, laptop computer 1206C, and / or automobile computer system 1206N, that are in communication with one or more computer systems / server 1204. In at least one embodiment, this allows infrastructure, platforms, and / or software as a service to be offered from cloud computing environment 1202 to clients, which can not need to individually maintain such resources. It should be understood that Figure 12 The types of computing devices 1206A-N shown in FIG. 12 are intended to be illustrative only and that cloud computing environment 1202 can communicate with any type of computerized device over any type of network and / or network / addressable connection (e.g., using a web browser).

[0206] In at least one embodiment, computer system / server 1204 can be operational with numerous other general purpose or special purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations that can be suitable for use with computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and / or variants thereof.

[0207] In at least one embodiment, computer system / server 1204 can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. In at least one embodiment, exemplary computer system / server 1204 can be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In at least one embodiment, in a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media, including memory storage devices.

[0208] Figure 13 The cloud computing environment 1202 ( Figure 12 ) provides a set of functional abstraction layers. It should be understood in advance that Figure 13 The components, layers, and functions shown in are intended to be illustrative only, and the components, layers, and functions may vary.

[0209] In at least one embodiment, the hardware and software layer 1302 includes hardware and software components. In at least one embodiment, the hardware components include mainframes, servers based on various RISC (Reduced Instruction Set Computer) architectures, various computing systems, supercomputing systems, storage devices, networks, networking components, and / or variations thereof. In at least one embodiment, the software components include network application server software, various application server software, various database software, and / or variations thereof.

[0210] In at least one embodiment, the virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities can be provided: virtual servers, virtual storage, virtual networks (including virtual private networks), virtual applications, virtual clients, and / or variations thereof.

[0211] In at least one embodiment, management layer 1306 provides various functions. In at least one embodiment, resource provisioning provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. In at least one embodiment, metering provides usage tracking of resources in use, for example, the usage of application software licenses. In at least one embodiment, provisioning provides a single point of management functionality that enables ubiquitous underwriting and rapid deployment of resources by orchestrating different layers of the cloud computing environment. In at least one embodiment, security provides identity verification for users and tasks, as well as protection for data and other resources. In at least one embodiment, user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides cloud computing resource allocation and management such that required service levels are met. In at least one embodiment, service level agreement (SLA) planning and fulfillment provides pre-arrangement for, and fulfillment of, cloud computing resources to provide desired level of service to a user.

[0212] In at least one embodiment, workload layer 1308 provides functionality for which the cloud computing environment can be utilized. In at least one embodiment, workloads and functions that can be provided from this layer include: mapping and navigation; software development and management; education services; data analysis and processing; transaction processing; and services delivery.

[0213] Supercomputing

[0214] The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that can be used to implement at least one embodiment.

[0215] In at least one embodiment, a supercomputer can refer to a hardware system that exhibits significant parallelism and includes at least one chip, where the chips in the system are interconnected by a network and are placed in a hierarchically organized enclosure. In at least one embodiment, a large hardware system that fills a machine room with several racks, each containing several board / rack modules, each containing several chips all interconnected by a scalable network, is at least one embodiment of a supercomputer. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits significant parallelism and contains several hardware components can also be considered a supercomputer, as the amount of hardware that can be incorporated in a single chip can increase as feature sizes can decrease.

[0216] Figure 14A supercomputer at the chip level is shown, according to at least one embodiment. In at least one embodiment, within an FPGA or ASIC chip, primary computation is performed within finite state machines (1404) called thread units. In at least one embodiment, a task and synchronization network (1402) connects finite state machines and is used to dispatch threads and perform operations in correct order. In at least one embodiment, a memory network (1406, 1410) is used to access a multi-level partitioned on-chip cache hierarchy (1408, 1412). In at least one embodiment, a memory controller (1416) and off-chip memory network (1414) is used to access off-chip memory. In at least one embodiment, an I / O controller (1418) is used for cross-chip communication when a design does not fit on a single logic chip.

[0217] Figure 15 A supercomputer at the rack module level is shown, according to at least one embodiment. In at least one embodiment, within a rack module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that make up a main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its neighboring FPGA / ASIC chip using a wide bus on board with differential high speed signaling (1506). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high speed serial communication cable.

[0218] Figure 16 A supercomputer at the rack level is shown, according to at least one embodiment. Figure 17 A supercomputer at the entire system level is shown, according to at least one embodiment. In at least one embodiment, see Figure 16 and Figure 17Between and across racks of rack modules, a scalable, possibly incomplete hypercube network is implemented using high-speed serial optical or copper cables (1602, 1702). In at least one embodiment, one of the FPGA / ASIC chips of an accelerator is connected to a host system (1704) through a PCI-Express connection. In at least one embodiment, a host system includes a host microprocessor (1708) on which software portions of an application run, and a memory consisting of one or more host memory DRAM units (1706) that are kept coherent with memory on an accelerator. In at least one embodiment, a host system can be a separate module on one of the racks, or can be integrated with one of the modules of a supercomputer. In at least one embodiment, a cyclic topology of cube connections provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a small group of FPGA / ASIC chips on a rack module can act as a single hypercube node, such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, a group contains chips A, B, C, and D on a rack module, which has an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables that connect the rack module to the outside world. In at least one embodiment, chip A on a rack module is connected to serial communication cables 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, chip D is connected to 9, 10, 11. In at least one embodiment, the entire group {A, B, C, D} making up a rack module can form a hypercube node within a supercomputer system, with up to 2i2= 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B with an on-board differential wide bus connection. In at least one embodiment, a message arriving on link 4 destined for the group {A, B, C, D} of chips (i.e., to B) must also first be routed to the correct destination chip (A) inside the group {A, B, C, D}. In at least one embodiment, other sizes of parallel supercomputer systems can also be implemented.

[0219] Artificial intelligence

[0220] The following figures illustrate, but are not limited to, example artificial intelligence-based systems that can be used to implement at least one embodiment.

[0221] Figure 18AInference and / or training logic 1815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1815 are provided below in conjunction with FIGS. 1 A, 1 B, and 8. Figure 18A and / or Figure 18B Details regarding inference and / or training logic 1815 are provided below in conjunction with FIGS. 1 A, 1 B, and 8.

[0222] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1801 for storing forward and / or output weight and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1801 for storing graph code or other software to control timing and / or order where weight and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALUs)). In at least one embodiment, code such as graph code loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or use of aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1801 can be included with other on-chip or off-chip data storage, including processor L1, L2, or L3 cache memory, or system memory.

[0223] In at least one embodiment, any portion of code and / or data storage 1801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1801 can be cache memory, dynamic random addressable memory (“DRAM”), static random addressable memory (“SRAM”), nonvolatile memory (e.g., Flash), or other storage. In at least one embodiment, whether code and / or code and / or data storage 1801 is internal or external to a processor, and / or the choice of including DRAM, SRAM, Flash, or some other type of storage, can depend on available storage on-chip relative to off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0224] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1805 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1805 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0225] In at least one embodiment, code such as graph code causes weight or other parameter information to be loaded into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, whether code and / or data storage 1805 is internal or external to a processor, or includes a choice of DRAM, SRAM, Flash, or some other storage type, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0226] In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be separate storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be a combined storage structure. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be partially combined and partially separated. In at least one embodiment, any portion of code and / or data store 1801 and code and / or data store 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0227] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, one or more arithmetic logic units (“ALUs”), including integer and / or floating-point units, for performing logical and / or mathematical operations based, at least in part, on training and / or inference code (e.g., graphics code) or instructions by training and / or inference code (e.g., graphics code), results of which can produce activations (e.g., output values from layers or neurons within a neural network) stored in activation storage 1820, which is a function of input / output and / or weight parameter data stored in code and / or data store 1801 and / or code and / or data store 1805. In at least one embodiment, activations stored in activation storage 1820 are generated from linear algebra and / or matrix-based mathematics performed by ALU 1810 in response to executing instructions or other code, where weight values stored in code and / or data store 1805 and / or data store 1801 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which can be stored in code and / or data store 1805 or code and / or data store 1801 or another storage on-chip or off-chip.

[0228] In at least one embodiment, one or more ALUs 1810 are included in a processor or other hardware logic or circuitry, while in another embodiment one or more ALUs 1810 can be external to a processor or other hardware logic or circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 1810 can be included within execution units of a processor or otherwise within a bank of ALUs that are accessible by execution units of a processor, either within a same processor or distributed between different types of processors (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1801, code and / or data storage 1805, and activation storage 1820 can share a processor or other hardware logic or circuitry, while in another embodiment they can be in different processors or other hardware logic or circuitry, or some combination thereof. In at least one embodiment, any portion of activation storage 1820 can be included with other on-chip or off-chip data storage including an LI, L2, or L3 cache of a processor or system memory. Moreover, inference and / or training code can be stored with other code that is accessible to and used by a processor or other hardware logic or circuitry to fetch and / or process with fetch, decode, schedule, execute, retirement, and / or other logic of a processor.

[0229] In at least one embodiment, activation storage 1820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash) or other storage. In at least one embodiment, activation storage 1820 can be entirely or partially within or outside of one or more processors or other logic circuitry. In at least one embodiment, whether activation storage 1820 is internal or external to a processor, and in at least one embodiment, or the selection of whether to include DRAM, SRAM, Flash, or some other type of storage, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0230] In at least one embodiment, Figure 18A Inference and / or training logic 1815 as shown in FIG. 18A can be used in combination with a special-purpose integrated circuit (‘ASIC”) such as Google’s Tensor Processing Unit (‘TPU”), an inference processing unit (‘IPU”) from Graphcore’s AI System, or an AI Accelerator from Inference and / or training logic 1815 as shown in FIG. 18A can be used in combination with a special-purpose integrated circuit (‘ASIC”) such as Google’s Tensor Processing Unit (‘TPU”), an inference processing unit (‘IPU”) from Graphcore’s AI System, or an AI Accelerator from TM ​(e.g., "Lake Crest") processor. In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown in FIG may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0231] Figure 18B Inference and / or training logic 1815 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown in FIG can be combined with an application specific integrated circuit (ASIC) (such as the one from Google Processing unit from Graphcore TM Inference Processing Unit (IPU), or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown in FIG can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage 1801 and code and / or data storage 1805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 18B In at least one embodiment described in

[0065] , each of code and / or data storage 1801 and code and / or data storage 1805 is associated with dedicated computing resources, such as computing hardware 1802 and computing hardware 1806, respectively. In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) solely on the information stored in code and / or data storage 1801 and code and / or data storage 1805, respectively, with the results being stored in activation storage 1820.

[0232] In at least one embodiment, each code and / or data store 1801 and 1805 and corresponding compute hardware 1802 and 1806, respectively, correspond to different layers of a neural network, such that resulting activations from one storage / compute pair 1801 / 1802 are provided as input to the next storage / compute pair 1805 / 1806 in code and / or data store 1805 and compute hardware 1806, mirroring a conceptual organization of a neural network. In at least one embodiment, each of storage / compute pairs 1801 / 1802 and 1805 / 1806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) after or in parallel with storage / compute pairs 1801 / 1802 and 1805 / 1806 can be included in inference and / or training logic 1815.

[0233] Figure 19 Training and deployment of a deep neural network is shown, in accordance with at least one embodiment. In at least one embodiment, an untrained neural network 1906 is trained using a training dataset 1902. In at least one embodiment, training framework 1904 is a PyTorch framework, while in other embodiments, training framework 1904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1904 trains untrained neural network 1906 and enables it to train using processing resources described herein to generate a trained neural network 1908. In at least one embodiment, weights can be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0234] In at least one embodiment, an untrained neural network 1906 is trained using supervised learning, where a training dataset 1902 includes inputs paired with desired outputs for inputs, or where a training dataset 1902 includes inputs with known outputs and outputs of the neural network 1906 are manually graded. In at least one embodiment, an untrained neural network 1906 is trained in a supervised manner and inputs from a training dataset 1902 are processed and resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 1906. In at least one embodiment, a training framework 1904 adjusts weights that control the untrained neural network 1906. In at least one embodiment, a training framework 1904 includes tools to monitor how well an untrained neural network 1906 is converging towards a model, such as a trained neural network 1908, that is suitable to generate correct answers, such as results 1914, based on input data, such as a new dataset 1912. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 repeatedly while using a loss function and adjustment algorithm, such as stochastic gradient descent, to adjust weights to refine outputs of the untrained neural network 1906. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 until the untrained neural network 1906 achieves a desired accuracy. In at least one embodiment, a trained neural network 1908 can then be deployed to implement any number of machine learning operations.

[0235] In at least one embodiment, an untrained neural network 1906 is trained using unsupervised learning, where an untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, an unsupervised learning training dataset 1902 will include input data without any associated output data or “ground truth” data. In at least one embodiment, an untrained neural network 1906 can learn groupings within a training dataset 1902 and can determine how individual inputs relate to the untrained dataset 1902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 1908 that is capable of performing operations useful in reducing a dimensionality of a new dataset 1912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identification of data points in a new dataset 1912 that deviate from a normal pattern of the new dataset 1912.

[0236] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mix of labeled and unlabeled data is included in a training dataset 1902. In at least one embodiment, training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables a trained neural network 1908 to adapt to new datasets 1912 without forgetting knowledge that was imprinted within trained neural network 1408 during initial training.

[0237] 5G network

[0238] The following figures illustrate, but are not limited to, exemplary 5G network-based systems that can be used to implement at least one embodiment.

[0239] Figure 20 An architecture of a system 2000 of a network is illustrated in accordance with at least one embodiment. In at least one embodiment, system 2000 is illustrated as including a user equipment (UE) 2002 and UE 2004. In at least one embodiment, UEs 2002 and 2004 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but can also include any mobile or non-mobile computing device, such as personal data assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets or any computing device including a wireless communications interface.

[0240] In at least one embodiment, any of UEs 2002 and 2004 can comprise an Internet of Things (IoT) UE, which can comprise an network access layer designed for low-power IoT applications using short-lived connections. In at least one embodiment, an IoT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), a proximity-based service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks. In at least one embodiment, M2M or MTC data exchanges can be machine-initiated exchanges in which data is exchanged between members of a M2M or MTC network. In at least one embodiment, an IoT network describes interconnecting IoT UEs, which can include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections.

[0241] In at least one embodiment, UEs 2002 and 2004 can be configured to connect with a radio access network (RAN) 2016 (e.g., communicatively coupled with the RAN 2016). In at least one embodiment, the RAN 2016 can be an evolved universal mobile telecommunications system (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN. In at least one embodiment, UEs 2002 and 2004 utilize connections 2012 and 2014, respectively, each of which includes a physical

[0242] In at least one embodiment, UEs 2002 and 2004 can also directly exchange communication data via a ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 can alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a physical sidelink control channel (PSCCH), a physical sidelink shared channel (PSSCH), a physical sidelink discovery channel (PSDCH), and a physical sidelink broadcast channel (PSBCH).

[0243] In at least one embodiment, UE 2004 is illustrated as being configured to access an access point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 2010 would comprise a wireless fidelity router. In at least one embodiment, AP 2010 is illustrated as connected to the Internet without connecting to the core network, although this is not required in every embodiment. In at least one embodiment, AP 2010 can represent a plurality of APs connected in a mesh network, turnkey network, or some other configuration.

[0244] In at least one embodiment, RAN 2016 can include one or more access nodes that enable the connections 2012 and 2014. In at least one embodiment, these access nodes (ANs) can be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNBs), RAN nodes, and so on, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage over a geographic area (e.g., a cell).

[0245] In at least one embodiment, any of the RAN nodes 2018 and 2020 can terminate the air interface protocol and can be the first point of contact for the UEs 2002 and 2004. In at least one embodiment, any of the RAN nodes 2018 and 2020 can implement various logical functions for the RAN 2016 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling, and mobility management.

[0246] In at least one embodiment, UEs 2002 and 2004 can be configured to communicate using orthogonal frequency division multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 2018 and 2020 over a multicarrier communication channel in accordance with various communication techniques, such as, but not limited to, an orthogonal frequency division multiple access (OFDMA) communication technique (e.g., for downlink communications) or a single carrier frequency division multiple access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), and / or variants thereof. In at least one embodiment, OFDM signals can comprise orthogonal frequency division multiplexed signals.

[0247] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from any of RAN node 2018 and 2020 to UEs 2002 and 2004, while uplink transmissions can utilize a similar approach. In at least one embodiment, a grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. In at least one embodiment, such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one slot, which depends on the downlink slot duration. In at least one embodiment, the minimum time-frequency unit in the resource grid is denoted as a resource element. In at least one embodiment, each resource element in the resource grid can be assigned to a particular physical channel and / or used for transmission of data and control information for UEs 2002 and 2004. In at least one embodiment, a resource grid can include a number of resource blocks, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block includes a collection of resource elements that can be utilized for transmission of the same data to UEs 2002 and 2004. In at least one embodiment, in the frequency domain, this can represent the smallest number of resources that can be allocated together in the frequency domain that encompasses the time-domain duration. In at least one embodiment, there are several different physical downlink channels that are conveyed using such resource blocks.

[0248] In at least one embodiment, a physical downlink shared channel (PDSCH) can carry user data and higher layer signaling to UEs 2002 and 2004. In at least one embodiment, a physical downlink control channel (PDCCH) can carry information about the transport format and resource allocations for the PDSCH channels, among other information. In at least one embodiment, it can also inform UEs 2002 and 2004 about the transport format, resource allocation, and HARQ information for uplink shared channel. Generally, in at least one embodiment, downlink scheduling (which allocates control and shared channel resource blocks to UEs 2002 within a cell) can be performed at any of RAN node 2018 and 2020 based on channel quality information feedback from any of UEs 2002 and 2004. In at least one embodiment, downlink resource allocation information can be sent on the PDCCH for each of UEs 2002 and 2004.

[0249] In at least one embodiment, a PDCCH can use control channel elements (CCEs) to convey control information. In at least one embodiment, PDCCH complex-valued symbols can first be organized into quadruplets, then permuted using a sub-block interleaver for rate matching, in at least one embodiment, one or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to nine sets of four resource element groups (REGs), referred to as resource element groups (REGs). In at least one embodiment, four Quadrature Phase Shift Keying (QPSK) symbols can be mapped to each REG. In at least one embodiment, depending on a downlink control information (DCI) size and a channel condition, one or more CCEs can be used to send a PDCCH. In at least one embodiment, there can be four or more different PDCCH formats (e.g., aggregation level, L=1, 2, 4, or 8) defined in LTE with different numbers of CCEs.

[0250] In at least one embodiment, an enhanced physical downlink control channel (EPDCCH) using PDSCH resources can be used for control information transmission. In at least one embodiment, one or more enhanced control channel elements (ECCEs) can be used to transmit an EPDCCH. In at least one embodiment, each ECCE can correspond to nine sets of four physical resource elements called enhanced resource element groups (EREGs). In at least one embodiment, an ECCE can have other numbers of EREGs in some situations.

[0251] In at least one embodiment, RAN 2016 is shown to be communicatively coupled to core network (CN) 2038 via an S1 interface 2022. In at least one embodiment, CN 2038 can be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, S1 interface 2022 is split into two parts: the S1 -U interface 2026, which carries traffic data between RAN nodes 2018 and 2020 and a serving gateway (S-GW) 2030, and the S1 -Mobility Management Entity (MME) interface 2024, which is a signaling interface between RAN nodes 2018 and 2020 and MME 2028.

[0252] In at least one embodiment, the CN 2038 includes a MME 2028, a S-GW 2030, a packet data network (PDN) gateway (P-GW) 2034, and a home subscriber server (HSS) 2032. In at least one embodiment, the MME 2028 can be similar in function to a control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN). In at least one embodiment, the MME 2028 can manage mobility aspects in access such as gateway selection and tracking area list management. In at least one embodiment, the HSS 2032 can include a database for network users, including subscription-related information to support the network entities’ handling of communication sessions. In at least one embodiment, the CN 2038 can include one or more HSSs 2032 depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc. In at least one embodiment, the HSS 2032 can provide support for routing / roaming, authentication, authorization, naming / addressing resolution, location dependencies, etc.

[0253] In at least one embodiment, the S-GW 2030 can terminate the S1 interface 2022 towards RAN 2016, and route data packets between the RAN 2016 and the CN 2038. In at least one embodiment, the S-GW 2030 can be a local mobility anchor for inter-RAN node handovers and also for intra-RAN mobility including handover between bases stations of a same base station type (e.g., handover between base stations of same type, such as between eNodeBs). In at least one embodiment, other responsibilities can include lawful intercept, charging, and some policy enforcement and steering functions.

[0254] In at least one embodiment, the P-GW 2034 can terminate an SGi interface towards a PDN. In at least one embodiment, the P-GW 2034 can route data packets between a EPC network 2038 and external networks such as a network including an application server 2040 (or as referred to as an application function (AF)) via an Internet Protocol (IP) interface 2042. In at least one embodiment, the application server 2040 can be an element offering applications that use IP bearer resources offered by the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In at least one embodiment, the P-GW 2034 is shown to be communicatively coupled to an application server 2040 via the IP communications interface 2042. In at least one embodiment, the application server 2040 can also be configured to support one or more communication services (e.g., Voice-over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 2002 and 2004 via the CN 2038.

[0255] In at least one embodiment, P-GW 2034 can also be a node for policy enforcement and charging data collection. In at least one embodiment, a Policy and Charging Enforcement Function (PCRF) 2036 is a policy and charging control element of CN 2038. In at least one embodiment, in a non-roaming scenario, there is one PCRF 2036 in a Home Public Land Mobile Network (HPLMN) associated with a UE’s Internet Protocol Connectivity Access Network (IP-CAN) session. In at least one embodiment, in a roaming scenario with local breakout of traffic, there can be two PCRFs associated with a UE’s IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). In at least one embodiment, PCRF 2036 can be communicatively coupled to an application server 2040 via P-GW 2034. In at least one embodiment, application server 2040 can signal a new service flow to PCRF 2036 and select an appropriate Quality of Service (QoS) and charging

[0256] Figure 21 An architecture of a system 2100 of a network is shown in accordance with some embodiments. In at least one embodiment, system 2100 is shown to include a UE 2102, a 5G access node or RAN node (shown as (R)AN node 2108), a user plane function (shown as UPF 2104), a data network (DN 2106), which in at least one embodiment can be operator services, Internet access, or 3rd party services, and a 5G core network (5GC) (shown as CN 2110).

[0257] In at least one embodiment, CN 2110 includes an Authentication Server Function (AUSF 2114); a Core Access and Mobility Management Function (AMF 2112); a Session Management Function (SMF 2118); a Network Exposure Function (NEF 2116); a Policy Control Function (PCF 2122); a Network Function (NF) Repository Function (NRF 2120); a Unified Data Management (UDM 2124); and an Application Function (AF 2126). In at least one embodiment, CN 2110 can also include other elements not shown, such as a Structured Data Storage Network Function (SDSF), an Unstructured Data Storage Network Function (UDSF), and variations thereof.

[0258] In at least one embodiment, the UPF 2104 can serve as an anchor point for intra-RAT and inter-RAT mobility, an external PDU session point interconnected to the DN 2106, and a branching point supporting multi-homed PDU sessions. In at least one embodiment, the UPF 2104 can also perform packet routing and forwarding, packet inspection, user plane enforcement of policy rules, lawful interception of packets (UP collection), service usage reporting, QoS processing for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), uplink service validation (e.g., SDF to QoS flow mapping), transport-level packet marking in the uplink and downlink, downlink packet buffering, and downlink data notification triggering. In at least one embodiment, the UPF 2104 can include an uplink classifier to support routing of service flows to the data network. In at least one embodiment, the DN 2106 can represent various network operator services, internet access, or third-party services.

[0259] In at least one embodiment, the AUSF 2114 may store data used for authentication of the UE 2102 and handle authentication-related functions. In at least one embodiment, the AUSF 2114 may facilitate a common authentication framework for various access types.

[0260] In at least one embodiment, the AMF 2112 may be responsible for registration management (e.g., for registering UE 2102, etc.), connection management, reachability management, mobility management, and lawful interception of AMF-related events, as well as access authentication and authorization. In at least one embodiment, the AMF 2112 may provide transport of SM messages for the SMF 2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, the AMF 2112 may also provide UE 2102 with an SMS function (SMSF) ( Figure 21 In at least one embodiment, the AMF 2112 may act as a Security Anchor Function (SEA), which may include interaction with the AUSF 2114 and the UE 2102 and receiving intermediate keys established as a result of the UE 2102 authentication process. In at least one embodiment, where USIM-based authentication is used, the AMF 2112 may retrieve security material from the AUSF 2114. In at least one embodiment, the AMF 2112 may also include a Security Context Management (SCM) function that receives keys from the SEA that it uses to derive access network-specific keys. In addition, in at least one embodiment, the AMF 2112 may be the termination point for the RAN CP interface (N2 reference point), the termination point for NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0261] In at least one embodiment, the AMF 2112 can also support NAS signaling with the UE 2102 over an N3 interworking function (IWF) interface. In at least one embodiment, the N3IWF can be used to provide access to untrusted entities. In at least one embodiment, the N3IWF can be a termination point for the N2 and N3 interfaces for control plane and user plane, respectively, and thus can handle N2 signaling from SMF and AMF for PDU session and QoS, encapsulate / decapsulate packets for IPSec and N3 tunneling, mark N3 user-plane packets in uplink, and enforce QoS corresponding to N3 packet marking taking into account QoS requirements associated with such marking received over N2. In at least one embodiment, the N3IWF can also relay uplink and downlink control-plane NAS (NI) signaling between the UE 2102 and AMF 2112, and relay uplink and downlink user-plane packets between the UE 2102 and UPF 2104. In at least one embodiment, the N3IWF also provides mechanisms for IPsec tunnel establishment with the UE 2102.

[0262] In at least one embodiment, the SMF 2118 can be responsible for session management (e.g., session establishment, modify, and release, including UPF and AN node tunnel maintenance); UE IP address allocation and management (including optional authorization); selection and control of UP function; configuration of traffic steering at UPF to route traffic to appropriate destination; interface termination towards policy control functions; control plane part of policy enforcement and QoS; lawful intercept (for SM events and interface to LI system); termination of SM parts of NAS messages; downlink data notification; initiator of AN specific SM information transmitted over N2 to AN via AMF; determining SSC mode of a session. In at least one embodiment, the SMF 2118 can include following roaming functionality: handling local enforcement to apply QoS SLAs (VPLMN); charging data collection and charging interface (VPLMN); lawful intercept (in VPLMN for SM events and interface to LI system); support for interaction with external DN to transfer signaling for PDU session authorization / authentication by external DN.

[0263] In at least one embodiment, the NEF 2116 can provide means for securely exposing services and capabilities offered by 3 GPP network functions for third party, internal exposure / re exposure, application functions (e.g., AF 2126), edge computing or fog computing systems, etc. In at least one embodiment, the NEF 2116 can authenticate, authorize, and / or throttle AFs. In at least one embodiment, NEF 2116 can also translate information exchanged with AF 2126 and information exchanged with internal network functions. In at least one embodiment, NEF 2116 can translate between AF service identifiers and internal 5GC information. In at least one embodiment, NEF 2116 can also receive information from other network functions (NFs) based on exposed capabilities of other network functions. In at least one embodiment, this information can be stored at the NEF 2116 as structured data, or at a data storage NF using standardized interfaces. In at least one embodiment, stored information can then be re-exposed by the NEF 2116 to other NFs and AFs, and / or used for other purposes such as analytics.

[0264] In at least one embodiment, the NRF 2120 can support service discovery functions, receive NF discovery requests from NF instances, and provide information of discovered NF instances to NF instances. In at least one embodiment, the NRF 2120 also maintains information of available NF instances and their supported services.

[0265] In at least one embodiment, the PCF 2122 can provide policy rules to control plane functions to enforce them, and can also support a unified policy framework to govern network behavior. In at least one embodiment, the PCF 2122 can also implement a front end (FE) to access subscription information relevant for policy decisions in a UDR of UDM 2124.

[0266] In at least one embodiment, the UDM 2124 can handle subscription-related information to support network entities handling communication sessions, and can store subscription data of UEs 2102. In at least one embodiment, UDM 2124 can include two parts, an application FE and a user data repository (UDR). In at least one embodiment, UDM can include a UDM FE that is responsible for processing credentials, location management, subscription management, etc. In at least one embodiment, several different front ends can service the same user in different transactions. In at least one embodiment, the UDM-FE accesses subscription information stored in the UDR and performs authentication credential processing; user identification processing; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR can interact with the PCF 2122. In at least one embodiment, UDM 2124 can also support SMS management, where an SMS-FE implements similar application logic as previously described.

[0267] In at least one embodiment, AF 2126 can provide application influence on traffic routing, access to network exposure capabilities (NCE), and interaction with policy framework for policy control. In at least one embodiment, NCE can be a mechanism allowing 5GC and AFs 2126 to provide information to each other via NEF 2116, which can be used for edge computing implementations. In at least one embodiment, network operators and third party services can be hosted close to UEs 2102’s point of attachment to the access network to enable efficient service delivery with reduced end-to-end latency and load on transport networks. In at least one embodiment, for edge computing implementations, 5GC can choose a UPF 2104 close to UE 2102 and perform traffic steering from UPF 2104 to DN 2106 via N6 interface. In at least one embodiment, this can be based on UE subscription data, UE location, and information provided by AFs 2126. In at least one embodiment, AFs 2126 can influence UPF (re)selection and traffic routing. In at least one embodiment, based on operator deployment, when AFs 2126 are considered trusted entities, network operators can allow AFs 2126 to directly interact with relevant NFs.

[0268] In at least one embodiment, CN 2110 can include an SMSF, which can be responsible for SMS subscription checking and verification, and relaying SM messages to / from UEs 2102 to / from other entities, such as SMS-GMSC / IWMSC / SMS-router. In at least one embodiment, SMS can also interact with AMF 2112 and UDM 2124 for a notification procedure that the UE 2102 is available for SMS transfer (e.g., setting a UE not reachable flag, and notifying UDM 2124 when UE 2102 is available for SMS).

[0269] In at least one embodiment, system 2100 can include the following service-based interfaces: Namf: service-based interface exposed by AMF; Nsmf: service-based interface exposed by SMF; Nnef: service-based interface exposed by NEF; Npcf: service-based interface exposed by PCF; Nudm: service-based interface exposed by UDM; Naf: service-based interface exposed by AF; Nnrf: service-based interface exposed by NRF; and Nausf: service-based interface exposed by AUSF.

[0270] In at least one embodiment, system 2100 can include the following reference points: N1: Reference point between UE and AMF; N2: Reference point between (R)AN and AMF; N3: Reference point between (R)AN and UPF; N4: Reference point between SMF and UPF; and N6: Reference point between UPF and Data Network. In at least one embodiment, there can be more reference points and / or service-based interfaces between NF services in NF, however, these interfaces and reference points have been omitted for clarity. In at least one embodiment, a NS reference point can be between a PCF and an AF; a N7 reference point can be between a PCF and a SMF; a N11 reference point between an AMF and a SMF; and / or the like. In at least one embodiment, CN 2110 can include an Nx interface, which is an inter-CN interface between MME and AMF 2112 in order to enable interworking between CN 2110 and CN 7221.

[0271] In at least one embodiment, system 2100 can include multiple RAN nodes, such as (R)AN nodes 2108, where an Xn interface is defined between two or more (R)AN nodes 2108 connected to 5GC 410, between a (R)AN node 2108 (e.g., gNB) and an eNB (e.g., macro RAN node) connected to CN 2110, and / or between two eNBs connected to CN 2110.

[0272] In at least one embodiment, Xn interface can include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, Xn-U can provide guaranteed delivery of user plane PDUs with some exceptions and support / provide data forwarding and flow control functionality. In at least one embodiment, Xn-C can provide management and error handling functionality, functionality to manage the Xn-C interface; mobility support for UEs 2102 in a connected mode (e.g., CM-CONNECTED) including functionality to manage connected mode UE mobility between one or more (R)AN nodes 2108. In at least one embodiment, mobility support can include context transfer from an old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108; and control of user plane tunnels between old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108.

[0273] In at least one embodiment, the Xn-U protocol stack can include a transport network layer built on top of an Internet Protocol (IP) transport layer and a GTP-U layer for carrying user plane PDUs on top of a UDP and / or one or more IP layers. In at least one embodiment, the Xn-C protocol stack can include an application layer signaling protocol, referred to as Xn Application Protocol (Xn-AP), and a transport network layer built on top of an SCTP layer. In at least one embodiment, the SCTP layer can be on top of an IP layer. In at least one embodiment, the SCTP layer provides a guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and / or the Xn-C protocol stack can be the same as or similar to user plane and / or control plane protocol stacks shown and described herein.

[0274] Figure 22 is an illustration of a control plane protocol stack in accordance with some embodiments. In at least one embodiment, control plane 2200 is illustrated as a communication protocol stack between UE 2002 (or, alternatively, UE 2004), RAN 2016, and MME 2028.

[0275] In at least one embodiment, PHY layer 2202 can transmit or receive information used by MAC layer 2204 over one or more air interfaces. In at least one embodiment, PHY layer 2202 can also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as RRC layer 2210. In at least one embodiment, PHY layer 2202 can further perform error detection on the transport channels, forward error correction (FEC) coding / decoding of the transport channels, modulation / demodulation of physical channels, interleaving, rate matching, mapping to physical channels, and Multiple Input Multiple Output (MIMO) antenna processing.

[0276] In at least one embodiment, MAC layer 2204 can perform mapping between logical channels and transport channels, multiplexing of MAC service data units (SDUs) from one or more logical channels into transport blocks (TB) to be delivered to PHY via transport channels, demultiplexing of MAC SDUs to one or more logical channels from TBs delivered via transport channels from PHY, multiplexing of MAC SDUs onto TBs, scheduling information reporting, error correction through hybrid automatic repeat request (HARQ), and logical channel prioritization.

[0277] In at least one embodiment, RLC layer 2206 can operate in multiple modes of operation, including: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). In at least one embodiment, RLC layer 2206 can perform transfer of upper layer protocol data units (PDUs), error correction through automatic repeat request (ARQ) for AM data transfers, and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transfers. In at least one embodiment, RLC layer 2206 can also perform re-segmentation of RLC data PDUs for AM data transfers, reordering of RLC data PDUs for UM and AM data transfers, detect duplicate data for UM and AM data transfers, discard RLC SDUs for UM and AM data transfers, detect protocol errors for AM data transfers, and perform RLC re-establishment.

[0278] In at least one embodiment, PDCP layer 2208 can perform header compression and decompression of IP data, maintain PDCP sequence numbers (SNs), perform in-sequence delivery of upper layer PDUs at re-establishment of lower layers, eliminate duplication of lower layer SDUs at re-establishment of lower layers for RLC AM mapped radio bearers, cipher and decipher control plane data, integrity protect and integrity verify control plane data, perform data

[0279] In at least one embodiment, main services and functions of RRC layer 2210 can include broadcast of system information (e.g., included in master information block (MIB) or system information blocks (SIBs) related to non-access stratum (NAS)), broadcast of system information related to access stratum (AS), paging of UEs in RRC_CONNECTED state, establishment, maintenance and release of an RRC connection between the UE and E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), setup, configuration, maintenance and release of point-to-point Radio Bearers, security functions including key management, inter-RAT mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, MIB and SIBs can include one or more information elements (IEs), which can include individual data fields or data structures.

[0280] In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., LTE-Uu interface) to exchange control plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208, and RRC layer 2210.

[0281] In at least one embodiment, a non-access stratum (NAS) protocol (NAS protocol 2212) forms a highest stratum of the control plane between UE 2002 and MME 2028. In at least one embodiment, NAS protocol 2212 supports mobility of UE 2002 and session management procedures to establish and maintain IP connectivity between UE 2002 and P-GW 2034.

[0282] In at least one embodiment, an Si application protocol (Si-AP) layer (Si-AP layer 2222) can support functions of the Si interface and include elementary procedures (EPs). In at least one embodiment, an EP is a unit of interaction between RAN 2016 and CN 2028. In at least one embodiment, S1-AP layer services can include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transfer, RAN Information Management (RIM), and configuration transfer.

[0283] In at least one embodiment, a stream control transmission protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol / internet protocol (SCTP / IP) layer) (SCTP layer 2220) can ensure reliable delivery of signaling messages between RAN 2016 and MME 2028 based, in part, on IP protocols supported by IP layer 2218. In at least one embodiment, L2 layer 2216 and L1 layer 2214 can refer to communication links (e.g., wired or wireless) used by RAN nodes and MMEs to exchange information.

[0284] In at least one embodiment, RAN 2016 and one or more MMEs 2028 can utilize an S1-MME interface to exchange control plane data via a protocol stack including L1 layer 2214, L2 layer 2216, IP layer 2218, SCTP layer 2220, and Si-AP layer 2222.

[0285] Figure 23 is a diagram of a user plane protocol stack, in accordance with at least one embodiment. In at least one embodiment, user plane 2300 is shown as a communication protocol stack between UE 2002, RAN 2016, S-GW 2030, and P-GW 2034. In at least one embodiment, user plane 2300 can utilize the same protocol layers as control plane 2200. In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208.

[0286] In at least one embodiment, a general packet radio service (GPRS) tunneling protocol (GTP-U) layer (GTP-U layer 2304) for user plane can be used to carry user data within a GPRS core network and between a radio access network and a core network. In at least one embodiment, user data transported can be packets of any size that the protocol stack is designed to handle, including any of IPv4, IPv6, or PPP encapsulation. In at least one embodiment, a UDP / IP layer (UDP / IP layer 2302) can provide checksums for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication on selected data flows. In at least one embodiment, RAN 2016 and S-GW 2030 can utilize an S1-U interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, S-GW 2030 and P-GW 2034 can utilize a S5 / S8a interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, as discussed above with respect to FIG. 22, NAS protocols support mobility and session management procedures for UE 2002 to establish and maintain IP connectivity between UE 2002 and P-GW 2034. Figure 22

[0287] Figure 24 Components of a core network are shown in accordance with at least one embodiment 2400. In at least one embodiment, components of CN 2038 can be implemented in one physical node or in separate physical nodes including components to read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network function virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage mediums (described in further detail below). In at least one embodiment, a logical instantiation of CN 2038 can be referred to as a network slice 2402 (e.g., network slice 2402 is shown to include HSS 2032, MME 2028, and S-GW 2030). In at least one embodiment, a logical instantiation of a portion of CN 2038 can be referred to as a network sub-slice 2404 (e.g., network sub-slice 2404 is shown to include P-GW 2034 and PCRF 2036).

[0288] ​In at least one embodiment, NFV architecture and infrastructure can be used to virtualize one or more network functions onto one or more physical servers that include a combination of industry-standard server hardware, storage hardware, or switches, which can alternatively be replaced by virtualized or reconfigurable hardware. In at least one embodiment, NFV systems can be used to perform virtual or reconfigurable implementations of one or more EPC components / functions.

[0289] Figure 25 FIG. 27 is a block diagram showing components of a system 2700 to support network function virtualization (NFV), according to at least one embodiment. In at least one embodiment, system 2700 is shown to include a virtualization infrastructure manager (shown as VIM 2702), a network function virtualization infrastructure (shown as NFVI 2704), a VNF manager (shown as VNFM 2706), a virtualized network function (shown as VNF 2708), an element manager (shown as EM 2710), an NFV orchestrator (shown as NFVO 2712), and a network manager (shown as NM 2714).

[0290] In at least one embodiment, VIM 2702 manages resources of NFVI 2704. In at least one embodiment, NFVI 2704 can include physical or virtual resources and applications (including hypervisors) used to execute system 2700. In at least one embodiment, VIM 2702 can utilize NFVI 2704 to manage life cycle of virtual resources (e.g., creation, maintenance, and tearing down of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, faults, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0291] In at least one embodiment, VNFM 2706 can manage VNF 2708. In at least one embodiment, VNF 2708 can be used to execute EPC components / functions. In at least one embodiment, VNFM 2706 can manage life cycle of VNF 2708 and track performance, faults, and security of virtual aspects of VNF 2708. In at least one embodiment, EM 2710 can track performance, faults, and security of functional aspects of VNF 2708. In at least one embodiment, tracking data from VNFM 2706 and EM 2710 can include, in at least one embodiment, performance measurement (PM) data used by VIM 2702 or NFVI 2704. In at least one embodiment, both VNFM 2706 and EM 2710 can scale up / down the number of VNFs of system 2700.

[0292] In at least one embodiment, NFVO 2512 can coordinate, authorize, release, and occupy resources of NFVI 2504 in order to provide the requested service (e.g., to execute an EPC function, component, or slice). In at least one embodiment, NM 2514 can provide a package of end-user functions that are responsible for managing a network that can include network elements that are VNFs, non-virtualized network functions, or both (management of VNFs can occur via EM 2510).

[0293] Computer-based system

[0294] The following figures illustrate, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment.

[0295] Figure 26 A processing system 2600, in accordance with at least one embodiment, is shown. In at least one embodiment, system 2600 includes one or more processor(s) 2602 and one or more graphics processor(s) 2608, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 2602 or processor cores 2607. In at least one embodiment, processing system 2600 is a processing platform incorporated within a system- on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0296] In at least one embodiment, processing system 2600 can include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 2600 is a mobile phone, a smart phone, a tablet device, or a mobile internet device. In at least one embodiment, processing system 2600 can also include or be coupled with a wearable device such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0297] In at least one embodiment, one or more processors 2602 each include one or more processor cores 2607 to process instructions which, when executed, perform operations such as operations for systems and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction set 2609. In at least one embodiment, instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0298] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 can have single-level or multi-level internal caches. In at least one embodiment, cache memory is shared among multiple components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a level three (L3) cache or last level cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherency techniques. In at least one embodiment, register file 2606 is additionally included in processor 2602, which can include different types of registers to store different kinds of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2606 can include a general register file or other registers.

[0299] In at least one embodiment, one or more processors 2602 are coupled with one or more interface buses 2610 for passing communication signals between processor 2602 and other components of system 2600. In at least one embodiment, one or more of interface buses 2610 can be versions of a Peripheral Component Interconnect (PCI) bus or PCI Express bus. In at least one embodiment, one or more of interface buses 2610 can be versions of an Industry Standard Architecture (ISA) bus, a MicroChannel Architecture (MCA) bus, an Intelll bus, a VESA local bus, an Accelerated Graphics Port (AGP) bus, a Video Electronics Standards Association (VESA) bus, or other suitable bus. In at least one embodiment, one or more of interface buses 2610 can be a bus using time-division multiplexing, a bus using Throttling, or another suitable bus structure at one or more embodiments. In at least one embodiment, one or more of interface buses 2610 can be a bus that is not standardized.

[0300] In at least one embodiment, memory device 2620 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, or a

[0301] In at least one embodiment, platform controller hub 2630 enables peripherals to connect to storage devices 2620 and processor 2602 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, audio controller 2646, network controller 2634, firmware interface 2628, wireless transceiver 2626, touch sensors 2625, data storage devices 2624 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage devices 2624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensors 2625 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2628 enables communication with system firmware, in at least one embodiment, and can be a unified extensible firmware interface (UEFI). In at least one embodiment, network controller 2634 can enable network connectivity to one or more wired networks. In at least one embodiment, a high-performance network controller (not shown) is coupled

[0302] In at least one embodiment, memory controller 2616 and instances of platform controller hub 2630 can be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, platform controller hub 2630 and / or memory controller 2616 can be external to one or more processor(s) 2602. In at least one embodiment, processing system 2600 can include an external memory controller 2616 and platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system-on-a-chip (SoC) implementation.

[0303] Figure 27A computer system 2700 according to at least one embodiment is shown. In at least one embodiment, computer system 2700 can be a system with interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, computer system 2700 is formed from a processor 2702 that can include execution units to execute an instruction. In at least one embodiment, computer system 2700 can include, without limitation, components such as processor 2702 that employ execution units including logic to perform algorithms for process data. In at least one embodiment, computer system 2700 can include processors such as Pentium®, CoreTM, XScaleTM, and / or StrongARM™, Core TM or Nervana TM microprocessors, although other systems (including PCs, workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, computer system 2700 can execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces can also be used.

[0304] In at least one embodiment, computer system 2700 can be used in other devices such as handheld devices and embedded applications. Some embodiments of at least one embodiment of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor (“DSP”), a SOC, a network computer (“NetPC”), a set-top box, a network hub, a wide area

[0305] In at least one embodiment, computer system 2700 can include, without limitation, a processor 2702 that can include, without limitation, one or more execution units 2708 that can be configured to execute a computational unified device architecture (“CUDA”) (registered trademark) algorithm. In at least one embodiment, execution units 2708 can be configured to execute other algorithms efficiently to perform at a CUDA program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 2700 is a single processor desktop or server system. In at least one embodiment, computer system 2700 can be a multiprocessor system. In at least one embodiment, processor 2702 can include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, in at least one embodiment. In at least one embodiment, processor 2702 can be coupled to a processor bus 2710 that can transmit data signals between processor 2702 and other components in computer system 2700.

[0306] In at least one embodiment, processor 2702 can include, without limitation, a level 1 (“Ll”) internal cache memory (“cache”) 2704. In at least one embodiment, processor 2702 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, cache memory can reside in the processor 2702’s external. In at least one embodiment, processor 2702 can include a combination of internal and external caches. In at least one embodiment, register file 2706 can store different types of data within various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer registers.

[0307] In at least one embodiment, execution unit 2708, including, without limitation, logic to perform integer and floating point operations, also resides in processor 2702. Processor 2702 can also include microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 2708 can include logic to handle a packed instruction set 2709. In at least one embodiment, by including the packed instruction set 2709 in the instruction set of a general-purpose processor 2702, along with associated circuitry to execute the instructions, the general-purpose processor 2702 can be used to perform the operations on packed data that many multimedia applications use. In at least one embodiment, by using the full width of the processor’s data bus when performing operations on packed data, many multimedia applications can be accelerated as compared to using load / store type architectures, which can require multiple Tens of load and store operations per application.

[0308] In at least one embodiment, execution unit 2708 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 2700 can include, but not limited to, memory 2720. In at least one embodiment, memory 2720 can be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 2720 can store instructions 2719 and / or data 2721 that can be executed by processor 2702 as signaled by data signals.

[0309] In at least one embodiment, system logic chip can be coupled to processor bus 2710 and memory 2720. In at least one embodiment, system logic chip can include, without limitation, a memory controller hub (“MCH”) 2716, and processor 2702 can communicate with MCH 2716 via processor bus 2710. In at least one embodiment, MCH 2716 can provide a high bandwidth memory path 2718 to memory 2720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2716 can direct data signals between processor 2702, memory 2720, and other components in computer system 2700, and can

[0310] In at least one embodiment, computer system 2700 can use system I / O 2722 as a proprietary hub interface bus to couple MCH 2716 to I / O controller hub (“ICH”) 2730. In at least one embodiment, ICH 2730 can provide direct connections to some I / O devices and a high-speed I / O bus to connect to other I / O devices. In at least one embodiment, the high-speed I / O bus can include, without limitation, a PCI Express bus. Examples can include, without limitation, audio controller 2729, firmware hub (“Flash BIOS”) 2728, wireless transceiver 2726, data storage 2724, legacy I / O controller 2723 containing user input 2725 and keyboard interface, serial expansion port 2777 (e.g., USB), and network controller 2734. Data storage 2724 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0311] In at least one embodiment, Figure 27 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, Figure 27 An exemplary SoC can be shown. In at least one embodiment, Figure 27 Devices shown in FIG. 27 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2700 are interconnected using Compute Express Link (CXL) interconnects.

[0312] Figure 28 System 2800 according to at least one embodiment is shown. In at least one embodiment, system 2800 is an electronic device that utilizes processor 2810. In at least one embodiment, system 2800 can be, without limitation, a laptop, a tower server, a rack server, a blade server, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0313] In at least one embodiment, system 2800 can include, without limitation, processor 2810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 2810 is coupled using a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment,Figure 28 Systems can be shown that include interconnected hardware devices or “chips.” In at least one embodiment, systems can include interconnected hardware devices or “chips.” Figure 28 An exemplary SoC can be shown. In at least one embodiment, an exemplary SoC can include a CPU 2802, a GPU 2804, a display 2824, a touchscreen 2825, a touchscreen controller 2826, a DSP 2860, a communication unit 2808, a flash memory 2806, a storage 2820, a sensor hub 2840, a thermal sensor 2846, a power management unit (“PMU”) 2803, a high definition audio CODEC 2805, a secure digital (“SD”) card controller 2807, a universal serial bus (“USB”) controller 2810, a camera controller 2813, a mobile industry processor interface (“MIPI”) controller 2814, a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 2815, a wireless local area network unit (“WLAN”) 2850, a Bluetooth unit 2852, a wireless wide area network unit (“WWAN”) 2856, a global positioning system 2855, a Figure 28 Devices shown in FIG. 28 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 28 are interconnected using compute express link (“CXL”) interconnects. Figure 28

[0314] In at least one embodiment, systems can include a display 2824, a touchscreen 2825, a touchpad 2830, a near field communication unit (“NFC”) 2845, a sensor hub 2840, a thermal sensor 2846, an express chipset (“EC”) 2835, a trusted platform module (“TPM”) 2838, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 2822, a DSP 2860, a solid state disk (“SSD”) or hard disk drive (“HDD”) 2820, a wireless local area network unit (“WLAN”) 2850, a Bluetooth unit 2852, a wireless wide area network unit (“WWAN”) 2856, a global positioning system (“GPS”) 2855, a camera (“USB 3.0 camera”) 2854 (e.g., a USB 3.0 camera), or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 2815 implemented in at least one embodiment LPDDR3 standard. These components can each be implemented in any suitable manner. Figure 28

[0315] ​​In at least one embodiment, other components can be communicatively coupled to processor 2810 by components discussed above. In at least one embodiment, an accelerometer 2841, an ambient light sensor (“ALS”) 2842, a compass 2843, and a gyroscope 2844 can be communicatively coupled to a sensor hub 2840. In at least one embodiment, a thermal sensor 2839, a fan 2837, a keyboard 2846, and a touchpad 2830 can be communicatively coupled to EC 2835. In at least one embodiment, a speaker 2863, a headphone 2864, and a microphone (“mic”) 2865 can be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 2864, which in turn can be communicatively coupled to DSP 2860. In at least one embodiment, audio unit 2864 can include, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 2857 can be communicatively coupled to WWAN unit 2856. In at least one embodiment, components such as WLAN unit 2850 and Bluetooth unit 2852, as well as WWAN unit 2856, can be implemented in a Next Generation Form Factor (NGFF).

[0316] Figure 29 An exemplary integrated circuit 2900 is shown, in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit 2900 is a SoC, which can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and can additionally include an image processor 2915 and / or a video processor 2920, any of which can be a modular IP core. In at least one embodiment, integrated circuit 2900 includes peripheral or bus logic including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I2S / I2C controller 2940. In at least one embodiment, integrated circuit 2900 can include a display device 2945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. In at least one embodiment, storage can be provided by flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via memory controller 2965 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2970.

[0317] Figure 30A computing system 3000 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 3000 includes a processing subsystem 3001 having one or more processor(s) 3002 and system memory 3004, which communicate via an interconnection path 3005 that can include a memory hub 3005. In at least one embodiment, the memory hub 3005 can be a separate component coupled with one or more processors 3002 via individual communication links 3007A-3007N. In at least one embodiment, memory hub 3005 can be integrated into one or more processors 3002.

[0318] In at least one embodiment, processing subsystem 3001 includes one or more parallel processor(s) 3012 coupled to memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, communication link 3013 can be one of many such links which can be implemented as standard system buses

[0319] In at least one embodiment, system storage 3014 can connect to I / O hub 3007 to provide storage mechanisms for computing system 3000. In at least one embodiment, I / O switches 3016 can be used to provide interface mechanisms to enable connections between I / O hub 3007 and other components such as network adapter 3018 and / or wireless network adapter 3019 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 3020. In at least one embodiment, network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0320] In at least one embodiment, computing system 3000 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and / or variations of the same, which can also connect to I / O hub 3007. In at least one embodiment, communication paths interconnecting various components in Figure 30 Communication paths interconnecting various components in at least one embodiment can use any suitable protocols including, for example, PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect, or inter-integrated circuit (I2C) protocols).

[0321] In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for graphics and video processing, in at least one embodiment including video output circuitry, and can be used in a graphics processing unit (GPU). In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for general use com puting. In at least one embodiment, components of computing system 3000 can be integrated with one or more other system elements on a single integrated circuit. In at least one embodiment, parallel processor(s) 3012, memory hub 3005, processor(s) 3002, and I / O hub 3007 can be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, components of computing system 3000 can be integrated into a single package to form a system in a package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 3000 can be integrated into a multichip module (MCM), which can be interconnected with other multichip modules to form a modular computing platform. In at least one embodiment, I / O subsystem 3011 and display device 3010B are omitted from computing system 3000.

[0322] Processing system

[0323] The following figures set forth, without limitation, example processing systems that can be used to implement at least one embodiment.

[0324] Figure 31 An accelerated processing unit (“APU”) 3100, in accordance with at least one embodiment, is shown. In at least one embodiment, APU 3100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, APU 3100 can be configured to execute application programs such as CUDA programs. In at least one embodiment, APU 3100 includes, without limitation, core complex 3110, graphics complex 3140, fabric 3160, I / O interface 3170, memory controllers 3180, display controllers 3192, and multimedia engines 3194. In at least one embodiment, APU 3100 can include, without limitation, any combination of any number of core complexes 3110, any number of graphics complexes 3140, any number of display controllers 3192, and any number of multimedia engines 3194. For purposes of illustration, multiple instances of similar objects are represented in this document by reference characters identifying the object, and a number in parentheses identifying the instance needed.

[0325] In at least one embodiment, core complex 3110 is a CPU, graphics complex 3140 is a GPU, and APU 3100 is a processing unit that integrates, without limitation, 3110 and 3140 onto a single chip. In at least one embodiment, some tasks can be assigned to core complex 3110, while other tasks can be assigned to graphics complex 3140. In at least one embodiment, core complex 3110 is configured to execute host control software associated with APU 3100, such as an operating system. In at least one embodiment, core complex 3110 is a master processor of APU 3100 that controls and coordinates the operations of the other processors. In at least one embodiment, core complex 3110 issues commands that control the operations of graphics complex 3140. In at least one embodiment, core complex 3110 can be configured to execute host executable code derived from CUDA source code, and graphics complex 3140 can be configured to execute device executable code derived from CUDA source code.

[0326] In at least one embodiment, core complex 3110 includes, without limitation, cores 3120(1)-3120(4) and L3 cache 3130. In at least one embodiment, core complex 3110 can include, without limitation, any combination of any number of cores 3120 and any number and type of caches. In at least one embodiment, cores 3120 are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core 3120 is a CPU core.

[0327] In at least one embodiment, each core 3120 includes, without limitation, a fetch / decode unit 3122, an integer execution engine 3124, a floating point execution engine 3126, and an L2 cache 3128. In at least one embodiment, fetch / decode unit 3122 fetches instructions, decodes such instructions, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3124 and floating point execution engine 3126. In at least one embodiment, fetch / decode unit 3122 can concurrently dispatch one micro-instruction to integer execution engine 3124 and another micro-instruction to floating point execution engine 3126. In at least one embodiment, integer execution engine 3124 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3126 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3122 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3124 and floating point execution engine 3126.

[0328] In at least one embodiment, each core 3120(i) has access to an L2 cache 3128(i) included in core 3120(i), where i is an integer representing a particular instance of core 3120. In at least one embodiment, each core 3120 included in core complex 3110(j) is connected to other cores 3120 included in core complex 3110(j) via an L3 cache 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, cores 3120 included in core complex 3110(j) have access to all L3 caches 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, L3 cache 3130 can include, without limitation, any number of slices.

[0329] In at least one embodiment, graphics complex 3140 can be configured to perform compute operations in a highly parallel manner. In at least one embodiment, graphics complex 3140 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, graphics complex 3140 is configured to perform operations that are not graphics related. In at least one embodiment, graphics complex 3140 is configured to perform graphics related operations and operations that are not graphics related.

[0330] In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of graphics processing clusters 3130 and shared L2 cache 3132. In at least one embodiment, graphics processing clusters 3130 share shared L2 cache 3132. In at least one embodiment, shared L2 cache 3132 is partitioned among graphics processing clusters 3130. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of graphics processing clusters 3130 and any number (including zero) and type of cache. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of specialized graphics hardware.

[0331] In at least one embodiment, each graphics processing cluster 3130 includes, without limitation, any number of SIMD units 3132 and shared memory 3134. In at least one embodiment, each SIMD unit 3132 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each graphics processing cluster 3130 can execute any number of thread blocks, but each thread block executes on a single graphics processing cluster 3130. In at least one embodiment, a thread block includes, without limitation, any number of threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3132 executes a different thread warp. In at least one embodiment, a thread warp is a group of threads (e.g., 16 threads), where each thread in a thread warp belongs to a single thread block and is configured to process a different set of data based on a single instruction set. In at least one embodiment, one or more threads in a thread warp can be disabled using predication. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3134.

[0332] In at least one embodiment, fabric 3160 is a system interconnect that facilitates data and control transmissions across core complex 3110, graphics complex 3140, I / O interface 3170, memory controllers 3180, display controller 3192, and multimedia engine 3194. In at least one embodiment, APU 3100 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3160 that facilitate data and control transmissions across any number and type of directly or indirectly linked components that can be internal or external to APU 3100. In at least one embodiment, I / O interface 3170 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3170. In at least one embodiment, peripheral devices coupled to I / O interface 3170 can include, without limitation, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0333] In at least one embodiment, display controller 3192 displays images on one or more display devices, such as liquid crystal display (“LCD”) devices. In at least one embodiment, multimedia engine 3194 includes, without limitation, any number and type of multimedia-related circuitry, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 3180 facilitate data transfers between APU 3100 and unified system memory 3190. In at least one embodiment, core complex 3110 and graphics complex 3140 share unified system memory 3190.

[0334] In at least one embodiment, APU 3100 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that can be dedicated to one component or shared among multiple components. In at least one embodiment, APU 3100 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which can be private to a component or shared among any number of components (e.g., core 3120, core complex 3110, SIMD unit 3152, compute unit 3150, and graphics complex 3140).

[0335] Figure 32A CPU 3200 is shown, in accordance with at least one embodiment. In at least one embodiment, CPU 3200 is developed by AMD Corporation, of Santa Clara, California. In at least one embodiment, CPU 3200 can be configured to execute application programs. In at least one embodiment, CPU 3200 is configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 3200 includes, without limitation, any number of core complexes 3210, fabric 3260, I / O interfaces 3270, and memory controllers 3280.

[0336] In at least one embodiment, core complex 3210 includes, without limitation, cores 3220(1)-3220(4) and L3 cache 3230. In at least one embodiment, core complex 3210 can include, without limitation, any number of cores 3220 and any combination and type of caches. In at least one embodiment, cores 3220 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 3220 is a CPU core.

[0337] In at least one embodiment, each core 3220 includes, without limitation, a fetch / decode unit 3222, an integer execution engine 3224, a floating point execution engine 3226, and an L2 cache 3228. In at least one embodiment, fetch / decode unit 3222 fetches instructions, decodes them, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3224 and floating point execution engine 3226. In at least one embodiment, fetch / decode unit 3222 can dispatch one micro-instruction to integer execution engine 3224 and another micro-instruction to floating point execution engine 3226 simultaneously. In at least one embodiment, integer execution engine 3224 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3226 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3222 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3224 and floating point execution engine 3226.

[0338] In at least one embodiment, each core 3220(i) has access to an L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a particular instance of a core 3220. In at least one embodiment, each core 3220 included in a core complex 3210(j) is connected to other cores 3220 in the core complex 3210(j) via an L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, a core 3220 included in a core complex 3210(j) has access to all L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, an L3 cache 3230 can include, without limitation, any number of slices.

[0339] In at least one embodiment, fabric 3260 is a system interconnect that facilitates data and control transfers across core complexes 3210(1)-3210(N) (where N is an integer greater than zero), I / O interface 3270, and memory controllers 3280. In at least one embodiment, CPU 3200 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3260 that facilitate data and control transfers across any number and type of directly or indirectly linked components that can be internal or external to CPU 3200. In at least one embodiment, I / O interface 3270 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3270. In at least one embodiment, peripheral devices coupled to I / O interface 3270 can include, without limitation, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other types of game controller, a media recording device, an external storage device, a network interface card, etc.

[0340] In at least one embodiment, memory controllers 3280 facilitate data transfers between CPU 3200 and system memory 3290. In at least one embodiment, core complex 3210 and graphics complex 3240 share system memory 3290. In at least one embodiment, CPU 3200 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3280 and memory devices that can be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 3200 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which can be private to a component or shared among any number of components (e.g., core 3220 and core complex 3210).

[0341] Figure 33 An exemplary accelerator integration slice 3390 is shown in accordance with at least one embodiment. As used herein, a “slice” comprises a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, an accelerator integration circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines that are part of graphics acceleration modules. Graphics processing engines can each comprise a separate GPU. Alternatively, graphics processing engines can comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module can be a GPU with a plurality of graphics processing engines. In at least one embodiment, a graphics processing engine can be a separate GPU integrated on a common package, line card, or chip as the CPU.

[0342] An application effective address space 3382 within system memory 3314 stores process elements 3383. In one embodiment, process elements 3383 are stored in response to GPU invocations 3381 from applications 3380 executing on processor 3307. Process elements 3383 contain processing state for corresponding applications 3380. A work descriptor (WD) 3384 contained in process element 3383 can be a single job requested by an application or can contain pointers to a queue of jobs. In at least one embodiment, WD 3384 is a pointer to a job request queue in application effective address space 3382.

[0343] Graphics acceleration module 3346 and / or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, infrastructure for establishing process state and sending WDs 3384 to graphics acceleration module 3346 to start jobs in a virtualized environment can be included.

[0344] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 3346 or individual graphics processing engines. As graphics acceleration module 3346 is owned by a single process, a hypervisor initializes the accelerator integration circuit for the owning partition and an operating system initializes the accelerator integration circuit for the owning partition when assigning graphics acceleration module 3346.

[0345] In operation, a WD fetch unit 3391 in accelerator integration slice 3390 fetches a next WD 3384 including an indication of work to be completed by one or more graphics processing engines of graphics acceleration module 3346. Data from WD 3384 can be stored in registers 3345 used by memory management unit (MMU) 3339, interrupt management circuit 3347, and / or environment management circuit 3348, as shown. At least one embodiment of MMU 3339 includes segment / page walk circuitry to access segment / page tables 3386 within an OS virtual address space 3385. Interrupt management circuit 3347 can handle interrupt events (INTs) 3392 received from graphics acceleration module 3346. Effective addresses 3393 produced by graphics processing engines, when executing graphics operations, are translated to real addresses by MMU 3339.

[0346] In one embodiment, a same set of registers 3345 is replicated for each graphics processing engine and / or graphics acceleration module 3346 and can be initialized by a system hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 3390. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0347] Table 1 - Hypervisor Initialized Registers

[0348]

[0349]

[0350] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0351] Table 2 - Operating System Initialized Registers

[0352] 1 Process and thread identification 2 Effective address (EA) environment save / restoration pointer 3 Virtual address (VA) accelerator utilization record pointer 4 Virtual address (VA) storage segment table pointer 5 Authority mask 6 Work descriptor

[0353] In one embodiment, each WD 3384 is specific to a particular graphics processing module 3346 and / or a particular graphics processing engine. It contains all information the graphics processing engine needs to work or work needed, or it can be a pointer to a memory location where an application has set up a command queue of work to be done.

[0354] Figures 34A-34B An exemplary graphics processor according to at least one embodiment is shown. In at least one embodiment, any of the exemplary graphics processors can be fabricated as one or more IP cores. In addition to the graphics processors illustrated, in at least one embodiment, other logic and circuits can be included, including additional graphics processors cores or special-purpose processing cores, peripheral interface controllers or general-purpose processor cores. In at least one embodiment, graphics processor is used in a SoC implementation.

[0355] Figure 34A An exemplary graphics processor 3410 of a SoC integrated circuit, according to at least one embodiment, can be fabricated using one or more IP cores. Figure 34B An additional exemplary graphics processor 3440 of a SoC integrated circuit, according to at least one embodiment, can be fabricated using one or more IP cores. In at least one embodiment, Figure 34A Graphics processor 3410 of FIG. 34 is a low power graphics processor core. In at least one embodiment, graphics processor 3410 is used in a SoC implementation. Figure 34B Graphics processor 3440 of FIG. 34 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 can be Figure 5 Variants of graphics processor 510 of FIG. 5.

[0356] In at least one embodiment, graphics processor 3410 includes a vertex processor 3405 and one or more fragment processor(s) 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D, through 3415N-1, and 3415N). In at least one embodiment, graphics processor 3410 can execute different shader programs via separate logic for vertex processing and / or for fragment / pixel processing. In at least one embodiment, vertex processor 3405 is optimized to execute operations on vertex data that frequently process complex, high-precision calculations for geometry transformations, motion blur, and dynamic shading. In at least one embodiment, one or more fragment processor(s) 3415A-3415N can be optimized to execute more SIMT-based calculations with structured general-purpose programmability. In at least one embodiment, a pinout I / O circuit 3425 is disposed on graphics processor 3410 for communicating with a system processor, memory, or other input / output devices. In at least one embodiment, graphics processor 3410 includes a display engine 3435 optimized to perform processing of multiple tiles of a tiled display in parallel. In at least one embodiment, a display engine 3435 can include memory objects in an L2 cache or system memory not explicitly specified by code in a shader program. In at least one embodiment, display engine 3435 can include one or more propagators (e.g., for stencil operations, general arithmetic operations, etc.). In at least one embodiment, a display engine 3435 can include one or more propagation units to perform gather operations on a set or multiple sets of data, propagate the gathered data through a computational unit, and scatter the results. In at least one embodiment, a display engine 3435 can include a propagation unit to gather, compute on, and scatter multiple sets of data. In at least one embodiment, a display engine 3435 can include a propagation unit to gather, compute on, and scatter multiple sets of data in parallel. In at least one embodiment, a display engine 3435 can include a propagation unit to gather, compute on, and scatter multiple sets of data in parallel with multiple computational units.

[0357] In at least one embodiment, graphics processor 3410 additionally includes one or more MMU(s) 3420A-3420B, cache memory 3425A-3425B, and circuit interconnect 3430A-3430B. In at least one embodiment, one or more MMU(s) 3420A-3420B provide for virtual to physical address mapping for graphics processor 3410, including for vertex processor 3405 and / or fragment processor 3415A-3415N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 3425A-3425B. In at least one embodiment, one or more MMU(s) 3420A-3420B can be synchronized with other MMUs within Figure 5 In at least one embodiment, one or more application processor(s) 505, image processor(s) 515, and / or video processor(s) 520 are associated with one or more MMUs such that each processor 505-520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3430A-3430B enable graphics processor 3410 to interface with other IP cores within a SoC, either via an internal bus, or via a direct connection.

[0358] In at least one embodiment, graphics processor 3440 includes Figure 34Aone or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnect 3430A-3430B of graphics processor 3410. In at least one embodiment, graphics processor 3440 includes one or more shader core(s) 3455A-3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, through 3455N-1, and 3455N), which provide for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary from one graphics processor to another graphics processor. In at least one embodiment, graphics processor 3440 includes an inter-core task manager 3445, which acts as a thread dispatcher to distribute execution threads to one or more shader cores 3455A-3455N and a tiling unit 3458 to accelerate tiling operations for tile-based rendering in which render operations for a scene are subdivided in image space, e.g., to

[0359] Figure 35A A graphics core 3500 according to at least one embodiment is shown. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410. Figure 24 A graphics core 3500 according to at least one embodiment is shown. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410. Figure 34B In at least one embodiment, graphics core 3500 includes shared instruction cache 3502, texture unit 3518, and cache / shared memory 3520, which are common to execution resources within graphics core 3500. In at least one embodiment, graphics core 3500 can include a number of slices 3501A-3501N or partitions of each core, and graphics processor can include multiple instances of graphics core 3500. Slices 3501A-3501N can include support logic including a local instruction cache 3504A-3504N, a thread scheduler 3506A-3506N, a thread dispatcher 3508A-3508N, and a set of registers 3510A-3510N. In at least one embodiment, slices 3501A-3501N can include a set of additional functional units (AFUs) 3512A-3512N, floating point units (FPUs) 3514A-3514N, integer arithmetic logic units (ALUs) 3516A-3516N, address computation units (ACUs) 3513A-3513N, double precision floating point units (DPFPUs) 3517A-3517N, and / or special function units (SFUs) 3511A-3511N, which can be specific to a particular type of graphics processing operation.

[0360] 3515A-3515N and matrix processing units (MPUs) 3517A-3517N.

[0361] In one embodiment, the FPUs 3514A-3514N can perform single precision (32-bit) and half precision (16-bit) floating point operations, while the DPFPUs 3515A-3515N can perform double precision (64-bit) floating point operations. In at least one embodiment, the ALUs 3516A-3516N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured to perform mixed precision operations. In at least one embodiment, the MPUs 3517A-3517N can also be configured to perform mixed precision matrix operations, including half-precision floating point operations and 8-bit integer operations. In at least one embodiment, the MPUs 3517A-3517N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, the AFUs 3512A-3512N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0362] Figure 35B A general purpose graphics processing unit (GPGPU) 3530 in at least one embodiment is shown. In at least one embodiment, GPGPU 3530 is highly parallel and is suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 3530 can be configured to enable highly parallel compute operations to be performed by a GPU array. In at least one embodiment, GPGPU 3530 can be directly linked to other instances of GPGPU 3530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 3530 includes a host interface 3532 to enable connection to a host processor. In at least one embodiment, host interface 3532 is a PCIe interface. In at least one embodiment, host interface 3532 can be a vendor-specific communications interface or communication structure. In at least one embodiment, GPGPU 3530 receives commands from a host processor and uses a global scheduler 3534 to dispatch execution threads associated with those commands to a group of compute clusters 3536A-3536H. In at least one embodiment, compute clusters 3536A-3536H share a cache memory 3538. In at least one embodiment, cache memory 3538 can be used as an upper level cache for cache memory within compute clusters 3536A-3536H.

[0363] In at least one embodiment, GPGPU 3530 includes memory 3544A-3544B coupled with compute clusters 3536A-3536H via a set of memory controllers 3542A-3542B. In at least one embodiment, memory 3544A-3544B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0364] In at least one embodiment, compute clusters 3536A-3536H each include a group of graphics cores, such as graphics core 3500, which can include multiple types of integer and floating point logic units that can perform computational operations at various precisions, including suitable for computations related to CUDA programs. In at least one embodiment, at least a subset of floating point units in each compute cluster 3536A-3536H can be configured to perform 16- or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. Figure 35A

[0365] In at least one embodiment, multiple instances of GPGPU 3530 can be configured to operate as compute clusters. In at least one embodiment, compute clusters 3536A-3536H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3530 communicate over host interface 3532. In at least one embodiment, GPGPU 3530 includes I / O hub 3539 that couples GPGPU 3530 with GPU link 3540, enabling a direct connection to other instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a specialized GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3530 are located in separate data processing systems and communicate over a network device accessible via host interface 3532. In at least one embodiment, GPU link 3540 can be configured to enable a connection to a host processor, in addition to or in place of host interface 3532. In at least one embodiment, GPGPU 3530 can be configured to execute CUDA programs.

[0366] Figure 36A ​A parallel processor 3600 according to at least one embodiment is shown. In at least one embodiment, various components of parallel processor 3600 can be implemented using one or more integrated circuits, for example, programmable processors, application specific integrated circuits (ASICs), or FPGAs.

[0367] In at least one embodiment, parallel processor 3600 includes a parallel processing unit 3602. In at least one embodiment, parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of parallel processing unit 3602. In at least one embodiment, I / O unit 3604 can be directly connected to other devices. In at least one embodiment, I / O unit 3604 connects with other devices via use of a hub or switch interface, for example, memory hub 605. In at least one embodiment, connections between memory hub 605 and I / O unit 3604 form a communication link. In at least one embodiment, I / O unit 3604 connects with a host interface 3606 and a memory crossbar 3616, where host interface 3606 receives commands directed to performing processing operations and memory crossbar 3616 receives commands directed to performing memory operations.

[0368] In at least one embodiment, when host interface 3606 receives a command buffer via I / O unit 3604, host interface 3606 can direct work operations to execute those commands to front end 3608. In at least one embodiment, front end 3608 couples with a scheduler 3610, which is configured to assign commands or other work items to processing array 3612. In at least one embodiment, scheduler 3610 ensures that processing array 3612 is properly configured and in an active state before assigning tasks to processing array 3612 of processing array 3612. In at least one embodiment, scheduler 3610 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller- implemented scheduler 3610 is configurable to perform complex scheduling and work distribution operations in a coarse and fine grain fashion, enabling quick preemption and context switching for threads executing on processing array 3612. In at least one embodiment, host software can prove a workload for scheduling on processing array 3612 through one of a number of graphics processing doorbells. In at least one embodiment, workload can then be automatically distributed by scheduler 3610 logic within microcontroller including scheduler 3610 on processing array 3612.

[0369] In at least one embodiment, processing array 3612 can include up to “N” processing clusters (e.g., cluster 3614A, cluster 3614B, through cluster 3614N). In at least one embodiment, each cluster 3614A-3614N of processing array 3612 can execute a large number of concurrent threads. In at least one embodiment, scheduler 3610 can allocate work to clusters 3614A-3614N of processing array 3612 using various scheduling and / or work distribution algorithms, which can be determined at least in part by workload arriving at processing array 3612, and / or received from other processor cores, processor arrays, or systems, which can be structured as a multi-core computer system, a multiprocessor computer system, or a distributed computer system.

[0370] In at least one embodiment, processing array 3612 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3612 is configured to perform general-purpose parallel compute operations. In at least one embodiment, processing array 3612 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0371] In at least one embodiment, processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3612 can include additional logic to support performance of such graphics processing operations, including, without limitation, texture sampling logic to perform texture operations, tiling logic, and other vertex processing logic. In at least one embodiment, processing array 3612 can be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 3602 can transfer data to be processed from a system memory via I / O unit 3604. In at least one embodiment, data can be stored to on-chip memory (e.g., parallel processor memory 3622) during processing, and then written back to system memory.

[0372] In at least one embodiment, when parallel processing unit 3602 is used to perform graphics processing, scheduler 3610 can be configured to divide incoming workloads into tasks of approximately equal size to better enable distribution of graphics processing operations across multiple clusters 3614A-3614N of processing array 3612. In at least one embodiment, portions of processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display on a display device. In at least one embodiment, intermediate data produced by one or more of clusters 3614A-3614N can be stored in buffers to allow transmission of intermediate data between clusters 3614A-3614N for further processing.

[0373] In at least one embodiment, processing array 3612 can receive processing tasks to be executed from scheduler 3610, which receives commands defining the processing tasks from front end 3608. In at least one embodiment, a processing task can include an index into data to be processed, which can include surface (patch) data, raw data, vertex data, and / or pixel data, for example, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 3610 can be configured to fetch the index corresponding to a task, or can receive the index from front end 3608. In at least one embodiment, front end 3608 can be configured to ensure that processing array 3612 is configured in an effective state before launching a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0374] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to a parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed by the processing array 3612, as well as the I / O unit 3604, via a memory crossbar 3616. In at least one embodiment, memory crossbar 3616 can be used to transfer data between memory elements and the processing array 3612. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar.

[0375] In at least one embodiment, memory units 3624A-3624N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A-3624N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 3624A-3624N, allowing partition units 3620A-3620N to write portions of each rendering target in parallel to effectively use available bandwidth of parallel processor memory 3622. In at least one embodiment, local instances of parallel processor memory 3622 can be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0376] In at least one embodiment, any of clusters 3614A-3614N of processing array 3612 can process data that is to be written into any of memory units 3624A-3624N within parallel processor memory 3622. In at least one embodiment, memory crossbar 3616 can be configured to transmit outputs of each cluster 3614A-3614N to any partition unit 3620A-3620N or another cluster 3614A-3614N, which can perform other processing operations on the outputs. In at least one embodiment, each cluster 3614A-3614N can communicate with memory interface 3618 through memory crossbar 3616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 3616 has a connection to memory interface 3618 to communicate with I / O unit 3604, as well as a local instance of parallel processor memory 3622, to enable processing elements within different processing clusters 3614A-3614N to communicate with system memory or other memory that is not local to the parallel processing elements 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate traffic streams between clusters 3614A-3614N and partition units 3620A-3620N.

[0377] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate in coordination with each other to enable single program multi-processing (SPMP). In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate as a single unit even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.

[0378] Figure 36B Processing cluster 3694 is shown according to at least one embodiment. In at least one embodiment, processing cluster 3694 is included in a parallel processing unit. In at least one embodiment, processing cluster 3694 is a Figure 36Aone of the processing clusters 3614A-3614N. In at least one embodiment, processing cluster 3694 can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executed by a particular group of one or more processing clusters. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads with no or negligible program overhead. In at least one embodiment, Single Instruction Multiple Thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster 3694.

[0379] In at least one embodiment, operation of processing cluster 3694 can be controlled via a pipeline manager 3632 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 3632 receives instructions from scheduler 3610 and manages execution of those instructions by graphics multiprocessor 3634 and / or texture unit 3636, in at least one embodiment, graphics multiprocessor 3634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures can be included within processing cluster 3694. In at least one embodiment, one or more instances of graphics multiprocessor 3634 can be included within processing cluster 3694. In at least one embodiment, graphics multiprocessor 3634 can process data and a data crossbar 3640 can be used to distribute processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, pipeline manager 3632 can facilitate distribution by specifying destinations for processed data as a function of the destination’s source in either a fixed function or switched fabric manner. Figure 36A

[0380] In at least one embodiment, each graphics multiprocessor 3634 within processing cluster 3694 can include an identical set of functional execution logic (e.g., arithmetic logic units, load store units (LSUs), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which instructions are issued at a first stage, passed through stages of the pipeline with each stage performing at least one instruction, and results from a last stage are used as inputs to subsequent instruction units at a subsequent stage in the pipeline. In at least one embodiment, there can be one instruction unit for every parallel thread. In at least one embodiment, functional execution logic is implemented using a variety of high-speed, low-latency circuitry and can be used for a wide variety of general purpose and special purpose computational needs.

[0381] ​In at least one embodiment, instructions delivered to processing cluster 3694 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines constitutes a warp. In at least one embodiment, a thread group is a group of threads executing the same program, although each thread within a thread group can be at different instruction points within the program. In at least one embodiment, a thread group is associated with a same set of instruction boundaries. In at least one embodiment, a thread group includes fewer threads than are available processing engines within graphics multiprocessor 3634. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines within graphics multiprocessor 3634 available to be invoked, one or more of the processing engines can be idle during a cycle when a thread group is not available; in at least one embodiment, graphics multiprocessor 3634 can be configured to handle multiple thread groups, with each thread group being allocated to “threads” (where threads in a thread group are concurrently executing instmctions on the processing engines).

[0382] In at least one embodiment, graphics multiprocessor 3634 includes internal cache memory, to perform load and store operations. In at least one embodiment, graphics multiprocessor 3634 can bypass internal cache and use cache memory within processing cluster 3694 (e.g., LI cache 3648). In at least one embodiment, each graphics multiprocessor 3634 can also have access to L2 Cache within a partition unit (e.g., partition units 3620A-3620N) that is shared among multiple processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3634 can also have access to off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processor 3602 can be used as global memory. In at least one embodiment, processing cluster 3694 includes multiple instances of graphics multiprocessor 3634 that share common instructions and data, which can be stored in LI cache 3648. Figure 36A

[0383] In at least one embodiment, each processing cluster 3694 can include an MMU 3645 configured to translate virtual addresses into physical addresses, as is known to those skilled in the art. In at least one embodiment, one or more instances of MMU 3645 can reside within graphics multiprocessor 3634. In at least one embodiment, graphics multiprocessor 3634 includes a cache memory 3648 to cache data stored in system memory. In at least one embodiment, graphics multiprocessor 3634 includes a shared memory 3650 to store data for threads executing on graphics multiprocessor 3634. Figure 36A ​In at least one embodiment, MMU 3645 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses at a granularity of a page row (e.g., 4K bytes). In at least one embodiment, MMU 3645 can include address translation lookaside buffers (TLBs) to improve translation speed by storing recently used virtual to physical mappings. In at least one embodiment, MMU 3645 can include a set of page table entries (PTEs) for mapping virtual addresses to physical addresses at a granularity of a cache line (e.g., 64 bytes). In at least one embodiment, MMU 3645 can reside in graphics processing cluster 3694, L1 cache 3648, or graphics multiprocessor 3634.

[0384] In at least one embodiment, processing cluster 3694 can be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data can be read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 3634 and cached in an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 3634 outputs processed tasks to data crossbar 3640 to provide processed task data to another processing cluster 3694 for further processing or to store processed task data in an L2 cache, local parallel processor memory, or system memory via memory crossbar 3616. Figure 36A In at least one embodiment, a pre-raster operations unit (Pre-ROP) 3642 is configured to receive data from graphics multiprocessor 3634, direct data to ROP unit in a graphics processing cluster 3694, which can be located within or outside of processing cluster 3694, in at least one embodiment. In at least one embodiment, Pre-ROP 3642 can perform optimizations to minimize processor fetch and memory traffic to data. In at least one embodiment, Pre-ROP 3642 includes a shared L1 cache.

[0385] Figure 36C A graphics multiprocessor 3696 according to at least one embodiment is shown. In at least one embodiment, graphics multiprocessor 3696 is a GPC as described herein, but in other embodiments graphics multiprocessor 3696 can be any processor capable of performing graphics, media, and compute operations, such as a GPU. In at least one embodiment, graphics multiprocessor 3696 can be a part of a graphics processing unit (GPU) which can further include a graphics memory controller (not shown) to process tasks such as graphics-intensive computations. Figure 36Bgraphics processor 3634. In at least one embodiment, graphics processor 3696 couples with the pipeline manager 3632 of processing cluster 3694. In at least one embodiment, graphics processor 3696 has an execution pipeline that includes, without limitation, an instruction cache 3652, an instruction unit 3654, an address mapping unit 3656, a register file 3658, one or more GPGPU cores 3662, and one or more LSU(s) 3666. GPGPU cores 3662 and LSUs 3666 couple with cache memory 3672 and shared memory 3670 through memory and cache interconnect 3668.

[0386] In at least one embodiment, instruction cache 3652 receives a stream of instructions 3650 to execute from pipeline manager 3632. In at least one embodiment, instructions are cached in instruction cache 3652 and dispatched for execution by instruction unit 3654. In one embodiment, instruction unit 3654 can dispatch instructions to the various functional units available on GPGPU cores 3662 including, but not limited to, integer algebraic units, floating point units, and others. In at least one embodiment, instructions are dispatched as groups, e.g., thread groups, which are executed via a thread group instruction. In at least one embodiment, thread groups are distributed to the cores 3662 for execution via inter-thread communication channel 3653.

[0387] In at least one embodiment, register file 3658 provides a set of registers for functional units of graphics processor 3696. In at least one embodiment, register file 3658 provides temporary storage for operands of the data paths connected to the functional units (e.g., GPGPU cores 3662, LSUs 3666) of graphics processor 3696. In at least one embodiment, register file 3658 is split between each functional unit such that there is a dedicated portion of the register file 3658 for each functional unit. In at least one embodiment, register file 3658 is partitioned between different thread groups executing on graphics processor 3696.

[0388] In at least one embodiment, GPGPU cores 3662 can each include FPUs and / or ALUs for executing instructions for graphics processing. GPGPU cores 3662 can be similar to each other in architecture or can include a mixture of different GPGPU core architectures. In at least one embodiment, a first portion of GPGPU cores 3662 include single precision FPUs and integer ALUs, while a second portion of GPGPU cores include double precision FPUs. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics processor 3696 can additionally include one or more fixed function or special-purpose processing units to perform specific computational tasks such as rectangle

[0389] In at least one embodiment, GPGPU cores 3662 include SIMD logic capable of performing a single -instruction multiple-data (SIMD) operation. In at least one embodiment GPGPU cores 3662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute a SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, a SIMD instruction implemented by GPGPU cores 3662 can be generated at compile time by a shader compiler from an application programming interface (API) or a high-level programming language.

[0390] In at least one embodiment, memory and cache interconnect 3668 is an interconnect network that connects each functional unit of graphics multiprocessor 3696 to register file 3658 and shared memory 3670. In at least one embodiment, memory and cache interconnect 3668 is a crossbar interconnect that allows LSUs 3666 to implement load and store operations between shared memory 3670 and register file 3658. In at least one embodiment, register file 3658 can operate at same frequency as GPGPU cores 3662, resulting in very low latency for data transfers between GPGPU cores 3662 and register file 3658. In at least one embodiment, shared memory 3670 can be used to enable communication between threads executing on functional units within graphics multiprocessor 3696. In at least one embodiment, cache memory 3672 can be used to store data for threads executing on functional units and texture data for textures accessed by these threads. In at least one embodiment, shared memory 3670 can also be used as a program managed cache.

[0391] In at least one embodiment, parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed

[0392] General-Purpose Computing

[0393] The following figures illustrate, without limitation, exemplary software configurations used in general-purpose computing to implement at least one embodiment.

[0394] Figure 37A software stack of a programming platform is shown, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate compute tasks. In at least one embodiment, a software developer can access a programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, a programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL TM ), SYCL, or Intel One API.

[0395] In at least one embodiment, software stack 3700 of a programming platform provides an execution environment for application 3701. In at least one embodiment, application 3701 can include any computer software capable of launching on software stack 3700. In at least one embodiment, application 3701 can include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0396] In at least one embodiment, application 3701 and software stack 3700 run on hardware 3707. In at least one embodiment, hardware 3707 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, software stack 3700 can be vendor-specific and compatible only with devices from a particular vendor, e.g., with CUDA. In at least one embodiment, software stack 3700 can be used with devices from different vendors, e.g., with OpenCL. In at least one embodiment, hardware 3707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform compute tasks. In at least one embodiment, in contrast to a host within hardware 3707, which can include, but is not limited to, a CPU (but can also include a computing device) and its memory, a device within hardware 3707 can include, but is not limited to, a GPU, FPGA, AI engine, or other computing device (but can also include a CPU) and its memory.

[0397] In at least one embodiment, software stack 3700 of a programming platform includes, without limitation, a plurality of libraries 3703, a runtime 3705, and a device kernel driver 3706. In at least one embodiment, each of libraries 3703 can include data and programming code that can be used by computer programs and leveraged during software development. In at least one embodiment, libraries 3703 can include, without limitation, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, libraries 3703 include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries 3703 can include, without limitation, functions for performing mathematical, deep learning, and / or other types of operations on a device. In at least one embodiment, libraries 3803 are associated with corresponding APIs 3802, which can include one or more APIs that expose functions implemented in libraries 3803.

[0398] In at least one embodiment, application 3701 is written as source code that is compiled into executable code, as discussed in more detail below with respect to FIG. 37B. Figure 42 In at least one embodiment, executable code of application 3701 can run, at least partially, on an execution environment provided by software stack 3700. In at least one embodiment, during execution of application 3701, code can be derived that needs to run on a device (as opposed to a host). In such a case, in at least one embodiment, runtime 3705 can be invoked to load and launch the necessary code on a device. In at least one embodiment, runtime 3705 can include any technically feasible runtime system capable of supporting execution of application 3701.

[0399] In at least one embodiment, runtime 3705 is implemented as one or more runtime libraries associated with corresponding APIs (which are shown as APIs 3704). In at least one embodiment, one or more such runtime libraries can include, without limitation, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions can include, without limitation, functions for allocating, deallocating, and copying device memory, as well as transferring data between host memory and device memory. In at least one embodiment, execution control functions can include, without limitation, functions for launching functions on a device (sometimes referred to as “kernels” when functions are global functions that can be called from a host), and functions for setting attribute values in buffers maintained by a runtime library for a given function to be executed on a device.

[0400] In at least one embodiment, runtime libraries and corresponding APIs 3704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number) of APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number) of APIs can expose a higher-level set of functions. In at least one embodiment, high-level runtime APIs can be built on top of low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of language-independent runtime APIs.

[0401] In at least one embodiment, device kernel driver 3706 is configured to facilitate communication with underlying devices. In at least one embodiment, device kernel driver 3706 can provide low-level functions relied upon by APIs such as APIs 3704 and / or other software. In at least one embodiment, device kernel driver 3706 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 3706 can compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a particular target device at runtime (caching compiled binary code), which is sometimes also referred to as “final” code. In at least one embodiment, doing so can allow final code to run on a target device that can not have existed when source code was initially compiled into PTX code. Alternatively, in at least one embodiment, device source code can be compiled into binary code offline without requiring device kernel driver 3706 to compile IR code at runtime.

[0402] Figure 38 A CUDA implementation of software stack 3700 is shown in accordance with at least one embodiment. Figure 37 In at least one embodiment, CUDA software stack 3800 on which application 3801 can be launched includes CUDA libraries 3803, CUDA runtime 3805, CUDA driver 3807, and device kernel driver 3808. In at least one embodiment, CUDA software stack 3800 executes on hardware 3809, which can include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0403] In at least one embodiment, application 3801, CUDA runtime 3805, and device kernel driver 3808 can perform similar functions as application 3701, runtime 3705, and device kernel driver 3706, respectively, described above in connection with Figure 37CUDA Driver 3807, which includes a library (libcuda.so) that implements the CUDA Driver API 3806. In at least one embodiment, similar to the CUDA Runtime API 3804 implemented by the CUDA Runtime Library (cudart), the CUDA Driver API 3806 can expose, without limitation, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, among others. In at least one embodiment, the CUDA Driver API 3806 differs from the CUDA Runtime API 3804 in that the CUDA Runtime API 3804 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to the high-level CUDA Runtime API 3804, in at least one embodiment, the CUDA Driver API 3806 is a low-level API that provides more granular control over a device, particularly with respect to context and module loading. In at least one embodiment, the CUDA Driver API 3806 can expose functions for context management that are not exposed by the CUDA Runtime API 3804. In at least one embodiment, the CUDA Driver API 3806 is also language agnostic and supports, for example, OpenCL in addition to the CUDA Runtime API 3804. Further, in at least one embodiment, development libraries including the CUDA Runtime 3805 can be considered separate from driver components, including the user-mode CUDA Driver 3807 and the kernel-mode device driver 3808 (sometimes also referred to as a “display” driver).

[0404] In at least one embodiment, CUDA Libraries 3803 can include, without limitation, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that can be utilized by parallel computing applications, such as application 3801. In at least one embodiment, CUDA Libraries 3803 can include mathematical libraries such as a cuBLAS library, which is an implementation of the Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations; a cuFFT library for computing Fast Fourier Transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA Libraries 3803 can include deep learning libraries such as a cuDNN library for primitives of deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

[0405] Figure 39 FIG. 38 shows a diagram of a system including a training data pipeline, in accordance with at least one embodiment Figure 37ROCm implementation of the software stack 3700. In at least one embodiment, the ROCm software stack 3900 on which the application 3901 can launch includes a language runtime 3903, a system runtime 3905, a thunk 3907, a ROCm kernel driver 3908, and a device kernel driver 3909. In at least one embodiment, the ROCm software stack 3900 executes on hardware 3909, which can include a GPU that supports ROCm, which was developed by AMD Corporation of Santa Clara, California.

[0406] In at least one embodiment, the application 3901 can perform similar functions as the application 3701 discussed above in conjunction with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 can perform similar functions as the runtime 3705 discussed above in conjunction with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 differ in that the system runtime 3905 is a language-agnostic runtime that implements the ROCr system runtime API 3904 and utilizes a Heterogeneous System Architecture (“HAS”) runtime API. In at least one embodiment, the HAS runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, execution control dispatching of kernels through the architecture, error handling, system and agent information, and runtime initialization and shutdown, among others. In at least one embodiment, the language runtime 3903 is an implementation of a language-specific runtime API 3902 layered on top of the ROCr system runtime API 3904 as compared to the system runtime 3905. In at least one embodiment, a language runtime API can include, without limitation, a Portable Compute Interface (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with functionally similar versions of CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes functions similar to the CUDA runtime API 3804 discussed above in conjunction with Figure 38

[0407] ​In at least one embodiment, thunk (ROCt) 3907 is an interface that can be used to interact with underlying ROCm drivers 3908. In at least one embodiment, ROCm drivers 3908 are ROCk drivers, which are a combination of AMDGPU drivers and HAS kernel drivers (amdkfd). In at least one embodiment, AMDGPU drivers are device kernel drivers for GPUs developed by AMD that perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, HAS kernel drivers are drivers that allow different types of processors to more efficiently share system resources via hardware features.

[0408] In at least one embodiment, various libraries (not shown) can be included in ROCm software stack 3900 above language runtime 3903 and provide similar functionality to CUDA libraries 3803 discussed above in connection with Figure 38 In at least one embodiment, various libraries can include, but are not limited to, math, deep learning, and / or other libraries such as a hipBLAS library that implements similar functions to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, etc.

[0409] Figure 40 FIG. 39 illustrates an OpenCL implementation of software stack 3700 in accordance with at least one embodiment Figure 37 In at least one embodiment, OpenCL software stack 4000 on which application 4001 can be launched includes an OpenCL framework 4005, an OpenCL runtime 4006, and drivers 4007. In at least one embodiment, OpenCL software stack 4000 executes on hardware 4008 that is not vendor-specific. In at least one embodiment, because device is supported by different vendors, specific OpenCL drivers can be required to interoperate with hardware from such vendors.

[0410] In at least one embodiment, application 4001, OpenCL runtime 4006, device kernel drivers 4007, and hardware 4008 can perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, application 4001 also inclu...

Claims

1. A data center cooling system, comprising: A modular unit attached to a server rack, the modular unit comprising a heat exchanger, a variable speed fan, and at least one flow controller, the modular unit being hot-replaceable from the server rack, the modular unit being fluidly coupled to a cold plate comprising microchannels, the at least one flow controller engaging the modular unit based at least in part on a first threshold cooling requirement of at least one computing device, passing a fluid through the microchannels to extract heat from the at least one computing device on the rack, and passing the fluid through the heat exchanger to enable the heat to be dissipated by forced air from the variable speed fan.

2. The data center cooling system of claim 1 , further comprising: At least one processor is configured to determine a temperature associated with the at least one computing device or the fluid and cause a change in the speed of the variable speed fan.

3. The data center cooling system of claim 1 , further comprising: The coils or plates forming the heat exchanger are used to enable the heat to be dissipated from the modular units.

4. The data center cooling system of claim 1 , further comprising: The cold plate has a first port for a first portion of the microchannels for supporting a coolant different from a second portion of the microchannels supporting a different fluid.

5. The data center cooling system of claim 1 , further comprising: At least one processor for receiving sensor input from a sensor associated with the at least one computing device or the fluid, the at least one processor for determining a change in the state of the fluid based in part on the sensor input and for causing or implementing one or more of the following: the at least one flow controller stopping the flow of the fluid or causing a change in the flow of the fluid, the at least one processor causing a change in the variable speed fan.

6. The data center cooling system of claim 5, further comprising: One or more neural networks for receiving the sensor input and inferring changes in the state of the fluid.

7. The data center cooling system of claim 5, further comprising: The at least one processor is configured to enable powering off the modular unit to enable replacement of the modular unit.

8. The data center cooling system of claim 1 , further comprising: At least one processor comprising one or more neural networks for determining a failure of a primary cooling circuit and the at least one processor for enabling the at least one flow controller to provide cooling from the modular unit.

9. The data center cooling system of claim 1 , further comprising: The cold plate is adapted to interface with the modular unit and an auxiliary cooling circuit associated with a primary cooling circuit and a cooling facility, the at least one flow controller being configured to prevent auxiliary coolant from a coolant distribution unit (CDU) from reaching the cold plate and to allow coolant associated with the modular unit to circulate between the cold plate and the heat exchanger.

10. The data center cooling system of claim 5, further comprising: The at least one flow controller engages the auxiliary cooling circuit based in part on a second threshold cooling requirement of the at least one computing device.

11. A processor comprising one or more circuits associated with at least one modular unit attached to a server rack, the at least one modular unit comprising a heat exchanger, a variable speed fan, and at least one flow controller, the modular unit being hot-replaceable from the server rack, the modular unit being fluidly coupled to a cold plate comprising microchannels, the one or more circuits being configured to cause the at least one flow controller to engage the modular unit based at least in part on a first threshold cooling requirement of at least one computing device, to pass fluid through the microchannels to extract heat from the at least one computing device on the rack, and to pass the fluid through the heat exchanger to enable the heat to be dissipated by forced air from the variable speed fan.

12. The processor of claim 11 , further comprising: An output for providing a signal to one or more of: the at least one flow controller for enabling fluid flow through the cold plate or the variable speed fan for achieving forced air at different speeds.

13. The processor of claim 11, further comprising: An input for receiving sensor input from a sensor associated with the at least one computing device or the fluid, the processor being configured to determine a change in the state of the fluid based in part on the sensor input and to cause or implement one or more of the following: the at least one flow controller stopping the flow of the fluid or causing a change in the flow of the fluid, the one or more circuits causing a change in the variable speed fan.

14. The processor of claim 13, further comprising: One or more neural networks for receiving the sensor input and inferring changes in the state of the fluid.

15. The processor of claim 11, further comprising: One or more neural networks for inferring a failure of the auxiliary cooling circuit or the primary cooling circuit, the one or more circuits for enabling the at least one flow controller to provide cooling from the modular unit.

16. A processor comprising one or more circuits associated with a modular unit, the modular unit comprising a heat exchanger, a variable speed fan, and at least one flow controller, the modular unit being hot-swappable from a rack and adapted to be fluidically coupled to a cold plate comprising microchannels, the one or more circuits configured to train one or more neural networks to infer from sensor inputs of sensors associated with at least one computing device on the rack or with the cold plate or fluid of the modular unit that a state of the fluid has changed, the processor configured to cause the at least one flow controller to engage the modular unit based at least in part on a first threshold cooling requirement of the at least one computing device, and the processor causing or implementing one or more actions comprising: At least one flow controller stops or changes the flow of the fluid, changes the speed of the variable speed fan, or replaces the modular unit.

17. The processor of claim 16, further comprising: An output that provides a signal to one or more of: the at least one flow controller for enabling the fluid to flow through the cold plate or the variable speed fan for achieving forced air at different speeds.

18. The processor of claim 16, further comprising: The one or more neural networks are configured to receive the sensor input and are trained to infer changes in the state of the fluid as part of an analysis of previous sensor input and previous states of the fluid.

19. The processor of claim 16, further comprising: An output provides a signal to the at least one flow controller, the at least one flow controller engaging an auxiliary cooling circuit based in part on a second threshold cooling requirement of the at least one computing device.

20. The processor of claim 16, further comprising: an input for receiving a sensor input associated with a temperature from the at least one computing device or the fluid, the one or more neural networks being trained to infer that a state of the fluid has changed based in part on the temperature and a previous temperature, and the one or more circuits being configured to cause a change in the speed of the variable speed fan based in part on the inference trained by the one or more neural networks.

21. A processor comprising one or more circuits comprising one or more neural networks for inferring from sensor inputs of sensors associated with at least one computing device on a rack or with a fluid in a modular unit or cold plate hot-swappable from the rack that a state of the fluid has changed, wherein The modular unit includes a heat exchanger, a variable speed fan, and at least one flow controller; and The one or more neural networks are further configured to cause the at least one flow controller to engage the modular unit based at least in part on a first threshold cooling requirement of the at least one computing device, and to cause or implement one or more actions, the one or more actions comprising: the at least one flow controller stopping or changing the flow of the fluid, changing the speed of the variable speed fan, or replacing the modular unit.

22. The processor of claim 21 , further comprising: An output that provides a signal to one or more of: the at least one flow controller for enabling the fluid to flow through the cold plate or the variable speed fan for achieving forced air at different speeds.

23. The processor of claim 21 , further comprising: The one or more neural networks are configured to receive the sensor input and infer a change in the state of the fluid as part of an analysis of previous sensor input and previous state of the fluid.

24. The processor of claim 21 , further comprising: An output that provides a signal to the at least one flow controller, the at least one flow controller being used to engage the modular unit based in part on a first threshold cooling requirement of the at least one computing device and to engage an auxiliary cooling loop based in part on a second threshold cooling requirement of the at least one computing device.

25. The processor of claim 21 , further comprising: an input for receiving the sensor input associated with a temperature of the fluid from the at least one computing device or the fluid, the one or more neural networks for inferring that a state of the fluid has changed based in part on the temperature and a previous temperature, and the one or more circuits for causing a change in the speed of the variable speed fan based in part on the inference made by the one or more neural networks.

26. A method for a data center cooling system, comprising: attaching a modular unit to a rack, the modular unit comprising a heat exchanger, a variable speed fan, and at least one flow controller, the modular unit being hot-replaceable from the rack; achieving fluid coupling between the modular unit and a cold plate comprising microchannels; enabling the at least one flow controller to engage the modular unit based at least in part on a first threshold cooling requirement of at least one computing device, passing fluid through the microchannels to extract heat from the at least one computing device on the rack, and passing the fluid through the heat exchanger; as well as This enables the heat to be dissipated by forced air from the variable speed fan.

27. The method of claim 26, further comprising: determining, by at least one processor, a temperature associated with the at least one computing device or the fluid; A change in the speed of the variable speed fan is caused.

28. The method of claim 26, further comprising: It is possible to implement coils or plates as the heat exchanger, which coils or plates enable the heat to be dissipated from the modular unit.

29. The method of claim 26, further comprising: The cold plate is implemented to include a first port for a first portion of the microchannels for supporting a coolant different from a second portion of the microchannels supporting a different fluid.

30. The method of claim 26, further comprising: implementing at least one processor for receiving sensor input from a sensor associated with the at least one computing device or the fluid; determining, by the at least one processor, a change in state of the fluid based in part on the sensor input; and Causing or implementing one or more of the following: the at least one flow controller stopping the flow of the fluid or causing a change in the flow of the fluid, the at least one processor causing a change in the variable speed fan.

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