A control method for multifunctional CPCI board

Abstract

The present invention discloses a multifunctional CPCI board and control method applied to a test, launch and control system, and relates to the field of aerospace test, launch and control technology. The multifunctional CPCI board includes an FPGA processing module, a CPCI bus module, a CAN bus module, an AD conversion module and a FLASH module. The FPGA processing module is used to complete the control of the PCI bus, the control of the Local bus, the CAN bus communication control, the analog quantity acquisition control and the state machine control through a bridge chip; the CPCI bus module is used to transfer data between the PCI bus and the Local bus through a bridge chip; the CAN bus module is used to realize the data transmission and reception between the FPGA processing module and the external device through a multi-channel CAN controller. The present invention can effectively meet the application requirements of aerospace test, launch and control systems.

Description

Technical Field

[0001] The present invention relates to the field of aerospace test, launch and control technology, and in particular to a multifunctional CPCI board card and a control method applied to a test, launch and control system. Background Art

[0002] Currently, in the application of aerospace test, launch and control system technology, boards or devices are usually used to realize CAN (Controller Area Network) bus communication, analog quantity acquisition, and equipment cumulative working time statistics functions respectively.

[0003] However, the existing methods have the following shortcomings: first, they are single-function and not universal; second, they are large in size and power consumption, and their applications are limited. Therefore, there is an urgent need for a multifunctional board based on CPCI (Compact Peripheral Component Interconnect) bus technology to meet the application requirements of aerospace test, launch and control systems. Summary of the invention

[0004] In view of the defects existing in the prior art, the purpose of the present invention is to provide a multifunctional CPCI board and control method applied to a test, launch and control system, which can effectively meet the application requirements of aerospace test, launch and control systems.

[0005] To achieve the above objectives, the present invention provides a multifunctional CPCI board card applied to a test, transmission and control system, comprising:

[0006] FPGA processing module, which is used to complete PCI bus control, Local bus control, CAN bus communication control, analog quantity acquisition control and state machine control through bridge chip;

[0007] CPCI bus module, which is used to transfer data between PCI bus and Local bus through bridge chip;

[0008] CAN bus module, which is used to realize data transmission and reception between FPGA processing module and external devices through multi-channel CAN controller;

[0009] The AD conversion module is used to select one channel of the multi-channel voltage signal in sequence through the relay switch and then send it to the isolation circuit;

[0010] The FLASH module is used to read the accumulated working time when the multi-function CPCI board is powered on, and store the read time;

[0011] Wherein, the Local bus is used to connect the FPGA processing module and the CPCI bus module, and the Local bus is used to connect the CPCI bus module and the computer mainboard.

[0012] Based on the above technical solutions,

[0013] The FPGA processing module is also used to implement code storage and loading functions by configuring the chip;

[0014] The FPGA processing module includes a clock circuit, and the clock circuit is used to provide a clock signal required for the operation of the FPGA processing module.

[0015] On the basis of the above technical solution, the CPCI bus module is also used to set the working mode of the Local bus and the matching impedance of the PCI bus through resistors, and to store the configuration information of the internal register of the bridge chip through EEPROM.

[0016] On the basis of the above technical solution, the CAN bus module is also used to realize level conversion between multiple CAN buses through a level conversion chip, and to realize CAN transceiver isolation function through an optocoupler isolation chip.

[0017] On the basis of the above technical solution, the AD conversion module is also used to send the isolated voltage signal to the operational amplifier follower circuit for processing, and send the signal processed by the operational amplifier follower circuit to the ADC conversion circuit to realize ADC conversion.

[0018] On the basis of the above technical solution, the multifunctional CPCI board also includes a power supply module, which is used to supply power to the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module and the FLASH module.

[0019] The present invention provides a control method for a multifunctional CPCI board, which is used to control the multifunctional CPCI board described above. The control method specifically comprises the following steps:

[0020] Receive data from the PCI bus to the Local bus based on a periodic polling method;

[0021] The data from the Local bus to the PCI bus is sent based on the interrupt mode.

[0022] On the basis of the above technical solution, the receiving of CAN data is also included, specifically:

[0023] Query the CAN status register to determine whether there is data in the receive register: if there is no data, continue to query whether there is data in the receive register in a loop; if there is data, query whether the FIFO is not full, and when the FIFO is not full, write the data in the receive register to the FIFO;

[0024] The loop queries whether the FIFO is in a non-empty state and whether the previous data of the left port of the DRAM interval has been read. If both are true, the data in the FIFO is read and written to the right port of the DRAM interval.

[0025] On the basis of the above technical solution, the CAN data transmission is also included, specifically:

[0026] Query the DRAM status register to determine whether there is data in the DRAM receiving area: if there is no data, continue to cyclically query whether there is data in the DRAM receiving area; if there is data, receive the data from the PCI bus to the Local bus, and query whether the FIFO is not full. When the FIFO is not full, read the data from the right port of the DRAM interval and write the read data into the FIFO;

[0027] Query the CAN status register to determine whether there is data in the transmit register: if there is data, continue to query in a loop whether there is data in the transmit register; if there is no data, query whether the FIFO is in a non-empty state, and when the FIFO is in a non-empty state, read the data in the FIFO and write the read data to the CAN transmit register to send data to the external device.

[0028] On the basis of the above technical solution, the acquisition of ADC data is also included, specifically:

[0029] Through relays, multiple analog signals are realized in a certain cycle and one channel is selected in sequence for collection;

[0030] The collected data is filtered and sent to the right port of the DRAM data area, and the left port of the DRAM data area provides the data to the computer mainboard for processing.

[0031] Compared with the prior art, the advantages of the present invention are: through the setting of FPGA processing module, CPCI bus module, CAN bus module, AD conversion module, FLASH module and power supply module, the whole control process is concise and clear, with strong real-time performance, which is conducive to improving the intelligence and integration of the test, launch and control system, and effectively meeting the application requirements of the aerospace test, launch and control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 This is a schematic diagram of the structure of a multifunctional CPCI board card used in a measurement, transmission and control system according to an embodiment of the present invention;

[0034] Figure 2 The present invention is a flowchart of a control method of a multifunctional CPCI board in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0036] See also Figure 1 As shown, a multifunctional CPCI board card applied to a measurement, transmission and control system provided by an embodiment of the present invention comprises an FPGA (Field Programmable Gate Array) processing module, a CPCI bus module, a CAN (Controller Area Network) bus module, an AD (Analog-to-Digital) conversion module, a FLASH (Flash memory) module and a power supply module. The Local bus is used to connect the FPGA processing module and the CPCI bus module, and the Local bus is used to connect the CPCI bus module and a computer mainboard. The multifunctional CPCI board card of the present invention is a device that organically combines CPCI bus communication, CAN bus communication, analog quantity acquisition and equipment accumulated working time.

[0037] The multifunctional board provided by the embodiment of the present invention is designed with FPGA+PCI bridge chip as the core architecture, exchanges information with the computer mainboard through CPCI bus, and transmits data with multiple other devices through CAN bus. The implementation method is to process these data by scheduling multiple tasks in parallel, wherein the response level of each task is reasonably set according to the importance of the device and the frequency of communication. The corresponding control operation can be executed according to the control instruction of the computer mainboard.

[0038] In the embodiment of the present invention, the FPGA processing module is used to complete the control of the PCI (Peripheral Component Interconnect) bus, the control of the Local bus, the CAN bus communication control, the analog quantity acquisition control and the state machine control through the bridge chip. The FPGA processing module is also used to realize the code storage and loading functions through the configuration chip; the FPGA processing module includes a clock circuit, and the clock circuit is used to provide the clock signal required for the operation of the FPGA processing module. The FPGA processing module is also used to realize the code storage and loading functions through the configuration chip.

[0039] Specifically, the FPGA processing module is connected to the CAN bus module to implement multi-channel CAN bus logic, the FPGA processing module is connected to the FLASH module to implement FLASH read and write logic, the FPGA processing module is connected to the AD conversion module to implement multi-channel AD acquisition logic, the FPGA processing module is connected to the Local bus interface in the CPCI bus module to implement Local bus logic, and the FPGA processing module is connected to the PCI bus interface in the CPCI bus module to implement PCI bus logic. The FPGA processing module also includes FIFO (First Input First Output), DRAM (Dynamic Random Access Memory), FPGA circuit and configuration circuit.

[0040] In an embodiment of the present invention, the CPCI bus module is used to transfer data between the PCI bus and the Local bus through a bridge chip; the CPCI bus module is also used to set the working mode of the Local bus and the matching impedance of the PCI bus through resistors, and to store the configuration information of the internal registers of the bridge chip through EEPROM (Electrically Erasable Programmable read only memory).

[0041] The CPCI bus module specifically includes an EEPROM circuit and a PCI bridge circuit, wherein the PCI bridge circuit includes a Local bus interface, a PCI bus interface and a serial EEPROM configuration register. The PCI bridge circuit is also used to implement corresponding control logic.

[0042] In an embodiment of the present invention, the CAN bus module is used to realize data transmission and reception between the FPGA processing module and the external device through a multi-channel CAN controller; the CAN bus module is also used to realize level conversion between multiple CAN buses through a level conversion chip, and realize the CAN transmission and reception isolation function through an optocoupler isolation chip. The CAN bus module is also used to remotely switch the bus resistance matching function through a relay. Specifically, the CAN bus module includes a CAN controller and a CAN transceiver, and the CAN transceiver is used to interact with external devices.

[0043] In an embodiment of the present invention, the AD conversion module is used to select one channel of the multi-channel voltage signal in sequence through a relay switch and then send it to the isolation circuit; the AD conversion module is also used to send the isolated voltage signal to the operational amplifier follower circuit for processing, and send the signal processed by the operational amplifier follower circuit to the ADC (analogue-to-digital conversion) conversion circuit to achieve ADC conversion.

[0044] In the embodiment of the present invention, the FLASH module is used to read the accumulated working time when the multifunctional CPCI board is powered on, and store the read time.

[0045] In the embodiment of the present invention, the power module is used to power the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module and the FLASH module. Specifically, the power module converts the input 5V into the voltages 3.3V, 1.8V, 1.2V, and 1.0V required for the board to work through the switching power chip, and converts the input 5V into the voltage 2.5V required for the board to work through the linear power chip. The power module is also used to convert the input 5V into the voltage ±15V required for the AD conversion module to work through the isolated non-regulated DC / DC converter chip, and is also used to convert the input 5V voltage into the isolated voltage 5V required for the CAN bus module to work through the isolated power chip.

[0046] The multifunctional CPCI board applied to the test, launch and control system of the embodiment of the present invention makes the entire control process concise and clear through the configuration of the FPGA processing module, CPCI bus module, CAN bus module, AD conversion module, FLASH module and power supply module, and has strong real-time performance, which is conducive to improving the intelligence and integration of the test, launch and control system and effectively meeting the application requirements of the aerospace test, launch and control system.

[0047] See also Figure 2 As shown, a control method of a multifunctional CPCI board provided by an embodiment of the present invention is used to control the multifunctional CPCI board described above. The control method specifically comprises the following steps:

[0048] S1: Receive data from the PCI bus to the Local bus based on a periodic polling method;

[0049] S2: Sending data from the Local bus to the PCI bus based on the interrupt mode.

[0050] The software uses the base address as the offset to allocate multiple DRAM areas for receiving and sending local bus data. Each DRAM area includes 32 bits*2 power data. When receiving local bus data, the DRAM is written; when sending local bus data, the DRAM is read.

[0051] In the embodiment of the present invention, the receiving of CAN data is also included, specifically:

[0052] Query the CAN status register to determine whether there is data in the receive register: if there is no data, continue to query whether there is data in the receive register in a loop; if there is data, query whether the FIFO is not full, and when the FIFO is not full, write the data in the receive register to the FIFO;

[0053] The loop queries whether the FIFO is in a non-empty state and whether the previous data of the left port of the DRAM interval has been read. If both are true, the data in the FIFO is read and the read data is written to the right port of the DRAM interval, and the receive interrupt is set to valid.

[0054] In the embodiment of the present invention, the sending of CAN data is specifically as follows:

[0055] Query the DRAM status register to determine whether there is data in the DRAM receiving area: if there is no data, continue to cyclically query whether there is data in the DRAM receiving area; if there is data, receive the data from the PCI bus to the Local bus, and query whether the FIFO is not full. When the FIFO is not full, read the data from the right port of the DRAM interval and write the read data into the FIFO;

[0056] Query the CAN status register to determine whether there is data in the transmit register: if there is data, continue to query in a loop whether there is data in the transmit register; if there is no data, query whether the FIFO is in a non-empty state, and when the FIFO is in a non-empty state, read the data in the FIFO and write the read data to the CAN transmit register to send data to the external device.

[0057] In the embodiment of the present invention, the collection of ADC data is specifically as follows:

[0058] Through relays, multiple analog signals are realized in a certain cycle and one channel is selected in sequence for collection;

[0059] The collected data is filtered and sent to the right port of the DRAM data area, and the left port of the DRAM data area provides the data to the computer mainboard for processing.

[0060] In the embodiment of the present invention, the FLASH data reading and writing includes: first, when the board is powered on, the software reads the cumulative working time of the last power failure from the two sectors of the FLASH on the board; compares the two data, and the one with the largest time is the cumulative working time reference value. Secondly, the cumulative working time reference value is accumulated to update the cumulative working time, and a ping-pong strategy is used to write one of the two sectors of the FLASH once every minute, and the updated cumulative working time is sent to the right port of the DRAM data area, and the left port of the DRAM data area is sent to the computer motherboard and then displayed by other devices.

[0061] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

[0062] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

Claims

1. A control method for a multifunctional CPCI board, used for controlling a multifunctional CPCI board applied to a measurement, transmission and control system, characterized in that: The control method specifically comprises the following steps: Receive data from the PCI bus to the Local bus based on a periodic polling method; Sending data from Local bus to PCI bus based on interrupt mode; Among them, the collection of ADC data is specifically as follows: Through relays, multiple analog signals are realized in a certain cycle and one channel is selected in sequence for collection; The collected data is filtered and sent to the right port of the DRAM data area, and the left port of the DRAM data area provides the data to the computer mainboard for processing; The multifunctional CPCI board used in the test, transmission and control system includes: FPGA processing module, which is used to complete PCI bus control, Local bus control, CAN bus communication control, analog quantity acquisition control and state machine control through bridge chip; CPCI bus module, which is used to transfer data between PCI bus and Local bus through bridge chip; CAN bus module, which is used to realize data transmission and reception between FPGA processing module and external devices through multi-channel CAN controller; The AD conversion module is used to select one channel of the multi-channel voltage signal in sequence through the relay switch and then send it to the isolation circuit; The FLASH module is used to read the accumulated working time when the multi-function CPCI board is powered on, and store the read time; Wherein, the Local bus is used to connect the FPGA processing module and the CPCI bus module, and the Local bus is used to connect the CPCI bus module and the computer mainboard; Among them, the FPGA processing module is also used to realize the code storage and loading functions through the configuration chip; the FPGA processing module includes a clock circuit, and the clock circuit is used to provide the clock signal required for the operation of the FPGA processing module; the CPCI bus module is also used to set the working mode of the Local bus and the matching impedance of the PCI bus through a resistor, and to store the configuration information of the internal register of the bridge chip through the EEPROM; the CAN bus module is also used to realize the level conversion between multiple CAN buses through a level conversion chip, and to realize the CAN transceiver isolation function through an optocoupler isolation chip; the AD conversion module is also used to send the isolated voltage signal to the operational amplifier follower circuit for processing, and to send the signal processed by the operational amplifier follower circuit to the ADC conversion circuit to realize ADC conversion; the multi-functional CPCI board also includes a power supply module, and the power supply module is used to power the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module and the FLASH module.

2. A control method for a multifunctional CPCI board as claimed in claim 1, characterized in that: It also includes the reception of CAN data, specifically: Query the CAN status register to determine whether there is data in the receive register: if there is no data, continue to query whether there is data in the receive register in a loop; if there is data, query whether the FIFO is not full, and when the FIFO is not full, write the data in the receive register to the FIFO; The loop queries whether the FIFO is in a non-empty state and whether the previous data of the left port of the DRAM interval has been read. If both are true, the data in the FIFO is read and written to the right port of the DRAM interval.

3. The control method of a multifunctional CPCI board as claimed in claim 1, characterized in that: It also includes the sending of CAN data, specifically: Query the DRAM status register to determine whether there is data in the DRAM receiving area: if there is no data, continue to cyclically query whether there is data in the DRAM receiving area; If there is data, the data from the PCI bus to the Local bus is received, and the FIFO is checked to see if it is not full. When the FIFO is not full, the data from the right port of the DRAM interval is read and the read data is written into the FIFO. Query the CAN status register to determine whether there is data in the transmit register: if there is data, continue to query in a loop whether there is data in the transmit register; if there is no data, query whether the FIFO is in a non-empty state, and when the FIFO is in a non-empty state, read the data in the FIFO and write the read data to the CAN transmit register to send data to the external device.

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