Single event upset resistant low power SRAM storage unit circuit and memory

Abstract

The present invention discloses a low-power SRAM memory cell circuit and memory that are resistant to single-event upsets. The circuit includes: seven NMOS transistors and four PMOS transistors, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor form a Schmitt trigger; the fourth PMOS transistor and the fourth NMOS transistor form an inverter; the output of the Schmitt trigger is connected to the input of the inverter, and the output of the inverter is connected to the input of the Schmitt trigger; the drain of the third PMOS transistor MP3 and the source of the third NMOS transistor forming the Schmitt trigger are connected to the output of the inverter. This memory cell circuit allows the drain of the second PMOS transistor, which serves as the first storage node Q, and the drain of the fourth PMOS transistor, which serves as the second storage node Qb, to form interlocked nodes, thereby improving the performance against single-event upsets. The circuit structure is relatively simple, power consumption is low, and manufacturing is also easy.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an SRAM storage unit circuit and an SRAM memory. Background Art

[0002] As CMOS transistor sizes reach submicron scale, when high-energy particles strike sensitive nodes in high-speed static random-access memory (SRAM) memory cells, their energy is deposited in the semiconductor material along their path, generating electron-hole pairs. These electron-hole pairs are effectively collected at sensitive nodes by the drift of the electric field, causing charge accumulation and generating transient voltage pulses. When the particle energy is high enough and the number of electron-hole pairs generated is sufficient, the logic value of the SRAM memory cell will be flipped, a phenomenon known as a single-event upset (SEU). Although SEUs are non-destructive events and there are many error detection and correction methods, the increased probability of SEUs can still pose serious problems for devices using large-scale SRAM.

[0003] Currently, in integrated circuit design, the commonly used SRAM unit is the traditional 6-tube unit structure, such as Figure 1 Figure 1 shows the circuit structure of a traditional 6-transistor SRAM memory cell. This 6-transistor SRAM cell structure not only consumes high write power but is also prone to single-event upsets (SEUs). Traditional SRAM hardening methods, such as DICE circuits and triple-mode redundant circuits, have been used to improve SRAM's resistance to SEUs. However, these measures suffer from complex circuit logic structures. While they can reduce the impact of collected charge, they also increase power consumption. Therefore, improving the inherent radiation resistance of SRAM memory cells while reducing their power consumption is a crucial and challenging task.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a low-power SRAM storage unit circuit and memory that are resistant to single-event upsets, which can reduce their power consumption while improving single-event upset performance, thereby solving the above-mentioned technical problems existing in the prior art.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] An embodiment of the present invention provides a low-power SRAM memory cell circuit resistant to single event upsets, comprising:

[0008] Seven NMOS tubes and four PMOS tubes; among them,

[0009] The gate of the first NMOS transistor MN1, the gate of the first PMOS transistor MP1, the source of the seventh NMOS transistor MN7 and the source of the fifth NMOS transistor MN5 are electrically connected;

[0010] The gate of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2, the drain of the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4, the source of the third NMOS transistor MN3, the source of the third PMOS transistor MP3 and the drain of the seventh NMOS transistor MN7 are electrically connected;

[0011] The drain of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3 are electrically connected;

[0012] The drain of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 and the drain of the third PMOS transistor MP3 are electrically connected;

[0013] The drain of the second NMOS transistor MN2, the drain of the second PMOS transistor MP2, the gate of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, the gate of the fourth NMOS transistor MN4, the gate of the fourth PMOS transistor MP4, and the source of the sixth NMOS transistor MN6 are electrically connected;

[0014] The gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6 are both electrically connected to the word line WL;

[0015] The gate of the seventh NMOS transistor MN7 is electrically connected to the write control line CL;

[0016] The drain of the fifth NMOS transistor MN5 is electrically connected to the second bit line BLB;

[0017] The drain of the sixth NMOS transistor MN6 is electrically connected to the first bit line BL;

[0018] The source of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 and the body terminals of all NMOS transistors are grounded GND;

[0019] The source of the first PMOS transistor MP1 , the source of the fourth PMOS transistor MP4 and the body terminals of all PMOS transistors are connected to a power source VDD.

[0020] An embodiment of the present invention further provides a low-power SRAM memory resistant to single event upsets, the storage circuit of which adopts the low-power SRAM storage unit circuit resistant to single event upsets described in the present invention.

[0021] Compared with the prior art, the low-power SRAM memory cell circuit and memory resistant to single event upset provided by the present invention have the following beneficial effects:

[0022] The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 form a Schmitt trigger; the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 form an inverter; the output of the Schmitt trigger is connected to the input of the inverter, and the output of the inverter is connected to the input of the Schmitt trigger; the drain of the third PMOS transistor MP3 and the source of the third NMOS transistor MN3 forming the Schmitt trigger are connected to the output of the inverter. This makes the drain of the second PMOS transistor MP2, which serves as the first storage node Q, and the drain of the fourth PMOS transistor MP4, which serves as the second storage node Qb, interlocked, thereby improving the performance against single-event upsets. Furthermore, the circuit structure is relatively simple, power consumption is low, and manufacturing is easy. This effectively improves the stability of the memory and maintains low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 This is a schematic diagram of the circuit structure of a 6-transistor SRAM storage unit provided by the prior art.

[0025] Figure 2 A schematic diagram of the circuit structure of a low-power SRAM storage unit resistant to single event upsets provided by an embodiment of the present invention.

[0026] Figure 3 This is a waveform diagram of the read 0 operation of the low-power SRAM memory cell circuit resistant to single event upset provided by an embodiment of the present invention.

[0027] Figure 4 This is a waveform diagram of a read 1 operation of a low-power SRAM memory cell circuit resistant to single event upsets provided by an embodiment of the present invention.

[0028] Figure 5 This is a write operation waveform diagram of a low-power SRAM memory cell circuit resistant to single event upsets provided by an embodiment of the present invention.

[0029] Figure 6A comparison chart of the noise margin maintained by the low-power SRAM memory cell circuit resistant to single-event upsets provided by an embodiment of the present invention and the existing common 6-transistor SRAM memory cell circuit.

[0030] Figure 7 This is a comparison chart of the write noise tolerance of the low-power SRAM memory cell circuit resistant to single-event upsets provided by an embodiment of the present invention and the existing ordinary 6-transistor SRAM memory cell circuit. DETAILED DESCRIPTION

[0031] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the specific content of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments, and do not constitute a limitation of the present invention. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0032] First, the following terms may be used in this article:

[0033] The term “and / or” means that either or both of them can be realized at the same time. For example, X and / or Y includes both “X” or “Y” and “X and Y”.

[0034] The terms "include," "comprises," "contains," "has," or other similar expressions should be interpreted as non-exclusive. For example, "including certain technical features (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products, or manufactured articles, etc.) should be interpreted as including not only the technical features explicitly listed, but also other technical features known in the art that are not explicitly listed.

[0035] The term "consisting of" excludes any technical features not explicitly listed. If used in a claim, this term renders the claim closed, excluding any technical features other than those explicitly listed, except for conventional impurities associated with them. If this term appears only in a clause of a claim, it limits only the elements explicitly listed in that clause; elements listed in other clauses are not excluded from the claim as a whole.

[0036] Unless otherwise specified or limited, the terms "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this document based on specific circumstances.

[0037] When concentration, temperature, pressure, size or other parameters are expressed in the form of a numerical range, the numerical range should be understood to specifically disclose all ranges formed by the pairing of any upper limit, lower limit, or preferred value within the numerical range, regardless of whether the range is explicitly stated. For example, if a numerical range of "2 to 8" is stated, the numerical range should be interpreted as including ranges of "2 to 7," "2 to 6," "5 to 7," "3 to 4 and 6 to 7," "3 to 5 and 7," "2 and 5 to 7," etc. Unless otherwise specified, the numerical ranges stated herein include both their endpoints and all integers and fractions within the numerical range.

[0038] The terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings and are only for the convenience and simplification of description, and do not explicitly or implicitly indicate that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as a limitation to this document.

[0039] The following describes in detail the SRAM memory cell circuit structure and memory with low power consumption and SEU resistance provided by the present invention. Any details not described in detail in the embodiments of the present invention are prior art known to those skilled in the art. In the embodiments of the present invention, where specific conditions are not specified, the procedures were performed according to conventional conditions in the art or the conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of the present invention, where the manufacturer is not specified, are all commercially available conventional products.

[0040] like Figure 2 As shown, an embodiment of the present invention provides a low-power SRAM storage cell circuit that is resistant to single-event upsets, including:

[0041] Seven NMOS tubes and four PMOS tubes; among them,

[0042] The gate of the first NMOS transistor MN1, the gate of the first PMOS transistor MP1, the source of the seventh NMOS transistor MN7 and the source of the fifth NMOS transistor MN5 are electrically connected;

[0043] The gate of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2, the drain of the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4, the source of the third NMOS transistor MN3, the source of the third PMOS transistor MP3 and the drain of the seventh NMOS transistor MN7 are electrically connected;

[0044] The drain of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3 are electrically connected;

[0045] The drain of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 and the drain of the third PMOS transistor MP3 are electrically connected;

[0046] The drain of the second NMOS transistor MN2, the drain of the second PMOS transistor MP2, the gate of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, the gate of the fourth NMOS transistor MN4, the gate of the fourth PMOS transistor MP4, and the source of the sixth NMOS transistor MN6 are electrically connected;

[0047] The gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6 are both electrically connected to the word line WL;

[0048] The gate of the seventh NMOS transistor MN7 is electrically connected to the write control line CL;

[0049] The drain of the fifth NMOS transistor MN5 is electrically connected to the first bit line BLB;

[0050] The drain of the sixth NMOS transistor MN6 is electrically connected to the second bit line BL;

[0051] The source of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 and the body terminals of all NMOS transistors are grounded GND;

[0052] The source of the first PMOS transistor MP1 , the source of the fourth PMOS transistor MP4 and the body terminals of all PMOS transistors are connected to a power source VDD.

[0053] The drain of the second PMOS transistor MP2 is the first storage node Q; the drain of the fourth PMOS transistor MP4 is the second storage node Qb;

[0054] The first storage node Q and the second storage node Qb are interlocked nodes.

[0055] An SRAM memory cell circuit according to an embodiment of the present invention is an 11-transistor SRAM memory cell circuit. A first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3 form a Schmitt trigger. A fourth PMOS transistor MP4 and a fourth NMOS transistor MN4 form an inverter. The output of the Schmitt trigger is connected to the input of the inverter, and the output of the inverter is connected to the input of the Schmitt trigger. The drain of the third PMOS transistor MP3 and the source of the third NMOS transistor MN3 forming the Schmitt trigger are connected to the output of the inverter. This interlocks the drain of the second PMOS transistor MP2, which serves as the first storage node Q, and the drain of the fourth PMOS transistor MP4, which serves as the second storage node Qb, to form an interlocked node. This improves single-event upset resistance. Furthermore, the circuit structure is relatively simple, power consumption is low, and manufacturing is easy. This effectively improves memory stability and maintains low power consumption.

[0056] Embodiments of the present invention also provide a low-power SRAM memory that is resistant to single-event upsets, including a low-power SRAM memory cell circuit resistant to single-event upsets. The SRAM memory cell circuit of the present invention improves single-event upset resistance while reducing power consumption. Furthermore, the circuit structure is relatively simple, ensuring stable memory performance and low power consumption.

[0057] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the low-power SRAM storage unit circuit and memory resistant to single-event upset provided by the embodiments of the present invention are described in detail below with reference to specific embodiments.

[0058] Example

[0059] like Figure 2 As shown, an embodiment of the present invention provides an SRAM memory cell circuit, which is a low-power SRAM memory cell circuit that is resistant to single-event upsets, including:

[0060] Seven NMOS transistors, namely: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7;

[0061] Four PMOS transistors, namely: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a fourth PMOS transistor MP4;

[0062] The gate of the first NMOS transistor MN1, the gate of the first PMOS transistor MP1, the source of the seventh NMOS transistor MN7 and the source of the fifth NMOS transistor MN5 are electrically connected;

[0063] The gate of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2, the drain of the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4, the source of the third NMOS transistor MN3, the source of the third PMOS transistor MP3 and the drain of the seventh NMOS transistor MN7 are electrically connected;

[0064] The drain of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3 are electrically connected;

[0065] The drain of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 and the drain of the third PMOS transistor MP3 are electrically connected;

[0066] The drain of the second NMOS transistor MN2, the drain of the second PMOS transistor MP2, the gate of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, the gate of the fourth NMOS transistor MN4, the gate of the fourth PMOS transistor MP4, and the source of the sixth NMOS transistor MN6 are electrically connected;

[0067] The gate of the fifth NMOS transistor MN5 is electrically connected to the gate of the sixth NMOS transistor MN6 and is also electrically connected to the word line WL;

[0068] The gate of the seventh NMOS transistor MN7 is electrically connected to the read control line CL;

[0069] The drain of the fifth NMOS transistor MN5 is electrically connected to the first bit line BLB;

[0070] The drain of the sixth NMOS transistor MN6 is electrically connected to the second bit line BL;

[0071] The source of the first NMOS transistor MN1 and the source of the fourth NMOS transistor MN4 are grounded GND;

[0072] The source of the first PMOS transistor MP1 and the source of the fourth PMOS transistor MP4 are connected to the power supply VDD;

[0073] The body terminals of all NMOS tubes are grounded GND;

[0074] The body terminals of all PMOS tubes are connected to the power supply voltage VDD.

[0075] Figure 2 The drain of the second PMOS transistor MP2 is the first storage node Q; the drain of the fourth PMOS transistor MP4 is the second storage node Qb.

[0076] The following combination Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The working principle of the 11-transistor SRAM storage unit circuit (hereinafter referred to as a unit for convenience of description) provided by the embodiment of the present invention is specifically described as follows:

[0077] (1) Read operation:

[0078] Before a read operation, the second bit line BL and the first bit line BLB are precharged to a high level, while the word line WL remains at a low level and the control line CL remains at a high level. Assuming that the logic value stored in the cell at this time is 1, the first storage node Q is at a high level and the second storage node Qb is at a low level. When the read operation begins, the control line CL remains at a high level and the voltage of the word line WL is increased, turning on the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6. At this time, since the first storage node Q is at a high level, the voltage on the second bit line BL remains almost unchanged. Since the second storage node Qb is at a low level, the voltage on the first bit line BLB is slowly discharged until the voltage difference between the second bit line BL and the first bit line BLB can be detected by the sense amplifier. Figure 3 、 Figure 4 The waveform diagrams of the read 0 and read 1 operations of the 11-transistor SRAM storage unit circuit of this embodiment are respectively shown.

[0079] (2) Write operation:

[0080] For a write operation, it is assumed that the logic stored in the cell before the write operation is performed is 0, that is, the first storage node Q is at a low level, the second storage node Qb is at a high level, and logic 1 is to be written; therefore, the second bit line BL is first set to a high level and BLB is set to a low level, and the control line CL is set to a low level. At this time, the inverter to the gate of the first NMOS transistor MN1 and the first PMOS transistor MP1 is disconnected, and the first bit line BLB is connected to the gate of the first NMOS transistor MN1 and the first PMOS transistor MP1 through the fifth NMOS transistor MN5. The gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are in a high-resistance state and their voltages are still high due to the effect of parasitic capacitance; the voltage of the word line WL is increased so that the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on; at this time, since the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are connected to the first bit line BLB only through the fifth NMOS transistor MN5, the voltages of the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 become low, and the path from the first storage node Q to the ground GND is disconnected; since the first storage node Q is connected to BL through the sixth NMOS transistor MN6, the first storage node Q is quickly charged to a high level; then the fourth PMOS transistor MP4 is turned off, the fourth NMOS transistor MMN4 is turned on, and the second storage node Qb is pulled down to a low level; since the second storage node Qb is at a low level, the second PMOS transistor MP2 is turned on, and the second NMOS transistor MN2 is turned off; at this time, the first storage node Q is connected to the power supply VDD through the first PMOS transistor MP1 and the second PMOS transistor MP2, thus completing the write-1 operation.

[0081] When writing a low level 0, if the first storage node Q is originally at a high level and the second storage node Qb is at a low level, the second bit line BL is first set to a high level, the first bit line BLB is set to a low level, and the control line CL is set to a low level. At this time, the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are disconnected from the inverter, and the first bit line BLB is connected to the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 through the fifth NMOS transistor MN5. The gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are in a high-impedance state and their voltages remain low due to the effect of parasitic capacitance. The voltage of the word line WL is increased to turn on the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6. At this time, due to the first NMOS transistor MN1 The gate of the first PMOS transistor MP1 is connected to the first bit line BLB only through the fifth NMOS transistor MN5. The voltages of the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 become high, and the path from the first storage node Q to the power supply is disconnected. Since the first storage node Q is connected to the second bit line BL through the sixth NMOS transistor MN6, the first storage node Q is quickly charged to a low level. Then, the fourth PMOS transistor MP4 is turned on, the fourth NMOS transistor MMN4 is turned off, and the second storage node Qb is pulled up to a high level. Since the second storage node Qb is at a high level, the second PMOS transistor MP2 is turned off, and the second NMOS transistor MN2 is turned on. At this time, the first storage node Q is grounded to GND through the first NMOS transistor MN1 and the second NMOS transistor MN2, completing the write-0 operation. Figure 5 The waveform diagram of the write operation of the 11-transistor SRAM storage unit circuit of this embodiment is shown.

[0082] Because there is a read control line, the feedback of the circuit is disconnected before the write operation, which can reduce the write power consumption of the circuit. Since the branches of the circuit are consistent with the existing ordinary SRAM storage cell circuit, the static power consumption is not much different.

[0083] (3) Single event upset:

[0084] The SRAM unit circuit implemented in the present invention is composed of four PMOS transistors MP1 to MP4 and seven NMOS transistors MN1 to MN7; these MOS transistors form an inverter and are interlocked with an inverter based on a Schmitt trigger, providing two interlocked nodes, a first storage node Q and a second storage node Qb, for data storage. The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 form a Schmitt trigger; the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 form an inverter; the output of the Schmitt trigger is connected to the input of the inverter, and the output of the inverter is connected to the input of the Schmitt trigger; the drain of the third PMOS transistor MP3 and the source of the third NMOS transistor MN3 forming the Schmitt trigger are connected to the output of the inverter; when the second storage node Qb=1, the first storage node Q=0, MP3 is turned on, and the drain of the third PMOS transistor MP3 is connected to the second storage node Qb, which is equivalent to being connected to the power supply VDD through the fourth PMOS transistor MP4, while the third NMOS transistor MN3 is turned off; when high-energy particles bombard the second storage node Qb, which is a sensitive node, the second storage node Qb jumps, and the flip occurs, so that the first storage node Q and the second storage node Qb are both 0. In this case, such a connection can function as a Schmitt trigger. Changes in the second storage node Qb increase the threshold required for the first storage node Q to flip from 0 to 1, making it less likely for the first storage node Q to flip, thereby achieving SEU robustness. When the second storage node Qb = 0, the first storage node Q = 1, and MN3 is turned on. The drain of the third NMOS transistor MN3 is connected to Qb, which is equivalent to being connected to ground GND through the fourth NMOS transistor MN4, while the third PMOS transistor MP3 is turned off. When high-energy particles bombard the sensitive second storage node Qb, the second storage node Qb jumps, causing the first and second storage nodes Q and Qb to be simultaneously 1. This connection can function as a Schmitt trigger. Changes in the second storage node Qb increase the threshold required for the first storage node Q to flip from 1 to 0, thereby achieving SEU robustness. When high-energy particles bombard the first storage node Q, due to its large parasitic capacitance, although the flip threshold of this node does not increase significantly, it can still be relied upon for SEU robustness.

[0085] In another embodiment, an existing common 6-transistor SRAM memory cell circuit ( Figure 6 、 7 6T in (structure as Figure 1 ) and the 11-tube SRAM storage unit circuit of the present invention ( Figure 6 、7 11T in (structure as Figure 2 ) to compare performance. In order to facilitate comparison, the Figure 1 The size and Figure 2 The inverter MN4 tube of the 11-tube SRAM storage unit circuit has the same size. Figure 1 The size of the MP1 and MP2 tubes of the 6-tube SRAM memory cell circuit and Figure 2 The inverter MP4 tube of the 11-tube SRAM memory cell circuit has the same size as the Figure 1 The access tubes MN3 and MN4 of the existing common 6-tube SRAM storage unit circuit and Figure 2 The access tubes MN5 and MN6 of the 11-tube SRAM memory cell circuit are the same size. Figure 6 The hold noise margins obtained by simulation of the 11-transistor SRAM memory cell circuit of this embodiment and the common 6-transistor SRAM memory cell circuit are shown. The length of the diagonal of the dotted square is the value of the noise margin. It can be seen that the hold noise margin is improved to a certain extent, that is, the flip threshold is improved. Figure 7 This figure shows a comparison of the write noise margins of the 11-transistor SRAM memory cell circuit of this embodiment and a conventional 6-transistor SRAM memory cell circuit. The length of the diagonal line of the dashed square represents the noise margin. It can be seen that the write noise margin of the 11-transistor SRAM memory cell circuit of this embodiment is twice that of the conventional 6-transistor SRAM memory cell circuit. Table 1 shows a comparison of the critical charge and power consumption of the two circuits.

[0086] Table 1 Comparison of critical charge and power consumption

[0087]

[0088]

[0089] In summary, the SRAM memory cell circuit of the embodiment of the present invention not only reduces power consumption but also significantly improves SEU resistance compared to the existing 6-transistor SRAM memory cell circuit, and can effectively ensure the power consumption and stability of the memory.

[0090] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art.

Claims

1. A low-power SRAM memory cell circuit resistant to single event upset, characterized in that: include: Seven NMOS tubes and four PMOS tubes; among them, The gate of the first NMOS transistor MN1, the gate of the first PMOS transistor MP1, the source of the seventh NMOS transistor MN7 and the source of the fifth NMOS transistor MN5 are electrically connected; The gate of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2, the drain of the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4, the source of the third NMOS transistor MN3, the source of the third PMOS transistor MP3 and the drain of the seventh NMOS transistor MN7 are electrically connected; The drain of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3 are electrically connected; The drain of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 and the drain of the third PMOS transistor MP3 are electrically connected; The drain of the second NMOS transistor MN2, the drain of the second PMOS transistor MP2, the gate of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, the gate of the fourth NMOS transistor MN4, the gate of the fourth PMOS transistor MP4, and the source of the sixth NMOS transistor MN6 are electrically connected; The gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6 are both electrically connected to the word line WL; The gate of the seventh NMOS transistor MN7 is electrically connected to the write control line CL; The drain of the fifth NMOS transistor MN5 is electrically connected to the first bit line BLB; The drain of the sixth NMOS transistor MN6 is electrically connected to the second bit line BL; The source of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 and the body terminals of all NMOS transistors are grounded GND; The source of the first PMOS transistor MP1 , the source of the fourth PMOS transistor MP4 and the body terminals of all PMOS transistors are connected to a power source VDD.

2. The low-power SRAM storage unit circuit resistant to single event upset according to claim 1, characterized in that: The drain of the second PMOS transistor MP2 is the first storage node Q; the drain of the fourth PMOS transistor MP4 is the second storage node Qb; The first storage node Q and the second storage node Qb are interlocked nodes.

3. A low-power SRAM memory resistant to single event upset, characterized in that: The storage circuit adopts the single-particle upset-resistant low-power SRAM storage unit circuit described in claim 1 or 2.

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