Table management method, memory storage device, and memory control circuit unit

Abstract

The present invention provides a table management method, a memory storage device, and a memory control circuit unit. The method includes: storing a plurality of table groups, wherein each of the plurality of table groups includes a plurality of voltage management tables; detecting the state of the memory storage device; determining one of the plurality of table groups as a target table group according to the state of the memory storage device, wherein the target table group includes a plurality of target voltage management tables; and reading data from a rewritable non-volatile memory module using at least one read voltage level according to at least one of the plurality of target voltage management tables. Thereby, data decoding efficiency can be improved or maintained under various states of the memory storage device.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a table management method, a memory storage device, and a memory control circuit unit. Background Art

[0002] In recent years, the growth of smart phones, tablet computers, and notebook computers has been very rapid, resulting in a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (e.g., flash memories) have the characteristics of data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] Generally, before storing data in a rewritable non-volatile memory module, the data is first encoded. When data is to be read, the read data can be decoded to try to correct the errors therein. In addition, the setting of the read voltage level for reading data also has a great impact on the correctness of the read data. Generally, a plurality of management tables can be stored in a rewritable non-volatile memory module. When data is to be read, these management tables can be queried according to a preset order, and the information in the management table ranked at the forefront among these management tables is used to determine the read voltage level used for the current read. If the data read using this read voltage level cannot be correctly decoded, the information in the next management table after this management table can be queried to determine the read voltage level used for the next read. However, when the operating environment changes, performing data reading using the preset management tables may result in a decrease in data decoding efficiency. Summary of the Invention

[0004] In view of this, the present invention provides a table management method, a memory storage device, and a memory control circuit unit, which can improve or maintain data decoding efficiency in various states of the memory storage device.

[0005] Exemplary embodiments of the present invention provide a table management method for a memory storage device. The memory storage device includes a rewritable non-volatile memory module. The table management method includes: storing a plurality of table groups, wherein each of the plurality of table groups includes a plurality of voltage management tables; detecting a state of the memory storage device; determining, based on the state of the memory storage device, one of the plurality of table groups as a target table group, wherein the target table group includes a plurality of target voltage management tables; and reading data from the rewritable non-volatile memory module using at least one read voltage level based on at least one of the plurality of target voltage management tables.

[0006] Exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: store a plurality of table groups, wherein each of the plurality of table groups includes a plurality of voltage management tables; detect a state of the memory storage device; determine, based on the state of the memory storage device, one of the plurality of table groups as a target table group, wherein the target table group includes a plurality of target voltage management tables; and read data from the rewritable non-volatile memory module using at least one read voltage level based on at least one of the plurality of target voltage management tables.

[0007] Exemplary embodiments of the present invention further provide a memory control circuit unit, which includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to a rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: store a plurality of table groups, wherein each of the plurality of table groups includes a plurality of voltage management tables; detect a state of the memory control circuit unit; determine, based on the state of the memory control circuit unit, one of the plurality of table groups as a target table group, wherein the target table group includes a plurality of target voltage management tables; and read data from the rewritable non-volatile memory module using at least one read voltage level based on at least one of the plurality of target voltage management tables.

[0008] Based on the above, multiple table groups can be stored in advance, and each table group can include multiple voltage management tables. According to the state of the memory storage device, one of the multiple table groups can be determined as the target table group, and the target table group can include multiple target voltage management tables. Then, at least one read voltage level can be used to read data from the rewritable non-volatile memory module according to at least one of the multiple target voltage management tables. Thereby, the data decoding efficiency can be improved or maintained under various states of the memory storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module shown according to an exemplary embodiment of the present invention;

[0015] Figure 7 is a schematic diagram of multiple table groups shown according to an exemplary embodiment of the present invention;

[0016] Figure 8 is a schematic diagram of a management table and its usage order shown according to an exemplary embodiment of the present invention;

[0017] Figure 9 is a schematic diagram of sequentially using different read voltage levels to read data in a decoding operation shown according to an exemplary embodiment of the present invention;

[0018] Figure 10 is a schematic diagram of a soft decoding operation shown according to an exemplary embodiment of the present invention;

[0019] Figure 11 is a flowchart of a table management method shown according to an exemplary embodiment of the present invention. Detailed Implementation Modes

[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0021] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0022] Figure 1 FIG. is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0023] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0024] In an exemplary embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0025] In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner.

[0026] In an exemplary embodiment, the memory storage device 10 can be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0027] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 the memory storage device 30 and the host system 31.

[0028] Figure 3 is a schematic diagram of the host system and the memory storage device shown in the exemplary embodiment of the present invention. Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342.

[0029] Figure 4 is a schematic diagram of the memory storage device shown in the exemplary embodiment of the present invention. Please refer toFigure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0030] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip containing the memory control circuit unit 42.

[0031] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0032] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which 1 bit can be stored in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which 2 bits can be stored in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which 3 bits can be stored in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which 4 bits can be stored in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0033] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple memory states. By applying a read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0034] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can form a plurality of physical programming units, and these physical programming units can form a plurality of physical erasure units. Specifically, the memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in a MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0035] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit for erasure. That is, each physical erasure unit contains the smallest number of memory cells that are erased together. For example, the physical erasure unit is a physical block.

[0036] Figure 5 It is a schematic diagram of the memory control circuit unit shown in the exemplary embodiment of the present invention. Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, a memory interface 53, and an error checking and correcting circuit 54.

[0037] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as data writing, reading, and erasing. When describing the operation of the memory management circuit 51 below, it is equivalent to describing the operation of the memory control circuit unit 42.

[0038] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions are executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0039] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of the rewritable non-volatile memory module 43 in the form of program code (for example, the system area in the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit runs these control instructions to perform operations such as data writing, reading, and erasing.

[0040] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0041] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 is used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0042] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating data writing, a read instruction sequence for indicating data reading, an erase instruction sequence for indicating data erasure, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated by the memory management circuit 51, for example, and are transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code and the memory address will be included.

[0043] The error checking and correcting circuit (also known as the decoding circuit) 54 is connected to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 will generate a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 will write the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. After that, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it will simultaneously read the error correcting code and / or error detecting code corresponding to this data, and the error checking and correcting circuit 54 will perform error checking and correcting operations on the read data based on this error correcting code and / or error detecting code.

[0044] In an exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56.

[0045] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0046] In an exemplary embodiment,Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0047] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to Figure 6 , the memory management circuit 51 may logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602.

[0048] In an exemplary embodiment, a physical unit refers to a physical address or a physical programmed unit. In an exemplary embodiment, a physical unit may also be composed of multiple consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programmed units.

[0049] The physical units 610(0) to 610(A) in the storage area 601 are used to store user data (such as user data from Figure 1 the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 may store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the spare area 602 do not store data (such as valid data). For example, if a certain physical unit does not store valid data, this physical unit may be associated (or added) to the spare area 602. In addition, the physical units in the spare area 602 (or physical units that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store this new data. In an exemplary embodiment, the spare area 602 is also referred to as a free pool.

[0050] The memory management circuit 51 may configure the logical units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programmed unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0051] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data stored in this physical unit currently includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it means that the data stored in this physical unit is invalid data.

[0052] The memory management circuit 51 can record management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 desires to read data from or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logical-to-physical mapping table.

[0053] Figure 7 is a schematic diagram of multiple table groups shown in an exemplary embodiment of the present invention. Please refer to Figure 7 , the memory management circuit 51 can store multiple table groups 71(0) to 71(D) in the rewritable non-volatile memory module 43 (for example, stored in a system area dedicated to storing system information). Each of the table groups 71(0) to 71(D) can include multiple management tables (also referred to as voltage management tables). The information in the voltage management tables can be used to determine the read voltage level. For example, the voltage management table can record a voltage offset value. The voltage offset value can be used to adjust the reference voltage level to obtain the desired read voltage level. The determined read voltage level can be used to read data from a specific physical unit (also referred to as the first physical unit) in the rewritable non-volatile memory module 43. In particular, different table groups can contain different voltage management tables, so that the read voltage levels determined according to the voltage management tables in different table groups can also be different.

[0054] In an exemplary embodiment, the memory management circuit 51 can detect the state of the memory storage device 10. The memory management circuit 51 can determine one of the table groups 71(0) to 71(D) as the target table group 72 according to the state of the memory storage device 10. For example, the memory management circuit 51 can select one of the table groups 71(0) to 71(D) as the target table group 72 according to the state of the memory storage device 10. The multiple voltage management tables in the target table group 72 are also referred to as target voltage management tables. Then, the memory management circuit 51 can use at least one read voltage level to read data from the rewritable non-volatile memory module 43 (i.e., the first physical unit) according to at least one of the multiple target voltage management tables.

[0055] In an exemplary embodiment, the error checking and correction circuit 54 may perform a decoding operation on the data read from the first physical unit to attempt to correct the error bits in the data. For example, the error checking and correction circuit 54 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code) or BCH. If a certain decoding operation can successfully decode a certain data, the successfully decoded data can be output, for example, transmitted to the host system 10 to reply to the read request of the host system 10. However, if a certain decoding operation cannot successfully decode a certain data, the memory management circuit 51 may use a different read voltage level according to the voltage management table (i.e., the target voltage management table) in the target table group 72 to read the first physical unit again, in an attempt to reduce the total number of error bits in the read data and / or improve the decoding success rate of the read data. Thereafter, the error checking and correction circuit 54 may decode the read data again.

[0056] Figure 8 is a schematic diagram of a management table and its use sequence according to an exemplary embodiment of the present invention. Figure 9 FIG. 4 is a schematic diagram showing how different read voltage levels are sequentially used to read data in a decoding operation according to an exemplary embodiment of the present invention.

[0057] Please refer to Figure 8 , assuming that the target table group 72 includes management tables 801(0)-801(E) (ie, target voltage management tables). The information in the management tables 801(0)-801(E) can be used to determine Figure 9 For example, the information in the management table 801(0) may be used to determine the read voltage level 901(0), the information in the management table 801(i) may be used to determine the read voltage level 901(i), and the information in the management table 801(E) may be used to determine the read voltage level 901(E). i may be a positive integer greater than 0 and less than E.

[0058] It should be noted that in the decoding operation of data read from the same physical unit using the target table group 72, the order of using the management tables 801(0) to 801(E) is as follows: Figure 8 For example, this usage order may reflect that the usage priority of management table 801(0) is higher than the usage priority of management table 801(i), and the usage priority of management table 801(i) is higher than the usage priority of management table 801(E). In addition, the usage order of management tables 801(0) to 801(E) may be dynamically adjusted according to specific rules.

[0059] Please refer toFigure 9 Assume that Figure 8 In the usage order of the management tables 801(0) to 801(E), the usage priority of the management table 801(0) is the highest. When data is to be read from the first physical unit, the memory management circuit 51 can first determine the read voltage level 901(0) according to the information in the management table 801(0). Then, the memory management circuit 51 can send a read instruction sequence to the rewritable non-volatile memory module 43 according to the read voltage level 901(0). This read instruction sequence can instruct the rewritable non-volatile memory module 43 to use the read voltage level 901(0) to read the data in the first physical unit.

[0060] In an exemplary embodiment, assume that the threshold voltage distribution of multiple memory cells in the first physical unit includes states 910 and 920. The memory cells belonging to state 910 are used to store a certain bit (or bit combination). The memory cells belonging to state 920 are used to store another bit (or another bit combination). For example, the memory cells belonging to state 910 can be used to store bit "1" (or bit combination "111"), and / or the memory cells belonging to state 920 can be used to store bit "0" (or bit combination "000"), etc., which are not limited in the present invention.

[0061] According to the received read instruction sequence, the rewritable non-volatile memory module 43 can apply the read voltage level 901(0) to multiple memory cells in the first physical unit. If a certain memory cell can be turned on by the read voltage level 901(0) (for example, the threshold voltage of this memory cell is less than the read voltage level 901(0)), the memory management circuit 51 can determine that this memory cell belongs to state 810. On the contrary, if a certain memory cell is not turned on by the read voltage level 801(0) (for example, the threshold voltage of this memory cell is greater than the read voltage level 901(0)), the memory management circuit 51 can determine that this memory cell belongs to state 920. Thereby, the memory management circuit 51 can obtain the data read from the first physical unit using the read voltage level 901(0). For example, this data can reflect the conduction state of the read voltage level 901(0) on the memory cells in the first physical unit. Then, the error checking and correcting circuit 54 can decode this data. If this data can be successfully decoded, the error checking and correcting circuit 54 can output the successfully decoded data.

[0062] However, if the data read using the read voltage level 901(0) cannot be successfully decoded, the memory management circuit 51 may read the information in the management table 801(i) according to the usage order of the management tables 801(0) to 801(E). The memory management circuit 51 may determine the next read voltage level, i.e., the read voltage level 901(i), according to the information in the management table 801(i). The memory management circuit 51 may send a read instruction sequence to the rewritable non-volatile memory module 43 according to the read voltage level 901(i). This read instruction sequence may instruct the rewritable non-volatile memory module 43 to use the read voltage level 901(i) to read the data in the first physical unit. According to this read instruction sequence, the rewritable non-volatile memory module 43 may apply the read voltage level 901(i) to a plurality of memory cells in the first physical unit. Thereby, the memory management circuit 51 may obtain the data read from the first physical unit using the read voltage level 901(i). This data may reflect the conduction state of the memory cells in the first physical unit by the read voltage level 901(i). Then, the error checking and correcting circuit 54 may decode this data. If this data can be successfully decoded, the error checking and correcting circuit 54 may output the successfully decoded data.

[0063] By analogy, if the data read using the read voltage level 901(i) cannot be successfully decoded, the memory management circuit 51 may read the information in the management table 801(E) according to the usage order of the management tables 801(0) to 801(E). The memory management circuit 51 may determine the next read voltage level, i.e., the read voltage level 901(E), according to the information in the management table 801(E). Then, the memory management circuit 51 may send a read instruction sequence to the rewritable non-volatile memory module 43 according to the read voltage level 901(E). This read instruction sequence may instruct the rewritable non-volatile memory module 43 to use the read voltage level 901(E) to read the data in the first physical unit. According to this read instruction sequence, the rewritable non-volatile memory module 43 may apply the read voltage level 901(E) to a plurality of memory cells in the first physical unit. Thereby, the memory management circuit 51 may obtain the data read from the first physical unit using the read voltage level 901(E). This data may reflect the conduction state of the memory cells in the first physical unit by the read voltage level 901(E). Then, the error checking and correcting circuit 54 may decode this data.

[0064] In an exemplary embodiment, Figure 9The repeatable decoding operation in an exemplary embodiment is also referred to as a hard decoding operation. This hard decoding operation can be used to repeatedly decode the data read from the first physical unit using different read voltage levels until the management tables 801(0) to 801(E) in the target table group 72 are exhausted or the read data is successfully decoded. It should be noted that Figure 9 the voltage positions of the respective read voltage levels 901(0) to 901(E), the total number of the read voltage levels 901(0) to 901(E), and the types of the states 910 and 920 are all examples and are not intended to limit the present invention.

[0065] In an exemplary embodiment, according to different states of the memory storage device 10, the memory management circuit 51 may determine different table groups in the table groups 71(0) to 71(D) as the target table group 72. For example, in a specific state (also referred to as the first state) of the memory storage device 10, the memory management circuit 51 may determine a specific table group (also referred to as the first table group) in the table groups 71(0) to 71(D) as the target table group 72. In addition, in another state (also referred to as the second state) of the memory storage device 10, the memory management circuit 51 may determine another table group (also referred to as the second table group) in the table groups 71(0) to 71(D) as the target table group 72. The first table group is different from the second table group.

[0066] In an exemplary embodiment, in response to a change in the state of the memory storage device 10, the memory management circuit 51 may switch the target table group 72 from a specific table group (such as the first table group) in the table groups 71(0) to 71(D) to another table group (such as the second table group) in the table groups 71(0) to 71(D). For example, in response to the state of the memory storage device 10 changing from the first state to the second state, the memory management circuit 51 may switch the target table group 72 from the first table group to the second table group.

[0067] In an exemplary embodiment, the state information detected and available for determining or changing the target table group 72 includes at least one of the working state, temperature state, usage state, and decoding state of the memory storage device 10. The memory management circuit 51 may determine one of the table groups 71(0) to 71(D) as the target table group 72 according to at least one of the working state, temperature state, usage state, and decoding state of the memory storage device 10.

[0068] In an exemplary embodiment, the operating state of the memory storage device 10 can reflect whether the memory storage device 10 is in a power-on stage. For example, during the power-on stage, the memory storage device 10 is executing a boot program. After completing the boot program, the memory storage device 10 can end the power-on procedure and enter the normal operation stage.

[0069] In an exemplary embodiment, in response to the memory storage device 10 being in a power-on stage (e.g., the memory storage device 10 is executing a boot program), the memory management circuit 51 can determine the table group 71(f) in the table groups 71(0) to 71(D) as the target table group 72. Later, in response to the memory storage device 10 not being in a power-on stage (e.g., the memory storage device 10 has completed the boot program), the memory management circuit 51 can instead determine the table group 71(g) as the target table group 72. The table group 71(f) is different from the table group 71(g).

[0070] In an exemplary embodiment, the temperature state of the memory storage device 10 can reflect the temperature of the rewritable non-volatile memory module 43 (or the memory storage device 10). In an exemplary embodiment, the temperature state of the memory storage device 10 can reflect whether the temperature of the rewritable non-volatile memory module 43 (or the memory storage device 10) is within a specific temperature range.

[0071] In an exemplary embodiment, in response to the temperature of the rewritable non-volatile memory module 43 (or the memory storage device 10) being within a specific temperature range (also referred to as the first temperature range), the memory management circuit 51 can determine the table group 71(h) in the table groups 71(0) to 71(D) as the target table group 72. In addition, in response to the temperature of the rewritable non-volatile memory module 43 (or the memory storage device 10) being within another temperature range (also referred to as the second temperature range), the memory management circuit 51 can determine the table group 71(j) in the table groups 71(0) to 71(D) as the target table group 72. The first temperature range is different from the second temperature range. The table group 71(h) is different from the table group 71(j).

[0072] In an exemplary embodiment, the usage status of the memory storage device 10 can reflect the wear level of the rewritable non-volatile memory module 43. For example, the wear level of the rewritable non-volatile memory module 43 can include the wear level of the first physical unit. For example, the wear level of the rewritable non-volatile memory module 43 can be positively correlated with the number of times the memory cells in the first physical unit are programmed, erased, read, and the bit error rate. For example, the number of times the memory cells in the first physical unit are programmed, erased, and read can be represented by a program count, an erase count, and a read count, respectively. In an exemplary embodiment, the memory management circuit 51 can obtain the wear level of the rewritable non-volatile memory module 43 based on the program count, erase count, read count, and / or bit error rate.

[0073] In an exemplary embodiment, in response to the wear level of the rewritable non-volatile memory module 43 meeting a specific condition (also referred to as the first condition), for example, the program count, erase count, read count, and / or bit error rate being within a specific value range (also referred to as the first value range), the memory management circuit 51 can determine the table group 71(k) in the table groups 71(0) to 71(D) as the target table group 72. Additionally, in response to the wear level of the rewritable non-volatile memory module 43 meeting another condition (also referred to as the second condition), for example, the program count, erase count, read count, and / or bit error rate being within another value range (also referred to as the second value range), the memory management circuit 51 can determine the table group 71(m) in the table groups 71(0) to 71(D) as the target table group 72. The first value range is different from the second value range. The table group 71(k) is different from the table group 71(m).

[0074] In an exemplary embodiment, the decoding status of the memory storage device 10 can reflect whether the memory storage device 10 is in a specific decoding stage. For example, the specific decoding stage can include the last (hard) decoding stage before the error checking and correction circuit 54 is about to enter the soft decoding operation.

[0075] In an exemplary embodiment, after determining that the hard decoding operation fails, the error checking and correction circuit 54 can perform a soft decoding operation. During the soft decoding operation, the error checking and correction circuit 54 can use more read voltage levels to read the first physical unit to obtain more auxiliary information (also referred to as soft information) available for decoding data. Based on the soft information, the decoding ability of the error checking and correction circuit 54 during the soft decoding operation can be higher than that during the hard decoding operation.

[0076] In an exemplary embodiment, in response to the memory storage device 10 not being in the specific decoding stage, the memory management circuit 51 may determine the table group 71(p) among the table groups 71(0) to 71(D) as the target table group 72. However, in response to the memory storage device 10 being in the specific decoding stage, for example, the error checking and correction circuit 54 operates in the last (hard) decoding stage before entering the soft decoding operation, the memory management circuit 51 may determine the table group 71(q) among the table groups 71(0) to 71(D) as the target table group 72. The table group 71(p) is different from the table group 71(q).

[0077] In an exemplary embodiment, the memory management circuit 51 may adjust the table group specifically used in the specific decoding stage (such as the table group 71(q)) according to the execution result of the soft decoding operation. For example, the memory management circuit 51 may adjust the information in one or more voltage management tables in the table group 71(q) according to the soft information obtained in the soft decoding operation. Then, in the last (hard) decoding stage before the error checking and correction circuit 54 is about to enter the soft decoding operation, the read voltage levels determined and used according to one or more voltage management tables in the table group 71(q) can be used to read data with a higher correct rate from the first physical unit. In addition, in an exemplary embodiment, the table group 71(q) may also be set as the target table group 72 in the soft decoding operation.

[0078] Figure 10 is a schematic diagram of the soft decoding operation shown in the exemplary embodiment of the present invention. Please refer to Figure 10 , in the soft decoding operation, a plurality of read voltage levels (also referred to as soft read voltage levels) 1001(0) to 1001(4) can be used to read the memory cells in the first physical unit. In particular, the read voltage levels 1001(0) to 1001(4) can be used to divide the threshold voltage distribution of the memory cells in the first physical unit into a plurality of voltage regions 1002(0) to 1002(5), as Figure 10As shown. For example, the voltage region 1002(1) is located between the read voltage levels 1001(0) and 1001(1), and so on. According to the read results of a certain memory cell in the first physical unit with respect to the read voltage levels 1001(0) to 1001(4), the memory management circuit 51 can obtain the soft information corresponding to the first physical unit. The soft information can reflect that the threshold voltages of the respective memory cells in the first physical unit are located in a certain voltage region among the voltage regions 1002(0) to 1002(5). The memory management circuit 51 can adjust the information in one or more voltage management tables in the table group 71(q) according to the soft information. In addition, the read results of the first physical unit with respect to the read voltage levels 1001(0) to 1001(4) (i.e., the soft information) can have more uses, such as being used to adjust the Log Likelihood Ratio (LLR) corresponding to the first physical unit, etc., to improve the decoding success rate of the soft decoding operation, which is not limited in the present invention.

[0079] In an exemplary embodiment, one or more of the above various state information that can reflect the current state of the memory storage device 10 can be used in combination to adopt the most suitable table group as the target table group 72 corresponding to the current state of the memory storage device 10. For example, in the state where the memory storage device 10 is in the power-on stage and the temperature of the rewritable non-volatile memory module 43 (or the memory storage device 10) is within the first temperature range, the memory management circuit 51 can determine the table group 71(r) in the table groups 71(0) to 71(D) as the target table group 72. Later, in the state where the memory storage device 10 is not in the power-on stage and the temperature of the rewritable non-volatile memory module 43 (or the memory storage device 10) is still within the first temperature range, the memory management circuit 51 can determine the table group 71(s) in the table groups 71(0) to 71(D) as the target table group 72. The table group 71(r) is different from the table group 71(s). More combinations of the states of the memory storage device 10 and the adopted target table group 72 can be paired and set according to actual requirements, which is not limited in the present invention.

[0080] Figure 11 is a flowchart of a table management method according to an exemplary embodiment of the present invention. Please refer to Figure 11, in step S1101, a plurality of table groups are stored, where each of the plurality of table groups includes a plurality of voltage management tables. In step S1102, the state of the memory storage device is detected. In step S1103, according to the state of the memory storage device, one of the plurality of table groups is determined as a target table group, where the target table group includes a plurality of target voltage management tables. In step S1104, data is read from the rewritable non-volatile memory module using at least one read voltage level according to at least one of the plurality of target voltage management tables.

[0081] However, Figure 11 Each step has been described in detail above and will not be repeated here. It should be noted that Figure 11 Each step can be implemented as multiple pieces of code or circuits, and the present invention does not limit this. In addition, Figure 11 The method of can be used in combination with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0082] In summary, the exemplary embodiments proposed by the present invention can dynamically determine a specific table group as the target table group according to the current state of the memory storage device. Subsequently, the read voltage level determined and used according to one or more voltage management tables in the target table group can be used to read data with a higher correct rate from the rewritable non-volatile memory module. Thereby, the data decoding efficiency of the memory storage device in different states can be effectively improved or maintained.

[0083] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A table management method, characterized in that, for a memory storage device, wherein the memory storage device includes a rewritable non-volatile memory module, and the table management method includes: Storing a plurality of table groups, wherein each table group of the plurality of table groups includes a plurality of voltage management tables; Detecting the state of the memory storage device, wherein the state includes the operating state of the memory storage device, and the operating state reflects whether the memory storage device is executing a boot program; According to the state of the memory storage device, determining one of the plurality of table groups as a target table group, wherein the target table group includes a plurality of target voltage management tables; and Reading data from the rewritable non-volatile memory module using at least one read voltage level according to at least one of the plurality of target voltage management tables, wherein the step of determining one of the plurality of table groups as the target table group according to the state of the memory storage device includes: In response to the memory storage device executing the boot program, determining the first table group of the plurality of table groups as the target table group; and In response to the memory storage device having completed the boot program, determining the second table group of the plurality of table groups as the target table group, and the first table group is different from the second table group.

2. The table management method according to claim 1, wherein the step of determining one of the plurality of table groups as the target table group according to the state of the memory storage device further includes: Switching the target table group in response to a change in the state of the memory storage device.

3. The table management method according to claim 1, wherein the step of determining one of the plurality of table groups as the target table group according to the state of the memory storage device further includes: Determining different table groups of the plurality of table groups as the target table group in different states of the memory storage device.

4. The table management method according to claim 1, wherein the step of determining one of the plurality of table groups as the target table group according to the state of the memory storage device further includes: Determining one of the plurality of table groups as the target table group according to at least one of the operating state, temperature state, usage state, and decoding state of the memory storage device.

5. The table management method according to claim 4, wherein the operating state reflects whether the memory storage device is in a power-on stage.

6. The table management method according to claim 4, wherein the temperature state reflects whether the temperature of the rewritable non-volatile memory module is within a specific temperature range.

7. The table management method according to claim 4, wherein the usage state reflects the degree of wear of the rewritable non-volatile memory module.

8. The table management method according to claim 4, wherein the decoding state reflects whether the memory storage device is in a specific decoding stage.

9. A memory storage device, characterized in that, comprising: a connection interface unit for connecting to a host system; a rewritable non-volatile memory module; and a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: store a plurality of table groups, wherein each of the plurality of table groups includes a plurality of voltage management tables; detect the state of the memory storage device, wherein the state includes the operating state of the memory storage device, and the operating state reflects whether the memory storage device is executing a boot program; determine one of the plurality of table groups as a target table group according to the state of the memory storage device, wherein the target table group includes a plurality of target voltage management tables; and read data from the rewritable non-volatile memory module using at least one read voltage level according to at least one of the plurality of target voltage management tables, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory storage device includes: in response to the memory storage device executing the boot program, determining the first table group among the plurality of table groups as the target table group; and in response to the memory storage device having completed the boot program, determining the second table group among the plurality of table groups as the target table group, and the first table group is different from the second table group.

10. The memory storage device according to claim 9, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory storage device further includes: switching the target table group in response to a change in the state of the memory storage device.

11. The memory storage device according to claim 9, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory storage device further includes: determining different table groups among the plurality of table groups as the target table group in different states of the memory storage device.

12. The memory storage device according to claim 9, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory storage device further includes: determining one of the plurality of table groups as the target table group according to at least one of the operating state, temperature state, usage state, and decoding state of the memory storage device.

13. The memory storage device according to claim 12, wherein the operating state reflects whether the memory storage device is in a power-on stage.

14. The memory storage device according to claim 12, wherein the temperature state reflects whether the temperature of the rewritable non-volatile memory module is within a specific temperature range.

15. The memory storage device according to claim 12, wherein the usage state reflects the degree of wear of the rewritable non-volatile memory module.

16. The memory storage device according to claim 12, wherein the decoding state reflects whether the memory storage device is in a specific decoding stage.

17. A memory control circuit unit characterized in that it includes: a host interface for connecting to a host system; a memory interface for connecting to a rewritable non-volatile memory module; and a memory management circuit connected to the host interface and the memory interface, wherein the memory management circuit is configured to: store a plurality of table groups, wherein each table group of the plurality of table groups includes a plurality of voltage management tables; detect the state of the memory control circuit unit, wherein the state includes the operating state of the memory control circuit unit, and the operating state reflects whether the memory control circuit unit is executing a boot program; determine one of the plurality of table groups as a target table group according to the state of the memory control circuit unit, wherein the target table group includes a plurality of target voltage management tables; and read data from the rewritable non-volatile memory module using at least one read voltage level according to at least one of the plurality of target voltage management tables, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory control circuit unit includes: in response to the memory control circuit unit executing the boot program, determining the first table group among the plurality of table groups as the target table group; and in response to the memory control circuit unit having ended the boot program, determining the second table group among the plurality of table groups as the target table group, and the first table group is different from the second table group.

18. The memory control circuit unit according to claim 17, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory control circuit unit further includes: switching the target table group in response to a change in the state of the memory control circuit unit.

19. The memory control circuit unit according to claim 17, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory control circuit unit further includes: determining different table groups among the plurality of table groups as the target table group in different states of the memory control circuit unit.

20. The memory control circuit unit according to claim 17, wherein the operation of determining one of the plurality of table groups as the target table group according to the state of the memory control circuit unit further comprises: determining one of the plurality of table groups as the target table group according to at least one of the working state, temperature state, usage state, and decoding state of the memory control circuit unit.

21. The memory control circuit unit according to claim 20, wherein the working state reflects whether the memory control circuit unit is in a power-on stage.

22. The memory control circuit unit according to claim 20, wherein the temperature state reflects whether the temperature of the rewritable non-volatile memory module is within a specific temperature range.

23. The memory control circuit unit according to claim 20, wherein the usage state reflects the degree of wear of the rewritable non-volatile memory module.

24. The memory control circuit unit according to claim 20, wherein the decoding state reflects whether the memory control circuit unit is in a specific decoding stage.

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