Signal circuit and control method thereof

Abstract

The present disclosure provides a signal circuit and a control method for the signal circuit. The signal circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit is coupled to a first light-emitting signal output terminal for pulling up the voltage level of the light-emitting signal output terminal. The pull-down circuit is coupled to the first light-emitting signal output terminal for pulling down the voltage level of the light-emitting signal output terminal. The pull-down circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is coupled between the system low voltage and the first light-emitting signal output terminal. The second transistor is coupled between the voltage signal source and the gate of the first transistor, and the gate of the second transistor receives a first clock signal. One end of the first capacitor is coupled to the gate of the first transistor, and the other end receives a second clock signal. The second clock signal partially overlaps with the first clock signal.

Description

Technical Field

[0001] This disclosure document relates to a signal circuit and its control method, and particularly to a wiring configuration of a pulse width modulation light emitting grid array signal circuit and its control method. Background Art

[0002] In the current driving technology of display panels, the pulse width modulation (PWM) driving technology can achieve the best display effect under the condition of a stable square wave current. However, the square wave imitation circuit manufactured to generate a stable square wave uses a large number of pins, which increases the circuit volume, thereby affecting the cost and resolution of high-end panels. Therefore, a general driving circuit is usually used in the process to replace the square wave imitation circuit. In the past driving circuits, there were problems of insufficient driving force or too small driving current. Due to the slow voltage change (decrease or increase), the voltage change would present a two-stage stepped waveform rather than a square wave. In the pulse width modulation technology, the time ratio of the square wave output represents the gray scale level. When the output time is shorter, the situation of insufficient current in the driving circuit causing a slow voltage change will have a larger proportion in the entire output waveform, thereby affecting the presentation of low gray scale images. Summary of the Invention

[0003] This disclosure document provides a signal circuit, including a pull-up circuit and a pull-down circuit. The pull-up circuit is coupled to a first light emitting signal output terminal to pull up the voltage level of the light emitting signal output terminal. The pull-down circuit is coupled to the first light emitting signal output terminal to pull down the voltage level of the light emitting signal output terminal. The pull-down circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is coupled between the system low voltage and the first light emitting signal output terminal. The second transistor is coupled between the voltage signal source and the gate of the first transistor, and the gate of the second transistor receives a first clock signal. One end of the first capacitor is coupled to the gate of the first transistor, and the other end receives a second clock signal. The second clock signal partially overlaps with the first clock signal.

[0004] This disclosure document also provides a control method for a signal circuit, and the steps are as follows. Turn on the system high voltage, system low voltage, and voltage signal source. Input a first clock signal to the signal circuit, and the pull-down circuit pulls down the voltage level of the first light emitting signal output terminal. Input a second clock signal to the signal circuit, and the pull-down circuit pulls down the voltage level of the first light emitting signal output terminal again. Description of the Drawings

[0005] When reading in conjunction with the accompanying drawings of the specification, the embodiments of the present disclosure will be best understood from the following detailed description. It should be noted that according to the standard practice in the industry, the features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the features can be arbitrarily increased or decreased.

[0006] Figure 1 Schematic diagram of a signal circuit according to some embodiments;

[0007] Figure 2 Schematic diagram of a signal circuit according to some embodiments;

[0008] Figure 3 Timing diagram of signals of a signal circuit according to some embodiments;

[0009] Figure 4 Flowchart of a control method for a signal circuit according to some embodiments; and

[0010] Figure 5 Schematic diagram of a signal circuit according to some embodiments.

[0011] Explanation of reference numerals:

[0012] 100: Signal circuit

[0013] 110: Pull-up circuit

[0014] 120: Pull-down circuit

[0015] 400: Control method of signal circuit

[0016] 410 - 450: Operations

[0017] 500: Signal circuit

[0018] CLK1: First clock signal

[0019] CLK2: Second clock signal

[0020] STV, STV_X: Voltage signal source

[0021] OUT1: First light emission signal output terminal

[0022] OUT2: Second light emission signal output terminal

[0023] VGH: System high voltage

[0024] VGL: System low voltage

[0025] T1 - T8: Transistors

[0026] C1, C2: Capacitors

[0027] CLK1a1, CLK1a2, CLK2a1, CLK2a2: Falling edges

[0028] CLK1b1, CLK1b2, CLK2b1, CLK2b2: Rising edges

[0029] t1a1, t2a1, t1a2, t2a2: Time Detailed implementation manners

[0030] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplification and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Figure 1 A circuit schematic diagram of a signal circuit 100 is shown according to some embodiments. In one embodiment, the signal circuit 100 is used to generate a light-emitting signal required to drive a display panel (not shown in the figure), which is also referred to as an EM signal in some practical applications. Generally speaking, the light-emitting signal is used to control the gates of transistor switches (not shown in the figure) in the display panel. As the light-emitting signal switches to a high level or a low level, the transistor switches are correspondingly turned on or off to allow the light-emitting elements to conduct and light up.

[0032] Generally speaking, the light-emitting signal is a pulse width modulation (PWM) signal. Ideally, the light-emitting signal is an ideal square wave signal, which can switch from a low level to a high level in a short time (short rising edge), and can switch from a high level to a low level in a short time (short falling edge). However, in reality, due to certain loads (such as capacitive loads or resistive loads) in each pixel of the display panel, the input light-emitting signal cannot reach the ideal square wave waveform. If the driving ability of the signal circuit is insufficient, it may cause the voltage to rise too slowly, resulting in the output voltage of the light-emitting signal presenting a two-stage stepped waveform. If a transistor with a larger element size is used to improve the driving ability of the signal circuit, it will be unfavorable for the space utilization efficiency of the display panel, and may cause the resolution of the display panel not to be improved, or the peripheral border of the display panel to become thicker, which goes against the mainstream development of current display technologies. Therefore, in the embodiments of this disclosure document, the circuit architecture of the signal circuit 100 can be used to avoid the output voltage of the light-emitting signal presenting a two-stage stepped waveform and achieve a more ideal waveform.

[0033] As Figure 1As shown, the signal circuit 100 includes a pull-up circuit 110 and a pull-down circuit 120. The pull-up circuit 110 is coupled to the first light-emitting signal output terminal OUT1 to pull up the voltage level of the light-emitting signal output terminal OUT1. The pull-down circuit 120 is coupled to the first light-emitting signal output terminal OUT1 to pull down the voltage level of the light-emitting signal output terminal OUT1. By alternately activating the pull-up circuit 110 and the pull-down circuit 120, the voltage level of the light-emitting signal output terminal OUT1 can be adjusted to a high / low level.

[0034] In some embodiments, the pull-down circuit 120 includes a first transistor T1, a second transistor T2, and a first capacitor C1. The first transistor T1 is coupled between the system low voltage VGL and the first light-emitting signal output terminal OUT1 to control whether to adjust the voltage level of the light-emitting signal output terminal OUT1 to the system low voltage VGL. In some embodiments, the second transistor T2 is coupled between the voltage signal source STV and the gate of the first transistor T1, and the gate of the second transistor T2 is configured to receive a first clock signal CLK1. According to the first clock signal CLK1, the second transistor T2 can control whether to allow the voltage signal source STV to pass through. In some embodiments, one end of the first capacitor C1 is coupled to the gate of the first transistor T1, and the other end of the first capacitor C1 is configured to receive a second clock signal CLK2.

[0035] In some embodiments, the voltage signal source STV has a high level (e.g., the system high voltage VGH) and a low level (e.g., the system low voltage VGL) to control whether to activate the pull-up circuit 110 or the pull-down circuit 120.

[0036] Please refer to Figure 2 . Figure 2 According to some embodiments, Figure 1 the circuit schematic diagrams of the signal circuit 100 and the pull-up circuit 110 are shown. Figure 2 In the illustrated embodiment, the pull-up circuit 110 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a second capacitor C2.

[0037] In Figure 2In the illustrated embodiment, the third transistor T3 is coupled between the system high voltage VGH and the first light-emitting signal output terminal OUT1. The fourth transistor T4 is coupled between the system high voltage VGH and the gate of the first transistor T1, and the gate of the fourth transistor T4 is coupled to the gate of the third transistor T3. The fifth transistor T5 is coupled between the system low voltage VGL and the gate of the fourth transistor T4. The sixth transistor T6 is coupled between the system high voltage VGH and the gate of the fourth transistor T4, and the gate of the sixth transistor T6 is coupled to the gate of the first transistor T1. The seventh transistor T7 is coupled between the system high voltage VGH and the gate of the fifth transistor T5, and the gate of the seventh transistor T7 is coupled to the voltage signal source STV. One end of the second capacitor C2 is coupled to the gate of the fifth transistor T5, and the other end of the second capacitor C2 receives the first clock signal CLK1.

[0038] In some embodiments, the transistors T1 to T7 are all P-type Metal Oxide Semiconductor (PMOS) transistors, or all N-type Metal Oxide Semiconductor (NMOS) transistors. For the sake of simplicity, Figure 2 only the symbols of PMOS transistors are used to represent the transistors T1 to T7.

[0039] Regarding the operation and timing of the scan circuit 100, please refer to Figure 3 and Figure 4 . Figure 3 According to some embodiments, a timing diagram of the signals of the signal circuit 100 using PMOS transistors is shown.

[0040] In some embodiments, the first clock signal CLK1 includes falling edges CLK1a1, CLK1a2 and rising edges CLK1b1, CLK1b2, and the second clock signal CLK2 includes falling edges CLK2a1, CLK2a2 and rising edges CLK2b1, CLK2b2. The times corresponding to the falling edges CLK1a1, CLK1a2 of the first clock signal CLK1 on the timing diagram are times t1a1, t1a2 respectively, while the times corresponding to the falling edges CLK2a1, CLK2a2 of the second clock signal CLK2 on the timing diagram are times t2a1, t2a2 respectively.

[0041] In some embodiments, the second clock signal CLK2 overlaps partially with the first clock signal CLK1. Further, the falling edge CLK2a1 of the second clock signal CLK2 is between the falling edge CLK1a1 and the rising edge CLK1b1 of the first clock signal CLK1, and the falling edge CLK2a1 of the second clock signal CLK2 is within 5 milliseconds later than the falling edge CLK1a1 of the first clock signal CLK1. In addition, the falling edge CLK2a2 of the second clock signal CLK2 is between the falling edge CLK1a2 and the rising edge CLK1b2 of the first clock signal CLK1, and the falling edge CLK2a2 of the second clock signal CLK2 is also within 5 milliseconds later than the falling edge CLK1a2 of the first clock signal CLK1. In other words, the time t2a1 is within 5 milliseconds later than the time t1a1 in the timing diagram, and the time t2a2 is also within 5 milliseconds later than the time t1a2 in the timing diagram. That is, as Figure 3 shown, the low-level intervals of the second clock signal CLK2 all overlap partially with the low-level intervals of the first clock signal CLK1.

[0042] Figure 4 The flowchart of the control method 400 of the signal circuit is shown according to some embodiments. In some embodiments, the control method 400 of the signal circuit includes operations 410 to 450.

[0043] As Figure 2 、 Figure 3 and Figure 4 shown, taking the signal circuit 100 as an example, in some embodiments, the signal circuit 100 initially performs operation 410 to turn on the system high voltage VGH, the system low voltage VGL, and the voltage signal source STV.

[0044] At the time t1a1, the signal circuit 100 performs operation 420 to input the first clock signal CLK1 to the second transistor T2, and the second transistor T2 conducts when receiving the falling edge CLK1a1 of the first clock signal CLK1. In the example of Figure 3 , since the voltage signal source STV is at a low level at the time t1a1, the step proceeds to operation 430.

[0045] Operation 430 is performed between the time t1a1 and the time t2a1. Due to the conduction of the second transistor T2, the gate of the first transistor T1 receives the low-level voltage signal source STV, further causing the first transistor T1 to conduct and allowing the light-emitting signal output terminal OUT1 to start pulling down towards the system low voltage VGL. In other words, between the time t1a1 and the time t2a1, the pull-down circuit 120 of the signal circuit 100 starts to pull down the light-emitting signal output terminal OUT1 towards the system low voltage VGL.

[0046] In some embodiments, the transistors T1 to T7 in the signal circuit 100 can all be NMOS. At this time, the charging power of the pull-down circuit 120 is sufficient, and the light-emitting signal output terminal OUT1 can be pulled down to the system low voltage VGL within a short time.

[0047] On the other hand, in the pull-up circuit 110, since the voltage signal source STV connected to the gate of the seventh transistor T7 is at a low level, the seventh transistor T7 is turned on, causing the gate of the fifth transistor T5 to become high level and not conduct. The gate of the sixth transistor T6 is coupled to the gate of the first transistor T1 (which is at a low level at this time) and is turned on at this time. As can be seen from the above, the gate of the third transistor T3 coupled between the fifth transistor T5 and the sixth transistor T6 is at a high level at this time, so the third transistor T3 does not conduct. In other words, between time t1a1 and time t2a1, the pull-up circuit 110 will not pull up the light-emitting signal output terminal OUT1 because the third transistor T3 does not conduct.

[0048] At time t2a1, the signal circuit 100 performs operation 440 and inputs the second clock signal CLK2 to the first capacitor C1. At this time, the second clock signal CLK2 is at the falling edge. Since the voltage of the second clock signal CLK2 connected to one end of the first capacitor C1 drops rapidly, the voltage of the other end of the first capacitor C1 (this end is connected to the gate of the first transistor T1) is also pulled down through the coupling effect of the first capacitor C1. Since the gate voltage of the first transistor T1 is pulled down again (due to the falling edge of the second clock signal CLK2), the conduction state of the first transistor T1 is further enhanced, causing the light-emitting signal output terminal OUT1 to be pulled down to the system low voltage VGL more rapidly. In addition, since the voltage signal source STV maintains the same level, it can be known that the pull-up circuit 110 still does not operate.

[0049] As Figure 3 shown, since the first low-level interval of the first clock signal CLK1 and the first low-level interval of the second clock signal CLK2 partially overlap, the light-emitting signal output terminal OUT1 will immediately perform a second drop after the first drop, making the drop waveform of the light-emitting signal output terminal OUT1 approximate to the drop waveform of a square wave.

[0050] In some other examples, assume that the first low-level interval of the first clock signal CLK1 and the first low-level interval of the second clock signal CLK2 do not overlap (as Figure 3 the second clock signal CLK2 shown by the dashed line, whose low-level interval continues after the low-level interval of the first clock signal CLK1, but the two do not overlap). At this time, there will be a flat voltage interval at the light-emitting signal output terminal OUT1 after the first drop (as Figure 3The light-emitting signal output terminal OUT1) drawn with a dashed line does not drop again until after the low-level interval of the first clock signal CLK1 ends. This phenomenon causes the output of the light-emitting signal output terminal OUT1 to exhibit an obvious two-stage drop, that is, the problem faced by the prior art described above.

[0051] Therefore, since the signal circuit 100 has the second clock signal CLK2 and the first capacitor C1 coupled to the gate of the first transistor T1, and the second clock signal CLK2 partially overlaps with the first clock signal CLK1, it can achieve the effect of quickly pulling down the voltage level of the light-emitting signal output terminal OUT1 and improve the display problem faced by the display panel at low gray levels.

[0052] In Figure 3 the example, after the signal circuit 100 finishes pulling down, it returns to operation 420 and receives the second falling edge CLK1a2 of the first clock signal CLK1 at time t1a2, causing the second transistor T2 to conduct again. Since the voltage signal source STV is at a high level at time t1a2, the step proceeds to operation 450.

[0053] Operation 450 is performed between time t1a2 and time t2a2. Due to the conduction of the second transistor T2, the gate of the first transistor T1 receives the high-level voltage signal source STV, so the first transistor T1 does not conduct. In other words, between time t1a2 and time t2a2, the pull-down circuit 120 of the signal circuit 100 does not pull down the light-emitting signal output terminal OUT1 because the first transistor T1 does not conduct.

[0054] On the other hand, in the pull-up circuit 110, since the voltage signal source STV connected to the gate of the seventh transistor T7 is at a high level, the seventh transistor T7 does not conduct, causing the gate of the fifth transistor T5 to turn low through the second capacitor C2 coupled to the first clock signal CLK1. Therefore, the fifth transistor T5 conducts. And the gate of the sixth transistor T6 does not conduct because it is coupled to the gate of the first transistor T1 (which is at a high level at this time). As can be seen from the above, the gate of the third transistor T3 coupled between the fifth transistor T5 and the sixth transistor T6 is at a low level at this time, so the third transistor T3 conducts. In other words, between time t1a1 and time t2a1, the pull-up circuit 110 of the signal circuit 100 starts to pull up the light-emitting signal output terminal OUT1 to the system high voltage VGH.

[0055] In addition, in Figure 3 the embodiment, since the transistors T1 to T7 are PMOS, the charging power of the pull-up circuit 110 is sufficient, and the light-emitting signal output terminal OUT1 can be pulled up to the system high voltage VGH in a short time.

[0056] In Figure 3 As described above, since the charging power of the pull-up circuit 110 is sufficient, the light-emitting signal output terminal OUT1 can be pulled up to the system high voltage VGH during the first rise, so that the rising waveform of the light-emitting signal output terminal OUT1 is approximately the same as the rising waveform of a square wave.

[0057] It should be noted in particular that the number of rising edges and falling edges of the first clock signal CLK1 and the second clock signal CLK2 is not limited to the embodiments in Figure 3 The number of other rising edges and falling edges is within the scope of this disclosure document. Therefore, the signal circuit 100 performs the same operation every time it receives the first clock signal CLK1 and the second clock signal CLK2.

[0058] By means of continuous pulling-down operations, the problem of the stepped light-emitting signal caused by insufficient driving force in the conventional signal circuit can be improved, so that the waveform of the light-emitting signal is approximately a square wave, improving the performance of the display panel at low gray levels.

[0059] Figure 5 The circuit schematic diagram of the signal circuit 500 is shown according to some embodiments. The signal circuit 500 is similar to the signal circuit 100, but the difference is that the intersection of the fifth transistor T5 and the sixth transistor T6 is not coupled to the gates of the third transistor T3 and the fourth transistor T4, but is coupled to the second light-emitting signal output terminal OUT2, and the signal circuit 200 further includes an eighth transistor T8, and the eighth transistor T8 is coupled between the voltage signal source STV_X with opposite phase and the gate of the fifth transistor T5. In some embodiments, the signal output by the second light-emitting signal output terminal OUT2 is the inverted signal of the signal output by the first light-emitting signal output terminal OUT1.

[0060] Figure 5 The signal circuit 500 of Figure 2 has the same function as the signal circuit 100 of

[0061] Taking the pull-down of the first light-emitting signal output terminal OUT1 in the embodiments of Figure 5 as an example, please also refer to Figure 3For the signal waveform diagram, between time t1a1 and time t2a1, due to the conduction of the second transistor T2, the gate of the first transistor T1 receives a low-level voltage signal source STV, further causing the first transistor T1 to conduct, and making the light-emitting signal output terminal OUT1 start to pull down towards the system low voltage VGL. In other words, between time t1a1 and time t2a1, the signal circuit 500 starts to pull down the light-emitting signal output terminal OUT1 towards the system low voltage VGL. At the arrival of time t2a1, because the gate voltage of the first transistor T1 is pulled down again (due to the falling edge of the second clock signal CLK2), the conduction state of the first transistor T1 is further enhanced, causing the light-emitting signal output terminal OUT1 to pull down towards the system low voltage VGL even faster. Therefore, the circuit architecture of the signal circuit 500 can also achieve two consecutive pull-downs of the light-emitting signal output terminal OUT1 during the falling period.

[0062] Similarly, the transistors T1 to T8 of the signal circuit 500 can all be PMOS transistors or all be NMOS transistors.

[0063] In the same situation, the circuit architecture of the signal circuit 500 can also achieve a rapid pull-up of the light-emitting signal output terminal OUT1 during the rising period.

[0064] By the methods mentioned in this disclosure document, it is possible to improve the output condition of the light-emitting signal and enhance the performance of the display panel at low gray levels while maintaining the advantage of the relatively small volume of the conventional signal circuit.

[0065] The foregoing has outlined the features of several embodiments so that those skilled in the art can better understand the implementation manners of the present disclosure. Those skilled in the art should understand that it is easy to use the present disclosure as a basis for designing or modifying other processes and structures in order to achieve the same purposes and / or realize the same advantages as those of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the concept and scope of the present disclosure, and various changes, substitutions, and modifications can be implemented herein without departing from the concept and scope of the present disclosure.

Claims

1. A signal circuit, comprising: A pull-up circuit, coupled to a first light-emitting signal output terminal, for pulling up the voltage level of the first light-emitting signal output terminal; and A pull-down circuit, coupled to the first light-emitting signal output terminal, for pulling down the voltage level of the first light-emitting signal output terminal, the pull-down circuit comprising: A first transistor, coupled between a system low voltage and the first light-emitting signal output terminal; A second transistor, coupled between a voltage signal source and the gate of the first transistor, the gate of the second transistor receiving a first clock signal, the voltage signal source having a high level and a low level; and A first capacitor, one end of the first capacitor being coupled to the gate of the first transistor, and the other end of the first capacitor receiving a second clock signal, the second clock signal partially overlapping with the first clock signal, Wherein the first clock signal and the second clock signal each comprise a falling edge and a rising edge, and the falling edge of the second clock signal is between the falling edge and the rising edge of the first clock signal.

2. The signal circuit according to claim 1, wherein the pull-up circuit comprises: A third transistor, coupled between a system high voltage and the first light-emitting signal output terminal; A fourth transistor, coupled between the system high voltage and the gate of the first transistor, the gate of the fourth transistor being coupled to the gate of the third transistor; A fifth transistor, coupled to the system low voltage; A sixth transistor, coupled between the system high voltage and the fifth transistor, the gate of the sixth transistor being coupled to the gate of the first transistor; A seventh transistor, coupled between the system high voltage and the gate of the fifth transistor, the gate of the seventh transistor being coupled to the voltage signal source; And A second capacitor, one end of the second capacitor being coupled to the gate of the fifth transistor, and the other end of the second capacitor receiving the first clock signal.

3. The signal circuit according to claim 2, wherein The gates of the third transistor and the fourth transistor are coupled to the intersection of the fifth transistor and the sixth transistor.

4. The signal circuit according to claim 2, wherein The gates of the third transistor and the fourth transistor are coupled to the gate of the fifth transistor, the fifth transistor being coupled between a second light-emitting signal output terminal and the system low voltage; and Further comprising an eighth transistor, coupled between the voltage signal source of opposite phase and the gate of the fifth transistor, the gate of the eighth transistor being coupled to the first clock signal.

5. The signal circuit according to claim 2, wherein When the signal circuit receives the first clock signal and the second clock signal, if the voltage signal source is at the low level, the pull-down circuit will pull down the voltage level of the first light-emitting signal output terminal.

6. The signal circuit according to claim 2, wherein When the signal circuit receives the first clock signal and the second clock signal, if the voltage signal source is at the high level, the pull-up circuit will pull up the voltage level of the first light-emitting signal output terminal.

7. A control method for a signal circuit, comprising: Turn on a system high voltage, a system low voltage, and a voltage signal source; Input a first clock signal to the signal circuit, and a pull-down circuit pulls down the voltage level of a first light-emitting signal output terminal; and Input a second clock signal to the signal circuit, and the pull-down circuit pulls down the voltage level of the first light-emitting signal output terminal again, wherein the first clock signal and the second clock signal each include a falling edge and a rising edge, the first clock signal and the second clock signal partially overlap, and the falling edge of the second clock signal is between the falling edge and the rising edge of the first clock signal.

8. The control method according to claim 7, further comprising: Input the first clock signal to the signal circuit, and a pull-up circuit pulls up the voltage level of the first light-emitting signal output terminal.

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