Parity data in dynamic random access memory (DRAM)

Abstract

This disclosure describes methods, apparatuses, and systems related to storing parity data in dynamic random access memory (DRAM). In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving, at a DRAM device, the parity data from the controller and writing the parity data to the DRAM device, receiving, at a non-volatile memory device, the user data from the controller and writing the user data to the non-volatile memory device, reading, via the controller, the user data from the non-volatile memory device, and receiving, at the controller, the parity data from the DRAM device.

Description

Technical Field

[0001] This disclosure generally relates to the management of parity data in dynamic random access memory (DRAM). Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), DRAM, and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications. Non-volatile memory can be used in, for example, personal computers, memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in arrays, where the array is used in a memory device.

[0004] The memory may be a portion of a memory module (e.g., a dual in-line memory module (DIMM)) used in a computing device. The memory module may contain volatile memory (e.g., DRAM) and / or non-volatile memory (e.g., flash memory or RRAM). The DIMM may be used as the main memory in a computing system. Summary of the Invention

[0005] In one aspect, this application provides a method for managing parity data in dynamic random access memory (DRAM), comprising: generating the parity data at a controller based on user data queued for writing to a non-volatile memory device coupled to the controller; receiving the parity data from the controller at the DRAM and writing the parity data into the DRAM; receiving the user data from the controller at the non-volatile memory device and writing the user data into the non-volatile memory device; reading the user data from the non-volatile memory device via the controller; and receiving the parity data from the DRAM at the controller.

[0006] In another aspect, this application further provides an apparatus for managing parity data in dynamic random access memory (DRAM), comprising: the DRAM configured to store the parity data; a non-volatile memory device coupled to the DRAM, wherein the non-volatile memory device is configured to store user data; and a controller coupled to the DRAM and the non-volatile memory device, wherein the controller includes an error correction code (ECC) module configured to receive the parity data from the DRAM; and to reconstruct the user data using the parity data in response to an error during a read operation of the user data from the non-volatile memory device.

[0007] In another aspect, this application further provides a system for managing parity data in dynamic random access memory (DRAM), comprising: a host device configured to send a write command containing user data; and a memory device coupled to the host device, wherein the memory device includes: a controller including an error correction code (ECC) module configured to: receive the write command containing the user data; and generate the parity data based on the user data; the DRAM configured to: receive the parity data from the controller; and store the parity data; and a non-volatile memory device configured to: receive the user data from the controller; and store the user data. Attached Figure Description

[0008] Figure 1 This is a block diagram of a device in the form of a computing system including a memory system, according to several embodiments of the present disclosure.

[0009] Figure 2 This is a block diagram of a device in the form of a dual in-line memory module (DIMM) according to several embodiments of the present disclosure.

[0010] Figure 3 This is a flowchart of a method for storing parity data in DRAM according to several embodiments of the present disclosure. Detailed Implementation

[0011] This disclosure includes methods, apparatus, and systems relating to: generating parity data at a controller based on user data queued for writing to a non-volatile memory device coupled to the controller; receiving the parity data from the controller and writing the parity data to the DRAM device at a DRAM device; receiving the user data from the controller and writing the user data to the non-volatile memory device at the non-volatile memory device; reading the user data from the non-volatile memory device via the controller; and receiving the parity data from the DRAM device at the controller.

[0012] Non-volatile memory devices and / or DRAM may be included in a DIMM. The DIMM may be a non-volatile dual in-line memory module (NVDIMM). In several embodiments, the non-volatile memory device may be a 3D cross-point device or a NAND device.

[0013] Non-volatile memory devices offer near-DRAM speeds and non-volatility, eliminating significant system overhead such as periodic checkpointing and / or degrading system state to hard disk drives and / or SSDs. Non-volatile memory devices can also provide large main memory capacities, for example, 1 terabyte (TB). In some instances, the memory capacity of a non-volatile memory device can be used for in-memory databases.

[0014] In several embodiments, non-volatile memory (e.g., 3D crosspoint) can have high defect rates and, in some cases, cannot tolerate die failures. Die failures can be absorbed using XOR and / or RAID methods. These methods may involve one or more dies storing only parity data of user data written to other dies, and in response to die failure, performing an XOR operation on the parity data to recover the user data. However, writing parity data to one or more dies and / or reconstructing user data in response to die failure may degrade write performance and / or read performance.

[0015] Non-volatile memory devices coupled to DRAM devices can absorb die failures without degrading system write and / or read performance. For example, a separate DRAM module for storing parity data allows the entire memory bandwidth of the non-volatile memory device to be used for high-performance writes. In several embodiments, the non-volatile memory device and the DRAM device can be contained within a relatively small footprint.

[0016] A controller including an error correction code (ECC) module can generate parity data by performing error correction code operations (e.g., XOR and / or RAID operations) on user data. The parity data can be stored (e.g., written to) a DRAM device and / or a non-volatile memory device along with the user data. In some instances, the parity data can be embedded within the user data in the non-volatile memory device. In several embodiments, the bit stream including user data may also include one or more bits of parity data.

[0017] Parity data can be used to reconstruct user data stored in a non-volatile memory device. The controller can receive (e.g., read) parity data from a DRAM device and reconstruct the user data in response to a read failure. A read failure can be attributed to memory corruption in the non-volatile memory device. In some instances, the controller can read and reconstruct the user data in one clock cycle because parity data is readily available at the DRAM device. For example, when reading user data from the non-volatile memory device, the corresponding parity data is also read from the DRAM device, so that if a read error occurs, the parity data is readily available and an ECC operation can be performed in one clock cycle.

[0018] In several embodiments, parity data may be stored in a non-volatile memory device before powering down the DRAM device and / or DIMM. The parity data may be rewritten to the DRAM device in response to powering it on. In some instances, the parity data may be regenerated at the controller and / or received at the DRAM device in response to powering down and on. For example, the controller may receive user data from the non-volatile memory device and perform an XOR operation on the user data in response to powering up the DRAM device and / or DIMM.

[0019] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form a part of this disclosure, and several embodiments of the disclosure are illustrated by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of the disclosure, and it should be understood that other embodiments may be utilized, and process, electrical, and / or structural changes may be made without departing from the scope of the disclosure. As used herein, the indicators “M,” “N,” “X,” and “Y” indicate that the specific features thus specified may be included in the several embodiments of the disclosure.

[0020] As used herein, “several” something can refer to one or more of such things. For example, “several DIMMs” can refer to one or more DIMMs. Additionally, indicators such as “M,” “N,” “X,” and “Y” as used herein (especially with respect to reference numerals in the drawings) indicate that several specific features thus specified may be included in several embodiments of this disclosure.

[0021] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the drawing number and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. As will be understood, elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, the scale and relative dimensions of the elements provided in the figures are intended to illustrate various embodiments of this disclosure and are not intended to be limiting.

[0022] Figure 1 This is a functional block diagram of a computing system 100 comprising devices in the form of a plurality of memory systems 104-1…104-N, according to one or more embodiments of the present disclosure. As used herein, “device” may refer to, but is not limited to, any of a variety of structures or combinations thereof, such as, for example, a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems.

[0023] exist Figure 1 In the embodiments described herein, memory systems 104-1…104-N may include one or more dual in-line memory modules (DIMMs) 110-1,…,110-X,110-Y. DIMMs 110-1,…,110-X,110-Y may include volatile memory and / or non-volatile memory. In several embodiments, memory systems 104-1,…,104-N may include multi-chip devices. Multi-chip devices may include several different memory types and / or memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module.

[0024] exist Figure 1 In this embodiment, the memory system 104-1, coupled to the host via channel 112-1, may include DIMMs 110-1, ..., 110-X, where DIMM 110-1 is an NVDIMM and 110-X is a DRAM DIMM. In this example, each DIMM 110-1, ..., 110-X, 110-Y includes a controller 114. The controller 114 may receive commands from the host 102 and control the execution of commands on the DIMM. Moreover, in several embodiments, the protocols of this disclosure may be implemented through a memory device (e.g., a DIMM) without a controller, and the execution of commands using the protocols of this disclosure may be built into the memory device.

[0025] Depending on the type of memory in the DIMM, host 102 can send commands to DIMMs 110-1, ..., 110-X, 110-Y using the protocols of this disclosure and / or existing protocols. For example, the host can communicate with an NVDIMM on the same channel (e.g., channel 112-1) using the protocols of this disclosure and with a DRAM DIMM using existing protocols, both of which are on the same memory system. The host and NVDIMM can communicate via read-ready (R_RDY) signals, read-send (R_SEND) signals, write credit increment (WC_INC) signals, and read identification (RID) signals according to the protocols of this disclosure. The Read Ready (R_RDY), Read Send (R_SEND), Write Credit Increment (WC_INC), and Read Identify (RID) signals can be sent via pins that are not used in existing protocols (e.g., DDR4) or are used for alternative purposes from existing protocols (e.g., DDR4) to make this protocol compatible with existing protocols. Furthermore, the pins can be assigned to the Read Ready (R_RDY), Read Send (R_SEND), Write Credit Increment (WC_INC), and Read Identify (RID) signals in protocols under development (e.g., DDR5).

[0026] like Figure 1 As described, host 102 can be coupled to memory systems 104-1…104-N. In several embodiments, each memory system 104-1…104-N can be coupled to host 102 via a channel. Figure 1 In this configuration, memory system 104-1 is coupled to host 102 via channel 112-1, and memory system 104-N is coupled to host 102 via channel 112-N. Host 102 may be a laptop computer, personal computer, digital camera, digital recording and playback device, mobile phone, PDA, memory card reader, interface hub, and other host systems, and may include memory access devices (e.g., processors). Those skilled in the art will understand that "processor" may mean one or more processors, such as parallel processing systems, several coprocessors, etc.

[0027] Host 102 includes host controller 108 for communication with memory systems 104-1…104-N. Host controller 108 can send commands to DIMMs 110-1,…,110-X,110-Y via channels 112-1…112-N. Host controller 108 can communicate with controller 114 on each of DIMMs 110-1,…,110-X,110-Y for reading, writing, erasing data, and other operations. A physical host interface provides an interface for transmitting control, address, data, and other signals between memory systems 104-1…104-N and host 102 having a compatible receiver for the physical host interface. Signals can be transmitted between 102 and DIMMs 110-1, ..., 110-X, 110-Y on several buses (e.g., data bus and / or address bus), for example via channels 112-1...112-N.

[0028] The host controller 108 and / or the controller 114 on the DIMM may include control circuitry, such as hardware, firmware, and / or software. In one or more embodiments, the host controller 108 and / or the controller 114 may be an application-specific integrated circuit (ASIC) coupled to a printed circuit board containing a physical interface. Furthermore, each DIMM 110-1, ..., 110-X, 110-Y may include a buffer 116 of volatile and / or non-volatile memory and an ECC module 118. The buffer 116 can be used to buffer data used during the execution of read and / or write commands. For example, the ECC module 118 may perform ECC operations on the data to correct errors before storing it in the buffer 116.

[0029] DIMMs 110-1, ..., 110-X, 110-Y may provide main memory for a memory system or may be used as additional memory or storage devices throughout the memory system. Each DIMM 110-1, ..., 110-X, 110-Y may contain one or more arrays of memory cells (e.g., non-volatile memory cells). For example, the array may be a flash array with a NAND architecture. Embodiments are not limited to a specific type of memory device. For example, memory devices may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, etc.

[0030] Figure 1Embodiments may include additional circuitry not described to avoid obscuring embodiments of this disclosure. For example, memory systems 104-1…104-N may include address circuitry to latch address signals provided via I / O connections through I / O circuitry. Address signals may be received and decoded by row and column decoders to access DIMMs 110-1,…,110-X,110-Y. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of DIMMs 110-1,…,110-X,110-Y.

[0031] Figure 2 This is a block diagram of a device in the form of a dual in-line memory module (DIMM) 210 according to several embodiments of the present disclosure. DIMM 210 may correspond to... Figure 1 The DIMMs are 110-1, ..., 110-X, 110-Y. Figure 2 In this context, DIMM 210 may include controller 214. Controller 214 may correspond to... Figure 1 The controller 114 is located within the controller. The controller 214 may include memory, such as SRAM memory, which may be a buffer 216 and / or an ECC module 218. The buffer 216 and the ECC module 218 may respectively correspond to... Figure 1 The buffer 116 and ECC module 118 are included. DIMM 210 may include a non-volatile memory device 220 and a DRAM device 222 coupled to the controller 214.

[0032] Non-volatile memory device 220 may include a non-volatile memory array. In some instances, non-volatile memory device 220 may be a 3D cross-point device or a NAND device. Non-volatile memory device 220 can provide near-DRAM speeds and non-volatility, which eliminates significant system overhead, such as periodic checkpointing and / or degrading system state to hard disk drives and / or SSDs. Non-volatile memory device 220 can also provide large main memory capacities, for example, 1TB. In some instances, the memory capacity of non-volatile memory device 220 can be used for in-memory databases.

[0033] In several embodiments, non-volatile memory (e.g., 3D crosspoint) can have high defect rates and, in some cases, cannot tolerate die failures. Die failures can be absorbed using XOR and / or RAID methods. These methods may involve one or more dies storing only parity data of user data written to other dies, and in response to die failure, performing an XOR operation on the parity data to recover the user data. However, writing parity data to one or more dies and / or reconstructing user data in response to die failure can degrade write performance and / or read performance.

[0034] The DIMM 210, which includes a non-volatile memory device 220 and a DRAM device 222, can absorb die failures without compromising the write and / or read performance of the DIMM 210. For example, the DIMM 210, which includes a separate DRAM device 222 for storing parity data 226, allows the entire memory bandwidth of the non-volatile memory device 220 to be used for high-performance writes. In several embodiments, the non-volatile memory device 220 and the DRAM device 222 may be contained in a relatively small footprint.

[0035] The non-volatile memory device 220 may include a control circuitry system 217-1 (e.g., hardware, firmware, and / or software) for executing commands on the non-volatile memory device 220. The control circuitry system 217-1 may receive commands from the controller 214. The control circuitry system 217-1 may be configured to execute commands to read and / or write data to the non-volatile memory device 220.

[0036] In several embodiments, user data 224 may be stored on a non-volatile memory device 220. The non-volatile memory device 220 may be configured to respond to a request from a controller 214 and / or a host (e.g., ...). Figure 1 The host 102 in the middle receives the read command and reads user data 224.

[0037] DRAM device 222 may include control circuitry 217-2 to execute commands on DRAM device 222. Control circuitry 217-2 may receive commands from controller 214 and / or host and may execute commands to read and / or write data in DRAM device 222.

[0038] The controller 214, including the ECC module 218, can generate parity data 226 by performing error correction code operations (e.g., XOR and / or RAID operations) on user data 224. The parity data 226 may be stored together with the user data 224 in a DRAM device 222 and / or a non-volatile memory device 220. In some instances, the parity data 226 may be embedded within the user data 224 in the non-volatile memory device 220. In several embodiments, the bit stream including user data 224 may also include one or more bits of the parity data 226.

[0039] Parity data 226 can be used to reconstruct user data 224 stored in non-volatile memory device 220. Non-volatile memory device 220 can transfer user data 224 to controller 214 in response to receiving a read command from host device. Controller 214 can receive parity data 226 from DRAM device 222 and reconstruct user data 224 in response to read failure (e.g., an error during a read operation of user data 224 from non-volatile memory device 220). Read failure may be attributed to memory corruption in non-volatile memory device 220. Controller 214 can reconstruct user data 224 by performing ECC operation on parity data 226 using ECC module 218. Controller 214 can send user data 224 to host device and / or non-volatile memory device 220 in response to reconstructing user data 224.

[0040] In some instances, controller 214 can read and / or reconstruct user data 224 within a single clock cycle because parity data 226 is readily available in DRAM device 222. For example, when user data 224 is read from non-volatile memory device 220, the corresponding parity data 226 is also read from DRAM device 222, making it easy to obtain parity data 226 and perform ECC operations within a single clock cycle should a read error occur. Reading and / or reconstructing user data 224 within a single clock cycle improves performance, reduces power consumption, and / or reduces the processing time of DIMM 210.

[0041] In several embodiments, parity data 226 may be stored in non-volatile memory device 220 before power is turned off DRAM device 222 and / or DIMM 210. Parity data 226 may be rewritten to DRAM device 222 in response to powering on DRAM device 222. In some instances, parity data 226 may be regenerated at controller 214 and / or received at DRAM device 222 in response to powering on and off DRAM device 222. For example, controller 214 may receive user data 224 from non-volatile memory device and perform an ECC operation (e.g., XOR operation) on user data 224 using ECC module 218 in response to powering on DRAM device 222 and / or DIMM 210 to regenerate parity data 226.

[0042] Figure 3This is a flowchart of a method 330 for storing parity data in DRAM according to several embodiments of the present disclosure. At block 332, method 330 may include generating parity data at a controller based on user data queued (e.g., scheduled) waiting to be written to a non-volatile memory device coupled to the controller. A controller including an ECC module may generate parity data by performing error correction code operations (e.g., XOR and / or RAID operations) on the user data.

[0043] At block 334, method 330 may include receiving parity data from a controller at a DRAM device and writing the parity data to the DRAM device. The parity data may be stored together with user data in the DRAM device and / or a non-volatile memory device. In some instances, the parity data may be embedded in user data in a non-volatile memory device.

[0044] At block 336, method 330 may include receiving user data from the controller at a non-volatile memory device and writing the user data to the non-volatile memory device. The non-volatile memory device may be a 3D cross-point device or a NAND device. The non-volatile memory device may be contained in a DIMM. In some instances, the DIMM may be an NVDIMM.

[0045] At block 338, method 330 may include reading user data from a non-volatile memory device via a controller. For example, the non-volatile memory device may transfer user data to the controller in response to receiving a read command. During the execution of the read command, a read failure may occur. For example, a read failure may occur due to memory corruption in the non-volatile memory device.

[0046] At block 340, method 330 may include receiving parity data from a DRAM device at a controller. The controller may receive the parity data from the DRAM device and reconstruct user data in response to a read failure. The controller may reconstruct the user data by performing an ECC operation on the parity data using an ECC module. In some instances, the controller may read and reconstruct the user data in one clock cycle. For example, when reading user data from a non-volatile memory device, the corresponding parity data may also be read from the DRAM device, so that if a read error occurs, the parity data is readily available and an ECC operation can be performed in one clock cycle. The controller may send the user data to the non-volatile memory device and / or the host device in response to reconstructing the user data.

[0047] In several embodiments, method 330 may further include storing parity data in a non-volatile memory device before powering down the DRAM device and / or DIMM. The parity data may be rewritten to the DRAM device in response to powering it up. In some instances, the parity data may be regenerated at the controller and / or received at the DRAM device in response to powering down and up on the DRAM device. For example, the controller may receive user data from the non-volatile memory device and perform an ECC operation (e.g., an XOR operation) on the user data using an ECC module in response to powering up the DRAM device and / or DIMM to regenerate the parity data.

[0048] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of the various embodiments of this disclosure. It should be understood that the foregoing description has been done in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the foregoing structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents entitled to by such claims.

[0049] In the foregoing detailed embodiments, various features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A method for managing parity data (226) in a dynamic random access memory (DRAM) (222), comprising: The parity data is generated at the controller (114, 214) based on user data (224) waiting to be written to a non-volatile memory device (220) coupled to the controller; The parity data is received from the controller at the DRAM and written into the DRAM; The user data is received from the controller at the non-volatile memory device and written to the non-volatile memory device. The user data is read from the non-volatile memory device via the controller; The parity data is received from the DRAM at the controller. and The user data is reconstructed in a clock cycle at the controller.

2. The method according to claim 1, further comprising generating the parity data by performing an error correction code (ECC) operation on the user data at the controller using an error correction code (ECC) module (118, 218).

3. The method of claim 1, further comprising writing the parity data to the non-volatile memory device.

4. The method of claim 3, wherein the bit stream of the user data further includes one or more bits of the parity data.

5. The method of claim 1, further comprising reconstructing the user data at the controller using the parity data in response to receiving the parity data at the controller.

6. The method of claim 1, further comprising storing the parity data in the non-volatile memory device before powering down the DRAM.

7. The method of claim 6, further comprising rewriting the parity data to the DRAM in response to energizing the DRAM.

8. The method of claim 1, further comprising regenerating the parity data at the controller in response to powering down and powering up the DRAM.

9. An apparatus for managing parity data (226) in a dynamic random access memory (DRAM) (222), comprising: The DRAM is configured to store the parity data; A non-volatile memory device (220) coupled to the DRAM, wherein the non-volatile memory device is configured to store user data (224); and Controllers (114, 214) coupled to the DRAM and the non-volatile memory device, wherein the controllers include error correction code (ECC) modules (118, 218) configured to: Receive the parity data from the DRAM; The user data is reconstructed using the parity data in response to an error during a read operation of the user data from the non-volatile memory device; and The parity data is regenerated in response to powering down and powering up the DRAM.

10. The device of claim 9, wherein the ECC module is configured to generate the parity data.

11. The device of claim 10, wherein the ECC module is configured to perform an XOR operation on the user data to generate the parity data.

12. The apparatus of claim 10, wherein the DRAM is configured to receive the parity data in response to the ECC module generating the parity data.

13. The device of claim 9, wherein the non-volatile memory device is a 3D crosspoint device.

14. The device of claim 9, wherein the non-volatile memory device is a NAND device.

15. A system for managing parity data (226) in a dynamic random access memory (DRAM) (222), comprising: The host device (102) is configured to send a write command containing user data (224); and Memory device (210) coupled to the host device, wherein the memory device includes: Controllers (114, 214) containing error correction code (ECC) modules (118, 218) configured to: Receive the write command containing the user data; and The parity check data is generated based on the user data; The DRAM is configured to: Receive the parity data from the controller; and Store the parity check data; and A non-volatile memory device (220) configured to: Receive the user data from the controller; Store the user data; and The parity data is stored before the DRAM is powered off.

16. The system of claim 15, wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).

17. The system of claim 15, wherein the non-volatile memory device is configured to transmit the user data to the controller in response to receiving a read command from the host device.

18. The system of claim 15, wherein the controller is configured to receive the parity data from the DRAM.

19. The system of claim 18, wherein the ECC module is configured to reconstruct the user data using the parity data and send the user data to the host device in response to an error during a read operation of the user data from the non-volatile memory device.

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