Display panel and display device

Abstract

The present invention provides a display panel comprising a first display area and a second display area, the display panel comprising: a base substrate and a plurality of first pixel units and a plurality of second pixel units located on the base substrate, the first pixel unit comprising a first light-emitting device and a first pixel circuit, and the second pixel unit comprising a second light-emitting device and a second pixel circuit; the first light-emitting device being located in the first display area, the first pixel circuit, the second light-emitting device, and the second pixel circuit being located in the second display area, the first light-emitting device and the first pixel circuit being connected via a connecting trace; the first light-emitting device and the second light-emitting device being independently reset. Embodiments of the present invention can control the display difference between the first display area and the second display area by controlling the independent reset of the first light-emitting device and the second light-emitting device.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The under-screen camera area of ​​a high-PPI (Pixels Per Inch) OLED (Organic Light-Emitting Diode) full-screen display panel typically only retains the EL (electroluminescence) device portion, placing its driver circuit portion in the compressed pixel position of the normal display area. The EL device portion and its corresponding driver circuit portion are then connected through a transparent material (such as ITO, indium tin oxide) for driving. At the same time, to improve the transmittance of the under-screen camera area, the EL device's light-emitting area is reduced. The external driver and the different light-emitting areas will result in different display effects between the under-screen camera area and the normal display area. Summary of the Invention

[0003] The present invention provides a display panel and a display device, which can reduce the display difference between the photosensitive area under the screen and the normal display area.

[0004] A first aspect of the present invention provides a display panel, comprising a first display area and a second display area, wherein the second display area at least partially surrounds the first display area;

[0005] The display panel includes: a base substrate and a plurality of first pixel units and a plurality of second pixel units located on the base substrate, wherein the first pixel unit includes a first light emitting device and a first pixel circuit, and the second pixel unit includes a second light emitting device and a second pixel circuit;

[0006] The first light-emitting device is located in the first display area, the first pixel circuit, the second light-emitting device, and the second pixel circuit are located in the second display area, an orthographic projection of the second light-emitting device on the base substrate and an orthographic projection of the second pixel circuit on the base substrate at least partially overlap, and the first light-emitting device and the first pixel circuit are connected via a connecting trace;

[0007] The first light emitting device and the second light emitting device are independently reset.

[0008] Wherein, the display panel further comprises: a third initialization signal line and a second initialization signal line located in the second display area;

[0009] The first light emitting device and the second light emitting device are reset independently, specifically:

[0010] The first pixel circuit is coupled to the third initialization signal line, and the second pixel circuit is coupled to the second initialization signal line; the third initialization signal line is configured to provide a third initialization signal to the first pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the second pixel circuit.

[0011] The absolute value of the voltage corresponding to the third initialization signal is smaller than the absolute value of the voltage corresponding to the second initialization signal.

[0012] The first pixel circuit and the second pixel circuit each include a seventh transistor, the third initialization signal line is coupled to a first electrode of the seventh transistor in the first pixel circuit, and the seventh transistor is coupled to the first light emitting device;

[0013] The second initialization signal line is coupled to a first electrode of a seventh transistor in the second pixel circuit, and the seventh transistor is coupled to the second light emitting device.

[0014] In which, the display panel includes a first gate metal layer, a second gate metal layer and a first source and drain metal layer stacked in sequence in a direction away from the base substrate, the third initialization signal line is made of the first source and drain metal layer, and the second initialization signal line is made of the second gate metal layer.

[0015] Wherein, the third initialization signal line is located in the second display area;

[0016] The display panel further includes: a light emitting control signal line and a second reset signal line, wherein the light emitting control signal line is made of the first gate metal layer, and the second reset signal line is made of the first gate metal layer;

[0017] An orthographic projection of the third initialization signal line on the base substrate is located between an orthographic projection of the light emission control signal line on the base substrate and an orthographic projection of the second reset signal line on the base substrate.

[0018] The plurality of second pixel units include a plurality of second pixel circuits, the plurality of second pixel circuits are divided into a plurality of groups of second pixel circuits, each group of second pixel circuits includes N columns of second pixel circuits, and the N columns of second pixel circuits are arranged along the first direction, wherein N ≥ 2 and N is a positive integer;

[0019] The plurality of first pixel units include a plurality of first pixel circuits, the plurality of first pixel circuits are divided into a plurality of columns of first pixel circuits, and the plurality of columns of first pixel circuits are arranged along a first direction.

[0020] Wherein, a column of first pixel circuits is arranged between two adjacent groups of the second pixel circuits.

[0021] The display panel further includes: a first data line located in the second display area and configured to provide a first data voltage to the first pixel circuit;

[0022] The first data line includes two first transfer portions and a second transfer portion, the two first transfer portions extend along a first direction, the second transfer portion extends along a second direction, the two first transfer portions are respectively connected to both ends of the second transfer portion, at least part of the first display area is located between the two first transfer portions, and the first direction and the second direction intersect with each other.

[0023] The two first transfer portions and the third initialization signal line are made of the same layer and material;

[0024] The orthographic projection of the first transition portion on the base substrate is located between the orthographic projection of the light emitting control signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

[0025] Wherein, the second transfer portion is made of a second source-drain metal layer.

[0026] The second display area further includes: a plurality of virtual pixel circuits located on the substrate; the plurality of virtual pixel circuits are divided into a plurality of columns of virtual pixel circuits, and at least part of the virtual pixel circuits in at least one column of virtual pixel circuits are multiplexed as the first pixel circuit;

[0027] The display panel further includes a second data line configured to provide a second data voltage to the column of virtual pixel circuits, and at least a portion of the second data line is multiplexed as the second switching portion.

[0028] Wherein, the display panel further includes:

[0029] a first initialization signal line, a power signal line, a first reset signal line, a first scan line, and a second scan line;

[0030] The first pixel driving circuit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a storage capacitor; wherein,

[0031] The gate of the first transistor is coupled to the first reset signal line, the first electrode of the first transistor is coupled to the first initialization signal line; the second electrode of the first transistor is coupled to the gate of the third transistor;

[0032] The first electrode of the second transistor is coupled to the second electrode of the third transistor, the second electrode of the second transistor is coupled to the gate of the third transistor, and the gate of the second transistor is coupled to the corresponding first scan line;

[0033] A first electrode of the third transistor is coupled to a second electrode of the fourth transistor, the second electrode of the third transistor is coupled to a first electrode of the sixth transistor, and a gate of the third transistor is a first plate of a storage capacitor;

[0034] A first electrode of the fourth transistor is coupled to the corresponding first data line, a second electrode of the fourth transistor is coupled to the first electrode of the third transistor, and a gate of the fourth transistor is coupled to the corresponding second scan line;

[0035] The gate of the fifth transistor is coupled to the corresponding light emitting control signal line, the first electrode of the fifth transistor is coupled to the power signal line, and the second electrode of the fifth transistor is coupled to the first electrode of the third transistor;

[0036] The gate of the sixth transistor is coupled to the corresponding light emitting control signal line, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the anode of the light emitting element;

[0037] The gate of the seventh transistor is coupled to the corresponding second reset signal line, the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor, and the first electrode of the seventh transistor is coupled to the third initialization signal line;

[0038] The first plate of the storage capacitor is reused as the gate of the third transistor, and the second plate of the storage capacitor is coupled to the power signal line.

[0039] A second aspect of the present invention provides a display device comprising the above-mentioned display panel and a photosensor, wherein the photosensor is located on the backlight side of the display panel, and the orthographic projection of the photosensor on the display panel is located within the first display area.

[0040] The embodiments of the present invention have the following beneficial effects:

[0041] The embodiment of the present invention can control the display difference between the first display area and the second display area by controlling the first light emitting device and the second light emitting device to reset independently. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the connection between the virtual pixel circuit and the first light-emitting device provided in an embodiment of the present invention;

[0043] Figure 2A circuit diagram of a first pixel circuit provided by an embodiment of the present invention;

[0044] Figure 3 A circuit layout diagram of a first pixel circuit provided by an embodiment of the present invention;

[0045] Figure 4 A circuit diagram of a second pixel circuit provided by an embodiment of the present invention;

[0046] Figure 5 A circuit layout diagram of a second pixel circuit provided by an embodiment of the present invention;

[0047] Figure 6 A schematic diagram of a third initialization signal line provided by an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of a third initialization signal line and a first data line provided by an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of the winding of a first data line provided by an embodiment of the present invention;

[0050] Figure 9 A schematic diagram of a first adapter provided in an embodiment of the present invention.

[0051] Reference numerals

[0052] A1-first display area A2-second display area

[0053] 1-first pixel circuit 2-second pixel circuit 3-first light-emitting device

[0054] 4-Second light emitting device 5-Dummy pixel circuit

[0055] L1-connection wiring

[0056] 627-connecting electrode 627a-first connecting electrode 627b-second connecting electrode

[0057] 31 - first adapter hole 32 - second adapter hole 33 - third adapter hole 34 - fourth adapter hole

[0058] 35-fifth adapter hole 36-sixth adapter hole

[0059] 111- Winding part

[0060] 1111-first adapter 1112-second adapter

[0061] 10-first scan line 11-first data line 12-second scan line 13-second initialization signal line

[0062] 14 - first reset signal line 15 - first initialization signal line 16 - power supply signal line 17 - light emission control signal line 18 - second reset signal line 19 - third initialization signal line

[0063] 20-Second data line DETAILED DESCRIPTION

[0064] In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, they will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0065] With the trend towards full-screen displays, the display screen ratio of mobile phones is an important indicator. The Full Display with Camera (FDC) places the camera under the screen, while the display screen area above the camera can still display normally, thus achieving a full screen. In order to improve the light transmittance of the FDC area, it is usually avoided to design pixel circuits in the FDC area, and only the light-emitting device part is retained, and the light-emitting area of ​​the light-emitting device is made smaller. The pixel circuit in the FDC area can use a virtual pixel circuit, which is a newly added pixel circuit after compressing the pixel circuit in the display area outside the FDC area. Since there is a certain distance between the virtual pixel circuit and the light-emitting device in the FDC area, the virtual pixel circuit and the light-emitting device in the FDC area are connected by connecting traces.

[0066] At low grayscale, tiny current differences can lead to differences in display quality. Since the luminous areas of the FDC area and the Normal area are different, and there is capacitance caused by transparent wiring in the FDC area, there are display differences between the under-screen camera area and the normal display area.

[0067] Embodiments of the present invention provide a display panel and a display device that can solve the problem of display differences between an under-screen camera area and a normal display area.

[0068] An embodiment of the present invention provides a display panel, comprising a first display area and a second display area, wherein the second display area at least partially surrounds the first display area;

[0069] The display panel includes: a base substrate and a plurality of first pixel units and a plurality of second pixel units located on the base substrate, wherein the first pixel unit includes a first light emitting device and a first pixel circuit, and the second pixel unit includes a second light emitting device and a second pixel circuit;

[0070] The first light-emitting device is located in the first display area, the first pixel circuit, the second light-emitting device, and the second pixel circuit are located in the second display area, an orthographic projection of the second light-emitting device on the base substrate and an orthographic projection of the second pixel circuit on the base substrate at least partially overlap, and the first light-emitting device and the first pixel circuit are connected via a connecting trace;

[0071] The first light emitting device and the second light emitting device are independently reset.

[0072] The embodiment of the present invention can reduce the display difference between the first display area and the second display area by controlling the first light emitting device and the second light emitting device to reset independently.

[0073] Optionally, the length of the connecting line is 2 mm to 4 mm.

[0074] The length of the connection line provided by the embodiment of the present invention is 2 mm to 4 mm, which can reduce the capacitance existing on the connection line and is conducive to improving the display effect.

[0075] refer to Figure 1 , Figure 6 and Figure 7 The display panel provided by the embodiment of the present invention includes a first display area A1 and a second display area A2. As an example, the first display area A1 is an FDC area, and the second display area A2 is a Normal area (normal display area).

[0076] The first display area A1 retains only the first light-emitting device 3 of the first pixel unit, while the first pixel circuit 1 of the first pixel unit is located in the second display area A2. This ensures light transmittance in the first display area A1. The first pixel circuit 1 is connected to the first light-emitting device 3 via a horizontal connection line L1, enabling the first display area A1 to achieve a luminous display effect.

[0077] The second display area A2 is further provided with a second pixel unit, a second light emitting device 4 and a second pixel circuit 2. The orthographic projection of the second light emitting device 4 on the substrate and the orthographic projection of the second pixel circuit 2 on the substrate at least partially overlap.

[0078] Figure 1 The diagram shows a second light-emitting device 4, a first light-emitting device 3, a second pixel circuit 2, a first pixel circuit 1, a connecting electrode 627, and a connecting trace L1. Each pixel circuit is connected to a light-emitting device via a connecting electrode 627. That is, each pixel unit has a connecting electrode 627. Specifically, the second pixel circuit 2 is connected to the second light-emitting device 4 via a connecting electrode 627 (a first connecting electrode 627a), and the first pixel circuit 1 is connected to the first light-emitting device 3 via a connecting electrode 627 (a second connecting electrode 627b).

[0079] For example, Figure 1 As shown, one end of the connecting line L1 is connected to the first light-emitting device 3, and the other end of the connecting line L1 is connected to the first pixel circuit 1 through the connecting electrode 627 (the second connecting electrode 627b). For example, the connecting electrode 627 can be formed by a single conductive component, or it can include two different conductive components located in different layers. For example, the connecting electrode 627 can include a conductive component located in one conductive layer and another conductive component located in another conductive layer.

[0080] like Figure 1 As shown, a connecting line L1 passes through the area where the pixel circuit of the pixel unit is located to connect the first pixel circuit 1 and the first light-emitting device 3 on both sides of the pixel unit. For example, the area where the pixel circuit of the pixel unit is located overlaps with multiple connecting lines L1 passing through this area. The area where the first pixel circuit 1 is located within the second display area A2 can be referred to as the auxiliary area Ra, which can also be referred to as the transition area. Figure 1 Taking the example that a second pixel circuit 2 overlaps with at most two connection lines L1, in other embodiments, a second pixel circuit 2 may also overlap with more connection lines L1. For example, in some embodiments, a second pixel circuit 2 may overlap with 5-15 connection lines L1. The number of connection lines L1 overlapped by a second pixel circuit 2 may be determined as needed. Figure 1 As shown, the first pixel circuit 1 may also overlap with the connection line L1 that is not connected to it.

[0081] In some embodiments, the area for arranging the first pixel circuit 1 can be obtained by compressing the size of the second pixel circuit 2 in the second direction. Figure 1 As shown, in the auxiliary area, a column of first pixel circuits 1 is provided for every set column of second pixel circuits 2. For example, the number of columns of second pixel circuits 2 between two adjacent columns of first pixel circuits 1 can be determined as needed.

[0082] In an embodiment of the present invention, in order to reduce the display difference between the first light emitting device 3 in the first display area A1 and the second light emitting device 4 in the second display area A2 , the first light emitting device 3 and the second light emitting device 4 are reset independently.

[0083] Optionally, the display panel further comprises: a third initialization signal line and a second initialization signal line located in the second display area;

[0084] The first light emitting device and the second light emitting device are reset independently, specifically:

[0085] The first pixel circuit is coupled to the third initialization signal line, and the second pixel circuit is coupled to the second initialization signal line; the third initialization signal line is configured to provide a third initialization signal to the first pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the second pixel circuit.

[0086] An embodiment of the present invention adds a third initialization signal line and couples the first pixel circuit to the third initialization signal, and couples the second pixel circuit to the second initialization signal line, so that the initialization signals of the first pixel circuit and the second pixel circuit can be set separately, thereby achieving the purpose of independently controlling the first pixel circuit and the second pixel circuit.

[0087] refer to Figures 2 to 7 The third initialization signal line 19 is located on opposite sides of the first display area A1 along the first direction D1, and is not located on opposite sides of the second display area A2 along the second direction D2. The third initialization signal line 19 is coupled to the first pixel circuit 1, and the second initialization signal line 13 is coupled to the second pixel circuit 2.

[0088] The first direction and the second direction intersect each other. Exemplarily, the first direction and the second direction are perpendicular to each other.

[0089] Optionally, an absolute value of a voltage value corresponding to the third initialization signal is smaller than an absolute value of a voltage value corresponding to the second initialization signal.

[0090] The embodiment of the present invention can compensate for the display difference between the FDC area and the Normal area due to the different light-emitting areas and the presence of ITO capacitance in the FDC area by making the absolute value of the voltage value corresponding to the third initialization signal smaller than the absolute value of the voltage value corresponding to the second initialization signal.

[0091] As an example, the voltage corresponding to the third initialization signal and the voltage corresponding to the second initialization signal are both negative voltages, the voltage corresponding to the third initialization signal is -2.5V, and the voltage corresponding to the second initialization signal is -3V.

[0092] At low grayscale, tiny current differences can lead to differences in display quality. Due to the difference in luminous area between the FDC area and the Normal area, and the presence of ITO capacitors in the FDC area, the initialization voltage is set independently to ensure that the off-state current remains consistent, thereby ensuring that the display effect in the FDC area is consistent with that in the Normal area.

[0093] Optionally, the first pixel circuit and the second pixel circuit each include a seventh transistor, the third initialization signal line is coupled to a first electrode of the seventh transistor in the first pixel circuit, and the seventh transistor is coupled to the first light-emitting device;

[0094] The second initialization signal line is coupled to a first electrode of a seventh transistor in the second pixel circuit, and the seventh transistor is coupled to the second light emitting device.

[0095] In an embodiment of the present invention, the initialization signals of the seventh transistor in the first pixel circuit and the seventh transistor in the second pixel circuit are set separately, and since the seventh transistor is configured to initialize the light-emitting device, the first light-emitting device and the second light-emitting device are reset independently, thereby achieving the purpose of independently controlling the first pixel circuit and the second pixel circuit.

[0096] refer to Figures 2 to 7 The first electrode of the seventh transistor T7 in the first pixel circuit is coupled to the third initialization signal line 19 via a fifth via 35, which penetrates the first gate insulating layer, the second gate insulating layer, and the first interlayer insulating layer. The first electrode of the seventh transistor T7 in the second pixel circuit is connected to the first source / drain metal layer via the fifth via 35 and then coupled to the second initialization signal line 13 via a sixth via 36, ​​which penetrates the first protective layer and the first planarization layer. The second electrode of the seventh transistor T7 in the first and second pixel circuits is coupled to the anode of the light-emitting device. Therefore, the different initialization signals coupled to the first electrode of the seventh transistor T7 achieve different initializations of the anode of the light-emitting device, further resulting in different display effects for the light-emitting devices located in different display areas.

[0097] Optionally, the display panel includes a first gate metal layer, a second gate metal layer and a first source / drain metal layer stacked in sequence in a direction away from the base substrate, the third initialization signal line is made of the first source / drain metal layer, and the second initialization signal line is made of the second gate metal layer.

[0098] In the embodiment of the present invention, the third initialization signal line is made of the first source-drain metal layer, and the second initialization signal line is made of the second gate metal layer, so that the third initialization signal line can be separated from the second initialization signal line.

[0099] The display panel provided by an embodiment of the present invention includes, from closest to the base substrate to farthest from the base substrate, the following: an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a first source-drain metal layer, a first protective layer, a first flat layer, a second source-drain metal layer, a second flat layer, ITO1, a third flat layer, ITO2, a fourth flat layer, ITO3, a fifth flat layer, an anode layer, a pixel defining layer, a spacer layer, an organic light-emitting functional layer and a cathode layer.

[0100] Optionally, the third initialization signal line is located in the second display area;

[0101] The display panel further includes: a light emitting control signal line and a second reset signal line, wherein the light emitting control signal line is made of the first gate metal layer, and the second reset signal line is made of the first gate metal layer;

[0102] An orthographic projection of the third initialization signal line on the base substrate is located between an orthographic projection of the light emission control signal line on the base substrate and an orthographic projection of the second reset signal line on the base substrate.

[0103] An embodiment of the present invention can avoid the formation of parasitic capacitance between the third initialization signal line and the light-emitting control signal line or the second reset signal line by making the orthographic projection of the third initialization signal line on the base substrate be located between the orthographic projection of the light-emitting control signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

[0104] refer to Figure 3 The light-emission control signal line 17 is configured to provide a light-emission control signal to the fifth transistor T5 and the sixth transistor T6. The second reset signal line 18 is configured to provide a reset signal to the gate of the seventh transistor T7 included in the first pixel circuit. A third initialization signal line 19 is obtained by longitudinally compressing the line width, spacing, and clearance space of the film layer. The orthographic projection of the third initialization signal line 19 on the substrate does not overlap with the orthographic projection of the light-emission control signal line 17 on the substrate. The orthographic projection of the third initialization signal line 19 on the substrate does not overlap with the orthographic projection of the second reset signal line 18 on the substrate.

[0105] Furthermore, the orthographic projection of the third initialization signal line 19 on the base substrate is located between the orthographic projection of the light emitting control signal line 17 on the base substrate and the orthographic projection of the second reset signal line 18 on the base substrate.

[0106] Optionally, the plurality of second pixel units include a plurality of second pixel circuits, the plurality of second pixel circuits are divided into a plurality of groups of second pixel circuits, each group of second pixel circuits includes N columns of second pixel circuits, and the N columns of second pixel circuits are arranged along the first direction, where N ≥ 2 and N is a positive integer;

[0107] The plurality of first pixel units include a plurality of first pixel circuits, the plurality of first pixel circuits are divided into a plurality of columns of first pixel circuits, and the plurality of columns of first pixel circuits are arranged along a first direction.

[0108] Optionally, a column of first pixel circuits is provided between two adjacent groups of second pixel circuits. Optionally, each group of second pixel circuits includes two columns of second pixel circuits.

[0109] The embodiment of the present invention realizes one column of first pixel circuits by compressing every two columns of second pixel circuits, which has shorter ITO connection lines compared to realizing one column of first pixel circuits by compressing every seven or eight columns of second pixel circuits.

[0110] Optionally, the second display area further includes: a plurality of dummy pixel circuits located on the substrate; the plurality of dummy pixel circuits are divided into a plurality of columns of dummy pixel circuits, and at least a portion of the dummy pixel circuits in at least one column of dummy pixel circuits are multiplexed as the first pixel circuit. By multiplexing at least a portion of the dummy pixel circuits located in the second display area as the first pixel circuit, the present invention avoids providing a driving circuit corresponding to the first light-emitting device in the first display area, thereby improving the transmittance of the first display area.

[0111] Figure 6 Only the virtual pixel circuit 5 multiplexed as the first pixel circuit 1 is shown, and the portion of the virtual pixel circuit 5 that is not multiplexed as the first pixel circuit 1 is not shown.

[0112] refer to Figure 6 and Figure 9 Every two columns of second pixel circuits 2 are laterally compressed to form a column of virtual pixel circuits 5. At least a portion of the virtual pixel circuits 5 are reused as first pixel circuits 1. The first pixel circuits 1 are used to drive the first light-emitting device located in the first display area A1. The second pixel circuits are arranged in multiple columns along the first direction, with every two columns of second pixel circuits alternating with one column of first pixel circuits.

[0113] Optionally, the display panel further includes: a first data line, located in the second display area, configured to provide a first data voltage to the first pixel circuit;

[0114] The first data line includes two first transfer portions and a second transfer portion, the two first transfer portions extend along a first direction, the second transfer portion extends along a second direction, the two first transfer portions are respectively connected to both ends of the second transfer portion, at least part of the first display area is located between the two first transfer portions, and the first direction and the second direction intersect with each other.

[0115] In an embodiment of the present invention, since there is a certain distance between the first light-emitting device and the first pixel circuit, and the main parts of the first light-emitting device and the first data line are located on the same straight line extending along the second direction, the first data line can provide the first data voltage to the first pixel circuit by adopting a winding design.

[0116] refer to Figures 7 to 9The display panel includes a first data line 11, and the first data line 11 includes a main portion and a winding portion 111. The main portion of the first data line 11 and the first light emitting device are located on the same straight line extending along the second direction.

[0117] The winding portion 111 of the first data line 11 includes two first transition portions 1111 and a second transition portion 1112. The first transition portion 1111 extends along a first direction D1, and the second transition portion 1112 extends along a second direction D2.

[0118] The main portion of the first data line 11 is coupled to one of the first transfer portions 1111 through a first transfer hole 31. One of the first transfer portions 1111 is coupled to the second transfer portion 1112 through a second transfer hole 32. The second transfer portion 1112 is coupled to another first transfer portion 1111 through a third transfer hole 33. The other first transfer portion is connected back to the main portion of the first data line 11 through a fourth transfer hole 34. At least a portion of the first display area A1 is disposed between the two first transfer portions 1111.

[0119] Optionally, the two first transfer portions and the third initialization signal line are made of the same layer and material;

[0120] The orthographic projection of the first transition portion on the base substrate is located between the orthographic projection of the light emitting control signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

[0121] The embodiment of the present invention compresses the longitudinal film layers, spacing and clearance space while keeping the longitudinal pitch unchanged, thereby compressing not only the third initialization signal line but also the first transfer portion, thereby solving the transfer problem of the first data line.

[0122] refer to Figure 7 The first connecting portion is not located on opposite sides of the first display area A1 along the first direction D1, but is located on opposite sides of the second display area A2 along the second direction D2, which is different from the location of the third initialization signal line. The horizontal signal lines obtained by longitudinal compression are divided into two types: one serves as the third initialization signal line, and the other serves as the horizontal connecting line for the first data line.

[0123] Optionally, the second transfer portion is made of a second source-drain metal layer.

[0124] In the embodiment of the present invention, the second transfer portion is made of the second source-drain metal layer, and the first transfer portion is made of the first source-drain metal layer, thereby reducing the overlap capacitance on the first data line.

[0125] In the prior art, due to limitations in the switching method, overlapping capacitance is generated between the main portion of a data line and the multiple lateral switching portions included in the other multiple data lines. The switching method of the present invention is more flexible and also avoids the first data line from generating more overlapping capacitance during the switching process.

[0126] Optionally, the display panel further includes: a second data line, the second data line is configured to provide a second data voltage to the column of virtual pixel circuits, the second data line is coupled to the virtual pixel circuits, and at least part of the second data line is multiplexed as the second switching portion.

[0127] In the embodiment of the present invention, at least a portion of the second data line is reused as the second transfer portion to achieve longitudinal transfer of the first data line.

[0128] refer to Figure 7 and Figure 9 , the second data line 20 is connected to the virtual pixel circuit 5. When the virtual pixel circuit 5 is multiplexed as the first pixel circuit 1, the first data line 11 is configured to provide the first data voltage to the first pixel circuit 1. At this time, the main portion of the first data line 11 and the first light-emitting device 3 are located on the same straight line extending along the second direction. There is a certain distance between the first data line 11 and the second data line 20. The first data line 11 needs to be transferred to the second data line 20, so at least part of the second data line is multiplexed as the second transfer portion 1112 of the first data line 11.

[0129] Optionally, the display panel further includes:

[0130] a first initialization signal line, a power signal line, a first reset signal line, a first scan line, and a second scan line;

[0131] The first pixel driving circuit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a storage capacitor; wherein,

[0132] The gate of the first transistor is coupled to the first reset signal line, the first electrode of the first transistor is coupled to the first initialization signal line; the second electrode of the first transistor is coupled to the gate of the third transistor;

[0133] The first electrode of the second transistor is coupled to the second electrode of the third transistor, the second electrode of the second transistor is coupled to the gate of the third transistor, and the gate of the second transistor is coupled to the corresponding first scan line;

[0134] A first electrode of the third transistor is coupled to a second electrode of the fourth transistor, the second electrode of the third transistor is coupled to a first electrode of the sixth transistor, and a gate of the third transistor is a first plate of a storage capacitor;

[0135] A first electrode of the fourth transistor is coupled to the corresponding first data line, a second electrode of the fourth transistor is coupled to the first electrode of the third transistor, and a gate of the fourth transistor is coupled to the corresponding second scan line;

[0136] The gate of the fifth transistor is coupled to the corresponding light emitting control signal line, the first electrode of the fifth transistor is coupled to the power signal line, and the second electrode of the fifth transistor is coupled to the first electrode of the third transistor;

[0137] The gate of the sixth transistor is coupled to the corresponding light emitting control signal line, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the anode of the light emitting element;

[0138] The gate of the seventh transistor is coupled to the corresponding second reset signal line, the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor, and the first electrode of the seventh transistor is coupled to the third initialization signal line;

[0139] The first plate of the storage capacitor is reused as the gate of the third transistor, and the second plate of the storage capacitor is coupled to the power signal line.

[0140] The first pixel circuit provided by the embodiment of the present invention is a 7T1C pixel circuit, which can ensure stable display of the first light-emitting device.

[0141] refer to Figures 2 to 7 , wherein the first transistor is a first reset transistor, the second transistor is a compensation transistor, the third transistor is a driving transistor, the fourth transistor is a data writing transistor, the fifth transistor is a first light-emitting control transistor, the sixth transistor is a second light-emitting control transistor, and the seventh transistor is a second reset transistor.

[0142] The second electrode of the first reset transistor T1 is coupled to the gate of the driving transistor T3 .

[0143] The gate of the first reset transistor T1 is coupled to the first reset signal line 14;

[0144] The initialization signal line includes a first initialization signal line 15 and a second initialization signal line 13;

[0145] A first electrode of the first reset transistor T1 is coupled to the first initialization signal line 15 .

[0146] The scan lines include a first scan line 10 and a second scan line 12;

[0147] The first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and the gate of the compensation transistor T2 is coupled to the first scan line 10;

[0148] A first electrode of the data writing transistor T4 is coupled to the corresponding first data line 11, a second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3, and a gate of the data writing transistor T4 is coupled to the second scanning line 12;

[0149] The gate of the first light-emitting control transistor T5 is coupled to the corresponding light-emitting control signal line 17, the first electrode of the first light-emitting control transistor T5 is coupled to the power signal line 16, and the second electrode of the first light-emitting control transistor T5 is coupled to the first electrode of the driving transistor T3;

[0150] The gate of the second light emitting control transistor T6 is coupled to the corresponding light emitting control signal line 17, the first electrode of the second light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, the second electrode of the second light emitting control transistor T6 is coupled to the anode of the light emitting element EL, and the cathode of the light emitting element EL receives the negative power supply signal VSS;

[0151] The gate of the second reset transistor T7 is coupled to the second reset signal line 18, the second electrode of the second reset transistor T7 is coupled to the second electrode of the second light emitting control transistor T6, and the first electrode of the second reset transistor T7 is coupled to the second initialization signal line 13;

[0152] Exemplarily, the second reset signal line 18 coupled to the gate of the second reset transistor T7 in the current first pixel circuit is the same line as the first reset signal line 14 coupled to the gate of the first reset transistor T1 in the next row of first pixel circuits adjacent along the first direction.

[0153] The second initialization signal line 13 or the first initialization signal line 15 is made of a second gate metal layer.

[0154] A second aspect of the present invention provides a display device comprising the above-mentioned display panel and a photosensor, wherein the photosensor is located on the backlight side of the display panel, and the orthographic projection of the photosensor on the display panel is located within the first display area.

[0155] The display panel includes an OLED display panel, a Microled (micron light emitting diode) display panel, a QLED (Quantum-Dots Light Emitting Diode) display panel, and an LCD (Liquid Crystal Display) display panel.

[0156] The sensor is used for under-screen photography, under-screen fingerprint recognition or under-screen facial recognition.

[0157] The display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will appreciate that the structure of the above-mentioned display device does not limit the display device, and the display device may include more or fewer of the above-mentioned components, or a combination of certain components, or a different arrangement of components. In embodiments of the present invention, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0158] The display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0159] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present invention.

[0160] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, since the embodiments are generally similar to the product embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the product embodiments.

[0161] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0162] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0163] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0164] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: comprising a first display area and a second display area, wherein the second display area at least partially surrounds the first display area; The display panel includes: a base substrate and a plurality of first pixel units and a plurality of second pixel units located on the base substrate, wherein the first pixel unit includes a first light emitting device and a first pixel circuit, and the second pixel unit includes a second light emitting device and a second pixel circuit; The first light-emitting device is located in the first display area, the first pixel circuit, the second light-emitting device, and the second pixel circuit are located in the second display area, an orthographic projection of the second light-emitting device on the base substrate and an orthographic projection of the second pixel circuit on the base substrate at least partially overlap, and the first light-emitting device and the first pixel circuit are connected via a connecting trace; The first light emitting device and the second light emitting device are reset independently; The display panel further includes: a third initialization signal line and a second initialization signal line located in the second display area; The first light emitting device and the second light emitting device are reset independently, specifically: The first pixel circuit is coupled to the third initialization signal line, and the second pixel circuit is coupled to the second initialization signal line; The third initialization signal line is made of a first source-drain metal layer, and the second initialization signal line is made of a second gate metal layer.

2. The display panel according to claim 1, wherein: The third initialization signal line is configured to provide a third initialization signal to the first pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the second pixel circuit.

3. The display panel according to claim 2, wherein: An absolute value of a voltage corresponding to the third initialization signal is smaller than an absolute value of a voltage corresponding to the second initialization signal.

4. The display panel according to claim 2, wherein: The first pixel circuit and the second pixel circuit each include a seventh transistor, the third initialization signal line is coupled to a first electrode of the seventh transistor in the first pixel circuit, and the seventh transistor is coupled to the first light emitting device; The second initialization signal line is coupled to a first electrode of a seventh transistor in the second pixel circuit, and the seventh transistor is coupled to the second light emitting device.

5. The display panel according to claim 2, wherein: The display panel includes A first gate metal layer, a second gate metal layer and a first source-drain metal layer are stacked in sequence in a direction away from the base substrate. The third initialization signal line is made of the first source-drain metal layer, and the second initialization signal line is made of the second gate metal layer.

6. The display panel according to claim 5, wherein: The third initialization signal line is located in the second display area; The display panel further includes: a light emitting control signal line and a second reset signal line, wherein the light emitting control signal line is made of the first gate metal layer, and the second reset signal line is made of the first gate metal layer; An orthographic projection of the third initialization signal line on the base substrate is located between an orthographic projection of the light emission control signal line on the base substrate and an orthographic projection of the second reset signal line on the base substrate.

7. The display panel according to claim 6, wherein: The plurality of second pixel units include a plurality of second pixel circuits, the plurality of second pixel circuits are divided into a plurality of groups of second pixel circuits, each group of second pixel circuits includes N columns of second pixel circuits, and the N columns of second pixel circuits are arranged along the first direction, where N ≥ 2 and N is a positive integer; The plurality of first pixel units include a plurality of first pixel circuits, the plurality of first pixel circuits are divided into a plurality of columns of first pixel circuits, and the plurality of columns of first pixel circuits are arranged along a first direction.

8. The display panel according to claim 7, wherein: A column of first pixel circuits is arranged between two adjacent groups of the second pixel circuits.

9. The display panel according to claim 8, wherein: The display panel further includes: a first data line located in the second display area and configured to provide a first data voltage to the first pixel circuit; The first data line includes two first transfer portions and a second transfer portion, the two first transfer portions extend along the first direction, the second transfer portion extends along the second direction, the two first transfer portions are respectively connected to both ends of the second transfer portion, at least part of the first display area is located between the two first transfer portions, and the first direction and the second direction intersect with each other.

10. The display panel according to claim 9, wherein: The two first transfer portions and the third initialization signal line are made of the same layer and material; The orthographic projection of the first transition portion on the base substrate is located between the orthographic projection of the light emitting control signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

11. The display panel according to claim 9, wherein The second transfer portion is made of a second source-drain metal layer.

12. The display panel according to claim 11, wherein: The second display area further includes: a plurality of virtual pixel circuits located on the base substrate; the plurality of virtual pixel circuits are divided into a plurality of columns of virtual pixel circuits, and at least part of the virtual pixel circuits in at least one column of virtual pixel circuits are multiplexed as the first pixel circuit; The display panel further includes a second data line configured to provide a second data voltage to the column of virtual pixel circuits, and at least a portion of the second data line is multiplexed as the second switching portion.

13. The display panel according to claim 9, wherein: The display panel further includes: a first initialization signal line, a power signal line, a first reset signal line, a first scan line, and a second scan line; The first pixel driving circuit further includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor; wherein, The gate of the first transistor is coupled to the first reset signal line, the first electrode of the first transistor is coupled to the first initialization signal line; the second electrode of the first transistor is coupled to the gate of the third transistor; The first electrode of the second transistor is coupled to the second electrode of the third transistor, the second electrode of the second transistor is coupled to the gate of the third transistor, and the gate of the second transistor is coupled to the corresponding first scan line; A first electrode of the third transistor is coupled to a second electrode of the fourth transistor, the second electrode of the third transistor is coupled to a first electrode of the sixth transistor, and a gate of the third transistor is a first plate of a storage capacitor; A first electrode of the fourth transistor is coupled to the corresponding first data line, a second electrode of the fourth transistor is coupled to the first electrode of the third transistor, and a gate of the fourth transistor is coupled to the corresponding second scan line; The gate of the fifth transistor is coupled to the corresponding light emitting control signal line, the first electrode of the fifth transistor is coupled to the power signal line, and the second electrode of the fifth transistor is coupled to the first electrode of the third transistor; The gate of the sixth transistor is coupled to the corresponding light emitting control signal line, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the anode of the light emitting element; The gate of the seventh transistor is coupled to the corresponding second reset signal line, the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor, and the first electrode of the seventh transistor is coupled to the third initialization signal line; The first plate of the storage capacitor is reused as the gate of the third transistor, and the second plate of the storage capacitor is coupled to the power signal line.

14. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 13, and a photosensor, wherein the photosensor is located on the backlight side of the display panel, and the orthographic projection of the photosensor on the display panel is located within the first display area.

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