Synchronous signal transmission and reception

Abstract

Embodiments of the present disclosure describe methods and apparatuses for synchronizing signal transmission and reception.

Description

[0001] This application is a divisional application of a patent application for invention, with international application number PCT / US2017 / 068349, international filing date Dec. 22, 2017, date of entry into the national phase in China Jun. 14, 2019, national application number 201780077424.X, and title of invention "Synchronization Signal Transmission and Reception".

[0002] Cross - Reference to Related Applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 444,113, filed Jan. 9, 2017, titled "Method of Synchronization Signal Transmission and Reception", the disclosure of which is incorporated herein by reference; claims priority to U.S. Provisional Patent Application No. 62 / 467,636, filed Mar. 6, 2017, titled "Synchronization Signal Transmission and Reception", the disclosure of which is incorporated herein by reference; and claims priority to U.S. Provisional Patent Application No. 62 / 474,467, filed Mar. 21, 2017, titled "Synchronization Signal Transmission and Reception", the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0004] Embodiments of the present disclosure generally relate to the field of networks, and more particularly to apparatuses, systems, and methods for synchronization signal transmission and reception. BACKGROUND ART

[0005] In a cellular communication system, a base station may enable a device such as a user equipment (UE) to access a cellular network supported by the base station, which may also be referred to as a cell. For each cell accessible to the UE, the base station may transmit a synchronization signal (SS). To access the cell, the UE may engage in a cell search process. The cell search process may include a synchronization process that includes detection of the SS of available cells. SUMMARY OF THE INVENTION

[0006] Generally, embodiments of the present disclosure relate to synchronization signal transmission and reception and corresponding devices.

[0007] In a first aspect, an embodiment of the present disclosure provides an apparatus for a base station. The apparatus includes: processing circuitry configured to: multiply two M-sequences to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a length; and map the sequence to a number of central subcarriers within the SSS bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence; and interface circuitry coupled to the processing circuitry, the interface circuitry configured to receive the two M-sequences from a memory.

[0008] In a second aspect, an embodiment of the present disclosure provides a computer-readable medium. The computer-readable medium has instructions that, when executed by one or more processors, cause a base station to: generate a sequence for a secondary synchronization signal (SSS) based on two M-sequences, wherein the sequence has a length; and map the sequence to a number of central subcarriers within the SSS bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence.

[0009] In a third aspect, an embodiment of the present disclosure provides an apparatus for a base station. The apparatus includes: means for multiplying two M-sequences to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a length; and means for mapping the sequence to a number of central subcarriers within the SSS bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. The embodiments are illustrated by way of example and not limitation in the figures.

[0011] Figure 1 An example of the SSS structure is illustrated.

[0012] Figure 2 An example of false cell detection is illustrated.

[0013] Figure 3 An example SSS sequence mapped within the SSS bandwidth is illustrated according to some embodiments.

[0014] Figure 4 Another example SSS sequence mapped within the SSS bandwidth is illustrated according to some embodiments.

[0015] Figure 5 Another example SSS sequence mapped within the SSS bandwidth is illustrated according to some embodiments.

[0016] Figure 6 Another example SSS sequence mapped within the SSS bandwidth is illustrated according to some embodiments.

[0017] Figure 7 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments.

[0018] Figure 8 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments.

[0019] Figure 9A and Figure 9B An example SSS sequence mapping is illustrated according to some embodiments, where:

[0020] Figure 9A An example SSS sequence mapping of a length-127 sequence is illustrated; and

[0021] Figure 9B An example SSS sequence mapping of a length-255 sequence is illustrated.

[0022] Figure 10 An example operation flow / algorithm structure of a base station is illustrated according to some embodiments.

[0023] Figure 11 Another example operation flow / algorithm structure of a base station is illustrated according to some embodiments.

[0024] Figure 12 Another example operation flow / algorithm structure of a base station is illustrated according to some embodiments.

[0025] Figure 13 An example detection of a transmitted SSS sequence is illustrated according to some embodiments.

[0026] Figure 14 An example operation flow / algorithm structure of a UE is illustrated according to some embodiments.

[0027] Figure 15 Another example operation flow / algorithm structure of a base station is illustrated according to some embodiments.

[0028] Figure 16 Another example operation flow / algorithm structure of a UE is illustrated according to some embodiments.

[0029] Figure 17 An example system architecture of a network is illustrated according to some embodiments.

[0030] Figure 18 An example component of a device is illustrated according to some embodiments.

[0031] Figure 19 An example interface of a baseband circuit is illustrated according to some embodiments.

[0032] Figure 20is a block diagram illustrating example components according to some embodiments. Detailed Description

[0033] The following detailed description refers to the accompanying drawings. The same reference numerals may be used in different drawings to identify the same or similar elements. In the following description, for purposes of illustration and not limitation, specific details such as particular structures, architectures, interfaces, techniques, etc. are set forth in order to provide a thorough understanding of various aspects of the claimed embodiments. However, those skilled in the art having the benefit of this disclosure will appreciate that the various aspects of the claimed embodiments may be implemented in other examples without these specific details. In some instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the embodiments of the present disclosure with unnecessary detail.

[0034] The various aspects of the illustrative embodiments will be described using terms that are ordinarily used by those skilled in the art to convey the substance of their work to others in the art. However, those skilled in the art will appreciate that alternative embodiments may be implemented using only some of the aspects described. For purposes of illustration, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the illustrative embodiments. However, those skilled in the art will appreciate that alternative embodiments may be implemented without these specific details. In other instances, well-known features are omitted or simplified so as not to obscure the illustrative embodiments.

[0035] In addition, the various operations will be described sequentially as a number of discrete operations in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations do not need to be performed in the order presented.

[0036] The phrases “in various embodiments,” “in some embodiments,” etc. are used repeatedly. Generally, this phrase does not refer to the same embodiment; however, it may refer to the same embodiment. The terms “comprising,” “having,” and “including” are synonyms unless the context dictates otherwise. The term “A or B” means (A), (B), or (A and B).

[0037] Example embodiments may be described as a process depicted as a flowchart, a job diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be rearranged. The process may terminate when its operations are completed, but may also have additional operations not included in the figures. The process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When the process corresponds to a function, its termination may correspond to the function returning to the calling function and / or the main function.

[0038] As used herein, the term "processor circuit" refers to a circuit, is part of a circuit, or includes a circuit that can sequentially and automatically perform a sequence of arithmetic or logical operations; record, store, and / or transmit digital data. The term "processor circuit" can refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core processor, a dual-core processor, a triple-core processor, a quad-core processor, and / or any other device capable of executing or otherwise operating on computer-executable instructions such as program code, software modules, and / or functional procedures. As used herein, the term "interface circuit" refers to a circuit, is part of such a circuit, or includes a circuit that supports information exchange between two or more components or devices. The term "interface circuit" can refer to one or more hardware interfaces (e.g., a bus, an input / output (I / O) interface, a peripheral component interface, etc.).

[0039] As used herein, the term "user equipment" or "UE" may be considered synonymous with client, mobile phone, mobile device, mobile terminal, user terminal, mobile unit, mobile station, mobile user, subscriber, user, remote station, access agent, user agent, receiver, etc. and will occasionally be referred to by these terms hereinafter, and can describe a remote user of network resources in a communication network. Additionally, the term "user equipment" or "UE" can include, for example, any type of wireless / wired device such as a consumer electronic device, a cellular phone, a smart phone, a tablet personal computer, an Internet of Things ("IoT") device, a smart sensor, a wearable computing device, a personal digital assistant (PDA), a desktop computer, and a laptop computer.

[0040] As used herein, the term "base station" may be considered synonymous with an access node (AN) or may occasionally be referred to hereinafter as an access node, which may be referred to as a base station (BS), NodeB, evolved NodeB (eNB), next Generation NodeB (gNB), radio access node (RAN) node, etc., and may include a terrestrial station (e.g., a terrestrial access point) or a satellite station providing coverage within a certain geographical area (e.g., a cell). A base station may be a device compliant with a cellular communication protocol, such as the Global System for Mobile Communications (GSM) protocol, the code-division multiple access (CDMA) network protocol, the Push-to-Talk (PTT) protocol, the PTT over Cellular (POC) protocol, the Universal Mobile Telecommunications System (UMTS) protocol, the 3GPP Long Term Evolution (LTE) protocol, the fifth generation (5G) protocol, or a protocol compliant with other existing generations, generations under development, or generations to be developed in the future (e.g., the second generation (2G), the sixth generation (6G), etc.), the New Radio (NR) protocol, etc.

[0041] As described in more detail hereinafter, the SS may enable the UE to detect and identify the cell to which it is connected. Additionally, the SS may be used to correct frequency offsets and find orthogonal frequency division multiplex (OFDM) symbol boundaries or transmission subframe boundaries. For example, the SS may roughly correct the frequency offset between the transmitter and the receiver and may derive a rough timing estimate. The timing estimate may be used to determine the OFDM symbol boundaries and subframe boundaries. A transmission subframe may refer to the smallest number of groups of OFDM symbols available for control and data transmission. This may be referred to as a scheduling unit.

[0042] A UE can communicate with a base station to access a cell supported by the base station. Downlink communication may refer to the communication link from the base station to the UE, and uplink communication may refer to the communication link from the UE to the base station. The UE and the base station can send data at the physical layer (also referred to as the PHY layer) of their network protocol stacks such as the Open Systems Interconnection (which may be referred to as OSI) or the Transmission Control Protocol / Internet Protocol (which may be referred to as TCP / IP). The channels defined for the physical layer in the downlink may include the physical broadcast channel (PBCH). The PBCH may be a physical channel that carries the system information used by the UE to access the network.

[0043] The detection of the SS can provide the physical cell identity of the available cells to the UE. The SS may include multiple components, such as including the primary synchronization signal (PSS), the secondary synchronization signal (SSS), and possibly including the tertiary synchronization signal (TSS). To access a cell, the UE may engage in a cell search process. At the physical layer, the cell search process may include the detection of the SS, and thus include the detection of the SSS. The SSS may be a signal defined for the physical layer in the downlink, which may include the physical cell identity of the available cells.

[0044] Figure 1 An example of the SSS structure is illustrated. Figure 1 The SSS structure in rd may comply with the Long Term Evolution (LTE) standard of the 3rd Generation Partnership Project (3GPP). As Figure 1 shown, the LTE SSS structure 100 may include two maximum length sequences (M-sequences) x1 to x N and y1 to y N interleaved in the SS bandwidth. As Figure 1 shown, the SSS structure 100 may also include several guard subcarriers before and after the interleaved M-sequences.

[0045] An M-sequence (which may also be referred to as a maximum length sequence) can be a type of pseudo-random sequence (which may also be referred to as a pseudo-random binary sequence), which can be created by cycling through the possible states of a shift register of a certain length and can generate a sequence of that length. The M-sequence can have a length of L bits, each bit can have a value of 0 or 1, and the M-sequence can repeat after every L bits. Thus, for example, an M-sequence with a length L of 255 can have a 255-bit sequence that repeats itself after every 255 bits. Two M-sequences in the SSS can be interleaved in the following sense, for example: both M-sequences can be mapped in the SS bandwidth, mapping a part of each M-sequence in an alternating manner, as Figure 1 shown. Since the SSS structure can include two interleaved M-sequences, a UE that receives the SSS from multiple cells simultaneously can have a problem of false cell detection.

[0046] Figure 2 illustrates an example of false cell detection. As Figure 2 shown, four cells can each provide a cell identity to UE 200, and the cell identity includes two information components in the SSS, one representing a first sequence and the other representing a second sequence interleaved with the first sequence. For each of the first and second sequences, a sequence for the cell is selected from the sequence pools for the first and second sequences respectively. For example, the first and second M-sequences can be {1,1} for cell #1 202, {1,2} for cell #2 204, {2,3} for cell #3 206, and {3,3} for cell #4 208. For a cell, {X,Y} refers to the Xth sequence in the sequence pool for the first sequence and the Yth sequence in the sequence pool for the second sequence.

[0047] If UE 200 detects a non-existent cell, a problem of false cell detection can occur, where UE 200 can combine the sequence index of one detected cell with the sequence index of another different detected cell to detect the cell identity of the non-existent cell. For example, Figure 2 the UE200 in can detect a first sequence of 1 and a second sequence of 3, obtaining a cell identity of {1,3}, which is not the cell identity of any of the four cells that sent the cell identity to UE 200. This can occur, for example, when one cell, such as cell #1 202 or cell #2 204, sends 1 as the first sequence, and another cell, such as cell #3 206 or cell #4 208, sends 3 as the second sequence. As a result, UE 200 can create a cell with a cell identity of {1,3} that can be referred to as a phantom cell, and thus has a problem of false cell detection, where UE 200 can detect a non-existent cell as one of the cells that sent the cell identity to UE 200.

[0048] Embodiments herein may include an SSS structure that may include a single long sequence that may span the SS bandwidth. The single long sequence may be generated, for example, by combining multiple M sequences and, for example, using a complex scrambling code. Embodiments herein may include an SS that includes a sequence of length N that may occupy the central N subcarriers of the SS bandwidth, where a sequence may be generated from one of a plurality of primitive polynomials of the M sequence. In various embodiments, the SSS structure may be generated from one or more primitive polynomials. In one embodiment, a primitive polynomial may be a polynomial that cannot be factored into the product of two polynomials, has a non-zero constant term, and has an odd number of terms (except for the primitive polynomial x + 1). The SSS structure generated from one or more primitive polynomials may prevent or reduce the occurrence of spurious cell detection, among other things, because a single sequence is sent to the UE instead of two interleaved M sequences. Additionally or alternatively, such an SSS structure may provide a large cell identity. The large cell identity may, for example, increase the number of available physical cell identities. Although the embodiments described herein may relate to the generation of the SSS, such embodiments may be applied to the generation of any component of the SS, including but not limited to, for example, the PSS or the TSS.

[0049] Figure 3 Example SSS sequences mapped within the SS bandwidth are illustrated according to some embodiments. In one embodiment, an M sequence may be selected from a set of M sequences and mapped within the SS bandwidth. In one embodiment, an M sequence of length L may be generated from a primitive polynomial G(x) (such as x 7 + x + 1) and mapped to the L central subcarriers of the SS bandwidth, where each bit may be modulated using binary phase shift keying (BPSK) modulation to provide the modulated bits x1 to x N of the SSS sequence 300. Although the embodiments herein may be described in terms of M sequences as pseudo-random sequences, the embodiments herein are not limited to M sequences. Other types of pseudo-random sequences may be used, such as but not limited to pseudo-random sequences generated from gold codes or pseudo-random sequences generated from Kasami codes. Additionally, although the embodiments herein are described in terms of BPSK modulation, the embodiments herein are not limited to BPSK modulation. Other types of modulation may be used, such as but not limited to quadrature phase shift keying (QPSK) modulation.

[0050] If Figure 3If the structure in 7 is used to generate the SSS, different cell identities can be represented by different cyclic shift versions of the M sequence. As a result, a transmitter (e.g., a base station) can indicate L different cell identities. Additionally, to provide more information bits, the selected M sequence can be from one of multiple primitive polynomials. For example, the transmitter can provide 3L different cell identities by transmitting one of the following three primitive polynomials as one of the L cyclic shift versions: G1(x) = x 7 + x + 1, G2(x) = x 3 + x 7 + 1, and G3(x) = x 3 + x 2 + x + 1. For example, if the length L equals 127, an M sequence is used, and 3 primitive polynomials are used in the set of M sequences, the polynomial index P ID can be derived from the cell identity (also referred to as cell ID) N ID as P ID = floor(N ID / L), and the cyclic shift (also referred to as CS) value of the selected M sequence can be derived from the cell ID as CS = (N ID ) mod L. The cyclic shift value can also be referred to as the cyclic shift parameter.

[0051] Figure 4 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments.

[0052] In one embodiment, as shown in Figure 4 , the M sequence can be mapped to every Kth subcarrier within the central K x N subcarriers, where the modulated bits x1 to x N of the SSS sequence 400 are mapped to every other subcarrier. In another embodiment, depending on the primitive polynomial used to generate the M sequence, the M sequence is mapped with a different subcarrier offset, where the modulated bits y1 to y N of the sequence 402 are mapped as shown.

[0053] Figure 5 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments. In one embodiment, the M sequence can be multiplied by a repeated complex scrambling code and mapped within the SS bandwidth. In one embodiment, an M sequence of length N can be generated from a primitive polynomial G(x) such as (x7 + x + 1) and BPSK modulated. Additionally, each BPSK modulated bit x1 to x NN central sub - carriers that can be mapped to the SS bandwidth, where each occupied sub - carrier can be multiplied by a real - valued 502 or a complex - valued 504, which can generate a BPSK - modulated M - sequence scrambled by a complex scrambling sequence.

[0054] If this structure is used to generate the SSS, different cell identities can be mapped to different cyclic - shift versions of the M - sequence. As a result, a transmitter (e.g., a base station) can indicate L different cell identities. Additionally, to provide more information bits, the selected M - sequence can, according to one embodiment, be from one of a plurality of primitive polynomials. M - sequences generated from different primitive polynomials can be multiplied by different complex scrambling sequences. For example, the transmitter can provide 2L different cell identities by transmitting one of the L cyclic - shift versions of one of the following two primitive polynomials: G1(x)=x7 + x + 1, and G2(x)=x7 + x6 + 1. The M - sequence generated using G1(x) can be BPSK - modulated and mapped to the central N sub - carriers of the SS bandwidth, while the M - sequence generated using G2(x) can be BPSK - modulated and scrambled using a repeated {+1,+j} complex scrambling sequence.

[0055] Figure 6 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments. In one embodiment, two M - sequences 600 and 604 can be mapped to the in - phase constellation and the quadrature constellation of the sub - carriers within the SS bandwidth, where the M - sequence 600 can be multiplied by a complex - valued 602, e.g., j, and the M - sequence 604 can be multiplied by a real - valued 606, e.g., 1.

[0056] In one embodiment, two M - sequences of length N can be generated from primitive polynomials G1(x) and G2(x) such as x 7 +x + 1 and x 7 +x 6 +1, and the BPSK - modulated bits z1 to z N of the SSS sequence 608 from the first and second primitive polynomials can be mapped to the in - phase and quadrature constellations of the N central sub - carriers of the SS bandwidth, which can generate a QPSK - modulated sequence.

[0057] If this structure is used for the SSS, different cell identities can be determined by two cyclic - shift versions of the two M - sequences. As a result, the transmitter can indicate L 2 different cell identities, which can increase the available number of cell IDs.

[0058] Figure 7 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments. In one embodiment, two M - sequences are subjected to a bit - by - bit exclusive - OR (XOR) calculation and mapped within the SS bandwidth, as Figure 7As shown, this may equivalently illustrate the SSS generated by performing a modulated symbol-by-symbol multiplication on two BPSK-modulated M sequences. In one embodiment, two M sequences 700 and 702 of length N may be derived from primitive polynomials G1(x) and G2(x), such as x 7 +x+1 and x 7 +x 6 +1, and the two M sequences 700 and 702 may be bitwise XOR computed, and the scrambled (i.e., XOR operation) sequence may be BPSK modulated to provide the modulated bits z1 to z N of the SSS sequence 704, and mapped to N central subcarriers of the SS bandwidth. Equivalently, two M sequences 700 and 702 of length N may be derived from primitive polynomials G1(x) and G2(x), such as x 7 +x+1 and x 7 +x 6 +1, and the two M sequences 700 and 702 may be BPSK modulated, and the modulated sequences may be multiplied with each other for each modulated symbol to provide the modulated bits z1 to z N of the SSS sequence 704, and mapped to N central subcarriers of the SS bandwidth.

[0059] If this structure is used for the SSS, different cell identities may be determined by two cyclic shift versions of the two M sequences. As a result, the transmitter may indicate L 2 different cell identities, thereby increasing the available number of cell IDs.

[0060] In one embodiment, two primitive polynomials may be selected to obtain good cross-correlation properties between two different SS sequences. Examples of primitive polynomial pairs are shown in Table 1.

[0061] Table 1. Primitive Polynomials

[0062]

[0063] In one embodiment, the sequence d(0),…,d(L-1) that may be used for the secondary synchronization signal may be a gold sequence, which may be a bitwise XOR of two length-127 binary M sequences respectively generated from G1(x) and G2(x) primitive polynomials.

[0064] The gold-like sequence d(n) as the SSS may be defined as:

[0065] d(n)=(1–2·((c0(n)+c1(n))mod2), n = 0,…L.

[0066] Two sequences c0(n) and c1(n) are defined as two different cyclic shifts of M sequences s0(n) and s1(n) according to the following equations:

[0067] c0(n) = s0((n + m0) mod L),

[0068] c1(n) = s1((n + m1) mod L),

[0069] where s0(n) and s1(n) are M sequences generated from primitive polynomials G1(x) and G2(x) respectively.

[0070] Physical cell ID N ID can be determined by the following equation:

[0071] N ID = L·m0 + m1,

[0072]

[0073] m1 = 0, …, L - 1.

[0074] When L = 127, s0(n) and s1(n) can be M sequences generated from G1(x) = x 7 + x 3 + 1 and G2(x) = x 7 + x 3 + x 2 + x + 1 respectively. Both M sequences can be generated using the initial condition {0,0,0,0,0,1}.

[0075] The following can be the sequence s0(n) of length 127:

[0076] {1,0,0,0,0,0,0,1,0,0,0,1,0,0,1,1,0,0,0,1,0,1,1,1,0,1,0,1,1,0,1,1,0,0,0,0,0,1,1,0,0,1,1,0,1,0,1,0,0,1,1,1,0,0,1,1,1,1,0,1,1,0,1,0,0,0,0,1,0,1,0,1,0,1,1,1,1,1,0,1,0,0,1,0,1,0,0,0,1,1,0,1,1,1,0,0,0,1,1,1,1,1,1,1,0,0,0,0,1,1,1,0,1,1,1,1,0,0,1,0,1,1,0,0,1,0,0}.

[0077] The above equation can be provided in the following recursive form:

[0078] s(n + 7) = (s(n + 3) + s(n)) mod 2, 0 ≤ n ≤ 127,

[0079] where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0

[0080] The following could be the sequence s1(n) of length 127:

[0081] {1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 1}.

[0082] The above formula can be provided in the following recursive form:

[0083] s(n + 7) = (s(n + 3) + s(n + 2) + s(n + 1) + s(n)) mod 2, 0 ≤ n ≤ 127,

[0084] where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

[0085] When L = 255, s0(n) and s1(n) can be M - sequences respectively generated from primitive polynomials such as G1(x) = x 8 + x 7 + x 6 + x 5 + x 2 + x + 1 and G2(x) = x 8 + x 7 + x 6 + x + 1. Both M - sequences can be generated using the initial condition {0, 0, 0, 0, 0, 0, 1}.

[0086] The following could be the sequence s0(n) of length 255:

[0087] {1,0,0,0,0,0,0,0,1,1,0,0,1,1,1,1,1,0,1,0,0,0,1,1,0,1,1,0,1,0,1,0,1,0,1,1,0,1,0,0,1,1,0,0,0,1,0,1,0,0,1,0,0,1,0,0,0,1,0,0,0,1,1,1,0,1,0,0,1,0,1,0,0,0,1,0,,1,1,1,1,0,1,0,1,1,1,1,1,0,0,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1,0,1,1,1,0,0,1,1,0,1,0,0,0,0,0,0,1,0,1,0,1,0,0,0,0,1,1,1,0,0,1,0,1,1,0,1,1,1,1,1,1,1,1,0,1,1,1,0,1,0,1,0,0,1,1,1,1,0,1,1,0,1,1,0,0,1,1,0,0,1,0,0,1,1,1,0,1,1,1,1,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,0,1,1,0,0,0,1,1,0,0,0,0,1,1,0,1,0,1,1,0,0,1,0,1,0,1,1,1,0,0,0,0,0,1,1,1,1,1,1,0,0,0,1,0,0,1,0,1,1,1,0,1}。

[0088] The above formula can be provided in the following recursive form:

[0089] s(n + 8) = (s(n + 7) + s(n + 6) + s(n + 5) + s(n + 2) + s(n + 1) + s(n)) mod 2, 0 ≤ n ≤ 255,

[0090] where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = s(7) = 0.

[0091] The sequence s1(n) can be provided in the following recursive form:

[0092] s(n + 8) = (s(n + 7) + s(n + 6) + s(n + 1) + s(n)) mod 2, 0 ≤ n ≤ 255,

[0093] where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = s(7) = 0.

[0094] This can generate the following sequence of length 255:

[0095] {1,0,0,0,0,0,0,0,1,1,0,1,1,0,1,0,1,0,0,0,1,0,0,1,0,1,1,1,1,0,0,1,0,1,0,0,0,1,0,0,0,1,1,0,0,1,1,0,0,0,1,1,1,0,0,0,0,1,1,0,0,0,0,0,1,1,1,0,1,1,0,0,0,0,1,0,1,0,1,1,0,0,1,0,0,1,1,1,0,0,1,1,1,0,1,0,1,0,1,1,1,1,1,1,1,1,0,1,1,0,1,1,0,0,1,1,1,1,0,0,0,1,1,0,1,0,1,1,1,0,0,1,0,0,0,0,1,1,1,1,0,1,1,1,0,1,1,1,1,0,1,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,1,0,1,1,1,1,1,0,0,1,1,0,1,1,1,0,0,0,1,0,1,1,1,0,1,0,0,1,1,0,0,1,0,1,0,1,0,1,0,0,1,0,0,1,0,0,0,1,0,1,0,0,0,0,1,0,0,1,1,0,1,0,0,0,1,1,1,1,1,0,1,0,1,1,0,1,0,0,1,0,1,0,0,1,1,1,1,1}。

[0096] In another embodiment, the SSS can be composed of the multiplication of two sequences. The first sequence can be determined by the sequence for the PSS and the PSS index. For example, if 3 sequences are available for the PSS, the PSS index can be 0, 1, and 2. Based on the PSS index, the first sequence can be determined. For example, if the first sequence is based on the M sequence, the PSS index can determine the cyclic shift of the M sequence (or equivalently, the initial state of the M sequence) for the first sequence. The second sequence that can be XORed bit-by-bit (or equivalently, multiplied symbol-by-symbol when each bit is BPSK modulated) with the first sequence can be selected from a set of sequences that can be generated using one or more polynomials. For example, for the length-127 sequence for the second sequence, one or more primitive polynomials can be selected from Table 2. In one embodiment, when both the first sequence and the second sequence are M sequences, the selected polynomial for the first sequence and the polynomial pool for the second sequence can be different polynomials (all different primitive polynomials).

[0097] Table 2. Primitive Polynomials for M Sequences

[0098]

[0099] For example, three sets of polynomials can be used, G0(x) = x8 +x 7 +x 6 +x 1 +1, G1(x) = x 8 +x 7 +x 2 +x 1 +1 and G2(x) = x 8 +x 7 +x 5 +x 3 +1. The polynomial G0(x) can be used to generate the first sequence, where it is initialized with {0,0,0,0,0,0,0,1} and cyclically shifted by the PSS index. The polynomials G1(x) and G2(x) can be used to generate a set of sequences, where they can be initialized with {0,0,0,0,0,0,0,1}. Depending on the cell ID, one of the sequences generated from G1(x) and G2(x) can be selected. The cell ID can also be determined by the cyclic shift of the selected sequence.

[0100] In the above example, the cell ID N ID , S ID can be calculated by the combination of two values P ID : N ID = P ID + 3*S ID , where P ID is the PSS index, and S ID is the SSS index. The group index F can determine the polynomial of the second sequence and can be calculated by F = floor(S ID / L), where L is the length of the second M sequence. For the above, L = 255. The second sequence can be generated by the G F (x) polynomial, and the cyclic shift value CS can be determined by CS = (S ID ) mod L. This may be able to support up to 2x255x3 = 1530 cell IDs.

[0101] The embodiments herein can reduce the peak-to-average-power ratio (PAPR) or cubic metric (CM) of the transmitted signal. The transmitted signal in an OFDM system can experience high fluctuations in amplitude, which can affect the power capabilities of cellular network communication devices. PAPR and CM can be used to determine the amplitude fluctuations in an OFDM signal. The generation of the SSS according to the embodiments herein can reduce the PAPR or CM of the transmitted signal.

[0102] According to the embodiments herein, for example, in combination with Figure 7 described herein, the generation of SSSd(n) using two M sequences can be described as follows:

[0103]

[0104] or equivalently

[0105]

[0106] Two sequences c0(n) and c1(n) can be defined as two different cyclic shifts of M sequences s0(n) and s1(n) according to, for example, the following equations:

[0107]

[0108]

[0109] where s0(n) and s1(n) are M sequences generated from primitive polynomials G1(x) and G2(x), respectively. The initial state of the M sequence can be set to s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0 for a sequence length of 127, and can be set to s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = s(7) = 0 for a sequence length of 255.

[0110] Physical cell ID N ID can be determined by the following equation:

[0111] N ID = L·m0 + m1,

[0112]

[0113] m1 = 0, ···, L - 1.

[0114] In one embodiment, the first M sequence generated by G1(x) can use a finite set of cyclic shifts, while the second M sequence generated by G2(x) can use all sets of cyclic shifts. If the first M sequence uses a finite set of cyclic shifts, then the PAPR or CM of the described SSS can be optimized based on, for example, the choice of the primitive polynomial of the M sequence and the cyclic shift of the first M sequence.

[0115] According to the embodiments herein (including, for example, in combination with Figure 7 as described), the SSS design for optimizing PAPR or CM can be described as:

[0116]

[0117] or equivalently

[0118]

[0119] Two sequences c0(n) and c1(n) can be defined as two different cyclic shifts of M sequences s0(n) and s1(n) according to the following equations:

[0120]

[0121]

[0122] where s0(n) and s1(n) can be M sequences generated from primitive polynomials G1(x) and G2(x) respectively.

[0123] Physical cell ID N ID can be determined by the following equation:

[0124] N ID = L·m0 + m1,

[0125]

[0126] m1 = 0, ···, L - 1.

[0127] N CS and N OFFSET values can be optimization parameters, where N CS represents the gap between two cyclic shifts, and N OFFSET is the cyclic shift offset.

[0128] Table 3 includes a list of primitive polynomials for M sequences of length 127 and their mapping to polynomial indices according to some embodiments. According to some embodiments, this polynomial index can be used in Table 4 and Table 5.

[0129] Table 3. List of candidate primitive polynomials for M sequences of length 127

[0130] Polynomial Index Polynomial 1 x^7 + x^1 + 1 2 x^7 + x^3 + 1 3 x^7 + x^3 + x^2 + x^1 + 1 4 x^7 + x^4 + 1 5 x^7 + x^4 + x^3 + x^2 + 1 6 x^7 + x^5 + x^2 + x^1 + 1 7 x^7 + x^5 + x^3 + x^1 + 1 8 x^7 + x^5 + x^4 + x^3 + 1 9 x^7 + x^5 + x^4 + x^3 + x^2 + x^1 + 1 10 x^7 + x^6 + 1 11 x^7 + x^6 + x^3 + x^1 + 1 12 x^7 + x^6 + x^4 + x^1 + 1 13 x^7 + x^6 + x^4 + x^2 + 1 14 x^7 + x^6 + x^5 + x^2 + 1 15 x^7 + x^6 + x^5 + x^3 + x^2 + x^1 + 1 16 x^7 + x^6 + x^5 + x^4 + 1 17 x^7 + x^6 + x^5 + x^4 + x^2 + x^1 + 1 18 x^7 + x^6 + x^5 + x^4 + x^3 + x^2 + 1

[0131] Table 4 shows an example list of the maximum cubic metric (CM) values of the SSS for various values of N CS 、N OFFSET and primitive polynomials according to some embodiments. Table 4 lists parameter sets from a randomly selected set of parameters from the smallest maximum CM to the highest maximum CM. According to some embodiments, different selections of the primitive polynomial and N CS 、N OFFSET parameters can produce a wide range of maximum CM values. Therefore, according to some embodiments, the selection of the primitive polynomial and cyclic shift parameters can optimize the PAPR and CM of the SSS.

[0132] Table 4. Maximum CM of SSS using two M sequences of length 127

[0133]

[0134]

[0135] In some embodiments, for a sequence length of 127, the SSS may be optimized for the cross - correlation profile between two SSS sequences that may belong to different cell identities.

[0136] Table 5 shows the minimum and maximum cross - correlations of parameter sets that may have low maximum CM and PAPR according to some embodiments. For example, Table 5 shows that G1(x)=x CS = 1 and N OFFSET = 0 gives G1(x)=x 7 + x 6 + x 4 + x + 1 and G2(x)=x 7 + x 5 + x 3 + x + 1 can produce low PAPR and CM profiles while maintaining a low cross - correlation profile.

[0137] Table 5. Cross - correlation analysis of SSS designs of length 127 with different polynomials and N CS and N OFFSET parameters

[0138]

[0139] Table 6 includes the primitive polynomials for M - sequences of length 127 and the mapping to polynomial indices according to some embodiments. According to some embodiments, this polynomial index can be used in conjunction with Tables 7 and 8.

[0140] Table 6. List of candidate primitive polynomials for M - sequences of length 255

[0141]

[0142]

[0143] Table 7 shows an example list of the maximum CM values of SSSs with various values of N CS , N OFFSET and primitive polynomials for a sequence length of 255. According to some embodiments, this table includes parameter sets from a randomly selected set of parameters, from the minimum maximum CM to the highest maximum CM. According to some embodiments, Table 7 shows the primitive polynomials and N CS , N OFFSETDifferent choices of parameters can result in a wide range of maximum CM values. Thus, according to some embodiments, the selection of the primitive polynomial and the cyclic shift parameter can optimize the PAPR and CM of the SSS.

[0144] Table 7. Maximum CM of SSS using two M-sequences of length 255

[0145]

[0146]

[0147] In some embodiments, the SSS can be optimized for the cross-correlation profile between two SSS sequences that can belong to different cell identities. Table 8 indicates, according to some embodiments, the minimum and maximum cross-correlations of parameter sets that can have low maximum CM and PAPR. For example, Table 8 shows that for G1(x) = x CS = 7 and N OFFSET = 11, and G2(x) = x 8 + x 7 + x 6 + x 5 + x 2 + x + 1 and G2(x) = x 8 + x 7 + x 6 + x 3 + x 2 + x + 1 can result in low PAPR and CM profiles while maintaining a low cross-correlation profile.

[0148] Table 8. Cross-correlation analysis of SSS designs of length 255 with different polynomials and N CS and N OFFSET parameters

[0149]

[0150]

[0151] Figure 8 Another example SSS sequence mapped within the SS bandwidth is illustrated according to some embodiments. In one embodiment, the SSS sequence 804 can be a hybrid of the SSS generation described in conjunction with Figure 3 and the SSS generation described in conjunction with Figure 7 where the first M-sequence 800 can be generated based on the PSS index and the second M-sequence 802 can be selected from a pool of M-sequences generated with a primitive polynomial, and the two M-sequences can be bitwise XORed or modulated and symbol-wise multiplied.

[0152] Figure 9A and Figure 9BAn example SSS sequence mapping is illustrated according to some embodiments. Downlink and uplink transmissions may be organized into frames, which may be divided into time slots, which may include symbols. Symbols may include resource blocks, and resource blocks may include resource elements. Resource elements, which may also be referred to as tones, may be the underlying data carriers in a frame and may thus include data from a signal.

[0153] The PSS and SSS may be transmitted from a base station to a UE in a synchronization signal and PBCH block, which may correspond to the SS bandwidth. The synchronization signal and PBCH block may include OFDM symbols and a number of consecutive subcarriers corresponding to the OFDM symbols, where the PSS and SSS may be spread across several subcarriers for transmission to the UE. The PSS and SSS may have a certain relationship in terms of their relative positions in the SS bandwidth. The base station may modulate data symbols for transmission on the PBCH.

[0154] Reference Figure 9A , for example, for a sequence of length 127, the SSS sequence d(n) may be mapped to resource elements according to the following equation:

[0155] a k,l+1 = d(n), n = 0, … 127

[0156] k = n – 64.

[0157] The PSS may be mapped to symbol l + 1 of the SS block.

[0158] The resource elements (k, l) in an OFDM symbol may be used for transmission of the PSS, where k = -72, -71, …, -65, 64, 65, …, 72 may be reserved and not used for transmission of the PSS, and may include 127 tones 900A, nine tones 902A before the 127 tones 900A, and eight tones 904A after the 127 tones 900A.

[0159] Reference Figure 9B , which illustrates another example sequence mapping according to some embodiments. For example, for a sequence of length 255, the SSS sequence d(n) may be mapped to resource elements according to the following equation:

[0160] a k,l+1 = d(n), n = 0, … 255

[0161] k = n – 128.

[0162] The PSS may be mapped to symbol l + 1 of the SS block.

[0163] The resource element (k, l) in the OFDM symbol can be used for the transmission of the PSS, where k = -143, -142, …, -129, 128, 129, …, 143 can be reserved and not used for the transmission of the PSS, and it can include 255 tones 900B, nine tones 902B before the 255 tones 900B, and eight tones 904B after the 255 tones 900B.

[0164] An antenna port can be a logical entity rather than a physical entity. For example, multiple antenna port signals can be transmitted on a single physical transmit antenna. Additionally, multiple antenna port signals can be transmitted on multiple physical transmit antennas. In one embodiment, the same antenna port can be used for both the PSS and the SSS.

[0165] Figure 10 Examples of the operational flow / algorithm structure of a base station are illustrated according to some embodiments. In the embodiments herein, the base station can be a gNB compliant with the 5G protocol or a base station compliant with a generation under development or a generation to be developed in the future (such as 6G, etc.). However, the embodiments herein are not limited to such base stations.

[0166] The operational flow / algorithm structure 1000 can include determining an M sequence of a certain length based on a primitive polynomial at 1002. In one embodiment, determining an M sequence of that length based on a primitive polynomial can include selecting an M sequence from a set of M sequences that are generated from a set of primitive polynomials. In another embodiment, determining an M sequence of that length based on a primitive polynomial can include generating an M sequence of that length based on the primitive polynomial, where the operational flow / algorithm structure 1000 can further include multiplying each central subcarrier by a repeated complex scrambling sequence. The operational flow / algorithm structure 1000 can further include performing a cyclic shift of the M sequence at 1004 to generate a cyclically shifted M sequence. The operational flow / algorithm structure 1000 can further include modulating the cyclically shifted M sequence using BPSK modulation at 1006 to generate the BPSK - modulated bits of the SSS sequence. The operational flow / algorithm structure 1000 can further include mapping the BPSK - modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth for transmission at 1008, where the number of central subcarriers corresponds to the length of the M sequence.

[0167] Figure 11 Another example of the operational flow / algorithm structure of a base station is illustrated according to some embodiments. The operational flow / algorithm structure 1100 can include generating two M sequences based on two different primitive polynomials at 1102, where each M sequence has a certain length. In one embodiment, the operational flow / algorithm structure 1100 can further include receiving two different primitive polynomials from a memory.

[0168] In one embodiment, the length may be, for example, 127. In another embodiment, the length may be, for example, 255.

[0169] The operation flow / algorithm structure 1100 may further include performing a cyclic shift of the M sequence at 1104 to generate two cyclic-shifted M sequences. In one embodiment, the cyclic shift may be based on the identity of the cellular network. In one embodiment, the operation flow / algorithm structure 1100 may further include performing a bitwise XOR operation on the two cyclic-shifted M sequences. The operation flow / algorithm structure 1100 may further include modulating the two cyclic-shifted M sequences using BPSK modulation at 1106 to generate the BPSK-modulated bits of the SSS sequence. In one embodiment, the operation flow / algorithm structure 1100 may further include performing a post-modulation symbol-wise multiplication on the BPSK-modulated bits of the two cyclic-shifted M sequences.

[0170] The operation flow / algorithm structure 1100 may further include mapping the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth at 1108 for transmission, where the number of subcarriers corresponds to the length of the M sequence. In one embodiment, the operation flow / algorithm structure 1100 may further include multiplying the first M sequence of the two M sequences by a complex value to provide a complex-valued M sequence, and multiplying the second M sequence of the two M sequences by a real value to provide a real-valued M sequence multiplication sequence. In one embodiment, mapping the modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth may further include mapping the BPSK-modulated bits of the complex-valued M sequence to the in-phase constellation of the central subcarriers of the SS bandwidth, and mapping the BPSK-modulated bits of the real-valued M sequence to the quadrature constellation of the central subcarriers of the SS bandwidth. In another embodiment, the BPSK-modulated bits of the real-valued M sequence may be mapped to the in-phase constellation of the central subcarriers of the SS bandwidth, and the BPSK-modulated bits of the complex-valued M sequence may be mapped to the quadrature constellation of the central subcarriers of the SS bandwidth.

[0171] Figure 12 Another example operation flow / algorithm structure of a base station is illustrated according to some embodiments. The operation flow / algorithm structure 1200 may include multiplying two cyclic-shifted BPSK-modulated M sequences at 1202 to generate a sequence for the SSS, where the sequence has a certain length. The operation flow / algorithm structure 1200 may further include mapping the sequence to N central subcarriers of the SS bandwidth at 1204 for transmission, where the number of subcarriers N corresponds to the length of the sequence. In one embodiment, the central subcarriers may be central consecutive subcarriers.

[0172] In one embodiment, multiplying the two cyclic-shifted BPSK-modulated M sequences includes according to Multiply two cyclically shifted BPSK - modulated M - sequences, where d(n) is the SSS sequence, where is the cyclic shift of the first M - sequence s0 of the two cyclically shifted BPSK - modulated M - sequences, and where is the cyclic shift of the second M - sequence s1 of the two cyclically shifted BPSK - modulated M - sequences, where m0 is the first cyclic - shift value and m1 is the second cyclic - shift value, where L is the length of the sequence, where n ranges from 0 to L - 1, where the first M - sequence s0(n) of the two cyclically shifted BPSK - modulated M - sequences is generated from a first primitive polynomial, and the second M - sequence s1(n) of the two cyclically shifted BPSK - modulated M - sequences is generated from a second primitive polynomial. In one embodiment, L is a length equal to 127. In one embodiment, the M - sequence s0 is from the first primitive polynomial x 7 +x 4 +1, and the second M - sequence s1 is from the second primitive polynomial x 7 +x + 1. In one embodiment, the initial state of the M - sequence is s(0)=1, s(1)=s(2)=s(3)=s(4)=s(5)=s(6)=0. In one embodiment, the first M - sequence s0 generated by the first polynomial may use a subset of the available set of cyclic shifts, and the second M - sequence s1 generated by the second primitive polynomial may use the entire available set of cyclic shifts. In one embodiment, the combination of the first cyclic - shift value and the second cyclic - shift value provides the cell identity. In one embodiment, the SSS may be mapped to the same antenna port as the corresponding PSS.

[0173] Figure 13 Example detected transmission sequences are illustrated according to some embodiments. In the embodiments herein, the length N of the M - sequence may be determined by the order of the polynomial used to generate the M - sequence. For example, if the order of the primitive polynomial is J, then the length N may be 2 J –1. For example, a polynomial order of 7 may generate a sequence of length 127(=2 7 –1), and the sequence may be unique and without repetition. Thus, the length N may be set to 127.

[0174] A receiver such as a UE may utilize differential cross - correlation to detect the transmitted sequence. The length N of the M - sequence may be set to 2 J , which may repeat the first bit at the 2 J th position of the sequence (i.e., at the last bit of the length - N sequence). Differential cross - correlation may use the fact that an M - sequence multiplied by a cyclically shifted version of itself produces an M - sequence with a specific cyclic shift. For example, using the primitive polynomial x 7The +x+1 generates an M-sequence of length 127, and can perform a bitwise XOR of the generated M-sequence (e.g., M-sequence 1300) and the same M-sequence circularly shifted to the right by 1 (e.g., M-sequence 1302). The resulting sequence (e.g., sequence 1304) can be the same M-sequence circularly shifted to the right by 8.

[0175] Utilizing this property, differential cross-correlation of the received M-sequence can be performed. For example:

[0176] r k = h k x k + n k can be the received signal of subcarrier k, and h k can be the channel coefficient of subcarrier k. x k can be the k-th value of the M-sequence modulated by BPSK, and n k can be the noise of subcarrier k. Since the channel is generally smooth and continuous, it can be assumed that h k ≈ h k+1 .

[0177] The receiver can perform differential multiplication of the received signals r k and r k+1 . The resulting signal z k can be the multiplication of two circularly shifted M-sequences and some additive noise. An example is shown in Figure 13 and the derivation is shown below.

[0178] z k = r k * r k+1 = (h k x k + n k ) * (h k+1 x k+1 + n k+1 )

[0179]

[0180] Because the result of multiplying two cyclically shifted M sequences can be another M sequence, the receiver can perform a fast Hadamard transform to perform maximum likelihood (ML) detection. This detection algorithm may not require multiplication and can be computed using operations such as addition and subtraction. The Hadamard transform (which may also be referred to as the Walsh-Hadamard transform, Hadamard-Rademacher-Walsh transform, Walsh transform, or Walsh-Fourier transform) can be an example of a generalized class of Fourier transforms. The Fourier transform can decompose a function of time (e.g., a signal) into the frequencies that make up the signal. The Hadamard transform H m can be a 2 m by 2 n matrix that transforms 2 m real numbers x k into 2 m real numbers X m . The Hadamard transform can be defined in two ways: recursively, or by using the binary (base 2) representation of the indices n and k. The Hadamard transform can perform an orthogonal, symmetric, involutive, linear operation on 2 m real numbers (or complex numbers, although the Hadamard matrix itself is real).

[0181] Figure 14 An example operation flow / algorithm structure of a UE is illustrated according to some embodiments. The operation flow / algorithm structure 1400 may include receiving an SS block at 1402, the SS block including an SSS sequence indicating a cellular network identity. The operation flow / algorithm structure 1400 may also include detecting the SSS sequence at 1404. In one embodiment, the SSS sequence may be based on the symbol-by-symbol multiplication of the BPSK-modulated bits of two cyclically shifted versions of M sequences. In one embodiment, the operation flow / algorithm structure 1400 may include determining two cyclically shifted versions of M sequences. In one embodiment, the cyclic shift parameter may be identified from the cyclic shift of the M sequence used to generate the SSS sequence.

[0182] The operation flow / algorithm structure 1400 may also include identifying a plurality of cyclic shift parameters at 1406, where the plurality of cyclic shift parameters are based on the M sequence used to generate the SSS sequence. In one embodiment, identifying the plurality of cyclic shift parameters may include performing one or more Hadamard transform functions on the SSS sequence, where the result of the Hadamard transform function is the cyclic shift parameter. The operation flow / algorithm structure 1400 may also include determining the cellular network identity at 1408 based on the application of the cyclic shift parameter to the cyclically shifted version of the M sequence. The cellular network identity may be sent to the memory.

[0183] Figure 15Another example operation flow / algorithm structure of a base station is illustrated according to some embodiments. The operation flow / algorithm structure 1500 may include mapping an M-sequence within the SS bandwidth at 1502. The operation flow / algorithm structure 1500 may further include generating an SS at 1502. The operation flow / algorithm structure 1500 may further include transmitting the SS at 1506.

[0184] Figure 16 Another example operation flow / algorithm structure of a UE is illustrated according to some embodiments. The operation flow / algorithm structure 1600 may include receiving an SS at 1602. The operation flow / algorithm structure 1600 may further include determining one or more maximum length sequences (M-sequences) based on the SS at 1602.

[0185] Figure 17 An example architecture of a network system 1700 is illustrated according to some embodiments. The system 1700 is shown to include user equipment (UE) 1701 and UE 1702. UE 1701 or UE 1702 may, for example, execute the operation flow / algorithm process 1400. UE 1701 and 1702 are shown as smart phones (e.g., handheld touchscreen mobile computing devices that can connect to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a personal data assistant (PDA), pager, laptop computer, desktop computer, wireless handset, or any computing device including a wireless communication interface.

[0186] In some embodiments, either of UE 1701 and 1702 may include an Internet of Things (IoT) UE, which may include a network access layer designed for low-power IoT applications that utilize short-term UE connections. The IoT UE may utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) to exchange data with an MTC server or device via a public land mobile network (PLMN), proximity-based service (ProSe), or device-to-device (D2D) communication, a sensor network, or an IoT network. The M2M or MTC data exchange may be machine-initiated data exchange. The IoT network describes interconnecting IoT UEs using short-term connections, and these IoT UEs may include uniquely identifiable embedded computing devices (within the Internet infrastructure). The IoT UE may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connection of the IoT network.

[0187] UEs 1701 and 1702 can be configured to be connected (e.g., communicatively coupled) to a radio access network (RAN) - in this embodiment, the radio access network is an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) 1710. UEs 1701 and 1702 utilize connections 1703 and 1704 respectively, each of which includes a physical communication interface or layer (discussed in more detail below); in this example, connections 1703 and 1704 are shown as air interfaces to enable communication coupling and may conform to cellular communication protocols such as Global System for Mobile Communications (GSM) protocol, code-division multiple access (CDMA) network protocol, Push-to-Talk (PTT) protocol, PTT over Cellular (POC) protocol, Universal Mobile Telecommunications System (UMTS) protocol, 3GPP Long Term Evolution (LTE) protocol, fifth generation (5G) protocol, New Radio (NR) protocol, and so on.

[0188] In this embodiment, UEs 1701 and 1702 can also directly exchange communication data via the ProSe interface 1705. The ProSe interface 1705 may alternatively be referred to as a sidelink interface including one or more logical channels, including but not limited to Physical Sidelink Control Channel (PSCCH), Physical Sidelink Shared Channel (PSSCH), Physical Sidelink Discovery Channel (PSDCH), and Physical Sidelink Broadcast Channel (PSBCH).

[0189] UE 1702 is shown as being configured to access an access point (AP) 1706 via connection 1707. Connection 1707 may include a logical wireless connection, such as a connection compliant with any IEEE 802.11 protocol, where AP 1706 will include a Wi-Fi router. In this example, AP 1706 is shown as being connected to the Internet and not to the core network of the wireless system (described in more detail below).

[0190] E-UTRAN 1710 may include one or more access nodes enabling connections 1703 and 1704. These access nodes (ANs) may be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next-generation NodeBs (gNBs), RAN nodes, etc., and may include terrestrial stations (e.g., terrestrial access points) or satellite stations providing coverage within a certain geographical area (e.g., a cell). These ANs may, for example, execute operational procedures / algorithmic processes 1000, 1100, or 1200. E-UTRAN 1710 may include one or more RAN nodes for providing macro cells, such as macro RAN node 1711, and one or more RAN nodes for providing femto cells or pico cells (e.g., cells having a smaller coverage area, smaller user capacity, or higher bandwidth compared to macro cells), such as low-power (LP) RAN node 1712.

[0191] Either of RAN nodes 1711 and 1712 may terminate the air interface protocol and may be the first point of contact for UEs 1701 and 1702. In some embodiments, either of RAN nodes 1711 and 1712 may perform various logical functions for E-UTRAN 1710, including but not limited to radio network controller (RNC) functions, such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling, as well as mobility management.

[0192] According to some embodiments, UEs 1701 and 1702 may be configured to communicate with each other or with any one of RAN nodes 1711 and 1712 over a multi-carrier communication channel using Orthogonal Frequency-Division Multiplexing (OFDM) communication signals according to various communication techniques, such as but not limited to Orthogonal Frequency-Division Multiple Access (OFDMA) communication techniques (e.g., for downlink communication) or Single Carrier Frequency Division Multiple Access (SC-FDMA) communication techniques (e.g., for uplink and ProSe or sidelink communication), although the scope of the embodiments is not limited thereto. The OFDM signals may include a plurality of orthogonal sub-carriers.

[0193] In some embodiments, a downlink resource grid may be used for downlink transmissions from any one of RAN nodes 1711 and 1712 to UEs 1701 and 1702, and uplink transmissions may utilize similar techniques. The grid may be a time-frequency grid, referred to as a resource grid or a time-frequency resource grid, which is the physical resources in the downlink in each time slot. Such a time-frequency plane representation is conventional in OFDM systems and is intuitive for radio resource allocation. Each column and each row of the resource grid corresponds to an OFDM symbol and an OFDM sub-carrier, respectively. The duration of the resource grid in the time domain corresponds to a time slot in a radio frame. The smallest time-frequency unit in the resource grid is denoted as a resource element. Each resource grid includes a number of resource blocks, which describe the mapping of a particular physical channel to resource elements. Each resource block includes a set of resource elements; in the frequency domain, this may represent the smallest number of resources that can currently be allocated. There are several different physical downlink channels carried using such resource blocks.

[0194] The physical downlink shared channel (PDSCH) can carry user data and higher layer signaling to UEs 1701 and 1702. The physical downlink control channel (PDCCH) can carry information about the transmission format and resource allocation related to the PDSCH channel, etc. It can also inform UEs 1701 and 1702 about the transmission format, resource allocation, and H-ARQ (Hybrid Automatic Repeat reQuest) information related to the uplink shared channel. Generally, downlink scheduling (assigning control and shared channel resource blocks to UEs 102 within a cell) can be performed at any one of RAN nodes 1711 and 1712 based on channel quality information fed back from any one of UEs 1701 and 1702. Downlink resource assignment information can be sent on the PDCCH for each of UEs 1701 and 1702 (e.g., assigned to).

[0195] The PDCCH can use control channel elements (CCEs) to carry control information. Before being mapped to resource elements, the PDCCH complex-valued symbols can first be organized into quadruples, which can then be transposed using a sub-block interleaver for rate matching. Each PDCCH can use one or more of these CCEs to transmit, where each CCE can correspond to nine sets of four physical resource elements called resource element groups (REGs). Four Quadrature Phase Shift Keying (QPSK) symbols can be mapped for each REG. Depending on the size of the downlink control information (DCI) and the channel conditions, one or more CCEs can be used to transmit the PDCCH. Four or more different PDCCH formats can be defined in LTE, with different numbers of CCEs (e.g., aggregation levels L = 1, 2, 4, or 8).

[0196] Some embodiments may use concepts of resource allocation for control channel information, which are extensions of the above concepts. For example, some embodiments may utilize an enhanced physical downlink control channel (EPDCCH) that uses PDSCH resources for control information transmission. One or more enhanced control channel elements (ECCEs) may be utilized to transmit the EPDCCH. Similar to the above, each ECCE may correspond to nine sets of four physical resource elements referred to as an enhanced resource element group (EREG). An ECCE may have other numbers of EREGs in some cases.

[0197] E-UTRAN 1710 is shown communicatively coupled to a core network - in this embodiment, an Evolved Packet Core (EPC) network 1720 via an S1 interface 1713. In this embodiment, the S1 interface 1713 is split into two parts: an S1-U interface 1714 that carries traffic data between RAN nodes 1711 and 1712 and a serving gateway (S-GW) 1722; and an S1 mobility management entity (MME) interface 1715, which is a signaling interface between RAN nodes 1711 and 1712 and the MME 1721.

[0198] In this embodiment, the EPC network 1720 includes a Mobility Management Entity (MME) 1721, a Serving Gateway (S-GW) 1722, a Packet Data Network (PDN) Gateway (P-GW) 1723, and a Home Subscriber Server (HSS) 1724. Functionally, the MME 1721 may be similar to the control plane of a legacy Serving General Packet Radio Service (GPRS) Support Node (SGSN). The MME 1721 may manage aspects of mobility in access, such as gateway selection and tracking area list management. The HSS 1724 may include a database for network users, including subscription-related information, to support the handling of communication sessions by network entities. The EPC network 1720 may include one or more HSSs 1724, depending on the number of mobile subscribers, the capacity of the devices, the organization of the network, and so on. For example, the HSS 1724 may provide support for routing / roaming, authentication, authorization, name / address resolution, location compliance, and so on.

[0199] The S-GW 1722 may terminate the S1 interface 1713 towards the E-UTRAN 1710 and route data packets between the E-UTRAN 1710 and the EPC network 1720. In addition, the S-GW 1722 may be a local mobility anchor point for handovers between RAN nodes and may also provide anchoring for inter-3GPP mobility. Other responsibilities may include lawful interception, charging, and some policy enforcement.

[0200] The P-GW 1723 may terminate the SGi interface towards the PDN. The P-GW 1723 may route data packets between the EPC network 1723 and an external network, such as a network including an Application Server 1730 (or referred to as an Application Function (AF)), via an Internet Protocol (IP) interface 1725. Generally, the Application Server 1730 may be an element that provides an application that uses IP bearer resources with the core network (e.g., UMTS Packet Service (PS) domain, LTE PS data service, etc.). In this embodiment, the P-GW 1723 is shown communicatively coupled to the Application Server 1730 via an IP communication interface 1725. The Application Server 1730 may also be configured to support one or more communication services (e.g., Voice-over-Internet Protocol (VoIP) sessions, Push-to-Talk (PTT) sessions, group communication sessions, social network services, etc.) for the UEs 1701 and 1702 via the EPC network 1720.

[0201] The P-GW 1723 can also be a node for policy enforcement and charging data collection. The Policy and Charging Enforcement Function (PCRF) 1726 is the policy and charging control element of the EPC network 1720. In a non-roaming scenario, there can be a single PCRF in the Home Public Land Mobile Network (HPLMN) associated with the Internet Protocol Connectivity Access Network (IP-CAN) session of the UE. In a roaming scenario with local breakout of traffic, there can be two PCRFs associated with the IP-CAN session of the UE: the Home PCRF (H-PCRF) within the HPLMN and the Visited PCRF (V-PCRF) within the Visited Public Land Mobile Network (VPLMN). The PCRF 1726 can be communicatively coupled to the application server 1730 via the P-GW 1723. The application server 1730 can signal the PCRF 1726 to indicate new service flows and select appropriate Quality of Service (QoS) and charging parameters. The PCRF 1726 can configure this rule into the Policy and Charging Enforcement Function (PCEF) (not shown) using an appropriate traffic flow template (TFT) and QoS class of identifier (QCI), which initiates the QoS and charging specified by the application server 1730.

[0202] Figure 18Example components of device 1800 are illustrated in accordance with some embodiments. In some embodiments, device 1800 may include application circuitry 1802, baseband circuitry 1804, radio frequency (RF) circuitry 1806, front-end module (FEM) circuitry 1808, one or more antennas 1810, and power management circuitry (PMC) 1812, coupled together as shown at least. The illustrated components of device 1800 may be included in a UE or a RAN node. In some embodiments, device 1800 may include fewer elements (e.g., a RAN node may not utilize application circuitry 1802, but instead include a processor / controller to process IP data received from the EPC). In some embodiments, device 1800 may include additional elements, such as memory / storage, a display, a camera, sensors, or input / output (I / O) interfaces. In other embodiments, the components described below may be included in more than one device (e.g., for a Cloud-RAN (C-RAN) implementation, the circuitry may be separately included in more than one device).

[0203] The application circuitry 1802 may include one or more application processors. For example, the application circuitry 1802 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The (one or more) processors may include any combination of general-purpose processors and dedicated processors (e.g., a graphics processor, an application processor, etc.). The processor may be coupled to the memory / storage or may include the memory / storage and may be configured to execute instructions stored in the memory / storage to enable various applications or operating systems to run on device 1800. In some embodiments, the processor of the application circuitry 1802 may process IP data packets received from the EPC.

[0204] The baseband circuit 1804 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuit 1804 may include one or more baseband processors or control logic to process baseband signals received from the receive signal path of the RF circuit 1806 and generate baseband signals for the transmit signal path of the RF circuit 1806. The baseband processor may, for example, execute operational flow / algorithm procedures 1000, 1100, 1200, or 1400. The baseband processing circuit 1804 may interface with the application circuit 1802 to generate and process baseband signals and control the operation of the RF circuit 1806. For example, in some embodiments, the baseband circuit 1804 may include a third-generation (3G) baseband processor 1804A, a fourth-generation (4G) baseband processor 1804B, a fifth-generation (5G) baseband processor 1804C, or other (one or more) baseband processors 1804D for other existing generations, generations under development, or generations to be developed in the future (e.g., second-generation (2G), sixth-generation (6G), etc.). The baseband circuit 1804 (e.g., one or more of the baseband processors 1804A-D) may process various radio control functions that enable communication with one or more radio networks via the RF circuit 1806. In other embodiments, some or all of the functions of the baseband processors 1804A-D may be included in modules stored in the memory 1804G and executed via the central processing unit (CPU) 1804E. The radio control functions may include, but are not limited to, signal modulation / demodulation, encoding / decoding, radio frequency offset, etc. In some embodiments, the modulation / demodulation circuit of the baseband circuit 1804 may include Fast-Fourier Transform (FFT), precoding, or constellation mapping / demapping functions. In some embodiments, the encoding / decoding circuit of the baseband circuit 1804 may include convolution, tail-biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder / decoder functions. Embodiments of the modulation / demodulation and encoder / decoder functions are not limited to these examples and may include other suitable functions in other embodiments.

[0205] In some embodiments, the baseband circuit 1804 may include one or more audio digital signal processors (DSPs) 1804F. The (one or more) audio DSPs 1804F may include elements for compression / decompression and echo cancellation, and in other embodiments may include other suitable processing elements. The components of the baseband circuit may be appropriately combined in a single chip, a single chipset, or in some embodiments arranged on the same circuit board. In some embodiments, some or all of the constituent components of the baseband circuit 1804 and the application circuit 1802 may be implemented together, for example, on a system on a chip (SOC).

[0206] In some embodiments, the baseband circuit 1804 may support communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuit 1804 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area network (WMAN), wireless local area network (WLAN), wireless personal area network (WPAN). Embodiments where the baseband circuit 1804 is configured to support radio communication for more than one wireless protocol may be referred to as multi-mode baseband circuits.

[0207] The RF circuit 1806 may enable communication with a wireless network using modulated electromagnetic radiation via a non-solid medium. In various embodiments, the RF circuit 1806 may include switches, filters, amplifiers, etc. to facilitate communication with the wireless network. The RF circuit 1806 may include a receive signal path that may include circuitry to down-convert an RF signal received from the FEM circuit 1808 and provide a baseband signal to the baseband circuit 1804. The RF circuit 1806 may also include a transmit signal path that may include circuitry to up-convert a baseband signal provided by the baseband circuit 1804 and provide an RF output signal to the FEM circuit 1808 for transmission.

[0208] In some embodiments, the receive signal path of RF circuit 1806 may include mixer circuit 1806a, amplifier circuit 1806b, and filter circuit 1806c. In some embodiments, the transmit signal path of RF circuit 1806 may include filter circuit 1806c and mixer circuit 1806a. RF circuit 1806 may also include synthesizer circuit 1806d for synthesizing frequencies for use by mixer circuit 1806a of the receive signal path and the transmit signal path. In some embodiments, mixer circuit 1806a of the receive signal path may be configured to down-convert an RF signal received from FEM circuit 1808 based on the synthesized frequency provided by synthesizer circuit 1806d. Amplifier circuit 1806b may be configured to amplify the down-converted signal and filter circuit 1806c may be a low-pass filter (LPF) or a band-pass filter (BPF) configured to remove unwanted signals from the down-converted signal to generate an output baseband signal. The output baseband signal may be provided to baseband circuit 1804 for further processing. In some embodiments, the output baseband signal may be a zero-frequency baseband signal, although this is not a requirement. In some embodiments, mixer circuit 1806a of the receive signal path may include a passive mixer, although the scope of the embodiments is not limited thereto.

[0209] In some embodiments, mixer circuit 1806a of the transmit signal path may be configured to up-convert an input baseband signal based on the synthesized frequency provided by synthesizer circuit 1806d to generate an RF output signal for FEM circuit 1808. The baseband signal may be provided by baseband circuit 1804 and may be filtered by filter circuit 1806c.

[0210] In some embodiments, mixer circuit 1806a of the receive signal path and mixer circuit 1806a of the transmit signal path may include two or more mixers and may be arranged respectively for quadrature down-conversion and up-conversion. In some embodiments, mixer circuit 1806a of the receive signal path and mixer circuit 1806a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, mixer circuit 1806a of the receive signal path and mixer circuit 1806a may be arranged respectively for direct down-conversion and direct up-conversion. In some embodiments, mixer circuit 1806a of the receive signal path and mixer circuit 1806a of the transmit signal path may be configured for superheterodyne operation.

[0211] In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of the embodiments is not limited thereto. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In these alternative embodiments, the RF circuit 1806 may include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) circuit and the baseband circuit 1804 may include a digital baseband interface to communicate with the RF circuit 1806.

[0212] In some dual-mode embodiments, separate radio IC circuits may be provided to process signals for each spectrum, although the scope of the embodiments is not limited thereto.

[0213] In some embodiments, the synthesizer circuit 1806d may be a fractional-N synthesizer or a fractional-N / N+1 synthesizer, although the scope of the embodiments is not limited thereto since other types of frequency synthesizers may be appropriate. For example, the synthesizer circuit 1806d may be an increment-sum synthesizer, a frequency multiplier, or a synthesizer including a phase-locked loop with a frequency divider.

[0214] The synthesizer circuit 1806d may be configured to synthesize an output frequency based on a frequency input and a frequency divider control input for use by the mixer circuit 1806a of the RF circuit 1806. In some embodiments, the synthesizer circuit 1806d may be a fractional-N / N+1 synthesizer.

[0215] In some embodiments, the frequency input may be provided by a voltage controlled oscillator (VCO), although this is not a requirement. Depending on the desired output frequency, the frequency divider control input may be provided by the baseband circuit 1804 or the application processor 1802. In some embodiments, the frequency divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the application processor 1802.

[0216] The synthesizer circuit 1806d of the RF circuit 1806 may include a frequency divider, a delay-locked loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the frequency divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide an input signal by N or N+1 (e.g., based on carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In these embodiments, the delay elements may be configured to divide a VCO period into Nd equal phase bins, where Nd is the number of delay elements in the delay line. Thus, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO period.

[0217] In some embodiments, the synthesizer circuit 1806d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and may be used with a quadrature generator and a frequency divider circuit to generate multiple signals having multiple different phases with respect to each other at the carrier frequency. In some embodiments, the output frequency may be the LO frequency (fLO). In some embodiments, the RF circuit 1806 may include an IQ / polarity converter.

[0218] The FEM circuit 1808 may include a receive signal path that may include circuitry configured to operate on an RF signal received from one or more antennas 1810, amplify the received signal, and provide an amplified version of the received signal to the RF circuit 1806 for further processing. The FEM circuit 1808 may also include a transmit signal path that may include circuitry configured to amplify a signal provided by the RF circuit 1806 for transmission by one or more of the one or more antennas 1810. In various embodiments, the amplification through the transmit or receive path may be done only in the RF circuit 1806, only in the FEM 1808, or in both the RF circuit 1806 and the FEM 1808.

[0219] In some embodiments, the FEM circuit 1808 may include a TX / RX switch to switch between transmit mode and receive mode operations. The FEM circuit may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuit may include an LNA to amplify the received RF signal and provide the amplified received RF signal as an output (e.g., to the RF circuit 1806). The transmit signal path of the FEM circuit 1808 may include a power amplifier (PA) to amplify the input RF signal (e.g., provided by the RF circuit 1806), and may include one or more filters to generate an RF signal for subsequent transmission (e.g., transmitted by one or more of the one or more antennas 1810).

[0220] In some embodiments, the PMC 1812 may manage the power provided to the baseband circuit 1804. Specifically, the PMC 1812 may control power selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMC 1812 may often be included when the device 1800 is capable of being battery-powered, such as when the device is included in a UE. The PMC 1812 may increase power conversion efficiency while providing desired implementation size and thermal characteristics.

[0221] Although Figure 18 it is shown that the PMC 1812 is only coupled to the baseband circuit 1804. However, in other embodiments, the PMC 1812 may additionally or alternatively be coupled to other components and perform similar power management operations for other components, such as but not limited to the application circuit 1802, the RF circuit 1806, or the FEM 1808.

[0222] In some embodiments, the PMC 1812 may control various power saving mechanisms of the device 1800 or otherwise be part of these power saving mechanisms. For example, if the device 1800 is in the RRC_Connected state of being connected to a RAN node because traffic is expected to be received soon, it may enter a state called Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 1800 may power off for short time intervals and thus save power.

[0223] If there is no data traffic activity for a relatively long period of time, device 1800 may transition to the RRC_Idle state, in which it is disconnected from the network and does not perform operations such as channel quality feedback, handover, etc. Device 1800 enters a very low power state and it performs paging, in which it wakes up again periodically to listen for the network and then powers off again. Device 1800 may not receive data in this state. To receive data, it must transition back to the RRC_Connected state.

[0224] Additional power saving modes may allow the device to be unavailable to the network for a period longer than the paging interval (ranging from a few seconds to several hours). During this time, the device is completely unreachable to the network and may be completely powered off. Any data sent during this time suffers a significant delay, and it is assumed that this delay is acceptable.

[0225] The processor of the application circuit 1802 and the processor of the baseband circuit 1804 may be used to execute elements of one or more instances of the protocol stack. For example, the processor of the baseband circuit 1804 alone or in combination may be used to execute layer 3, layer 2, or layer 1 functions, while the processor of the application circuit 1804 may utilize the data received from these layers (e.g., packet data) and further execute layer 4 functions (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). As mentioned herein, layer 3 may include the radio resource control (RRC) layer, which is described in more detail below. As mentioned herein, layer 2 may include the medium access control (MAC) layer, the radio link control (RLC) layer, and the packet data convergence protocol (PDCP) layer, which are described in more detail below. As mentioned herein, layer 1 may include the physical (PHY) layer of the UE / RAN node, which is described in more detail below.

[0226] Figure 19 Examples of interfaces of the baseband circuit are illustrated according to some embodiments. As described above, Figure 18The baseband circuit 1804 may include processors 1804A - 1804E and a memory 1804G utilized by the processors. Each of the processors 1804A - 1804E may respectively include a memory interface 1904A - 1904E for sending / receiving data to / from the memory 1804G, such as data that may be described in connection with the operation flows / algorithm procedures 1000, 1100, 1200, or 1400. The baseband circuit 1804 may include a memory interface for receiving a primitive polynomial from the memory 1804G.

[0227] The baseband circuit 1804 may also include one or more interfaces for communicatively coupling to other circuits / devices, such as a memory interface 1912 (e.g., an interface for sending / receiving data to / from a memory external to the baseband circuit 1804), an application circuit interface 1914 (e.g., an interface for sending / receiving data to / from Figure 18 the application circuit 1802), an RF circuit interface 1916 (e.g., an interface for sending / receiving data to / from Figure 18 the RF circuit 1806), a wireless hardware connectivity interface 1918 (e.g., an interface for sending / receiving data to / from a Near Field Communication (NFC) component, components (e.g., low power consumption ), components, and other communication components), and a power management interface 1920 (e.g., an interface for sending / receiving power or control signals to / from the PMC 1812).

[0228] Figure 20 is a block diagram illustrating example components that, according to some example embodiments, can read instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and perform any one or more of the methods discussed herein. Specifically, Figure 20 illustrates a graphical representation of hardware resources 2000 that includes one or more processors (or processor cores) 2010, one or more memory / storage devices 2020, and one or more communication resources 2030, where each may be communicatively coupled via a bus 2040. For embodiments that utilize node virtualization (e.g., NFV), a hypervisor 2002 may be executed to provide an execution environment for one or more network slices / sub-slices to utilize the hardware resources 2000.

[0229] The processor 2010 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) (e.g., a baseband processor), an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processors 2012 and 2014. The processor 2010 may execute, for example, operational flows / algorithmic processes 1000, 1100, 1200, or 1400.

[0230] The memory / storage device 2020 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 2020 may include, but is not limited to, any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random-access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid state storage devices, and the like.

[0231] The communication resources 2030 may include an interconnect or network interface component or other suitable device to communicate with one or more peripheral devices 2004 or one or more databases 2006 via a network 2008. For example, the communication resources 2030 may include a wired communication component (e.g., for coupling via a Universal Serial Bus (USB)), a cellular communication component, an NFC component, components (e.g., low power consumption ), components and other communication components.

[0232] Instruction 2050 may include software, a program, an application, an applet, an app, or other executable code for causing at least any one of processors 2010 to execute any one or more of the methods discussed herein. Instruction 2050 may reside in whole or in part within at least one of processors 2010 (e.g., within a cache memory of the processor), within memory / storage device 2020, or any suitable combination thereof. Additionally, any portion of Instruction 2050 may be transferred from any combination of peripheral device 2004 or database 2006 to hardware resource 2000. Accordingly, the memory of processors 2010, memory / storage device 2020, peripheral device 2004, and database 2006 are examples of computer-readable and machine-readable media.

[0233] In some embodiments, Figure 17 , Figure 18 , Figure 19 or Figure 20 an electronic device, component, or system or some portion or implementation thereof may be configured to perform one or more of the processes, techniques, or methods described herein or some portion thereof.

[0234] The description of the illustrated implementations herein, including those described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations and examples are described herein for purposes of illustration, as will be recognized by those of ordinary skill in the relevant art, various substitutions or equivalent embodiments or implementations that are intended to achieve the same purpose may be made in accordance with the above detailed description without departing from the scope of the disclosure.

[0235] Some non-limiting examples are provided below.

[0236] Examples

[0237] Example 1 may include one or more computer-readable media having instructions that, when executed by one or more processors, cause a base station to: multiply two cyclically shifted binary phase shift keying (BPSK)-modulated M sequences to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a certain length; and map the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence.

[0238] Example 2 may include one or more computer-readable media of Example 1 or some other example herein, wherein the central subcarriers are central consecutive subcarriers.

[0239] Example 3 may include one or more computer-readable media of Example 1 or 2 or some other example herein, wherein, to generate the sequence for the SSS, the instructions when executed further cause the base station to according to multiply the two cyclically shifted BPSK-modulated M sequences, where d(n) is the SSS sequence, and where is the cyclic shift of the first M sequence s0 of the two cyclically shifted BPSK-modulated M sequences, and is the cyclic shift of the second M sequence s1 of the two cyclically shifted BPSK-modulated M sequences, where m0 is the first cyclic shift value and m1 is the second cyclic shift value, where L is the length of the sequence, where n is from 0 to L minus 1, where the first M sequence s0(n) of the two cyclically shifted BPSK-modulated M sequences is generated from a first primitive polynomial, and where the second M sequence s1(n) of the two cyclically shifted BPSK-modulated M sequences is generated from a second primitive polynomial.

[0240] Example 4 may include one or more computer-readable media of Example 3 or some other example herein, where L is equal to 127.

[0241] Example 5 may include one or more computer-readable media of Example 3 or some other example herein, where the first M sequence s0 is generated from the first primitive polynomial x 7 +x 4 +1, and where the second M sequence s1 is generated from the second primitive polynomial x 7 +x + 1.

[0242] Example 6 may include one or more computer-readable media of Example 4 or 5, where the initial state of the M sequence is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

[0243] Example 7 may include one or more computer-readable media of Example 4 or 5 or some other example herein, where the first M sequence s0(n) generated by the first primitive polynomial uses a subset of the available set of cyclic shifts, and where the second M sequence s1(n) generated by the second primitive polynomial uses all of the available set of cyclic shifts.

[0244] Example 8 may include one or more computer-readable media of Example 7 or some other example herein, where the combination of the first cyclic shift value and the second cyclic shift value provides the cell identity.

[0245] Example 9 may include one or more computer-readable media of Example 1, 2, 4, 5, or 8 or some other example herein, wherein the SSS is mapped to the same antenna port as the primary synchronization signal.

[0246] Example 10 may include one or more computer-readable media having instructions that, when executed by one or more processors, cause a base station to: determine a maximum length sequence (M-sequence) of a certain length based on a primitive polynomial; perform a cyclic shift of the M-sequence to generate a cyclic shifted M-sequence; modulate the cyclic shifted M-sequence using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and map the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the M-sequence.

[0247] Example 11 may include one or more computer-readable media of Example 10 or some other example herein, wherein, to determine the M-sequence, the instructions, when executed, further cause the base station to select the M-sequence from a set of M-sequences generated according to a set of primitive polynomials.

[0248] Example 12 may include one or more computer-readable media of Example 10 or some other example herein, wherein, to determine the M-sequence, the instructions, when executed, further cause the base station to generate the M-sequence of the length based on the primitive polynomial.

[0249] Example 13 may include one or more computer-readable media of Example 12 or some other example herein, wherein the instructions, when executed, further cause the base station to multiply each of the central subcarriers by a repeated complex scrambling sequence.

[0250] Example 14 may include an apparatus for a base station, including: a processing circuit for: generating two maximum length sequences (M-sequences) based on two different primitive polynomials, wherein each M-sequence has a certain length; performing cyclic shifts of the two M-sequences to generate two cyclic shifted M-sequences; modulating the two cyclic shifted M-sequences using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the M-sequence; and an interface circuit coupled to the processing circuit, which receives the two different primitive polynomials from a memory.

[0251] Example 15 may include the apparatus of Example 14 or some other example herein, wherein the processing circuitry further: multiplies a first M-sequence of the two M-sequences by a complex value to provide a complex-valued M-sequence; and multiplies a second M-sequence of the two M-sequences by a real value to provide a real-valued M-sequence.

[0252] Example 16 may include the apparatus of Example 15 or some other example herein, wherein, to map the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth, the processing circuitry further: maps the BPSK-modulated bits of the complex-valued M-sequence to the in-phase constellation of the central subcarriers of the SS bandwidth; and maps the BPSK-modulated bits of the real-valued M-sequence to the quadrature constellation of the central subcarriers of the SS bandwidth.

[0253] Example 17 may include the apparatus of Example 14 or some other example herein, wherein the processing circuitry further performs a bitwise exclusive OR (XOR) operation on the two cyclically shifted M-sequences.

[0254] Example 18 may include the apparatus of Example 14 or some other example herein, wherein the processing circuitry further performs a post-modulation symbol-by-symbol multiplication of the BPSK-modulated bits of the two cyclically shifted M-sequences.

[0255] Example 19 may include the apparatus of Example 14, 15, 16, 17, or 18 or some other example herein, wherein the cyclic shift is based on the cell identity.

[0256] Example 20 may include the apparatus of Example 14, 15, 16, 17, or 18 or some other example herein, wherein the length is selected from one of 127 or 255.

[0257] Example 21 may include an apparatus for a user equipment (UE), comprising: processing circuitry configured to: receive a synchronization signal (SS) block including a secondary synchronization signal (SSS) sequence; detect the SSS sequence; identify a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on a maximum length sequence (M-sequence) used to generate the SSS sequence; determine a cellular network identity based on applying the cyclic shift parameters to a cyclically shifted version of the M-sequence; and an interface circuit coupled to the processing circuitry, which sends the cellular network identity to a memory.

[0258] Example 22 may include the apparatus of Example 21 or some other example herein, wherein the SSS sequence is based on a post-modulation symbol-by-symbol multiplication of BPSK-modulated bits of two cyclically shifted versions of the M-sequence.

[0259] Example 23 may include the apparatus of Example 22 or some other example herein, wherein the processing circuitry further determines a cyclic shift version of the two M-sequences.

[0260] Example 24 may include the apparatus of Example 21, 22, or 23 or some other example herein, wherein the cyclic shift parameter is identified from a cyclic shift of the M-sequence used to generate the SSS sequence.

[0261] Example 25 may include the apparatus of Example 21, 22, or 23 or some other example herein, wherein, to identify the plurality of cyclic shift parameters, the processing circuitry further performs one or more Hadamard transform functions on the SSS sequence, wherein the result of the Hadamard transform function is the cyclic shift parameter.

[0262] Example 26 may include a method of signal generation, including: multiplying two cyclically shifted binary phase shift keying (BPSK)-modulated M-sequences to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a certain length; and mapping the sequence to several central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence.

[0263] Example 27 may include the method of Example 26 or some other example herein, wherein the central subcarriers are central consecutive subcarriers.

[0264] Example 28 may include the method of Example 26 or 27 or some other example herein, wherein generating the sequence for the SSS includes according to multiplying the two cyclically shifted BPSK-modulated M-sequences, wherein d(n) is the SSS sequence, and wherein is a cyclic shift of a first M-sequence s0 of the two cyclically shifted BPSK-modulated M-sequences, and is a cyclic shift of a second M-sequence s1 of the two cyclically shifted BPSK-modulated M-sequences, wherein m0 is a first cyclic shift value and m1 is a second cyclic shift value, wherein L is the length of the sequence, wherein n is from 0 to L minus 1, wherein the first M-sequence s0(n) of the two cyclically shifted BPSK-modulated M-sequences is generated from a first primitive polynomial, and wherein the second M-sequence s1(n) of the two cyclically shifted BPSK-modulated M-sequences is generated from a second primitive polynomial.

[0265] Example 29 may include the method of Example 28 or some other example herein, wherein L is equal to 127.

[0266] Example 30 may include the method of Example 29 or some other example herein, wherein the first M-sequence s0 is generated from the first primitive polynomial x 7 +x 4 +1, and wherein the second M-sequence s1 is generated from the second primitive polynomial x 7 +x + 1.

[0267] Example 31 may include the method of Example 29 or 30, wherein the initial state of the M-sequence is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

[0268] Example 32 may include the method of Example 29 or 30 or some other example herein, wherein the first M-sequence s0(n) generated by the first primitive polynomial uses a subset of the available set of cyclic shifts, and wherein the second M-sequence s1(n) generated by the second primitive polynomial uses all of the available set of cyclic shifts.

[0269] Example 33 may include the method of Example 32 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

[0270] Example 34 may include the method of Example 26, 27, 29, 30 or 33 or some other example herein, wherein the SSS is mapped to the same antenna port as the primary synchronization signal.

[0271] Example 35 may include a method of signal generation, including: determining a maximum length sequence (M-sequence) having a certain length based on a primitive polynomial; performing a cyclic shift of the M-sequence to generate a cyclic shifted M-sequence; modulating the cyclic shifted M-sequence using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the M-sequence.

[0272] Example 36 may include the method of Example 35 or some other example herein, wherein determining the M-sequence includes selecting the M-sequence from a set of M-sequences generated according to a set of primitive polynomials.

[0273] Example 37 may include the method of Example 35 or some other example herein, wherein determining the M-sequence includes generating the M-sequence having the length based on the primitive polynomial.

[0274] Example 38 may include the method of Example 37 or some other example herein, further including instructions that, when executed, cause the base station to multiply each of the central subcarriers by a repeated complex scrambling sequence.

[0275] Example 39 may include an apparatus for a base station, including: processing circuitry configured to: multiply two cyclically shifted binary phase shift keying (BPSK)-modulated M sequences to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a certain length; and map the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence; and interface circuitry coupled to the processing circuitry, which transmits the sequence for the SSS to a memory.

[0276] Example 40 may include the apparatus of Example 39 or some other example herein, wherein the central subcarriers are central consecutive subcarriers.

[0277] Example 41 may include the apparatus of Example 39 or 40 or some other example herein, wherein, to generate the sequence for the SSS, the processing circuitry further according to multiplies the two cyclically shifted BPSK-modulated M sequences, where d(n) is the SSS sequence, and wherein is a cyclic shift of a first M sequence s0 of the two cyclically shifted BPSK-modulated M sequences, and is a cyclic shift of a second M sequence s1 of the two cyclically shifted BPSK-modulated M sequences, where m0 is a first cyclic shift value and m1 is a second cyclic shift value, where L is the length of the sequence, where n ranges from 0 to L minus 1, wherein the first M sequence s0(n) of the two cyclically shifted BPSK-modulated M sequences is generated from a first primitive polynomial, and wherein the second M sequence s1(n) of the two cyclically shifted BPSK-modulated M sequences is generated from a second primitive polynomial.

[0278] Example 42 may include the apparatus of Example 41 or some other example herein, wherein L is equal to 127.

[0279] Example 43 may include the apparatus of Example 41 or some other example herein, wherein the first M sequence s0 is generated from a first primitive polynomial x 7 +x 4 +1, and wherein the second M sequence s1 is generated from a second primitive polynomial x 7 +x + 1.

[0280] Example 44 may include the apparatus of Example 42 or 43, wherein the initial state of the M-sequence is s(0)=1, s(1)=s(2)=s(3)=s(4)=s(5)=s(6)=0.

[0281] Example 45 may include the apparatus of Example 42 or 43 or some other example herein, wherein a first M-sequence s0(n) generated by the first primitive polynomial uses a subset of the available set of cyclic shifts, and wherein a second M-sequence s1(n) generated by the second primitive polynomial uses the entire available set of cyclic shifts.

[0282] Example 46 may include the apparatus of Example 45 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

[0283] Example 47 may include the apparatus of Example 39, 40, 43, 44 or 46 or some other example herein, wherein the SSS is mapped to the same antenna port as the primary synchronization signal.

[0284] Example 48 may include an apparatus for a base station, comprising: processing circuitry for: determining a maximum length sequence (M-sequence) of a certain length based on a primitive polynomial; performing a cyclic shift of the M-sequence to generate a cyclic shifted M-sequence; modulating the cyclic shifted M-sequence using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the M-sequence; and interface circuitry coupled to the processing circuitry, which transmits the SSS sequence to a memory.

[0285] Example 49 may include the apparatus of Example 48 or some other example herein, wherein, to determine the M-sequence, the processing circuitry further selects the M-sequence from a set of M-sequences generated according to a set of primitive polynomials.

[0286] Example 50 may include the apparatus of Example 48 or some other example herein, wherein, to determine the M-sequence, the processing circuitry further generates the M-sequence of the length based on the primitive polynomial.

[0287] Example 51 may include the apparatus of Example 50 or some other example herein, wherein the processing circuitry further multiplies each of the central subcarriers by a repeated complex scrambling sequence.

[0288] Example 52 may include an apparatus for a base station, comprising: means for multiplying two cyclically shifted binary phase shift keying (BPSK)-modulated M-sequences to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a certain length; and means for mapping the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the sequence.

[0289] Example 53 may include the apparatus of Example 52 or some other example herein, wherein the central subcarriers are central consecutive subcarriers.

[0290] Example 54 may include the apparatus of Example 52 or 53 or some other example herein, wherein the means for generating the sequence for the SSS comprises means for multiplying the two cyclically shifted BPSK-modulated M-sequences according to where d(n) is the SSS sequence, and wherein is the cyclic shift of the first M-sequence s0 of the two cyclically shifted BPSK-modulated M-sequences, and is the cyclic shift of the second M-sequence s1 of the two cyclically shifted BPSK-modulated M-sequences, where m0 is the first cyclic shift value and m1 is the second cyclic shift value, where L is the length of the sequence, where n ranges from 0 to L minus 1, where the first M-sequence s0(n) of the two cyclically shifted BPSK-modulated M-sequences is generated from a first primitive polynomial, and wherein the second M-sequence s1(n) of the two cyclically shifted BPSK-modulated M-sequences is generated from a second primitive polynomial.

[0291] Example 55 may include the apparatus of Example 54 or some other example herein, wherein L is equal to 127.

[0292] Example 56 may include the apparatus of Example 54 or some other example herein, wherein the first M-sequence s0 is generated from a first primitive polynomial x 7 +x 4 +1, and wherein the second M-sequence s1 is generated from a second primitive polynomial x 7 +x+1.

[0293] Example 57 may include the apparatus of Example 55 or 56 or some other example herein, wherein the initial state of the M-sequence is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

[0294] Example 58 may include the apparatus of Example 55 or 56 or some other example herein, wherein the first M-sequence s0(n) generated by the first primitive polynomial uses a subset of the available set of cyclic shifts, and wherein the second M-sequence s1(n) generated by the second primitive polynomial uses the entire available set of cyclic shifts.

[0295] Example 59 may include the apparatus of Example 58 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

[0296] Example 60 may include the apparatus of Example 52, 53, 55, 56, or 59 or some other example herein, wherein the SSS is mapped to the same antenna port as the primary synchronization signal.

[0297] Example 61 may include an apparatus for a base station, comprising: means for determining a maximum length sequence (M-sequence) of a certain length based on a primitive polynomial; means for performing a cyclic shift of the M-sequence to generate a cyclic shifted M-sequence; means for modulating the cyclic shifted M-sequence using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and means for mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the M-sequence.

[0298] Example 62 may include the apparatus of Example 61 or some other example herein, wherein the means for determining the M-sequence includes selecting the M-sequence from a set of M-sequences generated according to a set of primitive polynomials.

[0299] Example 63 may include the apparatus of Example 61 or some other example herein, wherein the means for determining the M-sequence includes generating the M-sequence of the length based on the primitive polynomial.

[0300] Example 64 may include the apparatus of Example 63 or some other example herein, further comprising means for multiplying each of the central subcarriers by a repeated complex scrambling sequence.

[0301] Example 65 may include one or more computer-readable media having instructions that, when executed, cause a base station to: generate two maximum length sequences (M-sequences) based on two different primitive polynomials, where each M-sequence has a certain length; perform a cyclic shift of the two M-sequences to generate two cyclic-shifted M-sequences; modulate the two cyclic-shifted M-sequences using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and map the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, where the number of the central subcarriers corresponds to the length of the M-sequence.

[0302] Example 66 may include one or more computer-readable media of Example 65 or some other example herein, where the instructions when executed further cause the base station to: multiply a first M-sequence of the two M-sequences by a complex value to provide a complex-valued M-sequence; and multiply a second M-sequence of the two M-sequences by a real value to provide a real-valued M-sequence.

[0303] Example 67 may include one or more computer-readable media of Example 66 or some other example herein, where, to map the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth, the instructions when executed further cause the base station to: map the BPSK-modulated bits of the complex-valued M-sequence to the in-phase constellation of the central subcarriers of the SS bandwidth; and map the BPSK-modulated bits of the real-valued M-sequence to the quadrature constellation of the central subcarriers of the SS bandwidth.

[0304] Example 68 may include one or more computer-readable media of Example 65 or some other example herein, where the instructions when executed further cause the base station to perform a bitwise exclusive or (XOR) operation on the two cyclic-shifted M-sequences.

[0305] Example 69 may include one or more computer-readable media of Example 65 or some other example herein, where the instructions when executed further cause the base station to perform a post-modulation symbol-by-symbol multiplication of the BPSK-modulated bits of the two cyclic-shifted M-sequences.

[0306] Example 70 may include one or more computer-readable media of Example 65, 66, 67, 68, or 69 or some other example herein, where the cyclic shift is based on a cell identity.

[0307] Example 71 may include one or more computer-readable media of Example 65, 66, 67, 68, or 69 or some other example herein, where the length is selected from one of 127 or 255.

[0308] Example 72 may include a method for signal generation, including: generating two maximum length sequences (M-sequences) based on two different primitive polynomials, where each M-sequence has a certain length; performing a cyclic shift of the two M-sequences to generate two cyclic shifted M-sequences; modulating the two cyclic shifted M-sequences using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, where the number of the central subcarriers corresponds to the length of the M-sequence.

[0309] Example 73 may include the method of Example 72 or some other example herein, further including: multiplying a first M-sequence of the two M-sequences by a complex value to provide a complex-valued M-sequence; and multiplying a second M-sequence of the two M-sequences by a real value to provide a real-valued M-sequence.

[0310] Example 74 may include the method of Example 73 or some other example herein, where mapping the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth includes: mapping the BPSK-modulated bits of the complex-valued M-sequence to the in-phase constellation of the central subcarriers of the SS bandwidth; and mapping the BPSK-modulated bits of the real-valued M-sequence to the quadrature constellation of the central subcarriers of the SS bandwidth.

[0311] Example 75 may include the method of Example 72 or some other example herein, further including performing a bitwise exclusive OR (XOR) operation on the two cyclic shifted M-sequences.

[0312] Example 76 may include the method of Example 72 or some other example herein, further including performing a post-modulation symbol multiplication of the BPSK-modulated bits of the two cyclic shifted M-sequences.

[0313] Example 77 may include the method of Example 72, 73, 74, 75 or 76 or some other example herein, where the cyclic shift is based on a cell identity.

[0314] Example 78 may include the method of Example 72, 73, 74, 75 or 76 or some other example herein, where the length is selected from one of 127 or 255.

[0315] Example 79 may include an apparatus for a base station, comprising: means for generating two maximal length sequences (M-sequences) based on two different primitive polynomials, wherein each M-sequence has a certain length; means for performing a cyclic shift of the two M-sequences to generate two cyclic-shifted M-sequences; means for modulating the two cyclic-shifted M-sequences using binary phase shift keying (BPSK) modulation to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and means for mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the length of the M-sequence.

[0316] Example 80 may include the apparatus of Example 79 or some other example herein, further comprising: means for multiplying a first M-sequence of the two M-sequences by a complex value to provide a complex-valued M-sequence; and means for multiplying a second M-sequence of the two M-sequences by a real value to provide a real-valued M-sequence.

[0317] Example 81 may include the apparatus of Example 80 or some other example herein, wherein the means for mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of the SS bandwidth comprises: means for mapping the BPSK-modulated bits of the complex-valued M-sequence to the in-phase constellation of the central subcarriers of the SS bandwidth; and means for mapping the BPSK-modulated bits of the real-valued M-sequence to the quadrature constellation of the central subcarriers of the SS bandwidth.

[0318] Example 82 may include the apparatus of Example 79 or some other example herein, further comprising means for performing a bitwise exclusive OR (XOR) operation on the two cyclic-shifted M-sequences.

[0319] Example 83 may include the apparatus of Example 79 or some other example herein, further comprising means for performing a post-modulation symbol multiplication of the BPSK-modulated bits of the two cyclic-shifted M-sequences.

[0320] Example 84 may include the apparatus of Example 79, 80, 81, 82, or 83 or some other example herein, wherein the cyclic shift is based on a cell identity.

[0321] Example 85 may include the apparatus of Example 79, 80, 81, 82, or 83 or some other example herein, wherein the length is selected from one of 127 or 255.

[0322] Example 86 may include one or more computer-readable media having instructions that, when executed, cause a user equipment (UE) to: receive a synchronization signal (SS) block including a secondary synchronization signal (SSS) sequence; detect the SSS sequence; identify a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on a maximum length sequence (M-sequence) used to generate the SSS sequence; and determine a cellular network identity based on applying the cyclic shift parameters to a cyclic shift version of the M-sequence.

[0323] Example 87 may include one or more computer-readable media of Example 86 or some other example herein, wherein the SSS sequence is a modulation-by-symbol multiplication of BPSK-modulated bits based on cyclic shift versions of two M-sequences.

[0324] Example 88 may include one or more computer-readable media of Example 87 or some other example herein, wherein the instructions, when executed, further cause the UE to determine cyclic shift versions of the two M-sequences.

[0325] Example 89 may include one or more computer-readable media of Example 86, 87, or 88 or some other example herein, wherein the cyclic shift parameters are identified from cyclic shifts of the M-sequence used to generate the SSS sequence.

[0326] Example 90 may include one or more computer-readable media of Example 86, 87, or 88 or some other example herein, wherein, to identify the plurality of cyclic shift parameters, the instructions, when executed, further cause the UE to perform one or more Hadamard transform functions on the SSS sequence, wherein the result of the Hadamard transform function is the cyclic shift parameter.

[0327] Example 91 may include a method of signal detection, including: receiving a synchronization signal (SS) block including a secondary synchronization signal (SSS) sequence; detecting the SSS sequence; identifying a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on a maximum length sequence (M-sequence) used to generate the SSS sequence; and determining a cellular network identity based on applying the cyclic shift parameters to a cyclic shift version of the M-sequence.

[0328] Example 92 may include the method of Example 91 or some other example herein, wherein the SSS sequence is a modulation-by-symbol multiplication of BPSK-modulated bits based on cyclic shift versions of two M-sequences.

[0329] Example 93 may include the method of Example 92 or some other example herein, further including determining cyclic shift versions of the two M-sequences.

[0330] Example 94 may include the method of Example 91, 92, or 93 or some other example herein, wherein the cyclic shift parameter is identified from a cyclic shift of the M-sequence used to generate the SSS sequence.

[0331] Example 95 may include the method of Example 91, 92, or 93 or some other example herein, wherein identifying the plurality of cyclic shift parameters includes performing one or more Hadamard transform functions on the SSS sequence, and the result of the Hadamard transform function is the cyclic shift parameter.

[0332] Example 96 may include a device for a user equipment (UE), comprising: means for receiving a synchronization signal (SS) block including a secondary synchronization signal (SSS) sequence; means for detecting the SSS sequence; means for identifying a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on a maximum length sequence (M-sequence) used to generate the SSS sequence; and means for determining a cellular network identity based on applying the cyclic shift parameter to a cyclic shift version of the M-sequence.

[0333] Example 97 may include the device of Example 96 or some other example herein, wherein the SSS sequence is modulated by BPSK-modulated bits of a cyclic shift version of two M-sequences and then multiplied symbol-by-symbol.

[0334] Example 98 may include the device of Example 97 or some other example herein, further comprising means for determining a cyclic shift version of the two M-sequences.

[0335] Example 99 may include the device of Example 96, 97, or 98 or some other example herein, wherein the cyclic shift parameter is identified from a cyclic shift of the M-sequence used to generate the SSS sequence.

[0336] Example 100 may include the device of Example 96, 97, or 98 or some other example herein, wherein the means for identifying the plurality of cyclic shift parameters includes means for performing one or more Hadamard transform functions on the SSS sequence, and the result of the Hadamard transform function is the cyclic shift parameter.

[0337] Example 101 may include a signal, comprising a secondary synchronization signal based on a modulated cyclic shift version of an M-sequence generated from a primitive polynomial.

[0338] Example 102 may include a signal, comprising a secondary synchronization signal based on a first M-sequence of two M-sequences multiplied by a complex value and a second M-sequence of the two M-sequences multiplied by a real value.

[0339] Example 103 may include a signal including a secondary synchronization signal based on a bitwise exclusive OR (XOR) operation of cyclically shifted versions of two M-sequences generated from two different primitive polynomials.

[0340] Example 104 may include a signal including a secondary synchronization signal based on a post-modulation symbol-by-symbol multiplication of BPSK-modulated bits of cyclically shifted versions of two M-sequences generated from two different primitive polynomials.

[0341] Various embodiments may include any suitable combination of the above embodiments, including alternative (or) embodiments of the embodiments described above in a conjunctive form (and) (e.g., "and" may be "and / or"). Additionally, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, cause the actions of any of the above embodiments. Further, some embodiments may include a device or system having any suitable means for performing the various operations of the above embodiments.

[0342] The above description of the implementations of the drawings, including those described in the abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for purposes of illustration, various equivalent modifications are possible within the scope of the present disclosure, as will be recognized by those of ordinary skill in the relevant art.

[0343] These modifications may be made to the embodiments of the present disclosure in light of the above detailed description. The terms used in the appended claims should not be construed to limit the various embodiments of the present disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope is determined entirely by the appended claims, which are to be interpreted in accordance with established claim interpretation principles.

Claims

1. A user equipment, comprising: an interface circuit for receiving a synchronization signal SS block including a secondary synchronization signal SSS sequence, wherein the SSS sequence is based on a symbol-by-symbol multiplication of BPSK-modulated bits of two cyclically shifted versions of an M sequence; a processing circuit coupled to the interface circuit for: detecting the SSS sequence; identifying a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on the M sequence used to generate the SSS sequence; and determining a cellular network identity based on applying the plurality of cyclic shift parameters to a cyclically shifted version of the M sequence.

2. A method for signal detection, comprising: receiving a synchronization signal SS block including a secondary synchronization signal SSS sequence, wherein the SSS sequence is based on a symbol-by-symbol multiplication of BPSK-modulated bits of two cyclically shifted versions of an M sequence; detecting the SSS sequence; identifying a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on the M sequence used to generate the SSS sequence; and determining a cellular network identity based on applying the plurality of cyclic shift parameters to a cyclically shifted version of the M sequence.

3. The user equipment according to claim 1, wherein the SSS sequence is mapped to several central subcarriers of the SS block.

4. The user equipment according to claim 1, wherein the SSS sequence is generated by multiplying two cyclically shifted BPSK - modulated M sequences according to d(n)=(1–2·c0 (m 0 ) (n))·((1–2·c1 (m 1 ) (n)), where d(n) is the SSS sequence, and where c0 (m 0 ) (n)=s0((n + m0) mod L) is the cyclic shift of the first M sequence s0 of the two cyclically shifted BPSK - modulated M sequences, and c1 (m 1 ) (n)=s1((n + m1) mod L) is the cyclic shift of the second M sequence s1 of the two cyclically shifted BPSK - modulated M sequences, where m0 is the first cyclic shift value and m1 is the second cyclic shift value, where L is the length of the sequence, where n ranges from 0 to L - 1, where the first M sequence is generated from a first primitive polynomial, and the second M sequence is generated from a second primitive polynomial.

5. The user equipment according to claim 4, wherein L is equal to 127.

6. The user equipment according to claim 4, wherein the first M-sequence s0 is generated from the first primitive polynomial x 7 +x 4 +1, and wherein the second M-sequence s1 is generated from the second primitive polynomial x 7 +x + 1.

7. The user equipment according to claim 5 or 6, wherein an initial state of the M sequence is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

8. The user equipment according to claim 1, wherein the SSS sequence is generated by performing a bitwise exclusive OR (XOR) operation on a first M sequence and a second M sequence.

9. The user equipment according to claim 1, wherein the SSS sequence is generated by performing a symbol-by-symbol multiplication on BPSK-modulated bits of a first M sequence and BPSK-modulated bits of a second M sequence.

10. The method according to claim 2, wherein the SSS sequence is mapped to several central subcarriers of the SS block.

11. The method according to claim 2, wherein the SSS sequence is generated by multiplying two cyclically shifted BPSK - modulated M sequences according to d(n)=(1–2·c0 (m 0 ) (n))·((1–2·c1 (m 1 ) (n)), where d(n) is the SSS sequence, and where c0 (m 0 ) (n)=s0((n + m0) mod L) is a cyclic shift of the first M sequence s0 of the two cyclically shifted BPSK - modulated M sequences, and c1 (m 1 ) (n)=s1((n + m1) mod L) is a cyclic shift of the second M sequence s1 of the two cyclically shifted BPSK - modulated M sequences, where m0 is the first cyclic - shift value and m1 is the second cyclic - shift value, where L is the length of the sequence, where n ranges from 0 to L - 1, where the first M sequence is generated from a first primitive polynomial, and the second M sequence is generated from a second primitive polynomial.

12. The method according to claim 11, wherein the first M-sequence s0 is generated from the first primitive polynomial x 7 + x 4 + 1, and wherein the second M-sequence s1 is generated from the second primitive polynomial x 7 + x + 1.

13. The method according to claim 12, wherein an initial state of the M sequence is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

14. The method according to claim 2, wherein the SSS sequence is generated by performing a bitwise exclusive OR (XOR) operation on a first M sequence and a second M sequence.

15. The method according to claim 2, wherein the SSS sequence is generated by performing a symbol-by-symbol multiplication on BPSK-modulated bits of a first M sequence and BPSK-modulated bits of a second M sequence.

16. A non-transitory computer-readable medium having instructions that, when executed by one or more processors, cause a user equipment to: receive a synchronization signal SS block including a secondary synchronization signal SSS sequence, wherein the SSS sequence is based on a symbol-by-symbol multiplication of BPSK-modulated bits of two cyclically shifted versions of an M sequence; Detect the SSS sequence; Identify a plurality of cyclic shift parameters, wherein the plurality of cyclic shift parameters are based on the M sequence used to generate the SSS sequence; And Determine the cellular network identity based on applying the plurality of cyclic shift parameters to a cyclic shift version of the M sequence.

17. The non-transitory computer-readable medium according to claim 16, wherein the SSS sequence is mapped to several central subcarriers of the SS block.

18. The non-transitory computer-readable medium according to claim 16, wherein the SSS sequence is generated by multiplying two cyclically shifted BPSK-modulated M sequences according to d(n) = (1 – 2·c0 (m 0 ) (n))·((1 – 2·c1 (m 1 ) (n)), where d(n) is the SSS sequence, and where c0 (m 0 ) (n) = s0((n + m0) mod L) is a cyclic shift of the first M sequence s0 of the two cyclically shifted BPSK-modulated M sequences, and c1 (m 1 ) (n) = s1((n + m1) mod L) is a cyclic shift of the second M sequence s1 of the two cyclically shifted BPSK-modulated M sequences, where m0 is a first cyclic shift value and m1 is a second cyclic shift value, where L is the length of the sequence, where n ranges from 0 to L minus 1, where the first M sequence is generated from a first primitive polynomial, and the second M sequence is generated from a second primitive polynomial.

19. The non-transitory computer-readable medium according to claim 18, wherein the first M-sequence s0 is generated from the first primitive polynomial x 7 + x 4 + 1, and wherein the second M-sequence s1 is generated from the second primitive polynomial x 7 + x + 1.

20. The non-transitory computer-readable medium according to claim 16, wherein the SSS sequence is generated by performing a bitwise exclusive OR (XOR) operation on a first M sequence and a second M sequence.

Images