Three-dimensional memory devices including through-memory-level via structures and methods of manufacturing the same

Abstract

A three-dimensional memory device can include an alternating stack of insulating layers and electrically conductive layers over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric slabs interleaved with laterally extending portions of the insulating layers of the at least one alternating stack. Electrically conductive via structures can vertically extend through each dielectric slab and the insulating layers and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric slabs and into openings through the semiconductor material layer and can contact a lower level dielectric material layer in which the underlying metal interconnect structure is embedded to enhance structural support of the three-dimensional memory device during fabrication.

Description

[0001] Related applications

[0002] This application claims priority to the following patent applications: U.S. Non-Provisional Patent Application No. 16 / 893,933, filed June 5, 2020; and U.S. Non-Provisional Patent Application No. 16 / 893,995, filed June 5, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates in general to the field of semiconductor devices, and more specifically to three-dimensional memory devices including through-hole structures throughout the memory hierarchy and methods for manufacturing the same. Background Technology

[0004] Three-dimensional memory devices may include memory stack structures. The memory stack structure covers a substrate and extends through alternating stacks of insulating and conductive layers. The memory stack structure includes a vertical stack of memory elements disposed at levels of the conductive layers. Peripheral devices may be disposed on the substrate below the alternating stacks and the memory stack structure. Summary of the Invention

[0005] According to one aspect of this disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: at least one alternating stack of insulating and conductive layers, the at least one alternating stack being located above an underlying interconnect structure; memory stack structures extending vertically through the at least one alternating stack; a vertical stack of dielectric oxide plates interleaved with lateral extensions of the insulating layers of the at least one alternating stack, wherein each dielectric oxide plate is located between a pair of corresponding vertically adjacent insulating layers of the at least one alternating stack; and a conductive via structure extending vertically through each dielectric oxide plate within the vertical stack and each lateral extension of the at least one alternating stack of insulating layers, and contacting the underlying metal interconnect structure.

[0006] According to another aspect of this disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming at least one alternating stack of insulating layers and sacrificial material layers over an underlying interconnect structure; forming a memory stack structure through the at least one alternating stack; forming a recessed trench through the at least one alternating stack; replacing a first portion of the sacrificial material layers adjacent to the recessed trench with dielectric oxide plates, wherein the dielectric oxide plates are interleaved with portions of the at least one alternating stack of insulating layers; replacing a second portion of the sacrificial material layers with conductive layers; and forming a conductive via structure directly on the top surface of the underlying metal interconnect structure through the dielectric oxide plates and the insulating layers.

[0007] According to another aspect of this disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: a semiconductor material layer covering a substrate and including an opening therein; lower-level dielectric material layers located between the substrate and the semiconductor material layer and extending into the opening in the semiconductor material layer; at least one alternating stack of insulating and conductive layers covering the semiconductor material layer; memory stack structures extending vertically through the at least one alternating stack; a vertical stack of dielectric plates located at each level of the conductive layers; a contact via structure extending vertically through the vertical stack of dielectric plates and through the opening in the semiconductor material layer; a first support pillar structure extending vertically through the vertical stack of dielectric plates and contacting a portion of the lower-level dielectric material layer located within the opening in the semiconductor material layer; and a second support pillar structure extending vertically through the at least one alternating stack and contacting the semiconductor material layer.

[0008] According to another aspect of this disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming a lower-level dielectric material layer over a substrate in which metal interconnect structures are embedded; forming a semiconductor material layer including an opening over the lower-level dielectric material layer; forming at least one alternating stack of an insulating layer and a sacrificial material layer over the semiconductor material layer; forming a memory stack structure through the at least one alternating stack; forming a support pillar structure through the at least one alternating stack, wherein a first subset of the support pillar structures is formed over the opening in the semiconductor material layer on the dielectric material layer, and a second subset of the support pillar structures contacts the semiconductor material layer but does not contact the dielectric material layer; forming a vertical stack of dielectric plates over the opening in the semiconductor material layer by patterning the sacrificial material layers or by replacing portions of the sacrificial material layers with dielectric material portions; replacing the remaining portions of the sacrificial material layers with a conductive layer; and forming a contact via structure through the vertical stack of the dielectric plates and through the opening in the semiconductor material layer on one of the metal interconnect structures. Attached Figure Description

[0009] FIG. 1A This is a vertical cross-sectional view of a first exemplary structure following the formation of a semiconductor device, a lower-level dielectric layer, a lower-level metal interconnect structure, and a source-level material layer on a semiconductor substrate according to a first embodiment of the present disclosure.

[0010] FIG. 1B yes FIG. 1A The top view of the first exemplary structure. The hinged vertical plane A-A' is FIG. 1AThe vertical cross-sectional view of the plane.

[0011] FIG. 1C It is along FIG. 1B An enlarged view of the source layer material layer during the process of the vertical plane C-C'.

[0012] FIG. 2 This is a vertical cross-sectional view of a first exemplary structure after alternating stacking of a first insulating layer and a first sacrificial material layer, according to a first embodiment of the present disclosure.

[0013] FIG. 3 This is a vertical cross-sectional view of a first exemplary structure following a patterned first staircase area, a first backward stepped dielectric material portion, and an interlayer dielectric layer, according to a first embodiment of the present disclosure.

[0014] FIG. 4A This is a vertical cross-sectional view of a first exemplary structure after the formation of a first layer memory opening and a first layer support opening, according to a first embodiment of the present disclosure.

[0015] FIG. 4B yes FIG. 4A The top view of the first exemplary structure. The hinged vertical plane A-A' corresponds to... FIG. 4A The vertical cross-sectional view of the plane.

[0016] FIG. 4C yes FIG. 4A A top view of another region in the first exemplary structure.

[0017] FIG. 5 This is a vertical cross-sectional view of a first exemplary structure after various sacrificial infill structures have been formed, according to a first embodiment of the present disclosure.

[0018] FIG. 6A This is a vertical cross-sectional view of a first exemplary structure following the formation of a second layer of alternating stacking of a second insulating layer and a second sacrificial material layer, a second stepped surface, and a second backward stepped dielectric material portion, according to a first embodiment of the present disclosure.

[0019] FIG. 6B yes FIG. 6A The top view of the first exemplary structure. The hinged vertical plane A-A' corresponds to... FIG. 6A The vertical cross-sectional view of the plane.

[0020] FIG. 7A This is a vertical cross-sectional view of a first exemplary structure after the formation of the second layer memory opening and the second layer support opening, according to a first embodiment of the present disclosure.

[0021] FIG. 7B It is intercepted along plane B-B'. FIG. 7AThe first exemplary structure is shown in a horizontal cross-sectional view. The hinged vertical plane A-A' corresponds to... FIG. 7A The vertical cross-sectional view of the plane.

[0022] FIG. 7C yes FIG. 7A and FIG. 7B Another vertical cross-sectional view of the first exemplary structure.

[0023] FIG. 7D yes FIG. 7A A horizontal sectional view of another region at the height of the horizontal plane B-B' of the first exemplary structure. The hinged vertical plane C-C' corresponds to... FIG. 7C The vertical cross-sectional view of the plane.

[0024] FIG. 8A This is a vertical cross-sectional view of a first exemplary structure after the formation of interlayer memory openings and interlayer support openings, according to a first embodiment of the present disclosure.

[0025] FIG. 8B It is intercepted along plane B-B'. FIG. 8A The first exemplary structure is shown in a horizontal cross-sectional view. The hinged vertical plane A-A' corresponds to... FIG. 8A The vertical cross-sectional view of the plane.

[0026] FIG. 8C yes FIG. 8A and FIG. 8B Another vertical cross-sectional view of the first exemplary structure.

[0027] FIG. 8D yes FIG. 8A A horizontal sectional view of another region at the height of the horizontal plane B-B' of the first exemplary structure. The hinged vertical plane C-C' corresponds to... FIG. 8C The vertical cross-sectional view of the plane.

[0028] FIG. 9A This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of the sacrificial memory opening filling material portion, according to a first embodiment of the present disclosure.

[0029] FIG. 9B It is along FIG. 9A A horizontal cross-sectional view of the first exemplary structure taken from plane B-B'.

[0030] FIG. 10A This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a support column structure, according to a first embodiment of the present disclosure.

[0031] FIG. 10B It is along FIG. 10A A horizontal cross-sectional view of the first exemplary structure taken from plane B-B'.

[0032] FIG. 11A This is a vertical cross-sectional view of a region of a first exemplary structure after the removal of the sacrificial memory opening filler material portion, according to a first embodiment of the present disclosure.

[0033] FIG. 11B It is along FIG. 11A A horizontal cross-sectional view of the first exemplary structure taken from plane B-B'.

[0034] FIG. 12A to FIG. 12D A sequential vertical cross-sectional view of the memory openings during the formation of the memory opening filling structure, according to a first embodiment of the present disclosure, is shown.

[0035] FIG. 13A This is a vertical cross-sectional view of a first exemplary structure after the formation of a memory opening-filling structure, according to a first embodiment of the present disclosure.

[0036] FIG. 13B yes FIG. 8A and FIG. 8B Another vertical cross-sectional view of the first exemplary structure.

[0037] FIG. 13C It is along FIG. 13B The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 13B The vertical cross-sectional view of the plane.

[0038] FIG. 14A This is a vertical cross-sectional view of a first exemplary structure after the formation of the back side groove and the recessed groove, according to a first embodiment of the present disclosure.

[0039] FIG. 14B yes FIG. 14A Another vertical cross-sectional view of the first exemplary structure.

[0040] FIG. 14C It is along FIG. 14B The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 14B The vertical cross-sectional view of the plane.

[0041] FIG. 15A This is a vertical cross-sectional view of a first exemplary structure after the formation and patterning of an etched barrier pad, according to a first embodiment of the present disclosure.

[0042] FIG. 15B It is along FIG. 15A The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane B-B'. The hinged vertical plane A-A' corresponds to... FIG. 15AThe vertical cross-sectional view of the plane.

[0043] FIG. 16A This is a vertical cross-sectional view of a first exemplary structure after the formation and patterning of an etched barrier pad, according to a first embodiment of the present disclosure.

[0044] FIG. 16B It is along FIG. 16A The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane B-B'. The hinged vertical plane A-A' corresponds to... FIG. 16A The vertical cross-sectional view of the plane.

[0045] FIG. 17A This is a vertical cross-sectional view of a first exemplary structure after forming fin-like cavities around each recessed groove, according to a first embodiment of the present disclosure.

[0046] FIG. 17B It is along FIG. 17A The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane B-B'. The hinged vertical plane A-A' corresponds to... FIG. 17A The vertical cross-sectional view of the plane.

[0047] FIG. 18A This is a vertical cross-sectional view of a first exemplary structure after the formation of a dielectric oxide board, according to a first embodiment of the present disclosure.

[0048] FIG. 18B It is along FIG. 18A The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane B-B'. The hinged vertical plane A-A' corresponds to... FIG. 18A The vertical cross-sectional view of the plane.

[0049] FIG. 18C It is along FIG. 18B A vertical cross-sectional view of the first exemplary structure taken from the vertical plane C-C'.

[0050] FIG. 19A to FIG. 19D A sequential vertical cross-sectional view of the memory opening-filling structure and back-side trench during the formation of the source-level material layer, according to a first embodiment of the present disclosure, is shown.

[0051] FIG. 20A This is a vertical cross-sectional view of a first exemplary structure after forming a dielectric semiconductor oxide material plate, according to a first embodiment of the present disclosure.

[0052] FIG. 20B yes FIG. 20A Another vertical cross-sectional view of the first exemplary structure.

[0053] FIG. 20C It is along FIG. 20BThe horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 20B The vertical cross-sectional view of the plane.

[0054] FIG. 20D It is along FIG. 20C A vertical cross-sectional view of the first exemplary structure taken from the vertical plane D-D'.

[0055] FIG. 21A This is a vertical cross-sectional view of a first exemplary structure after the formation of the back recess according to a first embodiment of the present disclosure.

[0056] FIG. 21B yes FIG. 21A Another vertical cross-sectional view of the first exemplary structure.

[0057] FIG. 21C It is along FIG. 21B The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 21B The vertical cross-sectional view of the plane.

[0058] FIG. 21D It is along FIG. 21C A vertical cross-sectional view of the first exemplary structure taken from the vertical plane D-D'.

[0059] FIG. 22A This is a vertical cross-sectional view of a first exemplary structure after the formation of a conductive layer, according to a first embodiment of the present disclosure.

[0060] FIG. 22B yes FIG. 22A Another vertical cross-sectional view of the first exemplary structure.

[0061] FIG. 22C It is along FIG. 22B The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 22B The vertical cross-sectional view of the plane.

[0062] FIG. 22D It is along FIG. 22C A vertical cross-sectional view of the first exemplary structure taken from the vertical plane D-D'.

[0063] FIG. 23A This is a vertical cross-sectional view of a first exemplary structure after the formation of the back-side trench filling structure and the wall structure, according to a first embodiment of the present disclosure.

[0064] FIG. 23B yes FIG. 23A Another vertical cross-sectional view of the first exemplary structure.

[0065] FIG. 23C It is along FIG. 23B The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 23B The vertical cross-sectional view of the plane.

[0066] FIG. 23D It is along FIG. 23C A vertical cross-sectional view of the first exemplary structure taken from the vertical plane D-D'.

[0067] FIG. 24A This is a vertical cross-sectional view of a first exemplary structure after the formation of a contact via structure and a higher-level metal interconnect structure, according to a first embodiment of the present disclosure.

[0068] FIG. 24B yes FIG. 24A Another vertical cross-sectional view of the first exemplary structure.

[0069] FIG. 24C It is along FIG. 24B The horizontal cross-sectional view of the first exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 24B The vertical cross-sectional view of the plane.

[0070] FIG. 24D It is along FIG. 24C A vertical cross-sectional view of the first exemplary structure taken from the vertical plane D-D'.

[0071] FIG. 24E Along the layers of semiconductor material FIG. 24B The vertical plane E-E' intercepts FIG. 24A to FIG. 24D A horizontal cross-sectional view of the first exemplary structure.

[0072] FIG. 25A to FIG. 25C yes FIG. 24A to FIG. 24E A horizontal cross-sectional view of an alternative configuration of the first exemplary structure.

[0073] FIG. 26A This is a vertical cross-sectional view of a second exemplary structure after the formation of a contact via structure and a higher-level metal interconnect structure, according to a second embodiment of the present disclosure.

[0074] FIG. 26B yes FIG. 26A Another vertical cross-sectional view of the second exemplary structure.

[0075] FIG. 26C It is along FIG. 26B The horizontal cross-sectional view of the second exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 26BThe vertical cross-sectional view of the plane.

[0076] FIG. 26D It is along FIG. 26C A vertical cross-sectional view of the second exemplary structure taken from the vertical plane D-D'.

[0077] FIG. 26E At the layer level of semiconductor material FIG. 26A to FIG. 26D A horizontal cross-sectional view of the second exemplary structure.

[0078] FIG. 27A to FIG. 27D This is a vertical cross-sectional view of an alternative configuration of a second exemplary structure following the formation of a contact via structure and a higher-level metal interconnect structure, according to a second embodiment of the present disclosure.

[0079] FIG. 28A This is a vertical cross-sectional view of a third exemplary structure after the formation of the support column structure and the memory opening filling structure, according to a third embodiment of the present disclosure.

[0080] FIG. 28B yes FIG. 28A Another vertical cross-sectional view of the third exemplary structure.

[0081] FIG. 28C It is along FIG. 28B The horizontal cross-sectional view of the third exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 28B The vertical cross-sectional view of the plane.

[0082] FIG. 29A This is a vertical cross-sectional view of a third exemplary structure after the formation of the back side trench and the trench trench, according to a third embodiment of the present disclosure.

[0083] FIG. 29B yes FIG. 29A Another vertical cross-sectional view of the third exemplary structure.

[0084] FIG. 29C It is along FIG. 29B The horizontal cross-sectional view of the third exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 29B The vertical cross-sectional view of the plane.

[0085] FIG. 30A This is a vertical cross-sectional view of a third exemplary structure after the formation of a patterned etch barrier pad, according to a third embodiment of the present disclosure.

[0086] FIG. 30B yes FIG. 30A Another vertical cross-sectional view of the third exemplary structure.

[0087] FIG. 30C It is along FIG. 30B The horizontal cross-sectional view of the third exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 30B The vertical cross-sectional view of the plane.

[0088] FIG. 31 This is a vertical cross-sectional view of a third exemplary structure following the replacement of the source layer material layer during the process of replacing the source layer material layer according to the third embodiment of this disclosure.

[0089] FIG. 32A This is a vertical cross-sectional view of a third exemplary structure after the formation of the back recess according to a third embodiment of the present disclosure.

[0090] FIG. 32B yes FIG. 32A Another vertical cross-sectional view of the third exemplary structure.

[0091] FIG. 32C It is along FIG. 32B The horizontal cross-sectional view of the third exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 32B The vertical cross-sectional view of the plane.

[0092] FIG. 32D It is along FIG. 32C A vertical cross-sectional view of the third exemplary structure taken from the vertical plane D-D'.

[0093] FIG. 33A This is a vertical cross-sectional view of a first exemplary structure after the formation of the conductive layer, the back trench filling structure, and the dielectric trench filling structure, according to a third embodiment of the present disclosure.

[0094] FIG. 33B yes FIG. 33A Another vertical cross-sectional view of the third exemplary structure.

[0095] FIG. 33C It is along FIG. 33B The horizontal cross-sectional view of the third exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 33B The vertical cross-sectional view of the plane.

[0096] FIG. 33D It is along FIG. 33C A vertical cross-sectional view of the third exemplary structure taken from the vertical plane D-D'.

[0097] FIG. 34A This is a vertical cross-sectional view of a third exemplary structure after the formation of a contact via structure and a higher-level metal interconnect structure, according to a third embodiment of this disclosure.

[0098] FIG. 34B yes FIG. 34A Another vertical cross-sectional view of the third exemplary structure.

[0099] FIG. 34C It is along FIG. 34B The horizontal cross-sectional view of the third exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 34B The vertical cross-sectional view of the plane.

[0100] FIG. 34D It is along FIG. 34C A vertical cross-sectional view of the third exemplary structure taken from the vertical plane D-D'.

[0101] FIG. 34E At the layer level of semiconductor material FIG. 34A to FIG. 34D A horizontal cross-sectional view of the third exemplary structure.

[0102] FIG. 35A to FIG. 35D This is a vertical cross-sectional view of an alternative embodiment of the third exemplary structure.

[0103] FIG. 36A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a contact-level dielectric material layer, according to a fourth embodiment of the present disclosure.

[0104] FIG. 36B yes FIG. 36A Another vertical cross-sectional view of the fourth exemplary structure.

[0105] FIG. 36C It is along FIG. 36B The horizontal cross-sectional view of the fourth exemplary structure is taken from plane C–C'. Vertical plane B–B' is... FIG. 36B The vertical cross-sectional view of the plane.

[0106] FIG. 36D It is along FIG. 36B The horizontal cross-sectional view of the fourth exemplary structure is taken from plane C–C'. Vertical plane B–B' is... FIG. 36B The vertical cross-sectional view of the plane.

[0107] FIG. 37A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of the back side groove and through-hole opening, according to a fourth embodiment of the present disclosure.

[0108] FIG. 37B yes FIG. 37A Another vertical cross-sectional view of the fourth exemplary structure.

[0109] FIG. 37C It is along FIG. 37BThe horizontal cross-sectional view of the fourth exemplary structure is taken from plane C–C'. Vertical plane B–B' is... FIG. 37B The vertical cross-sectional view of the plane.

[0110] FIG. 38A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a patterned etch barrier pad, according to a fourth embodiment of the present disclosure.

[0111] FIG. 38B yes FIG. 38A Another vertical cross-sectional view of the fourth exemplary structure.

[0112] FIG. 38C It is along FIG. 38B The horizontal cross-sectional view of the fourth exemplary structure is taken from plane C–C'. Vertical plane B–B' is... FIG. 38B The vertical cross-sectional view of the plane.

[0113] FIG. 39 This is a vertical cross-sectional view of a fourth exemplary structure after forming a finned cavity around the through-hole opening according to a fourth embodiment of the present disclosure.

[0114] FIG. 40 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a dielectric material layer, according to a fourth embodiment of the present disclosure.

[0115] FIG. 41A This is a vertical cross-sectional view of a fourth exemplary structure following a vertical stack of dielectric oxide boards according to a fourth embodiment of the present disclosure.

[0116] FIG. 41B It is along FIG. 41A The horizontal cross-sectional view of the fourth exemplary structure is taken from plane B-B'. Vertical plane A-A' is... FIG. 41A The vertical cross-sectional view of the plane.

[0117] FIG. 42 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of at least one sacrificial barrier layer, according to a fourth embodiment of the present disclosure.

[0118] FIG. 43 This is a vertical cross-sectional view of a fourth exemplary structure after patterning the at least one sacrificial barrier layer, according to a fourth embodiment of the present disclosure.

[0119] FIG. 44 This is a vertical cross-sectional view of a fourth exemplary structure following the replacement of the source layer material layer with the source layer material layer according to the fourth embodiment of this disclosure.

[0120] FIG. 45AThis is a vertical cross-sectional view of a fourth exemplary structure after the formation of a conductive layer, according to a fourth embodiment of the present disclosure.

[0121] FIG. 45B It is along FIG. 45A A horizontal cross-sectional view of the fourth exemplary structure in plane B–B'. Vertical plane A–A' is... FIG. 45A The vertical cross-sectional view of the plane.

[0122] FIG. 46A This is a vertical cross-sectional view of a first exemplary structure after the formation of the back-side groove filling structure and t, according to the fourth embodiment of this disclosure.

[0123] FIG. 46B It is along FIG. 46A The horizontal cross-sectional view of the fourth exemplary structure is taken from plane B-B'. Vertical plane A-A' is... FIG. 46A The vertical cross-sectional view of the plane.

[0124] FIG. 47A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a contact via structure and a higher-level metal interconnect structure, according to a fourth embodiment of the present disclosure.

[0125] FIG. 47B yes FIG. 47A Another vertical cross-sectional view of the fourth exemplary structure.

[0126] FIG. 47C It is along FIG. 47B The horizontal cross-sectional view of the fourth exemplary structure is taken from the horizontal plane C–C'. The hinged vertical plane B–B' corresponds to... FIG. 47B The vertical cross-sectional view of the plane.

[0127] FIG. 47D It is along FIG. 47C A vertical cross-sectional view of the fourth exemplary structure taken from the vertical plane D-D'.

[0128] FIG. 47E It is along FIG. 47B A horizontal cross-sectional view of the fourth exemplary structure taken from the horizontal plane E–E'.

[0129] FIG. 48A to FIG. 48D This is a vertical cross-sectional view of an alternative embodiment of the fourth exemplary structure. Detailed Implementation

[0130] The embodiments disclosed herein provide a three-dimensional memory device including a through-hole structure throughout the memory hierarchy and a method for manufacturing the same, various embodiments of which are described in detail herein.

[0131] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0132] The same reference numerals denote the same or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements that provide a shared edge or surface. If two or more elements are not in direct contact with each other, the two elements are “separated” from each other. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path made of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “in-process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0133] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0134] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0135] A monolithic three-dimensional memory array is a memory array in which multiple memory stages are formed on a single substrate, such as a semiconductor wafer, without having an intermediate substrate. The term "monolithic" refers to the fact that the layers of each stage of the array are deposited directly on the layers of each lower stage of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory stages on separate substrates and vertically stacking the memory stages. The substrate may be thinned or removed from the memory stages prior to bonding, but since the memory stages are initially formed on separate substrates, such a memory is not a true monolithic three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein.

[0136] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips"), which are attached therein, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands simultaneously as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0137] refer to FIG. 1A to FIG. 1C This illustrates a first exemplary structure according to a first embodiment of the present disclosure. FIG. 1C yes FIG. 1A and FIG. 1BThe diagram shows an enlarged view of the source layer material layer 10' during the process. A first exemplary structure includes a substrate 8 and a semiconductor device 710 formed thereon. The substrate 8 may include a substrate semiconductor layer 9 at least in its upper portion. A shallow trench isolation structure 720 may be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between the semiconductor devices 710. The semiconductor device 710 may include, for example, field-effect transistors (FETs) including corresponding transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The FETs may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor device 710 may include any semiconductor circuitry to support the operation of a subsequently formed memory structure; this semiconductor circuitry is generally referred to as driver circuitry, and also as peripheral circuitry. As used herein, peripheral circuitry refers to any, each, or all of the word line decoder circuitry, word line switching circuitry, bit line decoder circuitry, bit line sensing and / or switching circuitry, power supply / distribution circuitry, data buffers, and / or latches, or may be any other semiconductor circuitry that can be implemented outside the memory array structure of the memory device. For example, the semiconductor device may include word line switching devices for electrically biasing word lines of the three-dimensional memory structure to be formed.

[0138] A dielectric layer, referred to herein as a lower-level dielectric layer 760, may be formed over the semiconductor device. The lower-level dielectric layer 760 may include, for example, a dielectric pad 762 (such as a silicon nitride pad that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric layer 764 overlying the dielectric pad 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier layer) 766 overlying the first dielectric layer 764, and at least one second dielectric layer 768. A dielectric layer stack (including the lower-level dielectric layer 760) may be used as a matrix of lower-level metal interconnect structures 780, which provide electrical wiring to and from the landing pads of the semiconductor device and subsequently formed through-memory interconnect via structures. The lower-level metal interconnect structures 780 may be formed within the dielectric layer stack of the lower-level dielectric layer 760 and overlying a field-effect transistor. The lower-level metal interconnect structure 780 may include a lower-level metal line structure positioned below and optionally in contact with the bottom surface of the silicon nitride layer 766.

[0139] For example, a lower-level metal interconnect structure 780 may be formed within a first dielectric layer 764. The first dielectric layer 764 may be a plurality of dielectric layers in which various elements of the lower-level metal interconnect structure 780 are sequentially formed. Each dielectric layer selected from the first dielectric layer 764 may include any of doped silicate glass, undoped silicate glass, organosilicon glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the first dielectric layer 764 may comprise or consist substantially of a dielectric layer with a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide). The lower-level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes of corresponding source and drain nodes or gate electrode contacts of devices), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and landing pad level metal interconnect structures 788, which are configured to serve as landing pads for subsequent through-memory level interconnect via structures to be formed.

[0140] A landing pad-level metal interconnect structure 788 can be formed within the topmost dielectric layer of the first dielectric layer 764 (which may be multiple dielectric layers). Each of the lower-level metal interconnect structures 780 may include a metal nitride pad and a metal filler structure. The top surface of the landing pad-level metal interconnect structure 788 and the topmost surface of the first dielectric layer 764 can be planarized using a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 can be formed directly on the top surface of the landing pad-level metal interconnect structure 788 and the topmost surface of the first dielectric layer 764.

[0141] At least one second dielectric layer 768 may comprise a single dielectric material layer or multiple dielectric material layers. Each dielectric material layer selected from at least one second dielectric layer 768 may comprise any of doped silicate glass, undoped silicate glass, and organosilicon glass. In one embodiment, at least one second dielectric material layer 768 may comprise or be substantially composed of a dielectric material layer with a dielectric constant not exceeding 3.9 of undoped silicate glass (silicon oxide).

[0142] Optional layers of metallic and semiconductor materials may be deposited over at least one second dielectric layer 768 or within a patterned recess of the second dielectric layer and photolithographically patterned to provide an optional conductive layer 6 and a process source-level material layer 10'. The optional conductive layer 6 (if present) provides a highly conductive path for current flowing into or out of the source-level material layer 10' during the process. The optional conductive layer 6 comprises conductive materials such as metals or heavily doped semiconductor materials. The optional conductive layer 6 may, for example, comprise a tungsten layer having a thickness in the range of 3 nm to 100 nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of the conductive layer 6 as a diffusion barrier layer. The conductive layer 6 may serve as a special source line in the finished device. Furthermore, the conductive layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor, or insulating layer. The optional conductive layer 6 may include a metal compound material, such as a conductive metal nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional conductive layer 6 can range from 5 nm to 100 nm, but smaller and larger thicknesses can also be used.

[0143] The source-level material layer 10' in the process may include various layers that are subsequently modified to form the source-level material layer. The source-level material layer includes a source contact layer during formation, which serves as a common source region for the vertical field-effect transistors of the three-dimensional memory device. During the process, the source-level material layer 10' may include at least one semiconductor material layer. In one embodiment, the source-level material layer 10' in the process may include, from bottom to top, a lower source-level material layer 112, a lower sacrificial pad 103, a source-level sacrificial layer 104, a higher sacrificial pad 105, a higher source-level semiconductor layer 116, a source-level insulating layer 117, and an optional source-selective conductive layer 118.

[0144] The lower source layer 112 and the higher source layer semiconductor layer 116 may comprise doped semiconductor materials, such as doped polycrystalline silicon or doped amorphous silicon. The conductivity type of the lower source layer 112 and the higher source layer semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a first conductivity type of doping, then the lower source layer 112 and the higher source layer semiconductor layer 116 have a second conductivity type of doping opposite to the first conductivity type. The thickness of each of the lower source layer 112 and the higher source layer semiconductor layer 116 may be in the range of 20 nm to 150 nm, from 10 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0145] The source-level sacrificial layer 104 includes sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the higher sacrificial pad 105. In one embodiment, the source-level sacrificial layer 104 may comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration greater than 20%. The thickness of the source-level sacrificial layer 104 can range from 30 nm to 400 nm, such as from 60 nm to 200 nm, but smaller and larger thicknesses are also possible.

[0146] The lower sacrificial pad 103 and the higher sacrificial pad 105 contain materials that can be used as etch-stop materials during the removal of the source-level sacrificial layer 104. For example, the lower sacrificial pad 103 and the higher sacrificial pad 105 may contain silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial pad 103 and the higher sacrificial pad 105 may contain a silicon oxide layer with a thickness in the range of 2 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0147] The source-level insulating layer 117 may comprise a dielectric material, such as silicon oxide. The thickness of the source-level insulating layer 117 may range from 20 nm to 400 nm, such as 40 nm to 200 nm, but smaller and larger thicknesses are also possible. An optional source-selection layer conductive layer 118 may comprise a conductive material that can be used as a source-selection layer gate electrode. For example, the optional source-selection layer conductive layer 118 may comprise a doped semiconductor material, such as doped polycrystalline silicon or doped amorphous silicon, which may subsequently be converted to doped polycrystalline silicon by an annealing process. The thickness of the optional source-selection layer conductive layer 118 may range from 30 nm to 200 nm, such as 60 nm to 100 nm, but smaller and larger thicknesses are also possible.

[0148] During the process, the source layer 10' may be formed directly above a subset of semiconductor devices on the substrate 8 (e.g., a silicon wafer). As used herein, the first element is positioned "directly above" the second element if the first element is positioned above a horizontal plane including the topmost surface of the second element and the region of the first element, and the region of the second element has regional overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8). In one embodiment, the source layer 10' may have openings in each region where a through-memory interconnect via structure is subsequently formed. For example, the source layer 10' may have openings in the memory array region 100. Thus, each of the at least one semiconductor material layer in the source layer 10' includes an opening therethrough. Each opening may be rectangular, circular, or have a shape with only a single perimeter, or may have an annular shape including an inner perimeter and an outer perimeter. In the case where the opening has an annular shape, the patterned portion of the source layer 10' may be located inside the inner perimeter.

[0149] The optional conductive plate layer 6 and the source-level material layer 10' in the process can be patterned to provide openings in regions where through-memory-level interconnect via structures and through-dielectric contact via structures will subsequently be formed. The patterned portion of the stack of conductive plate layer 6 and source-level material layer 10' in the process exists in each memory array region 100, in which a three-dimensional memory stack structure will subsequently be formed.

[0150] The optional conductive plate layer 6 and the source-level material layer 10' in the process can be patterned such that openings extend above the staircase region 200, where the contact via structure for the contact word line conductive layer will subsequently be formed. In one embodiment, the staircase region 200 may be laterally spaced from the memory array region 100 along a first horizontal direction hd1. The horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as a second horizontal direction hd2. In one embodiment, additional openings in the optional conductive plate layer 6 and the source-level material layer 10' in the process may be formed within the region of the memory array region 100, in which a three-dimensional memory array including a memory stack structure will subsequently be formed. A peripheral device region 400, which may subsequently be filled with a portion of field dielectric material, may be provided adjacent to the staircase region 200.

[0151] The region comprising the semiconductor device 710, a lower-level dielectric layer 760, and a lower-level metal interconnect structure 780, referred herein as the lower peripheral device region 700, is located below the memory tier assembly to be formed and includes peripheral devices for the memory tier assembly. The lower-level metal interconnect structure 780 may be formed in the lower-level dielectric layer 760.

[0152] Lower-level metal interconnect structures 780 may be electrically connected to active nodes (e.g., transistor active regions 742 or gate electrodes 754) of a semiconductor device 710 (e.g., a CMOS device) and may be located at the level of a lower-level dielectric layer 760. Through-memory interconnect via structures can then be formed directly on the lower-level metal interconnect structure 780 to provide electrical connections to memory devices to be formed subsequently. Generally, semiconductor devices may be formed on the top surface of a semiconductor substrate, and subsets of the lower-level metal interconnect structures 780 may be electrically connected to corresponding nodes of the semiconductor devices. In one embodiment, the pattern of the lower-level metal interconnect structures 780 may be selected such that a landing pad-level metal interconnect structure 788 (which is a subset of the lower-level metal interconnect structures 780 located at the topmost portion of the lower-level metal interconnect structure 780) may provide a landing pad structure for the subsequently formed through-memory interconnect via structures.

[0153] refer to FIG. 2 Alternating stacks of first and second material layers can be formed. Each first material layer may contain a first material, and each second material layer may contain a second material different from the first material. In embodiments where at least another alternating stack of material layers is subsequently formed over the alternating stack of first and second material layers, the alternating stack is referred to herein as a first layer alternating stack. The hierarchy of the first layer alternating stack is referred to herein as a first layer hierarchy, and the hierarchy of the alternating stack to be subsequently formed directly above the first layer hierarchy is referred to herein as a second layer hierarchy, and so on.

[0154] The first layer alternating stack may include a first insulating layer 132 as a first material layer and a first sacrificial material layer as a second material layer. In one embodiment, the first sacrificial material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first sacrificial material layer may be a conductive layer that is not subsequently replaced by other layers. Although this disclosure has been described using embodiments in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the sacrificial material layer is formed as a conductive layer (thus eliminating the need to perform a replacement process) are explicitly contemplated herein.

[0155] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. During the process, a plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the source layer material layer 10'. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

[0156] As used herein, alternating stacking of first and second elements refers to a structure in which instances of first and second elements alternate. Each instance of the first element in a non-alternating plurality of elements' end elements is adjacent to two instances of the second element on both sides, and each instance of the second element in a non-alternating plurality of elements' end elements is adjacent to two instances of the first element at both ends. The first elements may always have the same thickness or may have different thicknesses. The second elements may always have the same thickness or may have different thicknesses. Alternating plurality of first and second material layers may begin with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, instances of the first and second elements may form units that are periodically repeated within the alternating plurality of elements.

[0157] The first alternating stack (132, 142) may include a first insulating layer 132 made of a first material and a first sacrificial material layer 142 made of a second material, which is different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) commonly referred to as high dielectric constant (high k) dielectric oxides and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0158] The second material of the first sacrificial material layer 142 may be a sacrificial material that can be selectively removed with respect to the first material of the first insulating layer 132. As used herein, the removal of the first material is "selective" with respect to the second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0159] The second material of the first sacrificial material layer 142 can then be replaced by a conductive electrode, which can be used as, for example, a control gate electrode for a vertical NAND device. According to aspects of this disclosure, the first sacrificial material layer 142 comprises a dielectric material. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride.

[0160] In one embodiment, the first insulating layer 132 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. A second material may be formed for the first sacrificial material layer 142, for example, by CVD or atomic layer deposition (ALD).

[0161] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the alternating stack of first layers (132, 142) may have a substantially uniform thickness that remains constant within each respective first sacrificial material layer 142.

[0162] A first insulating cap layer 170 may then be formed over the alternating stack of first layers (132, 142). The first insulating cap layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating cap layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating cap layer 170 may range from 20 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0163] refer to FIG. 4A to FIG. 4C Various first-layer openings (149, 129, 119) can be formed by passing through the interlayer dielectric layer 180 and the first-layer structure (132, 142, 170, 165) into the process source layer material layer 10'. A photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be photolithographically patterned to form various openings passing through it.

[0164] The pattern of openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the source layer material layer 10' during the process by a first anisotropic etching process, to simultaneously (i.e., during the first isotropic etching process) form various first layer openings (149, 129, 119). The various first layer openings (149, 129, 119) may include first layer memory openings 149 and first layer support openings (129, 119). A first subset of the first layer support openings 119 is located in the memory array region 100, while a second subset of the first layer support openings 129 is located in the staircase region 200. FIG. 4B The position of step S in the first layer of alternating stacks (132, 142) is shown by dashed lines.

[0165] Generally, the cell pattern UP of the combination of the first layer memory opening 149 and the first layer support opening 129 can be repeated along the second horizontal direction hd2 (e.g., the bit line direction). Each cell pattern UP includes a group 339 of clusters 319 of the first layer memory openings 149 that are laterally spaced along the second horizontal direction hd2 and / or laterally spaced along the first horizontal direction hd1 (e.g., the word line direction).

[0166] The first layer memory opening 149 may be an opening formed in the memory array region 100 through each layer within the first layer alternating stack (132, 142), and subsequently used to form a memory stack structure therein. The first layer memory opening 149 may be formed as a cluster 319 of the first layer memory openings 149 spaced laterally along the second horizontal direction hd2. Each cluster 319 of the first layer memory opening 149 may be formed as a two-dimensional array of the first layer memory openings 149. A set of adjacent clusters 319 of the first layer memory opening 149 forms a group 339 of the first layer memory openings 149.

[0167] A first subset of the first layer support openings 119 may be formed in a segment of the memory array region 100 that is not filled with the first layer memory openings 149. For example, the first subset of the first layer support openings 119 may be located between adjacent groups 339 of the first layer memory openings 149, such as... FIG. 4C As shown. In the first exemplary structure, a first subset of the first layer support opening 119 may be formed into the process source layer 10' and does not extend into the lower layer dielectric material layer 760. In other words, the first subset of the first layer support opening 119 is laterally offset from the openings passing through the process source layer 10'. A second subset of the first layer support opening 129 may be formed in the stairwell area 200, as... FIG. 4B As shown.

[0168] During the first anisotropic etching process, the materials of the first alternating stack (132, 142) and the material of the first backward-stepped dielectric portion 165 are etched simultaneously. The chemical properties of the initial etching step can be alternating to optimize the etching of the first and second materials in the first alternating stack (132, 142) while providing an average etching rate comparable to that of the material of the first backward-stepped dielectric portion 165. The first anisotropic etching process can use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129, 119) can be substantially vertical or can be tapered.

[0169] refer to FIG. 5 Sacrificial first-layer opening fill portions (148, 128) can be formed in various first-layer openings (149, 129, 119). For example, sacrificial first-layer fill material can be deposited simultaneously in each of the first-layer openings (149, 129, 119). The sacrificial first-layer fill material includes material that can be selectively removed from the first insulating layer 132 and the first sacrificial material layer 142.

[0170] In one embodiment, the sacrificial first layer filler material may include a semiconductor material, such as silicon (e.g., a-Si or polycrystalline silicon), silicon-germanium alloy, germanium, III-V compound semiconductor materials, or combinations thereof. Optionally, a thin etch stop pad (such as a silicon oxide layer or silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first layer filler material. The sacrificial first layer filler material can be formed by non-conformal deposition or conformal deposition methods.

[0171] In another embodiment, the sacrificial first filler material may include a silicon oxide material having a higher etch rate than the materials of the first insulating layer 132, the first insulating cap layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first filler material may include borosilicate glass or porous or non-porous organosilicon glass having an etch rate at least 100 times higher than that of dense TEOS oxide in 100:1 diluted hydrofluoric acid (i.e., silicon oxide formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying it in an annealing process). In this case, a thin etch stop pad (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first filler material. The sacrificial first filler material can be formed by non-conformal deposition or conformal deposition methods.

[0172] In yet another embodiment, the sacrifice of the first layer of filler material may include amorphous silicon or carbon-containing material (such as amorphous carbon or diamond-like carbon) that can subsequently be removed by ashing, or a silicon-based polymer that can be selectively removed from the material of the alternating stacks (132, 142) of the first layer.

[0173] Portions of the deposited sacrificial material can be removed from above the topmost layer of the alternating stack of first layers (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial first layer fill material can be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 can be used as an etch stop layer or a planarization stop layer.

[0174] The remaining portion of the sacrificial first layer fill material comprises the sacrificial first layer opening fill portion (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes the sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support openings (129, 119) constitutes the sacrificial first layer support opening fill portion 128. The various sacrificial first layer opening fill portions (148, 128) are formed simultaneously, i.e., formed during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the alternating stack of first layers (132, 142) (e.g., from above the top surface of the interlayer dielectric layer 180). The top surface of the sacrificial first layer opening fill portion (148, 128) may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening fill portions (148, 128) may or may not include a cavity therein.

[0175] refer to FIG. 6A and FIG. 6B A second layer structure can be formed over the first layer structure (132, 142, 170, 148, 128). The second layer structure may include additional alternating stacks of insulating layers and sacrificial material layers, which may be sacrificial material layers. For example, a second alternating stack of material layers (232, 242) may subsequently be formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating third and fourth material layers. Each third material layer may contain a third material, and each fourth material layer may contain a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0176] In one embodiment, the third material layer may be the second insulating layer 232, and the fourth material layer may be a second sacrificial material layer providing a vertical spacing between each pair of vertically adjacent second insulating layers 232. In one embodiment, the third and fourth material layers may be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that can be selectively removed from the third material of the second insulating layer 232. According to aspects of this disclosure, the second sacrificial material layer 242 comprises a dielectric material, which may be the same material as the dielectric material of the first sacrificial material layer 142. The fourth material of the second sacrificial material layer 242 may subsequently be replaced by a conductive electrode, which may be used as, for example, a control gate electrode for a vertical NAND device.

[0177] In one embodiment, each second insulating layer 232 may comprise a second insulating material, and each second sacrificial material layer 242 may comprise a second sacrificial material. In this case, the alternating stack of second layers (232, 242) may comprise an alternating plurality of second insulating layers 232 and second sacrificial material layers 242. A third material for the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). A fourth material for the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0178] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that can be used in the second insulating layer 232 may be any material that can be used in the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed from the third material of the second insulating layer 232. The sacrificial material that can be used in the second sacrificial material layer 242 may be any material that can be used in the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material. In one embodiment, the first insulating layer 132 and the second insulating layer 232 may comprise silicon oxide, and the first sacrificial material layer 142 and the second sacrificial material layer 242 may comprise silicon nitride.

[0179] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can range from 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the pair of second insulating layers 232 and second sacrificial material layers 242 can range from 2 to 1,024, and is typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the alternating stack of second layers (232, 242) can have a uniform thickness that remains substantially constant within each respective second sacrificial material layer 242.

[0180] The second stepped surface in the second stepped region can be formed in the staircase region 200 using the same set of processing steps as those used to form the first stepped surface in the first stepped region, wherein the pattern of at least one mask layer is appropriately adjusted. A second backward stepped dielectric material portion 265 may be formed above the second stepped surface in the staircase region 200.

[0181] A second insulating cap layer 270 may then be formed over the second alternating stack (232, 242). The second insulating cap layer 270 contains a dielectric material different from that of the second sacrificial material layer 242. In one embodiment, the second insulating cap layer 270 may contain silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) may contain silicon nitride.

[0182] Generally, at least one alternating stack of insulating layers (132, 232) and sacrificial material layers (such as sacrificial material layers (142, 242)) may be formed above the source layer material layer 10' during the process, and at least one backward stepped dielectric material portion (165, 265) may be formed above the stair area on at least one alternating stack (132, 142, 232, 242).

[0183] refer to FIG. 7A to FIG. 7D Various second-layer openings (249, 229, 219) can be formed through the second-layer structure (232, 242, 265, 270). A photoresist layer (not shown) can be applied over the second insulating cap layer 270 and can be photolithographically patterned to form various openings passing through it. The pattern of the openings in the photoresist layer may include the pattern of the first-layer memory opening 149 and the pattern of the first-layer support openings (129, 119). In other words, the pattern of the second-layer openings (249, 229, 219) may be the same as the pattern of the first-layer openings (149, 129, 119) and may have overlapping areas.

[0184] Generally, the cell pattern UP of the combination of the second layer memory opening 249 and the second layer support opening (229, 219) can be repeated along the second horizontal direction hd2. Each cell pattern UP includes a group 439 of clusters 419 of the second layer memory openings 249 that are laterally spaced along the second horizontal direction hd2 and / or laterally spaced along the second horizontal direction hd1.

[0185] The second-layer memory opening 249 may be an opening formed in the memory array region 100 through each layer within the second alternating stack (232, 242), and subsequently used to form a memory stack structure therein. The second-layer memory opening 249 may be formed as a cluster 419 of second-layer memory openings 249 laterally spaced along a second horizontal direction hd2. Each cluster 419 of the second-layer memory openings 249 may be formed as a two-dimensional array of the second-layer memory openings 249. A set of adjacent clusters 419 of the second-layer memory openings 249 forms a group 439 of the first-layer memory openings 249.

[0186] A first subset of the second-layer support openings 219 may be formed in a segment of the memory array region 100 that is not filled with the second-layer memory openings 249. For example, the first subset of the second-layer support openings 219 may be located between adjacent groups 439 of the second-layer memory openings 249, such as... FIG. 7D As shown. A second subset of the second-level support opening 229 can be formed in the stairwell area 200, as... FIG. 7B As shown.

[0187] The second anisotropic etching process may include an etching step in which the material of the second alternating stack (232, 242) is etched simultaneously with the material of the second backward stepped dielectric portion 265. The chemical properties of the etching step may be alternating to optimize the etching of the material in the second alternating stack (232, 242) while providing an average etching rate comparable to that of the material of the second backward stepped dielectric portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various second-layer openings (249, 229, 219) may be substantially vertical or may be tapered. The bottom periphery of each second-layer opening (249, 229, 219) may be laterally offset from the periphery of the top surface of the underlying sacrificial first-layer opening filling portion (148, 128) and / or may be entirely located within that periphery. The photoresist layer may then be removed, for example, by ashing.

[0188] refer to FIG. 8A to FIG. 8DThe sacrificial first layer filler material of the sacrificial first layer opening fill portion (148, 128) can be removed using an etching process that selectively etches the sacrificial first layer filler material for the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating cap layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each combination of the second layer memory opening 249 and the volume from which the sacrificial first layer memory opening fill portion 148 is removed. A support opening 19 (also referred to as an interlayer support opening 19) can be formed in each combination of the second layer support opening (229, 219) and the volume from which the sacrificial first layer support opening fill portion 128 is removed. In a first exemplary structure, the support opening 19 may be formed into the process source layer material layer 10' and does not extend into the lower layer dielectric material layer 760. In other words, the support structure 19 is laterally offset from the opening of the source layer material layer 10' during the passage process.

[0189] refer to FIG. 9A and FIG. 9B Sacrificial filler material can be deposited into various openings (49, 19). The sacrificial filler material includes materials that can be selectively removed subsequently from the materials of the first alternating stack (132, 142) and the second alternating stack (232, 242). In one embodiment, the sacrificial filler material may include amorphous silicon, amorphous carbon, diamond-like carbon (DLC), polymeric materials, germanium, or silicon-germanium alloys. In one embodiment, the sacrificial filler material may be deposited anisotropically to form voids at the lower portion of each opening through the second alternating stack (232, 242) and the first alternating stack (132, 142) to facilitate removal during subsequent sacrificial material removal.

[0190] Excess sacrificial fill material can be removed from above a horizontal plane including the top surface of the second insulating cap layer 270 using a planarization process such as chemical mechanical planarization. Each remaining portion of the sacrificial fill material in the memory opening 49 constitutes a sacrificial memory opening fill material portion 359. A photoresist layer (not shown) can be applied over the first exemplary structure, and the photoresist layer can be photolithographically patterned to cover the sacrificial memory opening fill structure 359. An etching process can be performed to selectively etch the sacrificial fill material for the alternating stacks (132, 142, 232, 242) to remove the remaining portion of the sacrificial fill material from inside the support opening 19. According to an aspect of the first embodiment of the present disclosure, the support opening 19 extends vertically through the at least one alternating stack (132, 142, 232, 242), contacts at least one semiconductor material layer within the process source layer 10', and can be laterally spaced from portions of the lower-level dielectric material layer 760 located within the opening in the process source layer 10', such as FIG. 9A As shown.

[0191] refer to FIG. 10A and Figure 10B A conformal deposition of a dielectric filler material, such as silicon oxide, can be performed in the support opening 19. For example, a low-pressure chemical vapor deposition process can be performed to deposit the dielectric filler material in each support opening 19. Excess portions of the dielectric filler material covering the top surface of the second insulating cap layer 270 can be removed by planarization processes (such as recessed etching and / or chemical mechanical planarization). Each portion of the dielectric filler material filling the support opening 19 constitutes a support pillar structure 20. According to an aspect of a first embodiment of the present disclosure, the support pillar structure 20 extends vertically through the at least one alternating stack (132, 142, 232, 242), contacts at least one semiconductor material layer within the process source layer 10', and may be laterally spaced from portions of the lower-level dielectric material layer 760 located within openings in the process source layer 10', such as Figure 10A As shown.

[0192] refer to Figure 11A , Figure 11B and Figure 12AThe sacrificial memory opening fill material portion 359 can be selectively removed from the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), the backward stepped dielectric material portions (165, 265), and the support pillar structure 20. For example, if the sacrificial memory opening fill material portion 359 comprises a carbon-based material, it can be removed by ashing. If the sacrificial memory opening fill material portion 359 comprises a silicon-germanium alloy or germanium, it can be removed by wet etching using a mixture of ammonium hydroxide and hydrogen peroxide. The memory opening 49 becomes empty.

[0193] refer to Figure 12B A barrier dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60 may be sequentially deposited in each memory opening 49. The barrier dielectric layer 52 may be conformally deposited using a conformal deposition process (such as low-pressure chemical vapor deposition) and may comprise a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the barrier dielectric layer 52 may comprise a dielectric metal oxide layer substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. A dielectric metal oxide may consist substantially of at least one metal element and oxygen, or substantially of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the barrier dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer may range from 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer can serve as a dielectric material portion, preventing the stored charge from leaking to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. Alternatively or otherwise, the barrier dielectric layer 52 may comprise a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

[0194] A charge storage layer 54 may be conformally deposited over the barrier dielectric layer 52. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) patterned, for example, by forming a sacrificial material layer (142, 242) within a lateral recess into multiple electrically isolated portions (e.g., floating gates). In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically overlapping sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layers (142, 242) may be laterally recessed relative to the sidewalls of the insulating layers (132, 232), and a combination of deposition and anisotropic etching processes may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 may range from 2 nm to 20 nm, but smaller and larger thicknesses may also be used.

[0195] A tunneling dielectric layer 56 may be formed above the charge storage layer 54. The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. Charge tunneling can be performed via hot carrier injection or via Fowler-Nordheim tunneling-induced charge transfer, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, but smaller and larger thicknesses are also possible. The stacking of the barrier dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50 for storing memory bits. The combination of the barrier dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50.

[0196] A semiconductor channel material layer 60L may be formed above the tunneling dielectric layer 56. The semiconductor channel material layer 60L may include a doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The conductivity type of the dopants in the semiconductor channel material layer 60L is referred to herein as a first conductivity type, which may be p-type or n-type. In one embodiment, the semiconductor channel material layer 60L has p-type doping, wherein the p-type dopant (such as boron atoms) has a doping concentration of 1.0 × 10¹² / cm². 3 Up to 1.0×10¹⁸ / cm 3 Such as 1.0×10¹⁴ / cm 3 Up to 1.0×10¹⁷ / cm 3 The atomic concentration is present within a certain range. In one embodiment, the semiconductor channel material layer 60L comprises boron-doped amorphous silicon or boron-doped polycrystalline silicon and / or is substantially composed of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is at a concentration of 1.0 × 10¹² / cm². 3 Up to 1.0×10¹⁸ / cm 3 Such as 1.0×10¹⁴ / cm 3 Up to 1.0×10¹⁷ / cm 3 The atomic concentration is within a certain range. The semiconductor channel material layer 60L can be formed by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can range from 2 nm to 10 nm, but smaller and larger thicknesses can also be used. Cavities 49' are formed in the unfilled volumes of the deposited material layers (52, 54, 56, 60L) of each memory opening 49. Memory cavities 49' can exist within each unfilled volume of the memory opening 49.

[0197] refer to Figure 12CIn embodiments where the memory cavity 49' in each memory opening is not completely filled by the semiconductor channel material layer 60L, a dielectric core layer may be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer comprises a dielectric material, such as silicon oxide or organosilicon glass. The dielectric core layer may be deposited by conformal deposition methods (such as low-pressure chemical vapor deposition (LPCVD)) or by self-planarization deposition processes (such as spin coating). Horizontal portions of the dielectric core layer covering the second insulating cap layer 270 may be removed, for example, by recess etching. Recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to the height between the top and bottom surfaces of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0198] See Figure 12D A doped semiconductor material can be deposited in a cavity covering the dielectric core 62. The doped semiconductor material has a doping type opposite to that of the semiconductor channel material layer 60L. In one embodiment, the doped semiconductor material has n-type doping. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52, which cover a horizontal plane (including the top surface of the second insulating cap layer 270), can be removed by a planarization process such as chemical mechanical planarization (CMP).

[0199] Each remaining portion of the doped semiconductor material constitutes the drain region 63. The dopant concentration of the drain region 63 can be 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 Within a certain range, but smaller and larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0200] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60 through which current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent barrier dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 collectively constitutes a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the barrier dielectric layer 52 may be absent in the memory film 50 at this step, and a back-side barrier dielectric layer may subsequently be formed after the formation of the back-side recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0201] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 may be a combination of the vertical semiconductor channel 60, a tunneling dielectric layer 56, multiple memory elements including portions of a charge storage layer 54, and an optional barrier dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each drain region 63 in the memory opening fill structure 58 is electrically connected to the upper end of a corresponding one of the vertical semiconductor channels 60. In the process, the source layer material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265), the interlayer dielectric layer 180, and the memory opening fill structure 58 together constitute a memory layer assembly.

[0202] A memory stack structure 55 is formed by alternating stacks {(132,142), (232,242)}. Each memory stack structure in the memory stack structure 55 includes a vertical stack of memory elements in a memory film 50 located at a level of the sacrificial material layer (142,242). Each vertical stack of memory elements includes a portion of charge storage material (i.e., a portion of charge storage layer 54) located at each level of the sacrificial material layer 142 and laterally spaced from the vertical semiconductor channel 60 within the same memory opening 49 by a tunneling dielectric layer 56.

[0203] refer to Figures 13A to 13CThis illustrates a first exemplary structure after the formation of the memory opening filling structure 58. Each of the alternating stacks {(132,142),(232,242)} includes a plateau region, wherein each sacrificial material layer (142,242) within the alternating stacks {(132,142) and / or (232,242)}, except for the topmost sacrificial material layer (142,242), extends laterally beyond any covering sacrificial material layer (142,242) within the alternating stacks {(132,142) and / or (232,242)}. The plateau region includes stepped surfaces of the alternating stacks that extend continuously from the bottommost layer within the alternating stacks {(132,142) or (232,242)} to the topmost layer within the alternating stacks {(132,142) or (232,242)}. The support column structure 20 extends through the stepped surface and through the backward stepped dielectric material portion (165 or 265) covering the stepped surface.

[0204] A first subset of the memory stack structure 55 is located in a first portion of the memory array region 100, containing each layer of the first alternating stack (132, 142) and each layer of the second alternating stack (232, 242). A second subset of the memory stack structure 55 is located in a second portion of the memory array region 100, containing each layer of the first alternating stack (132, 142) and each layer of the second alternating stack (232, 242), and is laterally spaced from the first portion of the memory array region 100 along a first horizontal direction hd1.

[0205] refer to Figure 14A Referring to Figure 14D, a first contact-level dielectric layer 280 can be formed over the second layer structure (232, 242, 270, 265). The first contact-level dielectric layer 280 comprises a dielectric material such as silicon oxide and can be formed by conformal or non-conformal deposition processes. For example, the first contact-level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0206] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form various openings in the memory array region 100 and the staircase region 200. The openings in the photoresist layer include first elongated openings that extend laterally along a first horizontal direction hd1 through at least one staircase region 200 and at least a portion of the memory array region 100. A first subset of the first elongated openings may extend laterally along the first horizontal direction hd1 across the entire width of the memory array region 100. A second subset of the first elongated openings may extend laterally through a portion of the memory array region 100 and may terminate in a region of the memory array region 100 including an array of support pillar structures 20. The second subset of the first elongated openings extends laterally between a group of memory opening filling structures 58 and the support pillar structures 20 spaced laterally along the first horizontal direction hd1.

[0207] Furthermore, the openings in the photoresist layer may include second elongated openings that are entirely located within the region of the memory array region 100, including the array of support pillar structures 20. Therefore, each second elongated opening has a smaller lateral extent than the lateral extent of the memory array region 100 along the first horizontal direction hd1. The second elongated openings extend along the first horizontal direction hd1 between a pair of correspondingly adjacent elongated openings in a second subset of the first elongated openings, which are laterally spaced in a vertical plane extending along the first horizontal direction hd1.

[0208] Anisotropic etching can be performed to transfer patterns in a photoresist layer through an underlying material portion comprising alternating stacks {(132,142),(232,242)} and an upper portion of the source-level material layer 10' in the process. A back-side trench 79 can be formed beneath a first elongated opening in the photoresist layer to pass through the first contact-level dielectric layer 280, the second layer structure (232,242,270,265), and the first layer structure (132,142,170,165) and into the source-level material layer 10' in the process. The portion of the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the source-level material layer 10' in the process, below the first elongated opening in the photoresist layer, can be removed to form a back-side trench 79. In one embodiment, the back-side trench 79 can be formed between groups of memory stack structures 55 laterally spaced along a second horizontal direction. The top surface of the source-level sacrificial layer 104 can be physically exposed at the bottom of each back-side trench 79. Figures 13A to 13CThe alternating stacks {(132,232),(142,242)} provided at the processing step can be divided by the back-side trench 79 into multiple alternating stacks {(132,232),(142,242)} of corresponding insulating layers (132,232) and corresponding sacrificial material layers (142,242). A first subset passing through the first elongated opening in the photoresist layer forms a first subset of the back-side trench 79A. The first subset of the back-side trench 79A extends laterally along the first horizontal direction hd1 across the entire width of the memory array region 100. A second subset passing through the first elongated opening in the photoresist layer forms a first subset of the back-side trench 79B. The second subset of the back-side trench 79B may extend laterally through a portion of the memory array region 100 and may terminate in the region of the memory array region 100 including the array of support pillar structures 20.

[0209] The recessed trench 179 may be formed below a second elongated opening in the photoresist layer, passing through the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), and the first layer structure (132, 142, 170, 165) and entering the in-process source-level material layer 10'. The portions of the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the in-process source-level material layer 10' below the second elongated opening in the photoresist layer may be removed to form the recessed trench 179. The recessed trench 179 may be entirely located within the region of the memory array region 100, including the array of support pillar structures 20, situated between a pair of adjacent clusters of memory aperture-filling structures 58 laterally spaced along the first horizontal direction hd1. In one embodiment, a recessed trench 179 may be formed between a pair of back-side trenches 79B laterally spaced along a first horizontal direction hd1, and may be aligned with the pair of back-side trenches 79B along a second horizontal direction hd2. Each recessed trench 179 may be located between a pair of adjacent back-side trenches 79A. Along the first horizontal direction hd1, each recessed trench 179 has a smaller lateral extent than the lateral extent of the memory array region 100. The top surface of the source-level sacrificial layer 104 may be physically exposed at the bottom of each recessed trench 179. The back-side trenches 79 and the recessed trenches 179 are formed simultaneously using the same anisotropic etching process.

[0210] refer to Figure 15A and Figure 15BAn etch stop pad 71 can be conformally deposited in the backside trench 79 and the recessed trench 179 and over the first contact-level dielectric layer 280 using a conformal deposition process. The etch stop pad 71 comprises a dielectric material different from the materials of the first sacrificial material layer 142 and the second sacrificial material layer 242. For example, the etch stop pad 71 may comprise silicon oxide. The thickness of the etch stop pad 71 can range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although smaller and larger thicknesses are also possible.

[0211] A photoresist layer 77 may be applied over the first exemplary structure, and this photoresist layer may be photolithographically patterned to cover the back trench 79 without covering the recessed trench 179. Unmasked portions of the etch stop pad 71 may be removed by performing an isotropic etching process. For example, if the etch stop pad 71 comprises silicon nitride, a wet etching process using hydrofluoric acid may be performed to remove the unmasked portions of the etch stop pad 71. Thus, the etch stop pad 71 is removed from the sidewalls of the recessed trench 179 without removing it from the sidewalls of the back trench 79.

[0212] refer to Figure 16A and Figure 16B The photoresist layer 77 can then be removed, for example, by ashing. After the photoresist layer 77 is removed, the sidewalls of the recessed trench 179 are physically exposed. The sidewalls of the back side trench 79 are covered by an etch stop pad 71. Thus, the etch stop pad 71 can be used to mask the sidewalls of the back side trench 79, while the etch stop pad 71 does not cover the sidewalls of the recessed trench 179.

[0213] refer to Figure 17A and Figure 17B An isotropic etching process can be performed to selectively recess the first sacrificial material layer 142 and the second sacrificial material layer 242 laterally through the recessed trench 179 for the first insulating layer 132 and the second insulating layer 232. For example, if the first sacrificial material layer 142 and the second sacrificial material layer 242 comprise silicon nitride and if the first insulating layer 132 and the second insulating layer 232 comprise silicon oxide, a wet etching process using thermal phosphoric acid can be performed to selectively remove portions of the sacrificial material layers (142, 242) adjacent to the recessed trench 179 for the insulating layers (132, 232).

[0214] Fin-shaped lateral recesses are formed in the volume of the portion from which the sacrificial material layers (142, 242) are removed. These fin-shaped lateral recesses are referred to herein as fin-shaped cavities (153, 253). The fin-shaped cavities (153, 253) include a first fin-shaped cavity 153 formed at the level of the first sacrificial material layer 142 and a second fin-shaped cavity 253 formed at the level of the second sacrificial material layer 242. According to a first embodiment of this disclosure, a vertical stack of fin-shaped cavities (153, 253) may be formed around each recessed groove 179. The fin-shaped cavities (153, 253) may have a uniform thickness and may have outer boundaries equidistant from the sidewalls of the corresponding recessed groove 179.

[0215] In one embodiment, at least one support pillar structure 20 may be physically exposed to the finned cavities (153, 253). In one embodiment, at least one support pillar structure 20 may be laterally surrounded by each of the finned cavities (153, 253) formed around the recessed groove 179. In one embodiment, a plurality of support pillar structures 20 may be physically exposed to a vertical stack of finned cavities (153, 253) laterally surrounding the recessed groove 179, and may be laterally surrounded by the vertical stack.

[0216] Generally, finned cavities (153, 253) can be formed around each recessed trench 179 by selectively and isotropically etching portions of the sacrificial material layer (142, 242) adjacent to the recessed trench 179 of the insulating layer (132, 232). The duration of the isotropic etching process for forming the finned cavities (153, 253) can be selected such that a first subset of the support pillar structure 20 is physically exposed to the finned cavities (153, 253), while a second subset of the support pillar structure 20 is not physically exposed to the finned cavities (153, 253) after their formation.

[0217] refer to Figures 18A to 18CDielectric filler material can be deposited in the finned cavities (153, 253) using conformal deposition processes such as low-pressure chemical vapor deposition (LPCVD). In one embodiment, the dielectric filler material may include a dielectric oxide material, such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass. For example, the dielectric filler material may include undoped silicate glass. An etch-back process can be performed to remove portions of the dielectric filler material located in the recessed trench 179, the back trench 79, or above the first contact level dielectric layer 280. The etch-back process may include an isotropic etching process or anisotropic etching process. For example, if the dielectric filler material comprises silicon oxide, a timed wet etching process employing hydrofluoric acid can be used to etch back portions of the dielectric filler material from inside the recessed trench 179 and the back trench 79 and from above the first contact level dielectric layer 280. During wet etching, the silicon oxide etch-blocking pad 71 may also be removed from the back trench 79.

[0218] The remaining portion of the dielectric filler material filling the finned cavities (153, 253) comprises dielectric oxide plates (152, 252). The dielectric oxide plates (152, 252) comprise a first dielectric oxide plate 152 filling the first finned cavity 153 and a second dielectric oxide plate 252 filling the second finned cavity 253. Therefore, portions of the sacrificial material layers (142, 242) adjacent to the recessed trenches 179 are replaced by dielectric oxide plates (152, 252). A vertical stack of dielectric oxide plates (152, 252) is provided around each recessed trench 179. The vertical stack of dielectric oxide plates (152, 252) intersects with the laterally extending portions of the insulating layers (132, 232) of the at least one alternating stack {(132, 142), (232, 242)}. Each dielectric oxide plate (152, 252) is located between a pair of corresponding vertically adjacent insulating layers (132, 232) of the at least one alternating stack {(132, 142), (232, 242)}.

[0219] Each outer sidewall of the dielectric oxide board (152, 252) may contact the sidewall of the corresponding remaining portion of the sacrificial material layer (142, 242). In one embodiment, each dielectric oxide board (152, 252) may include a straight outer sidewall segment extending laterally along a first horizontal direction hd1 and a curved outer sidewall segment having a corresponding convex horizontal cross-sectional profile. Specifically, each dielectric oxide board (152, 252) may have at least one convex outer sidewall segment that contacts a concave sidewall segment of a corresponding insulating layer in the insulating layer (132, 232).

[0220] Figures 19A to 19DThe diagram shows a sequential vertical cross-sectional view of the memory opening filling structure 58 and the back trench 79 during the formation of the source layer material layer 10, according to a first embodiment of the present disclosure.

[0221] refer to Figure 19A The etch barrier pad 71 can be removed by performing an isotropic etching process. For example, if the etch barrier pad 71 comprises silicon nitride, a wet etching process using dilute hydrofluoric acid can be performed to remove the etch barrier pad 71.

[0222] refer to Figure 19B In an isotropic etching process, an etchant is introduced into the back-side trench to selectively etch the material of the source-level sacrificial layer 104 for the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), the first insulating cap layer and the second insulating cap layer (170, 270), the first contact-level dielectric layer 280, the higher sacrificial pad 105, and the lower sacrificial pad 103. For example, if the source-level sacrificial layer 104 comprises undoped amorphous silicon or undoped amorphous silicon-germanium alloy, and if the higher and lower sacrificial pads (105, 103) comprise silicon oxide, a wet etching process (which uses thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH)) can be used to selectively remove the source-level sacrificial layer 104 for the higher and lower sacrificial pads (105, 103). A source cavity 109 can be formed in the volume from which the source-level sacrificial layer 104 is removed.

[0223] Wet etching chemicals such as thermal TMY and TMAH are selective for the doped semiconductor materials of the higher source layer semiconductor layer 116 and the lower source layer semiconductor layer 112. Therefore, using selective wet etching chemicals such as thermal TMY and TMAH in the wet etching process for forming the source cavity 109 provides a larger process window to resist variations in etching depth during the formation of the back-side trench 79. Specifically, in the embodiment where the sidewalls of the higher source layer semiconductor layer 116 are physically exposed or where the surface of the lower source layer semiconductor layer 112 is physically exposed during the formation of the source cavity 109, incidental etching of the higher source layer semiconductor layer 116 and / or the lower source layer semiconductor layer 112 is minimized, and structural changes in the first exemplary structure caused by unintended physical exposure of the surfaces of the higher source layer semiconductor layer 116 and / or the lower source layer semiconductor layer 112 during the manufacturing steps do not lead to device failure. Each of the memory aperture filling structures 58 can be physically exposed to the source cavity 109. Specifically, each of the memory opening filling structures 58 may include sidewalls and bottom surfaces physically exposed to the source cavity 109.

[0224] refer to Figure 19C A sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the layer level of the source cavity 109. Higher and lower sacrificial pads (105, 103) can be etched incidentally during the removal of portions of the memory film 50 located at the layer level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the layer levels of the source cavity 109 and the higher and lower sacrificial pads (105, 103). The top surface of the lower source layer semiconductor layer 112 and the bottom surface of the higher source layer semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 can be formed by selectively and isotropically etching the source sacrificial layer 104 and the bottom portion of each memory film 50 onto at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the higher source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0225] refer to Figure 19D A doped semiconductor material with a second conductivity type can be deposited on a physically exposed semiconductor surface around the source cavity 109. The second conductivity type is the opposite of a first conductivity type, which is the doped conductivity type of the vertical semiconductor channel 60. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surface of at least one source-level semiconductor layer (112, 116). For example, the physically exposed semiconductor surface may include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the higher source-level semiconductor layer 116.

[0226] In one embodiment, a doped semiconductor material of a second conductivity type can be deposited on a physically exposed semiconductor surface surrounding a source cavity 109 using a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and an n-type dopant precursor gas can simultaneously flow into a processing chamber including the first exemplary structure. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the n-type dopant precursor gas may be phosphine, arsine, or antimony. In this case, the selective semiconductor deposition process grows in-situ doped semiconductor material from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114 that can contact the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the second conductivity type dopant in the deposited semiconductor material can be 1.0 × 10²⁰ / cm². 3Up to 2.0×1021 / cm 3 (such as 2.0×1020 / cm) 3 Up to 8.0×1020 / cm 3 Within the range of ), the initially formed source contact layer 114 may consist substantially of semiconductor atoms of a second conductivity type and dopant atoms. Alternatively, the source contact layer 114 may be formed using at least one non-selective doping semiconductor material deposition process. Optionally, one or more etch-back processes may be combined with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0227] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Therefore, the source-level sacrificial layer 104 can be replaced by the source contact layer 114.

[0228] A stack of layers including a lower source-level semiconductor layer 112, a source contact layer 114, and a higher source-level semiconductor layer 116 constitutes source regions (112, 114, 116). Source regions (112, 114, 116) are electrically connected to a first end (such as the bottom end) of each of the vertical semiconductor channels 60. A layer group including source regions (112, 114, 116), a source-level insulating layer 117, and a source-selective conductive layer 118 constitutes a source-level material layer 10, which replaces source-level material layer 10' in the process.

[0229] refer to Figure 20D to Figure 20D An oxidation process can be performed to convert physically exposed surface portions of a semiconductor material into dielectric semiconductor oxide portions. For example, surface portions of the source contact layer 114 and the higher source level semiconductor layer 116 can be converted into a dielectric semiconductor oxide plate 122, and surface portions of the source selection level conductive layer 118 can be converted into annular dielectric semiconductor oxide spacers 124. Figure 20D The dielectric semiconductor oxide plate 122 and the annular dielectric semiconductor oxide spacer 124 are shown. For clarity, in Figures 20A to 20C The dielectric semiconductor oxide plate 122 and the annular dielectric semiconductor oxide spacer 124 are omitted.

[0230] refer to Figure 21A and Figure 21DThe sacrificial material layer (142, 242) can be selectively removed from the insulating layer (132, 232), the first insulating cap layer and the second insulating cap layer (170, 270), the first contact level dielectric layer 280, the source contact layer 114, the dielectric semiconductor oxide plate 122, and the annular dielectric semiconductor oxide spacer 124. For example, an isotropic etching process can be used to introduce an isotropic etchant into the back trench 79 to selectively etch the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the first insulating cap layer and the second insulating cap layer (170, 270), the backward stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50.

[0231] The isotropic etching process can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which the etchant is introduced in the vapor phase into the back-side trench 79. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process can be a wet etching process in which a first exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. The duration of the isotropic etching process can be selected such that the entire sacrificial material layer (142, 242) is removed by the isotropic etching process.

[0232] Backside recesses (143, 243) can be formed in the volume from which sacrificial material layers (142, 242) are removed. The backside recesses (143, 243) include a first backside recess 143 that can be formed in the volume from which the first sacrificial material layer 142 is removed, and a second backside recess 243 that can be formed in the volume from which the second sacrificial material layer 242 is removed. Each backside recess (143, 243) can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess (143, 243) can be greater than the height of the corresponding backside recess (143, 243). Multiple backside recesses (143, 243) can be formed in the volume of material from which the sacrificial material layers (142, 242) are removed. Each of the back-side recesses (143, 243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. The back-side recesses (143, 243) may be vertically defined by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the back-side recesses (143, 243) may have a uniform height throughout.

[0233] See Figures 22A to 22DA back-side barrier dielectric layer (not shown) may optionally be deposited in the back-side recesses (143, 243) and the back-side trench 79, and over the first contact-level dielectric layer 280. The back-side barrier dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the back-side barrier dielectric layer may comprise aluminum oxide. The back-side barrier dielectric layer can be formed by conformal deposition processes such as atomic layer deposition or chemical vapor deposition. The thickness of the back-side barrier dielectric layer can range from 1 nm to 20 nm, such as from 2 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0234] At least one conductive material can be deposited in the plurality of back-side recesses (243, 243), on the sidewalls of the back-side trench 79, and over the first contact-level dielectric layer 280. The at least one conductive material can be deposited using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include elemental metals, intermetallic alloys of at least two elemental metals, conductive nitrides of at least one elemental metal, conductive metal oxides, conductive doped semiconductor materials, conductive metal-semiconductor alloys such as metal silicides, alloys thereof, and combinations or stacks thereof.

[0235] In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or combinations thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or combinations thereof. In one embodiment, the at least one conductive material used to fill the backside recesses (143, 243) may be a combination of a titanium nitride layer and a tungsten filler material.

[0236] Conductive layers (146, 246) can be formed in the back-side recesses (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 can be formed in a plurality of first back-side recesses 143, a plurality of second conductive layers 246 can be formed in a plurality of second back-side recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each back-side trench 79 and over the first contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 may include a corresponding conductive metal nitride pad and a corresponding conductive filler material. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced by the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced by an optional portion of the back-side barrier dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced by an optional portion of the back-side barrier dielectric layer and the second conductive layer 246. The dorsal cavity exists within the portion of each dorsal groove 79 that is not filled with a continuous layer of metallic material.

[0237] Residual conductive material can be removed from within the back trench 79. Specifically, the deposited metal material can be etched back from the sidewalls of each back trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first back trench 79 constitutes the first conductive layer 146. Each remaining portion of the deposited metal material in the second back trench 79 constitutes the second conductive layer 246. The sidewalls of the first conductive layer 146 and the second conductive layer can be physically exposed to the respective back trench 79.

[0238] Each conductive layer (146, 246) may be a conductive sheet including openings. A first subset of the openings through each conductive layer (146, 246) may be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) may be filled with a support pillar structure 20. Each of the memory stack structures 55 includes a vertically stacked memory element located at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. Semiconductor devices in the lower peripheral device region 700 may include word line switching devices configured to control bias voltages to the respective word lines. The memory hierarchy assembly is positioned above the substrate semiconductor layer 9. The memory hierarchy assembly includes at least one alternating stack {(132, 146), (232, 246)} and a memory stack structure 55 extending vertically through at least one alternating stack (132, 146, 232, 246).

[0239] refer to Figures 23A to 23DDielectric filler material can be deposited in the back trench 79 and the recessed trench 179. The dielectric filler material may include a silicon oxide-based filler material, such as undoped silicate glass or doped silicate glass. Excess dielectric material may optionally be removed from the top surface of the first contact level dielectric layer 280 by a planarization process (which may employ a recess etching process or a chemical mechanical planarization process). In one embodiment, each remaining portion of the dielectric filler material filling the back trench 79 constitutes a back trench fill structure 76, which is a dielectric filler material structure. Each remaining portion of the dielectric filler material filling the recessed trench constitutes a wall structure 176. The back trench fill structure 76 and the wall structure 176 may extend laterally along a first horizontal direction hd1.

[0240] In another embodiment, the dielectric filler material does not completely fill the back trench 79 and the recessed trench 179. Instead, after the etch-back process, the dielectric filler material forms insulating spacers on the sidewalls of the back trench 79 and the recessed trench 179. Conductive material (such as metals (e.g., tungsten) and / or conductive metal nitrides (e.g., TiN or WN)) is deposited onto the insulating spacers in the back trench 79 and the recessed trench 179. The conductive material is then planarized by a chemically mechanical planarizing etch-back process to form local interconnects such as source local interconnects that contact the source contact layer 114 as a combination of buried source lines and source electrodes. In this alternative embodiment, the back trench fill structure 76 and the wall structure 176 include conductive local interconnects that are defined laterally by insulating spacers rather than the entire dielectric filler material structure.

[0241] In one embodiment, each wall structure 176 may be laterally surrounded and contacted by a corresponding vertical stack of dielectric oxide plates (152, 252) filling finned cavities (153, 253) and an insulating layer (132, 232) that may also include dielectric oxide (such as silicon oxide). Thus, each wall structure may be surrounded by alternating stacks of first and second silicon oxide layers. A first back-side trench-filled structure 76A may extend laterally along a first horizontal direction hd1 through the entire memory array region 100 and through the staircase region 200, and may be laterally spaced from the dielectric oxide plates (152, 252). A second back-side trench-filled structure 76B may contact the corresponding vertical stack of dielectric oxide plates (152, 252). Wall structures 176 may be laterally spaced from the first back-side trench-filled structure 76A along a second horizontal direction hd2, and may be laterally spaced from a pair of second back-side trench-filled structures 76B along the first horizontal direction hd1. Each back-side trench fill structure 76 (i.e., 76A, 76B) may contact the at least one alternately stacked sidewall of the insulating layer (132, 232) and the conductive layer (146, 246). In one embodiment, the vertical stack of dielectric oxide plates (152, 252) that laterally surround the wall structure 176 may optionally contact a pair of second back-side trench fill structures 76B, depending on the duration of the isotropic etching forming the finned cavities (153, 253).

[0242] refer to Figures 24A to 24E Optionally, a drain selection layer isolation structure 72 can be formed through a subset of the second conductive layer 246. A second contact layer 282 can be formed over the first contact layer 280 by depositing a dielectric material such as silicon oxide. Alternatively, the second contact layer 282 can be formed by not removing the dielectric filler material from the top surface of the first contact layer 280 after forming the back-side trench fill structure 76 and the wall structure 176. The thickness of the second contact layer 282 can range from 200 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0243] Various via cavities can be formed through the second contact level dielectric layer 282 and the underlying dielectric material layer, and these via cavities can subsequently be filled with at least one conductive material to form various contact via structures (88, 86, 486, 798). Various via cavities can be formed using a single patterned photoresist layer as an etching mask layer and a single anisotropic etching process, or multiple patterned photoresist layers can be used as etching mask layers and multiple anisotropic etching processes can be used to form various via cavities.

[0244] When forming various via cavities using a single patterned photoresist layer and a single anisotropic etching process, the openings in the patterned photoresist layer may include: an opening covering the drain region 63 of the memory aperture filling structure 58; an opening covering a horizontal surface covering a first stepped surface of a first alternating stack of the first insulating layer 132 and the first conductive layer 146, and a second stepped surface of a second alternating stack of the second insulating layer 232 and the second conductive layer 246; an opening covering a corresponding opening in the respective vertical stacks of the dielectric oxide substrate (152, 252) and the source layer material 10; and an optional opening located above a portion of the backward stepped dielectric material portion (165, 265) that is not covered by the source layer material 10. In this case, the anisotropic etching process may have an etching chemical that selectively etches silicon oxide for the following materials: the material of the drain region 63, the material of the first conductive layer 146 and the second conductive layer 246, and the material of the lower-level metal interconnect structure 780.

[0245] When various via cavities are formed using multiple patterned photoresist layers and multiple anisotropic etching processes, the openings in each patterned photoresist layer include a corresponding subset of the following openings: an opening covering the drain region 63 of the memory opening-fill structure 58; an opening covering the horizontal surface of the first stepped surface of the first alternating stack of the first insulating layer 132 and the first conductive layer 146 and the second stepped surface of the second alternating stack of the second insulating layer 232 and the second conductive layer 246; an opening covering the corresponding openings in the corresponding vertical stacks of the dielectric oxide substrate (152, 252) and the source layer material layer 10; and an optional opening above the portion of the backward stepped dielectric material portion (165, 265) that does not cover the source layer material layer 10. In this case, each anisotropic etching process may have an etching chemical that selectively etches silicon oxide relative to a corresponding subset of the following materials: the material of drain region 63, the material of first conductive layer 146 and second conductive layer 246, and the material of lower-level metal interconnect structure 780. Various via cavities may include: drain contact via cavities formed above drain region 63; layer contact via cavities formed on conductive layers (146, 246); peripheral through-memory-level via cavities formed through backward stepped dielectric material portions (165, 265) on corresponding lower-level metal interconnect structures in lower-level metal interconnect structures 780 (such as landing pad level metal interconnect structures 788); and array region through-memory-level via cavities formed through corresponding vertical stacks of dielectric oxide plates (152, 252) and insulating layers (132, 232) on corresponding lower-level metal interconnect structures in lower-level metal interconnect structures 780 (such as landing pad level metal interconnect structures 788).

[0246] After forming various via cavities and removing the patterned photoresist layer, at least one conductive material can be deposited in the various via cavities, for example, by chemical vapor deposition, physical vapor deposition, electroplating, and / or electroless plating. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the second contact-level dielectric layer 282. Contact via structures (88, 86, 486, 798) can be formed in the various via cavities. In one embodiment, the at least one conductive material can be deposited into all of the aforementioned via cavities during the same deposition step.

[0247] The contact via structures (88, 86, 486, 798) include: drain contact via structures 88 that contact a corresponding drain region in drain region 63; layer contact via structures 86 (e.g., word line and select gate contact via structures) that contact a corresponding conductive layer in conductive layer (146, 246); peripheral through-memory-level via structures 486 that extend through backward stepped dielectric material portions (165, 265) and contact a corresponding lower-level metal interconnect in lower-level metal interconnect structure 780; and array region through-memory-level via structures 798 that extend through a corresponding vertical stack of dielectric oxide substrates (152, 252) and through an insulating layer (132, 232) and contact a corresponding lower-level metal interconnect in lower-level metal interconnect structure 780. Each peripheral through-memory-level via structure 486 is a contact via structure formed outside the regions of memory array region 100 and staircase region 200 and extending vertically through the memory layer (i.e., the layer located between the horizontal plane including the bottom surface of the source layer material layer 10 and the horizontal plane including the top surface of the memory opening filling structure 58). Each array region through-memory-level via structure 798 is a contact via structure formed within the region of memory array region 100 and extending vertically through the memory layer.

[0248] In one embodiment, each array region through the memory layer via structure 798 may extend vertically through a corresponding opening in the source layer material layer 10 and may contact a portion of a lower-level dielectric material layer 760 (such as the at least one second dielectric layer 768) filling the opening in the source layer material layer 10. In one embodiment, each array region through the memory layer via structure 798 may be formed in a region located between the support pillar structures 20 and may be laterally spaced from the conductive layers (146, 246) by the portion surrounding the dielectric oxide plates (152, 252). Furthermore, each array region through the memory layer via structure 798 may be laterally spaced from the source layer material layer 10 by the portion of the lower-level dielectric material layer 760 filling the opening in the source layer material layer 10. Figure 24B In one embodiment shown, the lower-level dielectric material layer 760 may include an etch-stop dielectric layer 767 that contacts the top surface of the pad-level metal interconnect structure 788. In this case, each array region through the memory-level via structure 798 may extend through and contact the etch-stop dielectric layer 767, which may include a silicon nitride layer or a dielectric metal oxide layer.

[0249] Subsequently, higher-level dielectric material layers and higher-level metal interconnect structures can be formed. For example, the higher-level dielectric material layer may include a line-level dielectric layer 290 embedded therein and metal line structures (96, 98). The metal line structures (96, 98) may include bit lines 98 of a corresponding subset of the contact drain contact via structure 88, and interconnect metal lines 96 of at least one of the contact layer contact via structure 86, the peripheral through-memory level via structure 486, and the array region through-memory level via structure 798.

[0250] Figures 25A to 25C yes Figures 24A to 24E A horizontal cross-sectional view of an alternative configuration of the first exemplary structure.

[0251] refer to Figure 25A A first alternative configuration of the first exemplary structure can be obtained from the first exemplary structure by forming additional back-side trenches 79 filled with additional back-side trench fill structures 76, which are referred to herein as third back-side trench fill structures 76C. The third back-side trench fill structure 76C may be formed in the same direction as the wall structure 176 and may be laterally offset from the wall structure 176 along the second horizontal direction hd2. The third back-side trench fill structure 76C may be used to limit the lateral extent of each vertical stack of dielectric oxide plates (152, 252) by limiting the lateral extent of the finned cavities (153, 253).

[0252] refer to Figure 25BA second alternative configuration of the first exemplary structure can be obtained from the first exemplary structure by forming recessed trenches 179 that are laterally offset from the back-side trenches 79B along the second horizontal direction hd2. In this case, each back-side trench 79 may extend continuously along the first horizontal direction hd1 through the entire length of the memory array region 100, and each recessed trench 179 may be formed in the middle between a pair of adjacent back-side trenches 79. Thus, wall structures 176 may be formed between a pair of laterally adjacent back-side trench filling structures 76. The width of each vertical stack of dielectric oxide plates (152, 252) between the pair of back-side trench filling structures 76 along the second horizontal direction hd2 may be smaller than the width of the alternating stacks of insulating layers (132, 232) and conductive layers (146, 246) between the pair of back-side trench filling structures 76 along the second horizontal direction hd2. In this configuration, the electrical connection between a portion of each conductive layer (146, 246) located on one side of the vertical stack of dielectric oxide plates (152, 252) along the first horizontal direction hd1 and a portion of each conductive layer (146, 246) located on the other side of the dielectric oxide plates (152, 252) can be provided by at least one strip portion of the corresponding conductive layer (146, 246) positioned adjacent to the vertical stack of dielectric oxide plates (152, 252). One or more array regions in the memory-level via structure 798 can be formed through the respective vertical stack of dielectric oxide plates (152, 252) and insulating layers (132, 32). Furthermore, one or more array regions in the memory-level via structure 798 can be formed through the wall structure 176, and these array regions can contact the wall structure.

[0253] refer to Figure 25C A third alternative configuration of the first exemplary structure can be obtained from the first exemplary structure by forming a plurality of recessed trenches 179 adjacent to each other. Each recessed trench 179 may have the following horizontal cross-sectional shape: rectangular, circular, rounded polygonal, or any other closed two-dimensional generally curved shape. One or more array regions in the through-memory via structure 798 may be formed through the respective vertical stacks of the dielectric oxide plates (152, 252) and the insulating layers (132, 232). Furthermore, one or more array regions in the through-memory via structure 798 may be formed through the wall structure 176, and the one or more array regions in the through-memory via structure may contact the wall structure.

[0254] refer to Figures 1A to 25CFurthermore, according to a first embodiment of this disclosure, a three-dimensional memory device is provided, comprising: at least one alternating stack of insulating layers (132, 232) and conductive layers (146, 246), the at least one alternating stack being located above an underlying metal interconnect structure (e.g., 788); a memory stack structure 55 (located within a corresponding memory opening filling structure 58), the memory stack structure extending vertically through the at least one alternating stack {(132, 146), (232, 246)}; and a vertical stack of dielectric oxide plates (152, 252), the vertical stack being adjacent to the at least one alternating stack {(132, 146)}. The laterally extending portions of the insulating layers (132,232) of the at least one alternating stack {(132,246)} are staggered, wherein each dielectric oxide plate (152,252) is located between a pair of corresponding vertically adjacent insulating layers (132,232) of the at least one alternating stack {(132,146),(232,246)}; and conductive via structures (such as memory region through memory level via structure 798) that extend vertically through each dielectric oxide plate in the vertical stack and each laterally extending portion of the at least one alternating stacked insulating layer, and contact the underlying metal interconnect structure (such as landing pad level metal interconnect structure 788).

[0255] In one embodiment, the three-dimensional memory device includes: a first back-side trench fill structure 76A extending laterally along a first horizontal direction hd1 and contacting the sidewalls of the at least one alternating stack {(132,146),(232,246)}; and a second back-side trench fill structure 76B extending laterally along the first horizontal direction hd1 and contacting additional sidewalls of the at least one alternating stack {(132,146),(232,246)}. In one embodiment, a wall structure 176 may contact each dielectric oxide board (152,252) within a vertical stack of dielectric oxide boards (152,252). The first back-side trench fill structure, the second back-side trench fill structure (76A,76B), and the wall structure 176 may each include either a dielectric fill structure surrounded by insulating spacers or a local interconnect.

[0256] In one embodiment, each dielectric oxide board (152, 252) within a vertical stack of dielectric oxide boards (152, 252) is laterally surrounded by a wall structure 176. In one embodiment, each dielectric oxide board (152, 252) has an inner sidewall of the contact wall structure 176 and an outer sidewall that is laterally offset uniformly from the nearest inner sidewall by a distance that may be approximately the same as the lateral etching distance of the etching process forming the finned cavities (153, 253).

[0257] In one embodiment, the dielectric oxide board (152, 252) includes a straight outer wall segment extending laterally along a first horizontal direction hd1 and a curved outer wall segment having a corresponding convex horizontal cross-sectional profile. In one embodiment, the dielectric oxide board (152, 252) contacts a second back-side trench fill structure 76B; wall structure 176 is laterally spaced from the first back-side trench fill structure 76A along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; and wall structure 176 is laterally spaced from the second back-side trench fill structure 76B along the first horizontal direction hd1.

[0258] In one embodiment, a conductive via structure (such as a memory region through-memory level via structure 798) contacts each insulating layer (132,232) within the at least one alternating stack {(132,146),(232,246)} and each dielectric oxide board (152,252) within the vertical stack of dielectric oxide boards (152,252).

[0259] In one embodiment, the three-dimensional memory device includes: a first support pillar structure 20 extending vertically through the at least one alternating stack {(132,146),(232,246)}; and a second support pillar structure 20 extending vertically through the vertical stack of dielectric oxide substrates (152,252) and the lateral extension of the insulating layer (132,232) of the at least one alternating stack {(132,146),(232,246)}, and contacting semiconductor material layers (such as a lower source level material layer 112, a source contact layer 114, and / or a higher source level semiconductor layer 116).

[0260] In one embodiment, a semiconductor material layer (such as a lower source level material layer 112, a source contact layer 114, and / or a higher source level semiconductor layer 116) includes an opening therethrough; and a contact via structure (such as a memory region through memory level via structure 798) extends through the opening in the semiconductor material layer and is laterally spaced from the periphery of the opening through the semiconductor material layer.

[0261] In one embodiment, each memory stack structure in the memory stack structure 55 includes: a vertical semiconductor channel 60 extending vertically through each conductive layer (146,246) within the at least one alternating stack {(132,146),(232,246)}; and a vertical stack of memory elements (including portions of charge storage layers 54) located at the level of the conductive layers (146,246) within the at least one alternating stack {(132,146),(232,246)}.

[0262] In one embodiment, the at least one alternating stack {(132,146),(232,246)} comprises: a first alternating stack of a first insulating layer 132 and a first conductive layer 146, the first alternating stack having a first stepped surface contacting a first backward stepped dielectric portion 165; and a second alternating stack of a second insulating layer 232 and a second conductive layer 246, the second alternating stack having a second stepped surface contacting a second backward stepped dielectric portion 265.

[0263] In one embodiment, the three-dimensional memory device includes: a substrate 8 located below an underlying interconnect structure 788; a semiconductor material layer (such as a lower source level material layer 112, a source contact layer 114, and / or a higher source level semiconductor layer 116) located between an alternating stack and the underlying interconnect structure 788; a lower level dielectric material layer 760 in which a lower level metal interconnect structure 780 is embedded and located between the substrate 8 and the semiconductor material layer; and a higher level dielectric material layer (such as a line-level dielectric layer 290) in which a higher level metal interconnect structure (such as a metal line structure (96, 98)) is embedded and located above the at least one alternating stack {(132, 146), (232, 246)}. The metal interconnect structure below is a lower-level metal interconnect structure in the lower-level metal interconnect structure 780; and the contact via structure can contact a higher-level metal interconnect structure in the higher-level metal interconnect structure (such as metal wire structure (96, 98)).

[0264] In one embodiment, substrate 8 includes a semiconductor substrate; driver circuit semiconductor device 710 is located on the top surface of the semiconductor substrate; and a subset of higher-level metal interconnect structure 780 is electrically connected to the corresponding node of the semiconductor device.

[0265] refer to Figures 26A to 26E It can be done through Figures 1A to 1C The processing steps modify the shape of the opening through the source layer material layer 10' during the process and then perform the remaining processing steps of the first embodiment to obtain from Figures 24A to 24E and Figures 25A to 25CAny configuration of the first exemplary structure shown yields the second exemplary structure. The shape of the semiconductor material layers (such as lower source-level material layer 112, source contact layer 114, and / or higher source-level semiconductor layer 116) is modified such that each support pillar structure 20 located within the outer periphery of the vertically stacked dielectric oxide plates (152, 252) extends into the lower-level dielectric material layer 760 (such as at least one second dielectric layer 768). Each such opening is filled with a corresponding portion of the lower-level dielectric material layer 760 before the first alternating stack (132, 142) of the first insulating layer 132 and the first sacrificial material layer 142 is formed.

[0266] During the filling process through the first alternating stack (132, 142) and through the lower dielectric material layer 760, portions of the openings in the source layer material layer 10' are formed. Figures 4A to 4C A subset of the first layer of support openings 119 formed at the processing step. Optionally, in... Figures 4A to 4C The chemicals used in the anisotropic etching process at the processing step cause the final portion of the anisotropic etching process forming the first layer support opening 119 to etch the lower layer dielectric material layer 760 within the opening passing through the source layer 10' during the process at a higher etching rate than the material of the source layer 10' during the process. A first subset of the first layer support opening 119 formed through the opening in the source layer 10' during the process can be formed to have a greater depth than a second subset of the first layer support opening 119 formed in the source layer 10' during the process.

[0267] Subsequently, it can be executed Figures 5 to 9B The processing steps are used to form support openings 19 of different depths. Generally, a first subset of the support openings 19 can be formed through at least one alternating stacked {(132,142),(232,242)} into a portion of a lower-level dielectric layer 760 within an opening in the at least one semiconductor material layer located within the source layer 10' of the process. A second subset of the support openings 19 can be formed into the at least one semiconductor material layer within the source layer 10' of the process. The bottom surface of the first subset of the support openings 19 lies below a first horizontal plane including the bottom surface of the second subset of the support openings 19.

[0268] Subsequently, a first support pillar structure 20A (which is a first subset of support pillar structures 20) may be formed in the first subset of support openings 19, and a second support pillar structure 20B (which is a second subset of support pillar structures 20) may be formed in the second subset of support openings 19. Therefore, the first support pillar structure 20A may be formed directly on the lower-level dielectric material layer 760 above the opening in the at least one semiconductor material layer within the source layer 10' during the process, and the second support pillar structure 20 contacts the at least one semiconductor material layer within the source layer 10' during the process but does not contact the lower-level dielectric material layer 760. The bottom surface of the first support pillar structure 20A is located below a first horizontal plane including the bottom surface of the second support pillar structure 20B. The top surface of the first support pillar structure 20A may be located within a second horizontal plane including the top surface of the second support pillar structure 20B.

[0269] Can be executed subsequently Figures 10A to 18C The processing steps. By replacing portions of the sacrificial material layers (142, 242) (which are dielectric material portions) with dielectric oxide plates (152, 252), a vertical stack of dielectric oxide plates (152, 252) can be formed above an opening in at least one semiconductor material layer within the source layer 10' during the process.

[0270] Subsequently, it can be executed Figures 19A to 22D The processing steps involve replacing the remaining portion of the sacrificial material layers (142, 242) with conductive layers (146, 246). This can then be performed... Figures 23A to 25C The processing steps. Various contact via structures (88, 86, 486, 798) can be formed, including an array region through memory layer contact via structure 798 that extends vertically through the corresponding vertical stack of dielectric oxide plates (152, 252) and through a corresponding opening in at least one semiconductor material layer in the source layer 10, and directly on one of the lower-level metal interconnect structures 780. In one embodiment, the bottom surface of the first support pillar structure 20A may be located between a horizontal plane including the bottom surface of the semiconductor material layer (which may be one of the layers within the source layer 10) and another horizontal plane including the top surface of the semiconductor material layer.

[0271] refer to Figure 27A This can be achieved by extending the depth of the first subset of the first layer support opening 119 so that the bottom surface of the first subset of the first layer support opening 119 extends vertically below the horizontal plane including the bottom surface of the source layer material layer 10' in the process, thereby... Figures 26A to 26EThe second exemplary structure yields a first alternative configuration of the second exemplary structure. In one embodiment, the bottom surface of the first support pillar structure 20A may be located below a horizontal plane including the bottom surface of a semiconductor material layer within the source-level material layer 10, which may be any one of a lower source-level material layer 112, a source contact layer 114, and a higher source-level semiconductor layer 116.

[0272] refer to Figure 27B This can be achieved by increasing the thickness of the dielectric material layer within at least one second dielectric layer 768. Figure 27A The first alternative configuration of the second exemplary structure yields a second alternative configuration of the second exemplary structure. For example, the thickness of the dielectric material layer that contacts the top surface of the contact etch-stop dielectric layer 767 and contacts the bottom surface of the optional conductive plate layer 6 or the bottom surface of the source layer material layer 10 (in the absence of the optional conductive plate layer 6) can be in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0273] refer to Figure 27C The depth of the first support pillar structure 20A can be vertically extended so that the first support pillar structure 20A contacts the etch stop dielectric layer 767, thereby... Figure 27A The first alternative configuration of the second exemplary structure yields the third configuration of the second exemplary structure. In one embodiment, the etch-stop dielectric layer 767 may serve as an etch-stop structure during the formation of the first layer support opening 119, and the first support pillar structure 20A may be vertically spaced from a horizontal plane including the top surface of the landing pad-level metal interconnect structure 788 by the etch-stop dielectric layer 767.

[0274] refer to Figure 27D This can be achieved by vertically extending the first support pillar structure 20A through the etch-stop dielectric layer 767. Figure 27A The first alternative configuration of the second exemplary structure yields a fourth configuration of the second exemplary structure. In one embodiment, the first support column structure 20A may contact the top surface of the mat-level metal interconnect structure 788.

[0275] Various configurations of the second exemplary structure provide first support pillar structures 20A adjacent to the array region through the memory layer via structure 798. By forming the first support pillar structures 20A adjacent to the volume that subsequently forms the array region through the memory layer via structure 798, the lateral separation distance between the first support pillar structures 20A can be reduced, and the mechanical strength of the second exemplary structure increases during the formation of the finned cavities (153, 253) and the formation of the dielectric oxide plates (152, 252) therein. Therefore, buckling or deformation of the second exemplary structure during the formation of the dielectric oxide plates (152, 252) can be reduced or prevented, and the process yield for manufacturing the second exemplary structure can be increased.

[0276] refer to Figures 28A to 28C This can be achieved by modifying the pattern of the first-layer support opening 119. Figures 4A to 4C The first exemplary structure yields the third exemplary structure according to the third embodiment of this disclosure. Specifically, the pattern of the first layer support opening 119 may be modified such that a first subset of the first layer support openings is formed in the region of the opening in the source layer material layer 10' during passage. Furthermore, the annular region laterally surrounding the region of the opening in the source layer material layer 10' during passage may not contain the first layer support opening 119. Thus, the first subset of the first layer support opening 119 may extend vertically into a portion of the lower layer dielectric material layer 760 that fills the opening in the source layer material layer 10' during passage, and the annular region without the first layer support opening 119 may laterally surround the region of the opening in the source layer material layer 10' during passage.

[0277] Subsequently, it can be executed Figures 5 to 13C The processing steps are used to form the support pillar structure 20 and the memory opening filling structure 58. The support pillar structure 20 includes a first support pillar structure 20A that contacts the lower-level dielectric material layer 760 and a second support pillar structure 20B that contacts the source-level material layer 10' during the contact process.

[0278] refer to Figures 29A to 29C A first contact-level dielectric layer 280 can be formed over the second layer structure (232, 242, 270, 265). The first contact-level dielectric layer 280 comprises a dielectric material such as silicon oxide and can be formed by conformal or non-conformal deposition processes. For example, the first contact-level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0279] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form various openings in the memory array region 100 and the staircase region 200. The openings in the photoresist layer include first openings that extend laterally along a first horizontal direction hd1 through at least one staircase region 200 and at least a portion of the memory array region 100. The first openings extend laterally between a group of memory opening filling structures 58 and support pillar structures 20 spaced laterally along a second horizontal direction hd2.

[0280] Furthermore, the openings in the photoresist layer may include second openings having a generally annular shape, laterally surrounding a corresponding array of first support pillar structures 20A and being laterally surrounded by a corresponding set of second support pillar structures 20B. The entire region of each second opening may be located within the region of the source layer material layer 10' during the process.

[0281] Anisotropic etching can be performed to transfer a pattern in a photoresist layer through an underlying material portion comprising alternating stacks {(132,142),(232,242)} and an upper portion of the source-level material layer 10' in the process. A back-side trench 79 can be formed below a first opening in the photoresist layer, passing through the first contact-level dielectric layer 280, the second layer structure (232,242,270,265), and the first layer structure (132,142,170,165) and entering the in-process source-level material layer 10'. The portion of the first contact-level dielectric layer 280, the second layer structure (232,242,270,265), the first layer structure (132,142,170,165), and the in-process source-level material layer 10' below the first opening in the photoresist layer can be removed to form the back-side trench 79. In one embodiment, back-side trenches 79 may be formed between groups of memory stack structures 55 laterally spaced along a second horizontal direction. The top surface of the source-level sacrificial layer 104 may be physically exposed at the bottom of each back-side trench 79. Alternating stacks {(132,232), (142,242)} may be divided by the back-side trenches 79 into multiple alternating stacks {(132,232), (142,242)} of corresponding insulating layers (132,232) and corresponding sacrificial material layers (142,242).

[0282] Trench 279 may be formed below a second opening in the photoresist layer, passing through the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), and the first layer structure (132, 142, 170, 165) and entering the process source-level material layer 10'. The portions of the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the process source-level material layer 10' below the second opening in the photoresist layer may be removed to form trench 279. Each trench 279 laterally surrounds a corresponding subset of the first support pillar structure 20A and is laterally surrounded by a corresponding subset of the second support pillar structure 20B. Each trench 279 may be located between a pair of adjacent back-side trenches 79. Backside trench 79 and trench 279 are formed simultaneously using the same anisotropic etching process.

[0283] The sacrificial material layers (142, 242) may include a dielectric material, such as silicon nitride. The portion of the insulating layer (132, 232) laterally surrounded by the trench groove 279 constitutes an insulating plate (132', 232'). The insulating plate (132', 232') includes a first insulating plate 132' as a patterned portion of the first insulating layer 132 and a second insulating plate 232' as a patterned portion of the second insulating layer 232. The patterned portion of the sacrificial material layer (142, 242) laterally surrounded by the trench groove 279 includes a dielectric plate (142', 242'). The dielectric plate (142', 242') includes a first dielectric material plate 142' (e.g., a first silicon nitride plate) as a patterned portion of the first sacrificial material layer 142 and a second dielectric plate 242' (e.g., a second silicon nitride plate) as a patterned portion of the second sacrificial material layer 242. The patterned portion of the first insulating cap layer 170, which is laterally surrounded by the trench grooves 279, includes a first insulating cap plate 170'. The patterned portion of the interlayer dielectric layer 180, which is laterally surrounded by the trench grooves 279, includes an interlayer dielectric plate 180'. The patterned portions of the insulating layers (132, 232) and the sacrificial material layers (142, 242) within each trench groove 279 include a vertical alternating sequence of insulating plates (132', 232') and dielectric plates (142', 242').

[0284] In one embodiment, each trench 279 may have a horizontal cross-sectional shape of a rectangular frame. In this case, the outer sidewall of each trench 279 may include a pair of longitudinal sidewalls extending laterally along a first horizontal direction hd1 and a pair of transverse sidewalls extending laterally along a second horizontal direction hd2. The inner sidewall of each trench 279 may include a pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1 and a pair of transverse sidewalls extending laterally along the second horizontal direction hd2.

[0285] Each insulating plate in the insulating plates (132', 232') is vertically spaced from the top surface of the source layer material layer 10' during the process by the same vertical distance as the corresponding insulating layer (132, 232) outside the trench 279 from the top surface of the source layer material layer 10' during the process. Each dielectric plate in the dielectric plates (142', 242') is vertically spaced from the top surface of the source layer material layer 10' during the process by the same vertical distance as the corresponding sacrificial material layer (142, 242) outside the trench 279 from the top surface of the source layer material layer 10' during the process.

[0286] refer to Figures 30A to 30C An etch stop pad 71 can be conformally deposited in the backside trench 79 and the trench 279 and above the first contact-level dielectric layer 280 using a conformal deposition process. The etch stop pad 71 comprises a dielectric material different from the material of the first sacrificial material layer 142 and the second sacrificial material layer 242. For example, the etch stop pad 71 may comprise silicon oxide. The thickness of the etch stop pad 71 can range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although smaller and larger thicknesses are also possible.

[0287] A photoresist (not shown) may be applied over the third exemplary structure, and the photoresist layer may be photolithographically patterned to cover the trench 279 without covering the back trench 79. Unmasked portions of the etch stop pad 71 may be removed by performing an isotropic etching process. For example, if the etch stop pad 71 comprises silicon nitride, a wet etching process using hydrofluoric acid may be performed to remove the unmasked portions of the etch stop pad 71. The photoresist layer may then be removed, for example, by ashing. The sidewalls of the back trench 79 are physically exposed, and the sidewalls of the trench 279 are covered by the etch stop pad 71. Therefore, the sidewalls of the trench 279 may be masked using the etch stop pad 71 without covering the sidewalls of the back trench 79.

[0288] refer to Figure 31 Executable Figures 19A to 19D The processing steps involve replacing the source layer material layer 10' with the source layer material layer 10 during the process.

[0289] refer to Figure 32A and Figure 32D Executable Figures 21A to 21DThe processing steps selectively remove the sacrificial material layer (142, 242) from the insulating layer (132, 232), etch stop pad 71, first insulating cap layer and second insulating cap layer (170, 270), first contact level dielectric layer 280, source contact layer 114, dielectric semiconductor oxide plate 122 and annular dielectric semiconductor oxide spacer 124. For example, an isotropic etching process can be used to introduce an isotropic etchant into the back trench 79 to selectively etch the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the first insulating cap layer and second insulating cap layer (170, 270), the backward stepped dielectric material portion (165, 265), and the outermost layer of the memory film 50.

[0290] refer to Figures 33A to 33D Executable Figures 22A to 22D The processing steps are used to form conductive layers (146, 246) in the back side recesses (143, 243). The conductive layers (146, 246) include a first conductive layer 146 formed in the first back side recess 143 and a second conductive layer 246 formed in the second back side recess 243.

[0291] Subsequently, it can be executed Figures 23A to 2 The 3E processing step involves depositing a combination of dielectric filler material or insulating spacers and local interconnects in the back trench 79 and the trench 279. Each portion of the dielectric filler material filling the back trench 79 includes a back trench filler structure 76. Each portion of the dielectric filler material filling the trench 279 includes a dielectric trench filler structure 276. The back trench filler structure 76 and the dielectric trench filler structure 276 comprise one or more of the same material and / or are substantially composed of one or more of the same material. Each dielectric trench filler structure 276 laterally surrounds the vertical stack of dielectric plates (142', 242') and the vertical stack of insulating plates (132', 232'), and contacts at least one alternating stack of insulating layers (132, 232) and conductive layers (146, 246).

[0292] refer to Figures 34A to 34E A second contact-level dielectric layer 282 can be formed over the first contact-level dielectric layer 280 by depositing a dielectric material such as silicon oxide. Alternatively, the second contact-level dielectric layer 282 can be formed by not removing the dielectric filler material from the top surface of the first contact-level dielectric layer 280 after forming the back-side trench fill structure 76 and the dielectric trench fill structure 276. The thickness of the second contact-level dielectric layer 282 can be in the range of 200 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0293] Various via cavities can be formed through the second contact level dielectric layer 282 and the underlying dielectric material layer, and these via cavities can subsequently be filled with at least one conductive material to form various contact via structures (88, 86, 486, 798). Various via cavities can be formed using a single patterned photoresist layer as an etching mask layer and a single anisotropic etching process, or multiple patterned photoresist layers can be used as etching mask layers and multiple anisotropic etching processes can be used to form various via cavities.

[0294] When forming various via cavities using a single patterned photoresist layer and a single anisotropic etching process, the openings in the patterned photoresist layer may include: an opening covering the drain region 63 of the memory opening-fill structure 58; an opening covering the horizontal surface of the first stepped surface of the first alternating stack of the first insulating layer 132 and the first conductive layer 146 and the second stepped surface of the second alternating stack of the second insulating layer 232 and the second conductive layer 246; an opening covering the respective vertical stacks of the dielectric plates (142', 242'), the respective vertical stacks of the insulating plates (132', 232'), and the respective openings in the source layer material layer 10; and an optional opening located above the portion of the backward stepped dielectric material portion (165, 265) that does not cover the source layer material layer 10. In this case, the anisotropic etching process may have an etching chemical that is selective for the following materials: the material of the drain region 63, the materials of the first conductive layer 146 and the second conductive layer 246, and the material of the lower-level metal interconnect structure 780.

[0295] When forming various via cavities using multiple patterned photoresist layers and multiple anisotropic etching processes, the openings in each patterned photoresist layer include a corresponding subset of the following openings: an opening covering the drain region 63 of the memory opening-fill structure 58; an opening covering the horizontal surface of the first stepped surface of the first alternating stack of the first insulating layer 132 and the first conductive layer 146 and the second stepped surface of the second alternating stack of the second insulating layer 232 and the second conductive layer 246; an opening covering the corresponding vertical stack of the dielectric plates (142', 242'), the corresponding vertical stack of the insulating plates (132', 232'), and the corresponding openings in the source layer material layer 10; and an optional opening located above the portion of the backward stepped dielectric material portion (165, 265) that does not cover the source layer material layer 10. In this configuration, each anisotropic etching process may employ an etching chemical that is selective for a corresponding subset of the following materials: the material of drain region 63, the materials of the first conductive layer 146 and the second conductive layer 246, and the material of the lower-level metal interconnect structure 780. Various via cavities may include: drain contact via cavities formed above drain region 63; layer contact via cavities formed on the conductive layers (146, 246); peripheral through-memory-level via cavities formed through backward-stepped dielectric material portions (165, 265) on corresponding lower-level metal interconnect structures within the lower-level metal interconnect structure 780 (e.g., landing pad level metal interconnect structure 788); and arrays. The array regions penetrate the memory-level via cavities. These array regions penetrate the memory-level via cavities and are formed through a portion of the corresponding vertical stack of dielectric plates (142', 242'), the corresponding vertical stack of insulating plates (132', 232'), and the lower-level dielectric material layer 760 (such as at least one second dielectric layer 768) that fills the openings in the source-level material layer 10, and directly on the corresponding lower-level metal interconnect structure of the lower-level metal interconnect structure 780 (such as the landing pad-level metal interconnect structure 788).

[0296] After forming various via cavities and removing the patterned photoresist layer, at least one conductive material can be deposited in the various via cavities, for example, by chemical vapor deposition, physical vapor deposition, electroplating, and / or electroless plating. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the second contact-level dielectric layer 282. Contact via structures (88, 86, 486, 798) can be formed in the various via cavities.

[0297] The contact via structures (88, 86, 486, 798) include: drain contact via structures 88 that contact a corresponding drain region in drain region 63; layer contact via structures 86 that contact a corresponding conductive layer in conductive layer (146, 246); peripheral through-memory layer via structures 486 that extend through backward stepped dielectric material portions (165, 265) and contact a corresponding lower-level metal interconnect in lower-level metal interconnect structure 780; and array region through-memory layer via structures 798 that extend through the vertical stack of dielectric plates (142', 242'), the vertical stack of insulating plates (132', 232'), and a portion of lower-level dielectric material layer 760, and contact a corresponding lower-level metal interconnect in lower-level metal interconnect structure 780. Each peripheral through-memory-level via structure 486 is a contact via structure formed outside the regions of memory array region 100 and staircase region 200 and extending vertically through the memory layer (i.e., the layer located between the horizontal plane including the bottom surface of the source layer material layer 10 and the horizontal plane including the top surface of the memory opening filling structure 58). Each array region through-memory-level via structure 798 is a contact via structure formed within the region of memory array region 100 and extending vertically through the memory layer.

[0298] In one embodiment, each array region through the memory layer via structure 798 may extend vertically through a corresponding opening in the source layer 10 and may contact a portion of a lower layer dielectric material layer 760 (such as the at least one second dielectric layer 768) filling the opening in the source layer 10. In one embodiment, each array region through the memory layer via structure 798 may contact a portion of a lower layer dielectric material layer 760 (such as the at least one second dielectric layer 768) filling the opening in the source layer 10. In one embodiment, each array region through the memory layer via structure 798 may extend vertically through and contact a vertically alternating sequence of insulating plates (132', 232') and dielectric plates (142', 242'). Furthermore, each array region through the memory layer via structure 798 may be laterally spaced from the source layer 10 by a portion of the lower layer dielectric material layer 760 filling the opening in the source layer 10. In one embodiment, the lower-level dielectric material layer 760 may include an etch-stop dielectric layer 767 that contacts the top surface of the pad-level metal interconnect structure 788. In this case, each array region through the memory-level via structure 798 may extend through and contact the etch-stop dielectric layer 767, which may include a silicon nitride layer or a dielectric metal oxide layer.

[0299] Subsequently, higher-level dielectric material layers and higher-level metal interconnect structures can be formed. For example, the higher-level dielectric material layer may include a line-level dielectric layer 290 embedded therein and metal line structures (96, 98). The metal line structures (96, 98) may include bit lines 98 of a corresponding subset of the contact drain contact via structure 88, and interconnect metal lines 96 of at least one of the contact layer contact via structure 86, the peripheral through-memory level via structure 486, and the array region through-memory level via structure 798.

[0300] Figures 35A to 35D This is a vertical cross-sectional view of an alternative embodiment of the third exemplary structure.

[0301] refer to Figure 35A This can be achieved by extending the depth of the first subset of the first layer support opening 119 so that the bottom surface of the first subset of the first layer support opening 119 extends vertically below the horizontal plane including the bottom surface of the source layer material layer 10' in the process, thereby... Figures 34A to 34E The third exemplary structure yields a first alternative configuration of the third exemplary structure. In one embodiment, the bottom surface of the first support pillar structure 20A may be located below a horizontal plane including the bottom surface of a semiconductor material layer within the source-level material layer 10, which may be any one of a lower source-level material layer 112, a source contact layer 114, and a higher source-level semiconductor layer 116.

[0302] refer to Figure 35B This can be achieved by increasing the thickness of the dielectric material layer within at least one second dielectric layer 768. Figure 35A The first alternative configuration of the third exemplary structure yields a second alternative configuration of the third exemplary structure. For example, the thickness of the dielectric material layer that contacts the top surface of the contact etch-stop dielectric layer 767 and contacts the bottom surface of the optional conductive plate layer 6 or the bottom surface of the source layer material layer 10 (in the absence of the optional conductive plate layer) can be in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0303] refer to Figure 35C The depth of the first support pillar structure 20A can be vertically extended so that the first support pillar structure 20A contacts the etch stop dielectric layer 767, thereby... Figure 35A The first alternative configuration of the third exemplary structure yields the third configuration of the third exemplary structure. In one embodiment, the etch-stop dielectric layer 767 may serve as an etch-stop structure during the formation of the first layer support opening 119, and the first support pillar structure 20A may be vertically spaced from a horizontal plane including the top surface of the landing pad-level metal interconnect structure 788 by the etch-stop dielectric layer 767.

[0304] refer to Figure 35D This can be achieved by vertically extending the first support pillar structure 20A through the etch-stop dielectric layer 767. Figure 35A The first alternative configuration of the third exemplary structure yields a fourth configuration of the third exemplary structure. In one embodiment, the first support column structure 20A may contact the top surface of the mat-level metal interconnect structure 788.

[0305] Various configurations of the third exemplary structure provide first support pillar structures 20A adjacent to the array region through the memory-level via structure 798. By forming the first support pillar structures 20A adjacent to the volume that subsequently forms the array region through the memory-level via structure 798, the lateral separation distance between the first support pillar structures 20A can be reduced, and the mechanical strength of the third exemplary structure increases during the formation of the finned cavities (153, 253) and the formation of the dielectric oxide plates (152, 252) therein. Therefore, buckling or deformation of the third exemplary structure during the formation of the dielectric oxide plates (152, 252) can be reduced or prevented, and the process yield for manufacturing the third exemplary structure can be increased.

[0306] refer to Figures 36A to 36D This can be achieved by modifying the pattern of the opening in the source layer material layer 10' and the pattern of the support pillar structure 20 during the passage process. Figures 13A to 13C The first exemplary structure yields the fourth exemplary structure according to the fourth embodiment of this disclosure. Specifically, a first support pillar structure 20A is formed in the region of the opening of the source layer 10' during passage, and a second support pillar structure 20B is formed outside the region of the opening of the source layer 10' during passage. Each of the first support pillar structures 20A is contactable with a portion of the lower dielectric material layer 760 located within the opening of the source layer 10' during passage.

[0307] refer to Figures 37A to 37C A first contact-level dielectric layer 280 can be formed over the second layer structure (232, 242, 270, 265). The first contact-level dielectric layer 280 comprises a dielectric material such as silicon oxide and can be formed by conformal or non-conformal deposition processes. For example, the first contact-level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0308] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form various openings in the memory array region 100 and the staircase region 200. The openings in the photoresist layer include first openings that extend laterally along a first horizontal direction hd1 through at least one staircase region 200 and at least a portion of the memory array region 100. The first openings extend laterally between a group of memory opening filling structures 58 and support pillar structures 20 spaced laterally along a second horizontal direction hd2.

[0309] Furthermore, the openings in the photoresist layer may include second openings that cover the area of ​​the first support pillar structure 20A. Each second opening may be laterally surrounded by a corresponding subset of the first support pillar structure 20A and may be formed entirely within the area of ​​the lower opening of the source layer 10' through the pass-through process, i.e., entirely within the area of ​​the corresponding portion of the lower dielectric material layer 760 that fills the opening of the source layer 10' through the pass-through process.

[0310] Anisotropic etching can be performed to transfer the pattern in the photoresist layer through underlying material portions, which include portions of alternating stacked {(132,142),(232,242)}, the upper portion of the in-process source layer 10', and the lower layer dielectric material layer 760 filling the openings in the in-process source layer 10'. A back-side trench 79 may be formed below the first opening in the photoresist layer, passing through the first contact layer dielectric layer 280, the second layer structure (232,242,270,265), and the first layer structure (132,142,170,165) and into the in-process source layer 10'. The portion of the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), the first layer structure (132, 142, 170, 165), and the source-level material layer 10' below the first opening in the photoresist layer can be removed to form a back-side trench 79. In one embodiment, the back-side trench 79 can be formed between groups of memory stack structures 55 laterally spaced along a second horizontal direction. The top surface of the source-level sacrificial layer 104 can be physically exposed at the bottom of each back-side trench 79. Alternating stacks {(132, 232), (142, 242)} can be divided by the back-side trench 79 into multiple alternating stacks {(132, 232), (142, 242)} of corresponding insulating layers (132, 232) and corresponding sacrificial material layers (142, 242).

[0311] The via cavity may be formed below the second opening in the photoresist layer, passing through the first contact-level dielectric layer 280, the second layer structure (232, 242, 270, 265), and the first layer structure (132, 142, 170, 165) and entering the process source-level material layer 10'. The via cavity is referred to herein as an array region through-memory-level via cavity 779. The array region through-memory-level via cavity 779 may extend vertically through the portion of the lower-level dielectric material layer 760 covering the top surface of the landing pad-level metal interconnect structure 788. In one embodiment, the top surface of the landing pad-level metal interconnect structure 788 may be physically exposed at the bottom of each array region through-memory-level via cavity 779. Alternatively, the array region through-memory-level via cavity 779 may extend vertically to the top surface of the etch-stop dielectric layer 767. The back trench 79 and the array region through-hole cavity 779 are formed simultaneously using the same anisotropic etching process.

[0312] refer to Figures 38A to 38C Optionally, a drain selection hierarchical isolation structure 72 can be formed through a subset of the second sacrificial material layer 242. An etch stop pad 71 can be conformally deposited over the first contact hierarchical dielectric layer 280 via a conformal deposition process within the back-side trench 79 and the array region through the memory hierarchical via cavity 779. The etch stop pad 71 comprises a dielectric material different from that of the first sacrificial material layer 142 and the second sacrificial material layer 242. For example, the etch stop pad 71 may comprise silicon oxide. The thickness of the etch stop pad 71 can range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although smaller and larger thicknesses are also possible.

[0313] A photoresist (not shown) may be applied over the fourth exemplary structure, and the photoresist layer may be photolithographically patterned to cover the back trench 79 without covering the array region through-memory via cavity 779. Unmasked portions of the etch stop pad 71 may be removed by performing an isotropic etching process. For example, if the etch stop pad 71 comprises silicon nitride, a wet etching process using hydrofluoric acid may be performed to remove the unmasked portions of the etch stop pad 71. The photoresist layer may then be removed, for example, by ashing. The sidewalls of the array region through-memory via cavity 779 are physically exposed, and the sidewalls of the back trench 79 are covered by the etch stop pad 71. Therefore, the sidewalls of the back trench 79 may be masked using the etch stop pad 71 without covering the sidewalls of the array region through-memory via cavity 779.

[0314] refer to Figure 39An isotropic etching process can be performed to selectively recess the first sacrificial material layer 142 and the second sacrificial material layer 242 laterally around the memory-level via cavity 779 in each array region. For example, if the first sacrificial material layer 142 and the second sacrificial material layer 242 comprise silicon nitride and if the first insulating layer 132 and the second insulating layer 232 comprise silicon oxide, a wet etching process using thermal phosphoric acid can be performed to selectively remove portions of the sacrificial material layers (142, 242) adjacent to the recessed trench 179 of the insulating layers (132, 232).

[0315] Fin-shaped lateral recesses are formed in the volume from which the sacrificial material layers (142, 242) are removed. These fin-shaped lateral recesses are referred to herein as fin-shaped cavities 743. According to a fourth embodiment of this disclosure, a vertical stack of fin-shaped cavities 743 may be formed around each array region through-memory via cavity 779. The fin-shaped cavities 743 may have a uniform thickness and may have outer boundaries equidistant from the sidewalls of the respective array region through-memory via cavity 779. The lateral extent of each fin-shaped cavity 743 may be selected such that the fin-shaped cavities 743 do not divide any alternating stacks of insulating layers (132, 232) and sacrificial material layers (142, 242) into multiple separate stacks.

[0316] In one embodiment, at least one first support pillar structure 20A may be physically exposed to finned cavities 743 surrounding each array region through-memory via cavity 779. In one embodiment, at least one first support pillar structure 20A may be laterally surrounded by each finned cavity 743 formed around the array region through-memory via cavity 779. In one embodiment, a plurality of first support pillar structures 20A may be physically exposed to a vertical stack of finned cavities 743 laterally surrounding the array region through-memory via cavity 779, and may be laterally surrounded by the vertical stack.

[0317] Generally, finned cavities 743 can be formed around the memory-level via cavity 779 in each array region by selectively isotropically etching portions of the sacrificial material layer (142, 242) adjacent to the recessed trench 179 of the insulating layer (132, 232). The duration of the isotropic etching process for forming the finned cavity 743 can be selected such that the first support pillar structure 20A is physically exposed to the finned cavity 743, while the second support pillar structure 20B is not physically exposed to the finned cavity 743 after its formation.

[0318] refer to Figure 40A dielectric filling material layer 171 can be deposited in the finned cavity 743 using a conformal deposition process, such as low-pressure chemical vapor deposition (LPCVD). In one embodiment, the dielectric filling material layer 171 may comprise undoped silicate glass, doped silicate glass, or a dielectric metal oxide material (such as alumina). For example, the dielectric filling material layer 171 may comprise undoped silicate glass.

[0319] refer to Figure 41A and Figure 41B An etch-back process can be performed to remove portions of the dielectric filler layer 171 located in the recessed trench 179, the back trench 79, or above the first contact level dielectric layer 280. The etch-back process can include isotropic or anisotropic etching processes. For example, if the dielectric filler material comprises silicon oxide, an isotropic etching process using hydrofluoric acid can be used to etch back portions of the dielectric filler material from within the recessed trench 179 and the back trench 79 and from above the first contact level dielectric layer 280.

[0320] The remaining portion of the dielectric filler layer 171 filling the finned cavity 743 comprises dielectric oxide plates (162, 262). The dielectric oxide plates (162, 262) include a first dielectric oxide plate 162 contacting the first sacrificial material layer 142 and a second dielectric oxide plate 262 contacting the second sacrificial material layer 142. Therefore, portions of the adjacent array regions of the sacrificial material layers (142, 242) penetrating the memory level via cavity 779 are replaced by dielectric oxide plates (162, 262). Vertical stacks of dielectric oxide plates (162, 262) are provided around each array region penetrating the memory level via cavity 779. The vertical stacks of dielectric oxide plates (162, 262) intersect with the laterally extending portions of the insulating layers (132, 232) of the at least one alternating stack {(132, 142), (232, 242)}. Each dielectric oxide plate (162, 262) is located between a pair of corresponding vertically adjacent insulating layers (132, 232) of the at least one alternating stack {(132, 142), (232, 242)}. The replacement of a portion of the adjacent array region of the sacrificial material layer (142, 242) through the memory level via cavity 779 with a dielectric oxide plate (162, 262) is performed while the etch stop pad 71 covers the sidewall of the back trench 79. Each outer sidewall of the dielectric oxide plate (162, 262) may contact the sidewall of the sacrificial material layer (142, 242). In one embodiment, each dielectric oxide plate (162, 262) may include a convex sidewall equidistant from the sidewall of the array region through the memory level via cavity 779. Subsequently, the etch stop pad 71 can be removed by extending the isotropic etching process.

[0321] In the case where multiple array regions are formed above a portion of the lower-level dielectric material layer 760 with an opening in the source-level material layer 10' during the filling process, penetrating the memory-level via cavity 779, a set of finned cavities 743 may be adjacent to each other at each level of the sacrificial material layers (142, 242). In this case, dielectric oxide plates (162, 262) may laterally surround the multiple array regions formed above a portion of the lower-level dielectric material layer 760 with an opening in the source-level material layer 10' during the filling process, penetrating the memory-level via cavity 779.

[0322] refer to Figure 42 Optionally, a sacrificial etch stop layer 175 may be formed in the back-side trench 79 and the array region through the memory-level via cavity 779 and over the first contact-level dielectric layer 280. For example, the sacrificial etch stop layer 75 may comprise a layer stack including a first silicon oxide barrier layer 175A, a silicon nitride barrier layer 175B, and a second silicon oxide barrier layer 175C. Each of the silicon oxide barrier layer 175A, the silicon nitride barrier layer 175B, and the second silicon oxide barrier layer 175C may have a corresponding thickness in the range of 3 nm to 30 nm, but smaller and larger thicknesses are also possible. Alternatively, the sacrificial etch stop layer 75 may comprise a layer stack including a silicon nitride barrier layer 175A, a silicon oxide barrier layer 175B, and an amorphous silicon barrier layer 175C.

[0323] refer to Figure 43 The sacrificial etch stop layer 175 can be patterned, for example, by applying and patterning a photoresist layer 87 over the sacrificial etch stop layer 75, such that the patterned photoresist layer 87 covers each array region through the memory level via cavity 779. Unmasked horizontal portions of the sacrificial etch stop layer 175 can be removed by performing an anisotropic etching process. Sacrificial etch stop spacers 75A, including the remaining portion of the sacrificial etch stop layer 175, can be formed on the sidewalls of the back-side trench 79. Sacrificial etch stop pads 75B, including the remaining portion of the sacrificial etch stop layer 175, can cover each array region through the memory level via cavity 779. The photoresist layer 87 can then be removed, for example, by ashing.

[0324] refer to Figure 44 Executable Figures 19A to 19D The processing steps are to replace the source layer 10' with the source layer 10 during the replacement process. The sacrificial etch stop spacer 75A and the sacrificial etch stop pad 75B can be removed in parallel during the replacement process of the source layer 10' with the source layer 10.

[0325] refer to Figure 45A and Figure 45B Executable Figures 21A to 21DThe processing steps selectively remove the sacrificial material layer (142, 242) from the insulating layer (132, 232), the dielectric oxide substrate (162, 262), the first insulating cap layer and the second insulating cap layer (170, 270), the first contact layer dielectric layer 280, the source contact layer 114, the dielectric semiconductor oxide substrate 122, and the annular dielectric semiconductor oxide spacer 124. For example, an isotropic etching process can be used to introduce an isotropic etchant into the back trench 79 to selectively etch the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the first insulating cap layer and the second insulating cap layer (170, 270), the backward stepped dielectric material portion (165, 265), and the outermost layer of the memory film 50. A back recess is formed in the volume from which the sacrificial material layer (142, 242) is removed.

[0326] Subsequently, it can be executed Figures 22A to 22D The processing steps are used to form conductive layers (146, 246) in the back side recess. The conductive layers (146, 246) include a first conductive layer 146 formed in the first back side recess 143 and a second conductive layer 246 formed in the second back side recess 243.

[0327] refer to Figure 46A and Figure 46B An insulating pad can be conformally deposited in the back-side trench 79 and the array region through-memory via cavity 779. The insulating pad comprises an insulating material such as silicon oxide or silicon nitride and can have a thickness ranging from 6 nm to 120 nm, but smaller and larger thicknesses are also possible. An anisotropic etching process can be performed to remove the horizontal portions of the insulating pad. The horizontal portions of the dielectric semiconductor oxide substrate 122 can be removed by an anisotropic etching process, and the top surface of the source contact layer 114 can be physically exposed at the bottom of each back-side trench 79. The top surface of the landing pad-level metal interconnect structure 788 can be physically exposed at the bottom of each array region through-memory via cavity 779. The remaining vertical extensions of the insulating pad include back-side trench insulating spacers 374 held at the peripheral region of the back-side trench 79 and insulating via spacers 774 held at the peripheral region of the array region through-memory via cavity 779.

[0328] At least one conductive material may be deposited in the remaining volume of the back-side trench 79 and the array region through-memory level via cavity 779. For example, the at least one conductive material may include, for example, conductive metal pad materials (such as TiN, TaN, and / or WN) and metal filler materials (such as W, Cu, Mo, Ru, Co, etc.). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the first contact level dielectric layer 280 by a planarization process. This planarization process may employ a recess etching process and / or a chemical mechanical planarization process. Each remaining portion of the at least one conductive material in the back-side trench 79 includes a source contact structure (e.g., a source local interconnect) 376, which is a conductive wall structure extending laterally along a first horizontal direction hd1. Each remaining portion of the at least one conductive material in the array region through-memory level via cavity 779 includes an array region through-memory level via structure 798 that contacts the top surface of a corresponding drop pad level metal interconnect structure 788.

[0329] refer to Figures 47A to 47E A second contact-level dielectric layer 282 can be formed above the first contact-level dielectric layer 280 by depositing a dielectric material such as silicon oxide. The thickness of the second contact-level dielectric layer 282 can be in the range of 200 nm to 600 nm, but smaller and larger thicknesses are also possible.

[0330] Various via cavities can be formed through the second contact level dielectric layer 282 and the underlying dielectric material layer, and these via cavities can subsequently be filled with at least one conductive material to form various contact via structures (88, 86, 486, 799). Various via cavities can be formed using a single patterned photoresist layer as an etching mask layer and a single anisotropic etching process, or multiple patterned photoresist layers can be used as etching mask layers and multiple anisotropic etching processes can be used to form various via cavities.

[0331] When forming various via cavities using a single patterned photoresist layer and a single anisotropic etching process, the openings in the patterned photoresist layer may include: an opening covering the drain region 63 of the memory via structure 58; an opening covering a horizontal surface covering a first stepped surface of a first alternating stack of the first insulating layer 132 and the first conductive layer 146, and a second stepped surface of a second alternating stack of the second insulating layer 232 and the second conductive layer 246; an opening covering the corresponding array region through the memory level via structure 798; and an optional opening located above a portion of the backward stepped dielectric material portion (165, 265) that does not cover the source level material layer 10. In this case, the anisotropic etching process may have an etching chemical that is selective for materials such as the material of the drain region 63, the material of the first conductive layer 146 and the second conductive layer 246, the material of the array region through the memory level via structure 798, and the material of the lower-level metal interconnect structure 780.

[0332] When forming various via cavities using multiple patterned photoresist layers and multiple anisotropic etching processes, the openings in each patterned photoresist layer include a corresponding subset of the following openings: an opening covering the drain region 63 of the memory via-fill structure 58; an opening covering a horizontal surface covering a first stepped surface of a first alternating stack of the first insulating layer 132 and the first conductive layer 146, and a second stepped surface of a second alternating stack of the second insulating layer 232 and the second conductive layer 246; an opening covering the corresponding array region through the memory level via structure 798; and an optional opening located above the portion of the backward stepped dielectric material portion (165, 265) that does not cover the source level material layer 10. In this case, each anisotropic etching process may have an etching chemical that is selective for a corresponding subset of the following materials: the material of the drain region 63, the material of the first conductive layer 146 and the second conductive layer 246, the material of the array region through the memory level via structure 798, and the material of the lower-level metal interconnect structure 780. Various via cavities may include: drain contact via cavities formed above drain region 63; layer contact via cavities formed on conductive layers (146, 246); peripheral through-memory-level via cavities formed through backward stepped dielectric portions (165, 265) on corresponding lower-level metal interconnect structures in lower-level metal interconnect structures 780 (such as landing pad level metal interconnect structures 788); and array region connection cavities formed on corresponding array region through-memory-level via structures in array region through-memory-level via structures 798.

[0333] After forming various via cavities and removing the patterned photoresist layer, at least one conductive material can be deposited in the various via cavities, for example, by chemical vapor deposition, physical vapor deposition, electroplating, and / or electroless plating. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the second contact-level dielectric layer 282. Contact via structures (88, 86, 486, 798) can be formed in the various via cavities.

[0334] The contact via structures (88, 86, 486, 799) include: drain contact via structures 88 that contact corresponding drain regions in drain regions 63; layer contact via structures 86 that contact corresponding conductive layers in conductive layers (146, 246); peripheral through-memory-level via structures 486 that extend through backward stepped dielectric material portions (165, 265) and contact corresponding lower-level metal interconnect structures in lower-level metal interconnect structures 780; and array region connection via structures 799 that contact corresponding array region through-memory-level via structures in array region through-memory-level via structures 798. Each peripheral through-memory layer via structure 486 is a contact via structure formed outside the regions of memory array region 100 and staircase region 200 and extending vertically through the memory layer (i.e., the layer located between the horizontal plane including the bottom surface of the source layer material layer 10 and the horizontal plane including the top surface of the memory opening filling structure 58). Each array region connecting via structure 799 is a conductive via structure that contacts the corresponding through-memory layer via structure 798.

[0335] In one embodiment, each array region through the memory layer via structure 798 may extend vertically through a corresponding opening in the source layer material layer 10 and may contact a portion of a lower layer dielectric material layer 760 (such as the at least one second dielectric layer 768) filling the opening in the source layer material layer 10. In one embodiment, each array region through the memory layer via structure 798 may contact a portion of a lower layer dielectric material layer 760 (such as the at least one second dielectric layer 768) filling the opening in the source layer material layer 10. In one embodiment, each array region through the memory layer via structure 798 may be formed in a region located between the support pillar structures 20 and may be laterally spaced from the conductive layers (146, 246) by the portion surrounding the dielectric oxide plates (162, 262). Furthermore, each array region through the memory layer via structure 798 may be laterally spaced from the source layer material layer 10 by the portion of the lower layer dielectric material layer 760 filling the opening in the source layer material layer 10. In one embodiment, the lower-level dielectric material layer 760 may include an etch-stop dielectric layer 767 that contacts the top surface of the pad-level metal interconnect structure 788. In this case, each array region through the memory-level via structure 798 may extend through and contact the etch-stop dielectric layer 767, which may include a silicon nitride layer or a dielectric metal oxide layer.

[0336] Subsequently, higher-level dielectric material layers and higher-level metal interconnect structures can be formed. For example, the higher-level dielectric material layer may include a line-level dielectric layer 290 embedded therein and metal line structures (96, 98). The metal line structures (96, 98) may include bit lines 98 of a corresponding subset of the contact drain contact via structure 88, and interconnect metal lines 96 of at least one of the contact layer contact via structure 86, the peripheral through-memory layer via structure 486, and the array region connection via structure 799.

[0337] Figures 48A to 48D This is a vertical cross-sectional view of an alternative embodiment of the fourth exemplary structure.

[0338] refer to Figure 48A This can be achieved by extending the depth of the first subset of the first layer support opening 119 so that the bottom surface of the first subset of the first layer support opening 119 extends vertically below the horizontal plane including the bottom surface of the source layer material layer 10' in the process, thereby... Figures 47A to 47EThe fourth exemplary structure yields a first alternative configuration of the fourth exemplary structure. In one embodiment, the bottom surface of the first support pillar structure 20A may be located below a horizontal plane including the bottom surface of a semiconductor material layer within the source-level material layer 10, which may be any one of a lower source-level material layer 112, a source contact layer 114, and a higher source-level semiconductor layer 116.

[0339] refer to Figure 48B This can be achieved by increasing the thickness of the dielectric material layer within at least one second dielectric layer 768. Figure 48A The first alternative configuration of the fourth exemplary structure yields a second alternative configuration of the fourth exemplary structure. For example, the thickness of the dielectric material layer that contacts the top surface of the contact etch-stop dielectric layer 767 and contacts the bottom surface of the optional conductive plate layer 6 or the bottom surface of the source layer material layer 10 (in the absence of the optional conductive plate layer) can be in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0340] refer to Figure 48C The depth of the first support pillar structure 20A can be vertically extended so that the first support pillar structure 20A contacts the etch stop dielectric layer 767, thereby... Figure 48A The first alternative configuration of the fourth exemplary structure yields the third configuration of the fourth exemplary structure. In one embodiment, the etch-stop dielectric layer 767 may serve as an etch-stop structure during the formation of the first layer support opening 119, and the first support pillar structure 20A may be vertically spaced from a horizontal plane including the top surface of the landing pad-level metal interconnect structure 788 by the etch-stop dielectric layer 767.

[0341] refer to Figure 48D This can be achieved by vertically extending the first support pillar structure 20A through the etch-stop dielectric layer 767. Figure 27A The first alternative configuration of the fourth exemplary structure yields the fourth configuration of the fourth exemplary structure. In one embodiment, the first support column structure 20A may contact the top surface of the mat-level metal interconnect structure 788.

[0342] refer to Figures 26A to 48DFurthermore, according to various embodiments of this disclosure, a three-dimensional memory device is provided, comprising: a semiconductor material layer (such as a lower source level material layer 112, a source contact layer 114, and / or a higher source level semiconductor layer 116), the semiconductor material layer covering a substrate 8 and including an opening therein; lower level dielectric material layers 760, these lower level dielectric material layers being located between the substrate 8 and the semiconductor material layer and extending into the opening in the semiconductor material layer; at least one alternating stack of insulating layers (132, 232) and conductive layers (146, 246), the at least one alternating stack covering the semiconductor material layer; a memory stack structure 55 (located within a memory opening-filling structure 58), the memory stack structure extending vertically through the at least one alternating stack {(132, 146), (232, 246)}; dielectric plates {(152, 252), (142', A vertical stack of (146, 246) or (162, 262)}, the vertical stack being located at each level of the conductive layer (146, 246); a contact via structure (such as a memory region through-substrate contact via structure 798), the contact via structure extending vertically through the vertical stack of dielectric plates {(152, 252), (142', 242') or (162, 262)} and through an opening in the semiconductor material layer; a first support pillar structure 20A, The first support pillar structure extends vertically through the vertical stack of dielectric plates {(152,252), (142',242') or (162,262)} and contacts a portion of the lower-level dielectric material layer 760 located within an opening in the semiconductor material layer; and the second support pillar structure 20B extends vertically through the at least one alternating stack {(132,146),(232,246)} and contacts the semiconductor material layer.

[0343] In one embodiment, the first support pillar structure 20A and the second support pillar structure 20B comprise the same dielectric material. In one embodiment, the bottom surface of the first support pillar structure 20A lies below a first horizontal plane including the bottom surface of the second support pillar structure 20B. In one embodiment, the top surface of the first support pillar structure 20A lies within a second horizontal plane including the top surface of the second support pillar structure 20B. In one embodiment, the bottom surface of the first support pillar structure 20A lies between a horizontal plane including the bottom surface of a semiconductor material layer (which may be one of a lower source layer 112, a source contact layer 114, or a higher source layer semiconductor layer 116) and another horizontal plane including the top surface of the semiconductor material layer. In one embodiment, the bottom surface of the first support pillar structure 20A lies below the horizontal plane including the bottom surface of the semiconductor material layer.

[0344] In one embodiment, a contact via structure (such as a memory region through-substrate level contact via structure 798) contacts the top surface of a metal interconnect structure (such as a landing pad level metal interconnect structure 788) embedded in a lower-level dielectric layer 760. In one embodiment, the lower-level dielectric layer 760 includes an etch-stop dielectric layer 767 that contacts the top surface of the metal interconnect structure; and the bottom surface of the first support pillar structure 20A contacts the etch-stop dielectric layer 767. In one embodiment, one or each of the first support pillar structures 20A contacts the metal interconnect structure.

[0345] In one embodiment, the dielectric plates {(152,252), (142',242') or (162,262)} in the vertical stack are interleaved with the lateral extensions of the insulating layer (132,232) of the at least one alternating stack {(132,146),(232,246)}.

[0346] In one embodiment, the wall structure 176 extends vertically through the at least one alternating stack {(132,146),(232,246)}, contacting the insulating layer (132,232) and the vertical stack of dielectric plates (152,252). In one embodiment, the vertical stack of insulating plates (132',232') may be staggered with the vertical stack of dielectric plates (142',242'). The insulating plates (132',232') comprise the same material as the insulating layer (132,232) and are laterally spaced from the insulating layer (132,232). In one embodiment, the dielectric trench filling structure 276 laterally surrounds the vertical stack of dielectric plates (142',242') and the vertical stack of insulating plates (132',232'), and contacts the at least one alternating stack of insulating layers (132,232) and conductive layers (146,246). In one embodiment, each dielectric plate {(152,252) or (162,262)} within a vertical stack of dielectric plates {(152,252) or (162,262)} includes a corresponding sidewall segment equidistant from the sidewall of the contact via structure.

[0347] Various embodiments of this disclosure can be employed to provide a configuration in which a first support pillar structure 20A is formed adjacent to each array region through the substrate-level via structure 798. The proximity between the first support pillar structure 20A and the volume in which the array regions through the substrate-level via structure 798 are formed can reduce the lateral spacing between the first support pillar structures 20A. Combined with dielectric plates {(152,252), (142',242') or (162,262)}, the first support pillar structure 20A can increase the mechanical strength of the regions in which the array regions through the substrate-level via structure 798 are subsequently formed, and enhance the structural integrity of the semiconductor structure during manufacturing.

[0348] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: At least one alternating stack of insulating and conductive layers is located above the underlying metal interconnect structure; A memory stack structure that extends vertically through the at least one alternating stack; Vertical stacking of dielectric oxide plates, the vertical stacking intersects with the lateral extensions of the at least one alternately stacked insulating layer, wherein each dielectric oxide plate is located between a pair of corresponding vertically adjacent insulating layers of the at least one alternately stacked layer; and A conductive via structure that extends vertically through each dielectric oxide plate within the vertical stack and each lateral extension portion of the at least one alternately stacked insulating layer, and contacts the underlying metal interconnect structure.

2. The three-dimensional memory device according to claim 1, further comprising: A first back-side groove filling structure extends laterally along a first horizontal direction and contacts the at least one alternately stacked sidewalls; and A second back-side groove filling structure extends laterally along the first horizontal direction and contacts the at least one alternately stacked additional sidewalls.

3. The three-dimensional memory device of claim 2, further comprising a wall structure that contacts each dielectric oxide plate within the vertical stack of the dielectric oxide plates.

4. The three-dimensional memory device of claim 3, wherein the first back-side trench filling structure, the second back-side trench filling structure, and the wall structure each comprise one of a dielectric filling structure surrounded by insulating spacers or a local interconnect.

5. The three-dimensional memory device of claim 3, wherein each dielectric oxide plate in the vertical stack of the dielectric oxide plates laterally surrounds the wall structure, and wherein each dielectric oxide plate has an inner wall that contacts the wall structure and an outer wall that is laterally offset by a uniform lateral offset distance from the inner wall that is closest to the inner wall.

6. The three-dimensional memory device of claim 3, wherein the dielectric oxide substrate includes a straight outer wall segment extending laterally along the first horizontal direction and a curved outer wall segment having a corresponding convex horizontal cross-sectional profile.

7. The three-dimensional memory device according to claim 3, wherein: The dielectric oxide plate contacts the second back-side trench filling structure; The wall structure is laterally spaced from the first back-side groove filling structure along a second horizontal direction perpendicular to the first horizontal direction; and The wall structure is laterally spaced from the second back-side groove filling structure along the first horizontal direction.

8. The three-dimensional memory device of claim 1, wherein the conductive via structure contacts each insulating layer within the at least one alternating stack and each dielectric oxide plate within the vertical stack of the dielectric oxide plates.

9. The three-dimensional memory device according to claim 1, further comprising: A first support column structure, the first support column structure extending vertically through the at least one alternating stack; and A second support column structure extends vertically through the vertical stack of the dielectric oxide board and the lateral extension portion of the at least one alternately stacked insulating layer.

10. The three-dimensional memory device of claim 1, further comprising a semiconductor material layer located between the underlying metal interconnect structure and the at least one alternating stack. in: The semiconductor material layer includes an opening therethrough; and The conductive via structure extends through the opening in the semiconductor material layer and is laterally spaced from the periphery of the opening that extends through the semiconductor material layer.

11. The three-dimensional memory device of claim 1, wherein each memory stack structure in the memory stack structure comprises: A vertical semiconductor channel that extends vertically through each conductive layer within the at least one alternating stack; and A vertical stack of memory elements, wherein the memory elements are located at the level of the conductive layer within the at least one alternating stack.

12. The three-dimensional memory device of claim 1, wherein the at least one alternating stack comprises: A first layer of alternating stacked first insulating layer and a first conductive layer, the first layer of alternating stacked first layers having a first stepped surface that contacts a first backward stepped dielectric material portion; and The second insulating layer and the second conductive layer are alternately stacked, the second layer having a second stepped surface that contacts the second backward stepped dielectric material portion.

13. The three-dimensional memory device according to claim 1, further comprising: Substrate, the substrate being located below the underlying metal interconnect structure; A semiconductor material layer, the semiconductor material layer being located between the underlying metal interconnect structure and the at least one alternating stack; A lower-level dielectric material layer, wherein a lower-level metal interconnect structure is embedded therein and located between the substrate and the semiconductor material layer; and A higher-level dielectric layer, wherein a higher-level metal interconnect structure is embedded in the higher-level dielectric layer and is located above the at least one alternating stack, wherein: The metal interconnect structure described below is a lower-level metal interconnect structure within the lower-level metal interconnect structures; and The conductive via structure contacts one of the higher-level metal interconnect structures in the higher-level metal interconnect structure.

14. The three-dimensional memory device according to claim 13, wherein: The substrate includes a semiconductor substrate; The driver circuit semiconductor device is located on the top surface of the semiconductor substrate; and The lower-level metal interconnect structure's subsets are electrically connected to the corresponding nodes of the driver circuit semiconductor device.

15. A three-dimensional memory device, the three-dimensional memory device comprising: A semiconductor material layer covering a substrate and including an opening therein; A lower-level dielectric material layer is located between the substrate and the semiconductor material layer and extends into the opening in the semiconductor material layer; At least one insulating layer and a conductive layer are stacked alternately, the at least one alternating stack covering the semiconductor material layer; A memory stack structure that extends vertically through the at least one alternating stack; Vertically stacked dielectric plates, the dielectric plates being located at each level of the conductive layer; A contact via structure that extends vertically through the vertical stack of the dielectric and through the opening in the semiconductor material layer; A first support pillar structure extends vertically through the vertical stack of the dielectric plate and contacts a portion of the lower-level dielectric material layer located within the opening in the semiconductor material layer; A second support pillar structure extends vertically through the at least one alternating stack and contacts the semiconductor material layer; and Vertical stacking of insulating plates, the vertical stacking of the insulating plates being staggered with the vertical stacking of the dielectric plates, wherein the insulating plates comprise the same material as the insulating layer and are laterally spaced apart from the insulating layer.

16. The three-dimensional memory device of claim 15, wherein the first support pillar structure and the second support pillar structure comprise the same dielectric material.

17. The three-dimensional memory device of claim 15, wherein the bottom surface of the first support pillar structure is located below a first horizontal plane including the bottom surface of the second support pillar structure.

18. The three-dimensional memory device of claim 17, wherein the top surface of the first support pillar structure lies within a second horizontal plane including the top surface of the second support pillar structure.

19. The three-dimensional memory device of claim 17, wherein the bottom surface of the first support pillar structure is located between a horizontal plane including the bottom surface of the semiconductor material layer and another horizontal plane including the top surface of the semiconductor material layer.

20. The three-dimensional memory device of claim 17, wherein the bottom surface of the first support pillar structure is located below a horizontal plane including the bottom surface of the semiconductor material layer.

21. The three-dimensional memory device of claim 15, wherein the contact via structure contacts the top surface of the metal interconnect structure embedded in the lower-level dielectric material layer.

22. The three-dimensional memory device according to claim 21, wherein: The lower-level dielectric material layer includes an etch-stop dielectric layer that contacts the top surface of the metal interconnect structure; and The bottom surface of the first support pillar structure contacts the etch-stop dielectric layer.

23. The three-dimensional memory device of claim 21, wherein one of the first support pillar structures contacts the metal interconnect structure.

24. The three-dimensional memory device of claim 15, wherein the dielectric plates in the vertical stack are interleaved with the lateral extensions of the at least one alternately stacked insulating layer.

25. The three-dimensional memory device of claim 24, further comprising a wall structure extending vertically through the at least one alternating stack, contacting the insulating layer and the vertical stack of the dielectric plate.

26. The three-dimensional memory device of claim 15, further comprising a dielectric trench filling structure that laterally surrounds the vertical stack of the dielectric substrate and the vertical stack of the insulating substrate, and contacts at least one alternating stack of the insulating layer and the conductive layer.

27. The three-dimensional memory device of claim 15, wherein each dielectric plate in the vertical stack of the dielectric plates includes a corresponding sidewall segment equidistant from the sidewall of the contact via structure.

28. A three-dimensional memory device, the three-dimensional memory device comprising: A semiconductor material layer covering a substrate and including an opening therein; A lower-level dielectric material layer is located between the substrate and the semiconductor material layer and extends into the opening in the semiconductor material layer; At least one insulating layer and a conductive layer are stacked alternately, the at least one alternating stack covering the semiconductor material layer; A memory stack structure that extends vertically through the at least one alternating stack; Vertically stacked dielectric plates, the dielectric plates being located at each level of the conductive layer; A contact via structure that extends vertically through the vertical stack of the dielectric and through the opening in the semiconductor material layer; A first support pillar structure extends vertically through the vertical stack of the dielectric plate and contacts a portion of the lower-level dielectric material layer located within the opening in the semiconductor material layer; as well as A second support pillar structure extends vertically through the at least one alternating stack and contacts the semiconductor material layer; The contact via structure contacts the top surface of the metal interconnect structure embedded in the lower-level dielectric material layer; and One of the first support pillar structures is in contact with the metal interconnect structure.

29. A three-dimensional memory device, the three-dimensional memory device comprising: A semiconductor material layer covering a substrate and including an opening therein; A lower-level dielectric material layer is located between the substrate and the semiconductor material layer and extends into the opening in the semiconductor material layer; At least one insulating layer and a conductive layer are stacked alternately, the at least one alternating stack covering the semiconductor material layer; A memory stack structure that extends vertically through the at least one alternating stack; Vertically stacked dielectric plates, the dielectric plates being located at each level of the conductive layer; A contact via structure that extends vertically through the vertical stack of the dielectric and through the opening in the semiconductor material layer; A first support pillar structure extends vertically through the vertical stack of the dielectric plate and contacts a portion of the lower-level dielectric material layer located within the opening in the semiconductor material layer; A second support pillar structure extends vertically through the at least one alternating stack and contacts the semiconductor material layer; and A wall structure that extends vertically through the at least one alternating stack, contacts the insulating layer and the vertical stack of the dielectric plate; The dielectric plates in the vertical stack are interleaved with the lateral extensions of the at least one alternately stacked insulating layer.

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