Light emitting diode chip, preparation method thereof and display device

Abstract

A light emitting diode chip includes a plurality of epitaxial structures, at least one first electrode, and a plurality of second electrodes. Any two adjacent epitaxial structures of the plurality of epitaxial structures have a gap therebetween. Each epitaxial structure includes a first semiconductor pattern, a light emitting pattern, and a second semiconductor pattern, which are sequentially stacked. The first semiconductor patterns of at least two epitaxial structures of the plurality of epitaxial structures are in communication with each other to form a first semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. Each second electrode is electrically connected to the second semiconductor pattern of at least one epitaxial structure of the plurality of epitaxial structures.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a light-emitting diode chip, its fabrication method, and a display device. Background Technology

[0002] Light-emitting diodes (LEDs) have many advantages, such as high efficiency, high brightness, high reliability, energy saving, and fast response speed. Compared with liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs), LED displays have significant advantages in image quality, refresh rate, power consumption, and brightness. As a result, LEDs are widely used in traditional displays, near-eye displays, 3D displays, and transparent displays. Summary of the Invention

[0003] On one hand, a light-emitting diode (LED) chip is provided. The LED chip includes: a plurality of epitaxial structures; at least one first electrode; and a plurality of second electrodes. A gap exists between any two adjacent epitaxial structures. Each epitaxial structure includes: a first semiconductor pattern, a light-emitting pattern, and a second semiconductor pattern sequentially stacked. The first semiconductor patterns of at least two of the plurality of epitaxial structures are interconnected to form a first semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. Each second electrode is electrically connected to the second semiconductor pattern of at least one of the plurality of epitaxial structures.

[0004] In some embodiments, the first electrode and the plurality of second electrodes are disposed on the same side of the first semiconductor layer.

[0005] In some embodiments, the orthographic projection of the first electrode onto the first plane lies within the orthographic projection range of the first semiconductor layer electrically connected to the first electrode onto the first plane, and does not overlap with the orthographic projections of the plurality of epitaxial structures onto the first plane. The first plane is a plane parallel to the first semiconductor layer.

[0006] In some embodiments, the orthographic projection of the second electrode onto the first plane and the orthographic projection of the second semiconductor pattern of the at least one epitaxial structure electrically connected to the second electrode onto the first plane at least partially overlap.

[0007] In some embodiments, the plurality of epitaxial structures are spaced apart along a first direction, and the epitaxial structures extend along a second direction. The first direction and the second direction intersect each other.

[0008] In some embodiments, a plurality of second semiconductor patterns in the plurality of epitaxial structures are spaced apart along the first direction, and the second semiconductor patterns extend along the second direction.

[0009] In some embodiments, the plurality of light-emitting patterns in the plurality of epitaxial structures are spaced apart along the first direction, and the light-emitting patterns extend along the second direction.

[0010] In some embodiments, the plurality of epitaxial structures are arranged in an array.

[0011] In some embodiments, the plurality of second semiconductor patterns in the plurality of epitaxial structures are arranged in an array.

[0012] In some embodiments, the plurality of light-emitting patterns in the plurality of epitaxial structures are arranged in an array.

[0013] In some embodiments, the first electrode is located within the gap between at least two adjacent epitaxial structures in the plurality of epitaxial structures. The first electrode includes at least one first portion extending along a first direction and at least one second portion extending along a second direction.

[0014] In some embodiments, the first electrode is disposed around the plurality of epitaxial structures.

[0015] In some embodiments, the size of the gap between any two adjacent epitaxial structures in the plurality of epitaxial structures ranges from 0.01 μm to 100 μm.

[0016] In some embodiments, the light-emitting diode chip further includes: at least one first conductive pin; the conductive pin is located on the side of the first electrode away from the first semiconductor layer and is electrically connected to the first electrode; and a plurality of second conductive pins; each second conductive pin is electrically connected to the second electrode.

[0017] In some embodiments, the light-emitting diode chip further includes an ohmic contact layer disposed between the second semiconductor pattern and a second electrode electrically connected thereto.

[0018] In some embodiments, the ohmic contact layer is a light-transmitting ohmic contact layer or a reflective ohmic contact layer.

[0019] On the other hand, a method for fabricating a light-emitting diode (LED) chip is provided. The method includes: providing a substrate; forming a plurality of epitaxial structures on one side of the substrate; a gap being present between any two adjacent epitaxial structures; each epitaxial structure comprising: a first semiconductor pattern, a light-emitting pattern, and a second semiconductor pattern sequentially stacked; the first semiconductor patterns of at least two of the plurality of epitaxial structures being interconnected to form a first semiconductor layer; forming at least one first electrode; the first electrode being electrically connected to the first semiconductor layer; and forming a plurality of second electrodes; each second electrode being electrically connected to the second semiconductor pattern of at least one of the plurality of epitaxial structures.

[0020] On the other hand, a display device is provided. The display device includes: a driving backplane; and a plurality of light-emitting diode (LED) chips as described in any of the above embodiments. The driving backplane includes a plurality of connection pads, the plurality of connection pads including a plurality of first pads and a plurality of second pads. Each first electrode of the plurality of LED chips is electrically connected to a first pad, and each second electrode of the plurality of LED chips is electrically connected to a second pad. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a structural diagram of a light-emitting diode chip according to some embodiments of the present disclosure;

[0023] Figure 2 This is a structural diagram of another light-emitting diode chip according to some embodiments of the present disclosure;

[0024] Figure 3 This is a structural diagram of another light-emitting diode chip according to some embodiments of the present disclosure;

[0025] Figure 4 for Figure 3 A cross-sectional view of the light-emitting diode chip shown along the DD' direction;

[0026] Figure 5 for Figure 3 Another cross-sectional view of the LED chip shown along the DD' direction;

[0027] Figure 6 This is a structural diagram of another light-emitting diode chip according to some embodiments of the present disclosure;

[0028] Figure 7 for Figure 6 A cross-sectional view of the light-emitting diode chip shown along the EE' direction;

[0029] Figure 8 This is a structural diagram of another light-emitting diode chip according to some embodiments of the present disclosure;

[0030] Figure 9 This is a structural diagram of another light-emitting diode chip according to some embodiments of the present disclosure;

[0031] Figure 10 for Figure 9 A cross-sectional view of the light-emitting diode chip shown along the FF' direction;

[0032] Figure 11 for Figure 9 Another cross-sectional view of the light-emitting diode chip shown along the FF' direction;

[0033] Figure 12 for Figure 9 A cross-sectional view of the light-emitting diode chip shown along the GG' direction;

[0034] Figures 13(a) to 13(g) This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to some embodiments of the present disclosure;

[0035] Figures 14(a) to 14(g) This is a flowchart illustrating another method for fabricating a light-emitting diode chip according to some embodiments of the present disclosure;

[0036] Figures 15(a) to 15(i) This is a flowchart illustrating another method for fabricating a light-emitting diode chip according to some embodiments of the present disclosure;

[0037] Figures 16(a) to 16(g) This is a flowchart illustrating another method for fabricating a light-emitting diode chip according to some embodiments of the present disclosure;

[0038] Figure 17 This is a structural diagram of a display device according to some embodiments of the present disclosure. Detailed Implementation

[0039] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0040] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0041] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0042] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0043] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0044] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0045] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0046] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0047] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0048] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] In related technologies, LED display devices may include a display backplane and a plurality of LEDs electrically connected to the display backplane. These LEDs are typically transferred to the display backplane using mass transfer technology. However, due to the inherent limitations of mass transfer technology, the transfer efficiency and yield of the LEDs are relatively low.

[0051] Based on this, such as Figures 1-12As shown, some embodiments of this disclosure provide a light-emitting diode (LED) chip 100. The LED chip 100 may include, for example, a miniature light-emitting diode (MiniLED) chip or a micro light-emitting diode (Micro LED) chip.

[0052] In some embodiments, such as Figures 4-5 , Figure 7 and Figures 10-12 As shown, the LED chip 100 may include: multiple epitaxial structures 1.

[0053] In some examples, such as Figures 4-5 , Figure 7 and Figures 10-12 As shown, each epitaxial structure 1 may include a first semiconductor pattern 11, a light-emitting pattern 12, and a second semiconductor pattern 13 stacked sequentially. The first semiconductor pattern 11 and the light-emitting pattern 12 may be in direct contact, for example, and the light-emitting pattern 12 and the second semiconductor pattern 13 may be in direct contact, for example.

[0054] For example, the light-emitting pattern 12 can be a multiple quantum well (MQW) layer. The material of the light-emitting pattern 12 can be, for example, gallium nitride (GaN).

[0055] For example, the material of the first semiconductor pattern 11 can be a P-type semiconductor material, and correspondingly, the material of the second semiconductor pattern 13 can be an N-type semiconductor material. Alternatively, the material of the first semiconductor pattern 11 can be an N-type semiconductor material, and correspondingly, the material of the second semiconductor pattern 13 can be a P-type semiconductor material.

[0056] The materials of the first semiconductor pattern 11 and the second semiconductor pattern 13 can include various types and can be selected according to actual needs. For example, the intrinsic semiconductor materials in the first semiconductor pattern 11 and the second semiconductor pattern 13 are the same, and can be any one of GaN, gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), and aluminum gallium indium phosphide (AlGaInP).

[0057] Specifically, when different voltages are applied to the first semiconductor pattern 11 and the second semiconductor pattern 13 to form an electric field between them, if the intrinsic semiconductor materials of the first semiconductor pattern 11 and the second semiconductor pattern 13 are both GaN, the epitaxial structure 1 can emit green or blue light; if the intrinsic semiconductor materials of the first semiconductor pattern 11 and the second semiconductor pattern 13 are both GaP, AlGaAs, or AlGaInP, the epitaxial structure 1 can emit red light.

[0058] It should be noted that when different voltages are applied to the first semiconductor pattern 11 and the second semiconductor pattern 13 to form an electric field between them, that is, when a PN junction with a potential barrier is formed between the first semiconductor pattern 11 and the second semiconductor pattern 13, when minority carriers and majority carriers recombine in the overlapping region along the stacking direction of the first semiconductor pattern 11, the light-emitting pattern 12, and the second semiconductor pattern 13, excess energy is released in the form of light, thereby directly converting electrical energy into light energy. Therefore, the overlapping region along the stacking direction of these three elements is essentially the light-emitting region of the epitaxial structure 1, and the area of ​​the overlapping region along the stacking direction of these three elements is essentially the light-emitting area of ​​the epitaxial structure 1.

[0059] In some examples, such as Figures 4-5 , Figure 7 and Figures 10-12 As shown, there is a gap between any two adjacent epitaxial structures 1 in the above plurality of epitaxial structures 1. This means that each epitaxial structure 1 can have a corresponding light-emitting region. The plurality of epitaxial structures 1 included in the LED chip 100 can make the LED chip 100 have multiple light-emitting regions.

[0060] It should be noted that when the LED chip 100 is applied to an LED display device, one or more light-emitting areas (e.g., two or three) of the LED chip 100 can correspond to one sub-pixel area in the LED display device. This means that one LED chip can correspond to multiple sub-pixel areas in the LED display device. Therefore, during the transfer of the LED chip 100, transferring one LED chip 100 can correspond to multiple sub-pixel areas. Compared to related technologies where each sub-pixel area requires the transfer of a separate LED, this effectively improves transfer efficiency and yield.

[0061] In some examples, such as Figures 1-5 and Figures 7-12 As shown, there are gaps between the second semiconductor patterns 13 belonging to different epitaxial structures 1, and the different second semiconductor patterns 13 are independent of each other. The gap between two adjacent second semiconductor patterns 13 can be, for example, the same as the gap between any two adjacent epitaxial structures 1. This helps to ensure that the multiple light-emitting regions of the multiple epitaxial structures 1 are independent of each other, avoiding light emission crosstalk.

[0062] Considering the manufacturing process of the epitaxial structure 1, the second semiconductor pattern 13 can be formed later than the light-emitting pattern 12 and the first semiconductor pattern 11. By independently arranging the multiple second semiconductor patterns 13 in the multiple epitaxial structures 1, it is beneficial to simplify the manufacturing processes of the epitaxial structure 1 and the LED chip 100.

[0063] In some examples, as Figures 1 to 11 shown, the first semiconductor patterns 11 of at least two of the multiple epitaxial structures 1 are interconnected to form a first semiconductor layer 11a.

[0064] Exemplarily, among the multiple epitaxial structures 1, the first semiconductor patterns 11 of two adjacent epitaxial structures 1 are interconnected to form a first semiconductor layer 11a; or, the first semiconductor patterns 11 of four adjacent epitaxial structures 1 (the four epitaxial structures 1 can be arranged in a "one" shape or a "field" shape along a certain direction, etc.) are interconnected to form a first semiconductor layer 11a; or, multiple first semiconductor patterns 11 belonging to different epitaxial structures 1 are interconnected to form a first semiconductor layer 11a; and so on.

[0065] By interconnecting the first semiconductor patterns 11 of at least two epitaxial structures 1, the number of first semiconductor patterns 11 can be reduced, and the structure of the epitaxial structure 1 can be simplified.

[0066] Exemplarily, the part in the first semiconductor layer 11a for interconnecting at least two first semiconductor patterns 11 can be made of the same material as the first semiconductor pattern 11. As Figures 1-3 、 Figure 6 and Figures 8-9 shown, this part can not only be located in the gap between any two adjacent first semiconductor patterns 11, but also be located beside the area determined by the at least two first semiconductor patterns 11 as a whole.

[0067] For example, the first semiconductor patterns 11 of the at least two epitaxial structures 1 and the part for interconnecting the at least two first semiconductor patterns 11 can be formed using the same thin film in the same patterning process. This is beneficial to simplify the manufacturing process of the LED chip 100.

[0068] Here, there are various ways to set the surface of the first semiconductor layer 11a close to the second semiconductor pattern 13, which can be selected according to actual needs. Of course, this setting method is not limited to the two examples below.

[0069] Exemplarily, as Figure 4As shown, the surface of the first semiconductor layer 11a near the second semiconductor pattern 13 can be, for example, a relatively flat surface. That is, the portion of the first semiconductor layer 11a used to connect at least two first semiconductor patterns 11 near the surface of the second semiconductor pattern 13 can be a relatively flat surface, and the portion of the first semiconductor layer 11a covered by the second semiconductor pattern 13 (i.e., the first semiconductor pattern 11) near the surface of the second semiconductor pattern 13 can be a relatively flat surface.

[0070] For example, such as Figure 12 As shown, the surface of the first semiconductor layer 11a near the second semiconductor pattern 13 can be, for example, an uneven surface. For example, the portion of the first semiconductor layer 11a located in the gap between any two adjacent epitaxial structures 1 (i.e., the portion used to connect at least two first semiconductor patterns 11) near the surface of the second semiconductor pattern 13 can be located in the same plane (e.g., plane M), and the portion of the first semiconductor layer 11a covered by the second semiconductor pattern 13 (i.e., the first semiconductor pattern 11) near the surface of the second semiconductor pattern 13 can be located in the same plane (e.g., plane N). There is a gap between the two planes, and the vertical distance between plane M and the second semiconductor pattern 13 is greater than the vertical distance between plane N and the second semiconductor pattern 13.

[0071] The following is a schematic description of the structure of the LED chip 100, using the example that the first semiconductor pattern 11 can be an N-type semiconductor pattern and the second semiconductor pattern 13 can be a P-type semiconductor pattern.

[0072] In some embodiments, such as Figures 1-12 As shown, the LED chip 100 may include at least one first electrode 2 and a plurality of second electrodes 3. Each first electrode 2 may be electrically connected to a first semiconductor layer 11a, and each second electrode 3 may be electrically connected to a second semiconductor pattern 13 in at least one epitaxial structure 1. Each first electrode 2 and the first semiconductor layer 11a electrically connected thereto may be in direct contact, and each second electrode 3 and the second semiconductor pattern 13 in the at least one epitaxial structure 1 electrically connected thereto may be in direct contact.

[0073] In this case, the first electrode 2 can be called the N electrode, through which electrons can be injected into the first semiconductor layer 11a and the light-emitting pattern 12. The second electrode 3 can be called the P electrode, through which holes can be injected into the corresponding second semiconductor pattern 13 and the light-emitting pattern 12. The electrons and holes can recombine to emit light in the light-emitting pattern 12.

[0074] In some examples, such as Figures 1-3 and Figures 8-9As shown, the orthographic projection of the first electrode 2 onto the first plane is located within the orthographic projection range of the first semiconductor layer 11a, which is electrically connected to the first electrode 2, onto the first plane, and does not overlap with the orthographic projections of the plurality of epitaxial structures 1 onto the first plane. The first plane can be a plane parallel to the first semiconductor layer 11a.

[0075] For example, the orthographic projection of the first electrode 2 onto the first plane is located within the orthographic projection range of the first semiconductor layer 11a (hereinafter referred to as the first semiconductor layer 11a) electrically connected to the first electrode 2 on the first plane. This may include, for example, that: the orthographic projection area of ​​the first electrode 2 on the first plane is smaller than the orthographic projection area of ​​the first semiconductor layer 11a on the first plane; the orthographic projection boundary of the first electrode 2 on the first plane and the orthographic projection boundary of the first semiconductor layer 11a on the first plane do not intersect; and the distance between the orthographic projection boundary of the first electrode 2 on the first plane and the orthographic projection boundary of the first semiconductor layer 11a on the first plane is greater than 0 (e.g., ...). Figure 2 (As shown), or, a portion of the orthographic projection boundary of the first electrode 2 on the first plane may coincide with a portion of the orthographic projection boundary of the first semiconductor layer 11a on the first plane, and the spacing between the other portion of the orthographic projection boundary of the first electrode 2 on the first plane and the other portion of the orthographic projection boundary of the first semiconductor layer 11a on the first plane is greater than 0, (as shown) Figure 1 (As shown). Of course, exemplarily, in cases such as Figure 1 Based on the above, misalignment may occur between the first electrode 2 and the first semiconductor layer 11a. That is, the orthographic projection boundary of the first electrode 2 on the first plane and the orthographic projection boundary of the first semiconductor layer 11a on the first plane may partially overlap. For example, a portion of the orthographic projection of the first electrode 2 on the first plane may exceed the orthographic projection range of the first semiconductor layer 11a on the first plane.

[0076] By setting the positional relationship between the orthographic projection of the first electrode 2 on the first plane, the orthographic projection of the first semiconductor layer 11a electrically connected to the first electrode 2 on the first plane, and the orthographic projection of the multiple epitaxial structures 1 on the first plane, the situation where the first electrode 2 directly contacts the light-emitting pattern 12 or the second semiconductor pattern 13 can be avoided. Moreover, when the LED chip 100 includes multiple first semiconductor layers 11a (for example, a portion of the first semiconductor patterns 11 of the epitaxial structures 1 in the LED chip 100 are interconnected to form a first semiconductor layer 11a, and another portion of the first semiconductor patterns 11 of the epitaxial structures 1 are interconnected to form a first semiconductor layer 11a), the situation where signal crosstalk occurs between different first semiconductor layers 11a can be avoided.

[0077] In some examples, the number of first electrodes 2 can be determined based on the number of first semiconductor layers 11a. That is, the number of first electrodes 2 can be the same as the number of first semiconductor layers 11a.

[0078] Based on this, at least two epitaxial structures 1 corresponding to the first semiconductor layer 11a can share a single first electrode 2. Thus, when electrons are injected into the first conductor layer 11a and the light-emitting pattern 12 of the at least two epitaxial structures 1 through the first electrode 2, the amount of electrons injected into the at least two epitaxial structures 1 can be the same or approximately the same, thereby reducing the current difference between the at least two epitaxial structures 1 and improving the current uniformity of the at least two epitaxial structures 1. Furthermore, the number of first electrodes 2 can be reduced, allowing for a greater number of epitaxial structures 1 to be disposed on a single LED chip 100, simplifying the structure of the LED chip 100.

[0079] For example, multiple first semiconductor patterns 11 belonging to different epitaxial structures 1 are interconnected to form a first semiconductor layer 11a. In this case, the number of first semiconductor layers 11a is one, and the number of first electrodes 2 electrically connected to the first semiconductor layer 11a can be one. This allows the amount of electrons injected into all epitaxial structures 1 to be the same or approximately the same, which is beneficial to further improve the current uniformity of different epitaxial structures 1. This allows more epitaxial structures 1 to be set on a single LED chip 100, further simplifying the structure of the LED chip 100.

[0080] In some examples, such as Figures 1-12 As shown, each second electrode 3 can be electrically connected to a second semiconductor pattern 13 in one epitaxial structure 1, or to multiple (e.g., two or three) second semiconductor patterns 13 in epitaxial structures 1.

[0081] For example, when each second electrode 3 is electrically connected to a second semiconductor pattern 13 of an epitaxial structure 1, the number of second electrodes 3 can be equal to the number of epitaxial structures 1. In this case, the second electrodes 3 can be used to achieve independent control of the light emission state of each epitaxial structure 1.

[0082] For example, when each second electrode 3 is electrically connected to the second semiconductor pattern 13 of a plurality of epitaxial structures 1, the number of second electrodes 3 is greater than or equal to two, and less than the number of epitaxial structures 1. In this case, the light emission state of the epitaxial structure 1 electrically connected to it can be independently controlled using each second electrode 3.

[0083] In some examples, such as Figures 1-12As shown, the orthographic projection of each second electrode 3 on the first plane and the orthographic projection of the second semiconductor pattern 13 of at least one epitaxial structure 1 electrically connected to the second electrode 3 on the first plane at least partially overlap.

[0084] Here, taking the electrical connection of each second electrode 3 with an epitaxial structure 1 and a second semiconductor pattern 13 in the epitaxial structure 1 as an example, exemplarily, the orthographic projection of the second electrode 3 on the first plane and the orthographic projection of the second semiconductor pattern 13 electrically connected to the second electrode 3 (hereinafter referred to as the second semiconductor pattern 13) on the first plane at least partially overlap, for example, including: Figure 2 and Figure 3 As shown, a portion of the orthographic projection of the second electrode 3 onto the first plane overlaps with a portion of the orthographic projection of the second semiconductor pattern 13 onto the first plane, while another portion of the orthographic projection of the second electrode 3 onto the first plane does not overlap with another portion of the orthographic projection of the second semiconductor pattern 13 onto the first plane; or, as... Figure 6 As shown, the orthographic projection of the second electrode 3 onto the first plane coincides with the orthographic projection of the second semiconductor pattern 13 onto the first plane; or, as... Figure 8 and Figure 9 As shown, the orthographic projection of the second electrode 3 on the first plane is located within the orthographic projection range of the second semiconductor pattern 13 on the first plane.

[0085] By setting the positional relationship between the orthographic projection of each second electrode 3 on the first plane and the orthographic projection of the second semiconductor pattern 13 of at least one epitaxial structure 1 electrically connected to the second electrode 3 on the first plane, it can be ensured that each second electrode 3 and the second semiconductor pattern 13 of at least one epitaxial structure 1 electrically connected to the second electrode 3 can have a large electrical connection area, ensuring good electrical connection between the two.

[0086] The LED chip 100 provided in some embodiments of this disclosure, by setting multiple epitaxial structures 1 and ensuring that there is a gap between any two adjacent epitaxial structures 1, can have multiple independently controllable light-emitting regions spaced apart. When the LED chip 100 is applied to an LED display device, one or more light-emitting regions of the LED chip 100 can correspond to a sub-pixel region in the LED display device; that is, one LED chip 100 can correspond to multiple sub-pixel regions in the LED display device. Thus, during the transfer of the LED chip 100, transferring one LED chip 100 can correspond to multiple sub-pixel regions. Compared to related technologies where each sub-pixel region requires the transfer of a separate LED, this effectively improves transfer efficiency and yield.

[0087] Furthermore, by interconnecting the first semiconductor patterns 11 of at least two of the multiple epitaxial structures 1 to form a first semiconductor layer 11a, and electrically connecting each first electrode 2 to a first semiconductor layer 11a, the current uniformity of different epitaxial structures 1 can be effectively improved, and the structure of the LED chip 100 can be simplified.

[0088] It should be noted that the arrangement of the multiple epitaxial structures 1 in the LED chip 100 and the setting of the first electrode 2 and the second electrode 3 are related to the shape of the epitaxial structure 1, and can be selected and set according to actual needs.

[0089] In some embodiments, such as Figure 2 and Figure 3 As shown, the plurality of extensional structures 1 are spaced apart along the first direction X, and each extensional structure 1 extends along the second direction Y, wherein the first direction X and the second direction Y intersect each other. This means that the orthographic projection shape of the plurality of extensional structures 1 on the first plane can be, for example, a quadrilateral or a strip, and the dimension of each extensional structure 1 in the second direction Y is greater than or much greater than its dimension in the first direction X.

[0090] For example, such as Figure 2 and Figure 3 As shown, the above-mentioned multiple extensional structures 1 can be arranged in parallel to each other and arranged in one or more rows along the first direction X.

[0091] Here, the angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 89° or 90°, etc.

[0092] By arranging multiple epitaxial structures 1 in the above manner, the limited area of ​​the LED chip 100 can be effectively utilized. Within this limited area, a greater number of epitaxial structures 1 can be arranged, enabling the LED chip 100 to have more light-emitting areas. Thus, when the LED chip 100 is applied to an LED display device, it can correspond to more sub-pixel areas. During the transfer process of the LED chip 100, transferring one LED chip 100 can correspond to multiple sub-pixel areas. Compared to related technologies where each sub-pixel area requires the transfer of a separate LED, this effectively improves transfer efficiency and yield.

[0093] For example, such as Figure 2 and Figure 3 As shown, along the first direction X, the spacing between any two adjacent extensional structures 1 is equal or approximately equal. That is, multiple extensional structures 1 can be arranged at equal intervals.

[0094] This improves the uniformity of the distribution of multiple epitaxial structures 1 in the LED chip 100, and also improves the uniformity of the distribution of multiple light-emitting regions. Furthermore, it facilitates the placement of more epitaxial structures 1 within the limited area of ​​the LED chip 100, thereby further improving transfer efficiency and yield.

[0095] Based on this, in some examples, such as Figure 2 and Figure 3 As shown, the plurality of second semiconductor patterns 13 in the aforementioned plurality of epitaxial structures 1 can be spaced apart along the first direction X, and each second semiconductor pattern 13 extends along the second direction Y. That is, the orthographic projection shape of each second semiconductor pattern 13 on the first plane can be a quadrilateral or a strip, and the size of each second semiconductor pattern 13 in the second direction Y is greater than or much greater than its size in the first direction X.

[0096] For example, the orthographic projection shape of each second semiconductor pattern 13 on the first plane may be the same as or approximately the same as the orthographic projection shape of its corresponding epitaxial structure 1 on the first plane.

[0097] For example, if the orthographic projection shape of the epitaxial structure 1 on the first plane is a quadrilateral, the orthographic projection shape of the second semiconductor pattern 13 in the epitaxial structure 1 on the first plane can also be a quadrilateral. If the orthographic projection shape of the epitaxial structure 1 on the first plane is a stripe, the orthographic projection shape of the second semiconductor pattern 13 in the epitaxial structure 1 on the first plane can also be a stripe.

[0098] For example, the size of the orthographic projection of each second semiconductor pattern 13 onto the first plane may be equal to or approximately equal to the size of the orthographic projection of its corresponding epitaxial structure 1 onto the first plane.

[0099] Here, the same or approximately the same size of the two projections can mean that, based on the fact that the orthographic projection of the second semiconductor pattern 13 on the first plane and the orthographic projection of its corresponding epitaxial structure 1 on the first plane are the same or approximately the same shape, the orthographic projection of the second semiconductor pattern 13 on the first plane is located within the orthographic projection range of the light-emitting pattern 12 or the first semiconductor pattern 11 on the first plane, or the orthographic projection of the second semiconductor pattern 13 on the first plane coincides with or approximately coincides with the orthographic projection of the light-emitting pattern 12 or the first semiconductor pattern 11 on the first plane.

[0100] By defining the shape and size of each second semiconductor pattern 13, the orthographic projection of the second semiconductor pattern 13 onto the first plane can have a large area, thereby enabling a large facing area between the second semiconductor pattern 13 and the light-emitting pattern 12 and the first semiconductor pattern 11 in the same epitaxial structure 1. This helps to further ensure that the light-emitting region of each epitaxial structure 1 has a large area.

[0101] In some examples, the multiple light-emitting patterns 12 in the aforementioned multiple extensional structures 1 can have multiple configurations.

[0102] For example, the plurality of light-emitting patterns 12 in the plurality of extensional structures 1 are arranged independently at intervals. In this case, the plurality of light-emitting patterns 12 can be arranged at intervals along the first direction X, and each light-emitting pattern 12 can extend along the second direction Y. That is, the orthographic projection shape of each light-emitting pattern 12 on the first plane can be a quadrilateral or a strip, and the size of each light-emitting pattern 12 in the second direction Y is greater than or much greater than its size in the first direction X.

[0103] Here, the orthographic projection shape of each light-emitting pattern 12 on the first plane may be the same as or approximately the same as the orthographic projection shape of the second semiconductor pattern 13 of its corresponding epitaxial structure 1 on the first plane. For an example of the two being the same or approximately the same, refer to the schematic illustration of the orthographic projection of the second semiconductor pattern 13 and the epitaxial structure 1 on the first plane.

[0104] The light-emitting pattern 12 in this disclosure adopts the above-described arrangement, which helps to ensure that the light-emitting pattern 12, the second semiconductor pattern 13, and the first semiconductor pattern 11 in each epitaxial structure 1 have a large facing area, thereby ensuring that the light-emitting area of ​​each epitaxial structure 1 has a large area.

[0105] For example, such as Figures 4-5 As shown, the light-emitting patterns 12 of at least two of the plurality of epitaxial structures 1 are interconnected to form a light-emitting layer 12a. The epitaxial structure 1 to which the light-emitting layer 12a belongs may, for example, be the same as the epitaxial structure 1 to which the first semiconductor layer 11a belongs.

[0106] Here, the portion of the light-emitting layer 12a used to connect the at least two light-emitting patterns 12 may, for example, be located in the gap between the at least two epitaxial structures 1, and the material of the portion of the light-emitting layer 12a used to connect the at least two light-emitting patterns 12 may, for example, be the same as the material of the light-emitting patterns 12.

[0107] In this way, during the fabrication of the light-emitting layer 12a, the same thin film can be used to form the aforementioned multiple light-emitting patterns 12 and the portion used to connect the multiple light-emitting patterns 12 in the same patterning process to obtain the light-emitting layer 12a. This eliminates the need to pattern the portion of the thin film located between two adjacent epitaxial structures 1. This not only simplifies the fabrication process of the LED chip 100 but also avoids adverse effects on the material properties (or crystal quality) of the edge portions of the light-emitting patterns 12 caused by the patterning process, ensuring that each epitaxial structure 1 and the LED chip 100 including multiple epitaxial structures 1 have good light-emitting performance.

[0108] Here, when the light-emitting patterns 12 of at least two of the multiple epitaxial structures 1 are interconnected to form a light-emitting layer 12a, and the first semiconductor patterns 11 of the at least two epitaxial structures 1 are interconnected to form a first semiconductor layer 11a, the projected area of ​​the light-emitting layer 12a on the first plane is smaller than the projected area of ​​the first semiconductor layer 11a on the first plane. The light-emitting layer 12a does not completely cover the first semiconductor layer 11a and exposes a part of the surface of the first semiconductor layer 11a. This leaves space for the first electrode 2, which facilitates the electrical connection between the first semiconductor layer 11a and the first electrode 2.

[0109] In some examples, such as Figure 2 and Figure 3 As shown, the first electrode 2 can be arranged around the above-mentioned multiple epitaxial structures 1.

[0110] Here, "surrounding" means that the first electrode 2 can be located on one side, two sides, three sides, or around the region defined by the plurality of epitaxial structures 1 as a whole.

[0111] For example, when the first semiconductor patterns 11 of a portion of the aforementioned plurality of epitaxial structures 1 are interconnected to form a first semiconductor layer 11a, the LED chip 100 may include a plurality of first electrodes 2. These plurality of first electrodes 2 may be located on one side (e.g., the orthographic projection of the first electrode 2 on the first plane can be strip-shaped), both sides (e.g., the orthographic projection of the first electrode 2 on the first plane can be polygonal), three sides (e.g., the orthographic projection of the first electrode 2 on the first plane can be polygonal), or the periphery of the region defined by the plurality of epitaxial structures 1 as a whole, and the orthographic projection of each first electrode 2 on the first plane is located within the orthographic projection range of the first semiconductor layer 11a electrically connected to it on the first plane. When the plurality of first electrodes 2 are located on the periphery of the region defined by the plurality of epitaxial structures 1 as a whole, there are gaps between the plurality of first electrodes 2, and no connection is formed.

[0112] For example, when multiple first semiconductor patterns 11 in the aforementioned multiple epitaxial structures 1 are interconnected to form a first semiconductor layer 11a, the LED chip 100 may include only one first electrode 2. The first electrode 2 may be located on one side, two sides, three sides, or the periphery of the region defined by the multiple epitaxial structures 1 as a whole. Wherein, when the first electrode 2 is located on the periphery of the region defined by the multiple epitaxial structures 1 as a whole, the first electrode 2 may be ring-shaped, forming a closed pattern; or, the first electrode 2 may not be connected end-to-end, thus not forming a closed pattern.

[0113] In some examples, such as Figure 2 and Figure 3 As shown, the second electrode 3, which is electrically connected to the second semiconductor pattern 13, may be arranged at intervals along the first direction X.

[0114] For example, when the second electrode 3 is electrically connected to the second semiconductor pattern 13 in a one-to-one correspondence, each second electrode 3 may also extend along the second direction Y. In this case, the shape of the orthographic projection of the second electrode 3 on the first plane may also be a quadrilateral or a strip, and the size of each second electrode 3 in the second direction Y is greater than or much greater than its size in the first direction X.

[0115] For example, when the second electrode 3 is electrically connected to a plurality of second semiconductor patterns 13, the orthographic projection shape of the second electrode 3 on the first plane can be the same as the graphic shape formed by connecting the orthographic projections of the plurality of second electrodes 3 on the first plane in the example above.

[0116] In this example, such as Figure 2 and Figure 3 As shown, the orthographic projection of the second semiconductor pattern 13 onto the first plane and the orthographic projection of the second electrode 3 electrically connected to the second semiconductor pattern 13 onto the first plane may, for example, at least partially overlap.

[0117] For example, the orthographic projection of the second semiconductor pattern 13 onto the first plane and the orthographic projection of the second electrode 3 electrically connected to the second semiconductor pattern 13 onto the first plane may partially overlap.

[0118] For example, the orthographic projection of the second semiconductor pattern 13 onto the first plane can be located within the orthographic projection range of the second electrode 3, which is electrically connected to the second semiconductor pattern 13, onto the first plane.

[0119] This helps to ensure a large contact area between the second semiconductor pattern 13 and the second electrode 3 electrically connected to the second semiconductor pattern 13, thereby ensuring good electrical contact between the two and improving the electrical performance of the LED chip 100.

[0120] In other embodiments, such as Figure 1 , Figure 6 and Figures 8-9 As shown, the aforementioned multiple epitaxial structures 1 are arranged in an array. That is, the multiple epitaxial structures 1 can be arranged into multiple rows of epitaxial structures 1 along the first direction X, and into multiple columns of epitaxial structures 1 along the second direction Y. Each row of epitaxial structures 1 may include multiple epitaxial structures 1 that are spaced apart from each other, and each column of epitaxial structures 1 may include multiple epitaxial structures 1 that are spaced apart from each other.

[0121] Regarding the first direction X and the second direction Y, please refer to the illustrative descriptions in some of the above embodiments, which will not be repeated here.

[0122] For example, multiple extensional structures 1 can be arranged in four rows along the first direction X and in four columns along the second direction Y; or, multiple row extensional structures 1 can be arranged in five rows along the first direction X and in seven columns along the second direction Y.

[0123] In this case, the difference between the dimensions in the first direction X and the dimensions in the second direction Y in the orthographic projection of each two adjacent extensional structures 1 on the first plane is small or negligible.

[0124] For example, such as Figure 1 , Figure 6 and Figures 8-9 As shown, the shape of the orthographic projection of the above-mentioned plurality of extensional structures 1 onto the first plane may include at least one of polygons (e.g., triangles, rectangles, or hexagons), circles, and ellipses.

[0125] By arranging multiple epitaxial structures 1 in the above manner, a greater number of epitaxial structures 1 can be set within the limited area of ​​the LED chip 100, enabling the LED chip 100 to have more light-emitting areas. Thus, when the LED chip 100 is applied to an LED display device, it can correspond to more sub-pixel regions. During the transfer process of the LED chip 100, transferring one LED chip 100 can correspond to multiple sub-pixel regions. Compared to related technologies where each sub-pixel region requires the transfer of a separate LED, this further improves transfer efficiency and yield.

[0126] For example, the shapes of the above-mentioned plurality of extensional structures 1 projected onto the first plane may be the same or approximately the same (e.g., all are rectangles or all are circles, etc.), and the spacing between any two adjacent extensional structures 1 is equal or approximately equal. That is, the above-mentioned plurality of extensional structures 1 are arranged at equal intervals.

[0127] This improves the uniformity of the distribution of multiple epitaxial structures 1 in the LED chip 100, and also improves the uniformity of the distribution of multiple light-emitting regions. Furthermore, it facilitates the placement of more epitaxial structures 1 within the limited area of ​​the LED chip 100, thereby further improving transfer efficiency and yield.

[0128] For example, the dimensions of the orthographic projections of the plurality of extensional structures 1 onto the first plane are equal or approximately equal. This is beneficial in making the areas of the light-emitting regions of each light-emitting structure 1 equal or approximately equal.

[0129] Based on this, in some examples, such as Figure 1 , Figure 6 and Figures 8-9 As shown, the multiple second semiconductor patterns 13 in the above-mentioned multiple epitaxial structures 1 can be arranged in an array.

[0130] For example, the orthographic projection shape of each second semiconductor pattern 13 on the first plane may be the same as or approximately the same as the orthographic projection shape of its corresponding epitaxial structure 1 on the first plane.

[0131] For example, if the orthographic projection of the epitaxial structure 1 on the first plane is circular (or square), the orthographic projection shape of the second semiconductor pattern 13 in the epitaxial structure 1 on the first plane can also be circular (or square).

[0132] For example, the size of the orthographic projection of each second semiconductor pattern 13 onto the first plane may be equal to or approximately equal to the size of the orthographic projection of its corresponding epitaxial structure 1 onto the first plane.

[0133] Here, the same or approximately the same size of the two projections can mean that, based on the fact that the orthographic projection of the second semiconductor pattern 13 on the first plane and the orthographic projection of its corresponding epitaxial structure 1 on the first plane are the same or approximately the same shape, the orthographic projection of the second semiconductor pattern 13 on the first plane is located within the orthographic projection range of the light-emitting pattern 12 or the first semiconductor pattern 11 on the first plane, or the orthographic projection of the second semiconductor pattern 13 on the first plane coincides with or approximately coincides with the orthographic projection of the light-emitting pattern 12 or the first semiconductor pattern 11 on the first plane.

[0134] By defining the shape and size of each second semiconductor pattern 13, the orthographic projection of the second semiconductor pattern 13 onto the first plane can have a large area, thereby enabling a large facing area between the second semiconductor pattern 13 and the light-emitting pattern 12 and the first semiconductor pattern 11 in the same epitaxial structure 1. This helps to further ensure that the light-emitting region of each epitaxial structure 1 has a large area.

[0135] In some examples, the multiple light-emitting patterns 12 in the above-mentioned multiple extensional structures 1 can have multiple configurations.

[0136] For example, such as Figure 12 As shown, the multiple light-emitting patterns 12 in the aforementioned multiple extensional structures 1 are arranged independently at intervals. At this time, the multiple light-emitting patterns 12 can be arranged in an array. The orthographic projection shape of each light-emitting pattern 12 on the first plane can be a polygon, a circle, or an ellipse, etc., and the difference between the size of each light-emitting pattern 12 in the first direction X and the size in the second direction Y is small or negligible.

[0137] Here, the orthographic projection shape of each light-emitting pattern 12 on the first plane may be the same as or approximately the same as the orthographic projection shape of the second semiconductor pattern 13 of its corresponding epitaxial structure 1 on the first plane. For an example of the two being the same or approximately the same, refer to the schematic illustration of the relationship between the orthographic projections of the second semiconductor pattern 13 and the epitaxial structure 1 on the first plane.

[0138] The light-emitting pattern 12 in this disclosure adopts the above-described arrangement, which helps to ensure that each light-emitting pattern 12 and the second semiconductor pattern 13 have a large facing area, thereby ensuring that the light-emitting area of ​​each epitaxial structure 1 has a large area.

[0139] For example, such as Figure 7 and Figure 11 As shown, the light-emitting patterns 12 of at least two of the plurality of epitaxial structures 1 are interconnected to form a light-emitting layer 12a. The epitaxial structure 1 to which the light-emitting layer 12a belongs may, for example, be the same as the epitaxial structure 1 to which the first semiconductor layer 11a belongs.

[0140] Here, the portion of the light-emitting layer 12a used to connect the at least two light-emitting patterns 12 may, for example, be located in the gap between the at least two epitaxial structures 1, and the material of the portion of the light-emitting layer 12a used to connect the at least two light-emitting patterns 12 may, for example, be the same as the material of the light-emitting patterns 12.

[0141] In this way, during the fabrication of the light-emitting layer 12a, the same thin film can be used to form the aforementioned multiple light-emitting patterns 12 and the portion used to connect the multiple light-emitting patterns 12 in the same patterning process to obtain the light-emitting layer 12a, omitting the patterning of the portion of the thin film located between two adjacent epitaxial structures 1. This not only simplifies the fabrication process of the LED chip 100, but also avoids adverse effects on the material properties (or crystal quality in the material) of the edge portion of the light-emitting pattern 12 due to the patterning process, ensuring that each epitaxial structure 1 and the LED chip 100 including multiple epitaxial structures 1 have good light-emitting performance.

[0142] Here, when the light-emitting patterns 12 of at least two of the multiple epitaxial structures 1 are interconnected to form a light-emitting layer 12a, and the first semiconductor patterns 11 of the at least two epitaxial structures 1 are interconnected to form a first semiconductor layer 11a, the projected area of ​​the light-emitting layer 12a on the first plane is smaller than the projected area of ​​the first semiconductor layer 11a on the first plane. The light-emitting layer 12a does not completely cover the first semiconductor layer 11a and exposes a part of the surface of the first semiconductor layer 11a. This leaves space for the placement of the first electrode 2, which facilitates the formation of an electrical connection between the first semiconductor layer 11a and the first electrode 2.

[0143] Here, the first electrode 2 can be configured in multiple ways, which are related to the configuration of the light-emitting pattern 12. The specific configuration can be selected according to actual needs.

[0144] In some examples, where the light-emitting patterns 12 of at least two of the multiple epitaxial structures 1 are interconnected to form a light-emitting layer 12a, the first electrode 2 may be disposed around the multiple epitaxial structures 1.

[0145] For example, the positional relationship between the first electrode 2 and the plurality of epitaxial structures 1 can be referred to the illustrative description of "surrounding" in some of the above embodiments, which will not be repeated here.

[0146] In other examples, such as Figure 8 and Figure 9 As shown, when the light-emitting patterns 12 of at least two of the plurality of epitaxial structures 1 are arranged independently at intervals, the first electrode 2 may be located in the gap between at least two adjacent epitaxial structures 1 of the plurality of epitaxial structures 1, and the first electrode 2 includes at least one first portion 21 extending along the first direction X and at least one second portion 22 extending along the second direction Y.

[0147] Here, we take the example of multiple first semiconductor patterns 11 in multiple epitaxial structures 1 interconnected to form a first semiconductor layer 11a, so as to more clearly describe the arrangement of the first electrode 2.

[0148] For example, when multiple light-emitting patterns 12 in multiple epitaxial structures 1 are arranged independently at intervals, the multiple light-emitting patterns 12 expose portions of the first semiconductor layer 11a located in the gaps between each pair of adjacent epitaxial structures 1. Furthermore, the multiple light-emitting patterns 12 also expose portions of the first semiconductor layer 11a located around and surrounding the multiple epitaxial structures 1.

[0149] At this time, as Figure 8 and Figure 9As shown, the first electrode 2 may include a plurality of first portions 21 and at least one (e.g., one or more) second portions 22. Each first portion 21 of the first electrode 2 may, for example, be located within the gap between any two adjacent rows of epitaxial structures 1 arranged along the first direction X, and extend beyond the region defined by those adjacent rows of epitaxial structures 1. The second portions 22 of the first electrode 2 may connect the ends of the first portions 21 of the plurality of first electrodes 2 extending beyond the region defined by those arbitrary rows of epitaxial structures 1, such that the orthographic projection shape of the first electrode 2 on the first plane can be comb-shaped. This is beneficial for improving the current uniformity of each epitaxial structure 1 in the LED chip 100.

[0150] Of course, while the first electrode 2 includes multiple first portions 21 and multiple second portions 22, the first electrode 2 can also surround multiple epitaxial structures 1. For example, two of the multiple first portions 21 can be located on opposite sides of the region defined by the entire region of the multiple epitaxial structures 1, and the remaining first portions 21 can be located between two adjacent rows of epitaxial structures 1; the number of second portions 22 can be two, and these two second portions 22 can be located on opposite sides of the region defined by the entire region of the multiple epitaxial structures 1; wherein, the two first portions 21 and the two second portions 22 can be connected end to end to surround the multiple epitaxial structures 1. When the number of second portions 22 is greater than two, the second portions 22 other than the two mentioned above can be located between any two adjacent columns of epitaxial structures 1. This is beneficial for further improving the current uniformity of each epitaxial structure 1 in the LED chip 100.

[0151] In some examples, such as Figure 1 , Figure 6 and Figures 8-9 As shown, the second electrodes 3, which are electrically connected to the second semiconductor pattern 13, can be arranged in an array, for example.

[0152] For example, when the second electrode 3 is electrically connected to the second semiconductor pattern 13 in a one-to-one correspondence, the shape of the orthographic projection of each second electrode 3 on the first plane can be the same as or approximately the same as the orthographic projection shape of the second semiconductor pattern 12 electrically connected to it on the first plane.

[0153] For example, when the second electrode 3 is electrically connected to a plurality of second semiconductor patterns 13, the orthographic projection shape of the second electrode 3 on the first plane can be the same as the graphic shape formed by connecting the orthographic projections of the plurality of second electrodes 3 on the first plane in the example above.

[0154] In this example, the orthographic projection of the second semiconductor pattern 13 onto the first plane and the orthographic projection of the second electrode 3 electrically connected to the second semiconductor pattern 13 onto the first plane may, for example, at least partially overlap.

[0155] This helps to ensure a large contact area between the second semiconductor pattern 13 and the second electrode 3 electrically connected to the second semiconductor pattern 13, thereby ensuring good electrical contact between the two and improving the electrical performance of the LED chip 100.

[0156] In some embodiments, the gap between any two adjacent epitaxial structures 1 in the plurality of epitaxial structures 1 included in the LED chip 100 can be determined according to the specific structure of the epitaxial structure 1.

[0157] In some examples, such as Figures 4-5 and Figure 11 As shown, when the multiple light-emitting patterns 12 in the above-mentioned multiple epitaxial structures 1 are interconnected to form a light-emitting layer 12a, the gap between any two adjacent epitaxial structures 1 is the gap between any two adjacent second semiconductor patterns 13 in the epitaxial structures 1.

[0158] Considering the differences in the fabrication processes of epitaxial structures 1 with different projection shapes, the size of the gap between epitaxial structures 1 with different projection shapes will be different.

[0159] For example, such as Figures 4-5 and Figure 11 As shown, when the orthographic projection shape of the epitaxial structure 1 in the LED chip 100 on the first plane is a strip or when the orthographic projection shape of the epitaxial structure 1 in the LED chip 100 on the first plane is a polygon, the fabrication processes of these two types of LED chips 100 (for example, see the illustrative description below) can be the same or approximately the same. In this case, the size range of the gap between any two adjacent epitaxial structures 1 in each type of LED chip 100 can be 0.01 μm to 100 μm.

[0160] For example, the size of the gap between any two adjacent epitaxial structures 1 in each LED chip 100 can be 0.01μm (i.e., 10nm), 0.1μm (i.e., 100nm), 1μm (i.e., 1000nm), 10μm, 50μm or 100μm, etc.

[0161] Here, the dimensions of the LED chip 100 (for example, the dimensions in the first direction X, the dimensions in the second direction Y, or the diagonal dimensions when the overall shape of the LED chip 100 is rectangular) can be selected and set according to actual needs.

[0162] For example, the size of the LED chip 100 can range from 100μm to 500μm. Considering the size of the gap between each pair of adjacent epitaxial structures 1 in the LED chip 100, 50 to 500 epitaxial structures 1 can be included in the LED chip 100.

[0163] It should be noted that in related technologies, after mass transfer technology is used to transfer multiple LEDs onto the display backplane of an LED display device, the limitations of mass transfer technology result in the spacing between any two adjacent LEDs being on the micrometer level (e.g., 80μm to 1000μm). This large spacing can easily limit the LED display device from achieving higher pixel density (Pixels Per Inch, or PPI).

[0164] This disclosure, by setting the size of the gap between any two adjacent epitaxial structures 1 to the aforementioned range (smaller than the spacing between two adjacent LEDs in related technologies), enables the gap size to reach the nanometer scale, resulting in a smaller size between two adjacent light-emitting regions. When the LED chip 100 is applied to an LED display device, more LED chips 100 can be disposed within a limited area, resulting in more epitaxial structures 1 (or light-emitting regions) within that limited area, which is beneficial for achieving a higher PPI display in the LED display device. Furthermore, it also enables applications in 3D displays.

[0165] In this example, such as Figures 3-5 and Figure 11 As shown, an insulating material (the first insulating layer 101 shown in the figure) can be disposed in the gap between any two adjacent epitaxial structures 1. In this way, the insulating material can be used to insulate between any two adjacent epitaxial structures 1, between any two adjacent second electrodes 3, and between the first electrode 2 and the second electrode 3.

[0166] For example, such as Figure 6 and Figure 7 As shown, when the orthographic projection shape of the epitaxial structure 1 in the LED chip 100 on the first plane is circular or elliptical, the size range of the gap between any two adjacent epitaxial structures 1 can be 0.01μm to 10μm.

[0167] For example, the size of the gap between any two adjacent epitaxial structures 1 in each LED chip 100 can be 0.01μm (i.e., 10nm), 0.1μm (i.e., 100nm), 1μm (i.e., 1000nm), 5μm or 10μm, etc.

[0168] Considering the fabrication process of the LED chip 100 (see, for example, the illustrative description below), it is possible to form a smaller gap between any two adjacent epitaxial structures 1. This allows for the application of the LED chip 100 in an LED display device, enabling the presence of more epitaxial structures 1 (or light-emitting areas) within a limited area, and further enabling the LED display device to achieve a higher PPI display.

[0169] In other examples, such as Figure 12 As shown, when the multiple light-emitting patterns 12 in the above-mentioned multiple epitaxial structures 1 are arranged independently at intervals, the gap between any two adjacent epitaxial structures 1 is the gap between any two adjacent light-emitting patterns 12 in the epitaxial structures 1.

[0170] Here, in this example, if the orthographic projection shape of the epitaxial structure 1 on the first plane is the same as that of the epitaxial structure 1 on the first plane in some of the above examples, the epitaxial structure 1 can be fabricated using the same fabrication process as in some of the above examples. The difference between this example and some of the above examples is that in this example, the second semiconductor pattern 13 and the light-emitting pattern 12 can be formed simultaneously in one patterning process, while in some of the above examples, only the second semiconductor pattern 13 can be formed in one patterning process. This allows the size range of the gap between any two adjacent epitaxial structures 1 in this example to be the same as or approximately the same as the size range of the gap between any two adjacent epitaxial structures 1 in some of the above examples.

[0171] For a detailed explanation of the gap between any two adjacent extensional structures 1 in this example, please refer to the illustrative explanations in some of the examples above, which will not be repeated here.

[0172] In some embodiments, such as Figures 1-12 As shown, the LED chip 100 may further include: at least one first conductive pin 4 and a plurality of second conductive pins 5.

[0173] In some examples, such as Figures 1-12 As shown, the at least one first conductive pin 4 is located on the side of the at least one first electrode 2 in the LED chip 100 away from the first semiconductor layer 11a, and is electrically connected to the at least one first electrode 2. The first conductive pin 4 can, for example, be in direct contact with the corresponding first electrode 2.

[0174] For example, the first conductive pin 4 and the first electrode 2 can be configured in a one-to-one correspondence, that is, one first conductive pin 4 can be electrically connected to one first electrode 2. In this way, electrons can be independently transferred from the first conductive pin 4 to the first electrode 2 to which it is electrically connected.

[0175] In some examples, such as Figures 1-12 As shown, each second conductive pin 5 is electrically connected to a second electrode 5. The second conductive pin 5 may, for example, be in direct contact with the corresponding second electrode 3.

[0176] For example, the second conductive pin 5 and the second electrode 3 can be configured in a one-to-one correspondence, that is, one second conductive pin 5 can be electrically connected to one second electrode 3. In this way, holes can be independently transmitted from the second conductive pin 5 to the second electrode 3 to which it is electrically connected.

[0177] For example, the arrangement of the second conductive pin 5 is related to the orthographic projection of the epitaxial structure 1 onto the first plane.

[0178] Here, for example, such as Figures 6-12 As shown, when the orthographic projection shape of the epitaxial structure 1 on the first plane is a polygon, a circle, or an ellipse, the second electrode 3 can serve as the second conductive pin 5. This simplifies the structure of the LED chip 100.

[0179] For example, such as Figures 2-5 As shown, when the orthographic projection of the epitaxial structure 1 onto the first plane is a quadrilateral or a strip, the second conductive pin 5 can be disposed on the same layer as the second electrode 3 and be an integral structure. The orthographic projection of the second conductive pin 5 onto the first plane can overlap with the orthographic projection portion of the first electrode 2 onto the first plane (e.g., Figure 3 As shown), or they can be non-overlapping (as shown). Figure 2 (As shown).

[0180] In this case, multiple second conductive pins 5 can be located at the same end of the region defined by multiple second electrodes 3.

[0181] Of course, a portion of the plurality of second conductive pins 5 can be located at one end of the region defined by the plurality of second electrodes 3, and another portion of the plurality of second conductive pins 5 can be located at the opposite end of the region defined by the plurality of second electrodes 3. The plurality of second conductive pins 5 can, for example, be arranged alternately (e.g., ...). Figure 2 and Figure 3 As shown in the diagram, each pair of adjacent second conductive pins 5 is positioned at opposite ends of the region defined by the corresponding two second electrodes 3. This increases the spacing between adjacent second conductive pins 5. When the LED chip 100 is applied to an LED display device, the transfer accuracy can be effectively reduced.

[0182] It should be noted that the term "same layer" in this article refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, the second conductive pin 5 and the second electrode 3 can be fabricated simultaneously in a single patterning process, which simplifies the fabrication process of the LED chip 100.

[0183] In some embodiments, such as Figure 11 and Figure 12 As shown, the LED chip 100 further includes an ohmic contact layer 6 disposed between each second semiconductor pattern 13 and a second electrode 3 electrically connected thereto (i.e., the second semiconductor pattern 13).

[0184] In some examples, the second semiconductor pattern 13 is disposed in a one-to-one correspondence with the ohmic contact layer 6, and the orthographic projection of the second semiconductor pattern 13 onto the first semiconductor layer 11a coincides with or approximately coincides with the orthographic projection of the corresponding ohmic contact layer 6 onto the first semiconductor layer 11a. This allows the ohmic contact layer 4 to effectively increase the mobility of charge carriers (e.g., holes).

[0185] The materials of the aforementioned ohmic contact layer 6 include a variety of options, which can be selected and set according to actual needs.

[0186] In some examples, the ohmic contact layer 6 can be a light-transmitting ohmic contact layer. In this case, the material of the ohmic contact layer 6 can be, for example, a material with high light transmittance such as indium tin oxide (ITO).

[0187] In other examples, the ohmic contact layer 6 can be a reflective ohmic contact layer. In this case, the material of the ohmic contact layer 6 can be, for example, gold (Au), nickel (Ni), or platinum (Pt). This also allows the ohmic contact layer 6 to reflect the light emitted from the light-emitting pattern 12 and incident on the ohmic contact layer 6, thereby improving the light utilization rate of the LED chip 100.

[0188] In some embodiments, such as Figure 12 As shown, the LED chip 100 also includes a buffer layer 7 disposed on one side of the plurality of epitaxial structures 1. Here, one side of the epitaxial structure 1 refers to the side of the first semiconductor layer 11a away from the second semiconductor pattern 13.

[0189] By setting the buffer layer 7, it is beneficial to ensure that the first semiconductor layer 11a has better crystal quality.

[0190] The material of the buffer layer 7 can include a variety of materials. For example, the material of the buffer layer 7 can be GaN.

[0191] It is worth mentioning that the LED chip 100 has various structural types, which can be selected according to actual needs. For example, the LED chip 100 can be a regular structure, a vertical structure, or a flip-chip structure.

[0192] In some embodiments, such as Figures 1-12 As shown, the first electrode 2 and the plurality of second electrodes 3 can be disposed on the same side of the first semiconductor layer 11a.

[0193] In some examples, "the same side of the first semiconductor layer 11a" means that the first electrode 2 can be disposed on the side of the first semiconductor layer 11a closer to the light-emitting pattern 12, and the second electrode 3 can be disposed on the side of the second semiconductor pattern 13 away from the light-emitting pattern 12.

[0194] Based on this, the LED chip 100 can be referred to as a flip-chip LED chip. In this case, the LED chip 100 can be directly electrically connected to the backplane of the LED display device through the first electrode 2 and the second electrode 3 without the need for additional leads, which helps to simplify the structure of the LED display device using the LED chip 100.

[0195] Some embodiments of this disclosure provide a method for fabricating an LED chip. This fabrication method may include steps S100 to S400.

[0196] S100, providing substrate 8.

[0197] The type of substrate 8 can include various types. For example, the substrate 8 can be a GaP substrate, a GaAs substrate, a silicon substrate, a silicon carbide substrate, or a sapphire substrate.

[0198] It should be noted that the type of substrate 8 can be determined according to the materials of the first semiconductor pattern 11 and the second semiconductor pattern 13 to be formed.

[0199] For example, when the intrinsic semiconductor materials of the first semiconductor pattern 11 and the second semiconductor pattern 13 are GaP, AlGaAs, or AlGaInP, the substrate 8 can be a GaP substrate or a GaAs substrate. When the intrinsic semiconductor materials of the first semiconductor pattern 11 and the second semiconductor pattern 13 are GaN, the substrate 8 can be a silicon carbide substrate or a sapphire substrate, etc.

[0200] S200, a plurality of epitaxial structures 1 are formed on one side of the substrate 8. Among them, any two adjacent epitaxial structures 1 have a gap; each epitaxial structure 1 includes: a first semiconductor pattern 11, a light-emitting pattern 12 and a second semiconductor pattern 13 stacked in sequence; the first semiconductor patterns 11 of at least two epitaxial structures 1 are interconnected to form a first semiconductor layer 11a.

[0201] Here, there are various methods for forming multiple epitaxial structures 1 on one side of the substrate 8, which can be selected according to actual needs. The following is an illustrative description of the methods for forming multiple epitaxial structures 1. Of course, the methods for forming multiple epitaxial structures 1 are not limited to the three examples given below.

[0202] In some examples, in the above S200, a plurality of epitaxial structures 1 are formed on one side of the substrate 8, which may include: S210a to S220a.

[0203] As shown in Figure 13(a), S210a, a first semiconductor thin film 11', a light-emitting thin film 12', and a second semiconductor thin film 13' are sequentially formed on one side of the substrate 8.

[0204] For example, a first semiconductor thin film 11', a light-emitting thin film 12', and a second semiconductor thin film 13' can be sequentially epitaxially grown on one side of the substrate 8 using a metal-organic vapor phase epitaxy (MOCVD) process.

[0205] Here, the materials of the first semiconductor thin film 11', the light-emitting thin film 12', and the second semiconductor thin film 13' can be referred to the description of the materials of the first semiconductor pattern 11, the light-emitting pattern 12, and the second semiconductor pattern 13 in some of the above embodiments, and will not be repeated here.

[0206] S220a, as shown in Figure 13(c), the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11' are patterned to form a first semiconductor pattern 11, a light-emitting pattern 12, and a second semiconductor pattern 13, resulting in multiple epitaxial structures 1. Among them, at least two first semiconductor patterns 11 are interconnected to form a first semiconductor layer 11a.

[0207] For example, the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11' can be patterned using a photolithography process.

[0208] Here, during the patterning of the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11', the etching depth may be greater than or equal to the thickness of the second semiconductor thin film 13' (i.e., the dimension in the direction perpendicular to the substrate 8), and less than the sum of the thicknesses of the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11'.

[0209] For example, if the etching depth is greater than or equal to the thickness of the second semiconductor thin film 13' and less than the sum of the thicknesses of the second semiconductor thin film 13' and the light-emitting thin film 12', multiple mutually spaced and mutually independent second semiconductor patterns 13 can be formed first.

[0210] In this case, the edge portion of the patterned light-emitting thin film 12' can be further patterned (e.g., by photolithography) to expose the patterned first semiconductor thin film 11'. At this point, a light-emitting layer 12a (where the multiple light-emitting patterns 12 in the multiple epitaxial structures 1 are interconnected) and a first semiconductor layer 11a (where the multiple first semiconductor patterns 11 in the multiple epitaxial structures 1 are interconnected) are obtained.

[0211] Of course, while further patterning the edge portion of the patterned light-emitting thin film, the portion located between any two adjacent second semiconductor patterns 13 can also be etched to obtain multiple light-emitting layers 12a.

[0212] It should be noted that during the further patterning of the edge portion of the patterned light-emitting film, or the further patterning of the edge portion of the patterned light-emitting film and the portion located between any two adjacent second semiconductor patterns 13: the etching depth can be the thickness of the light-emitting film 12', exposing only the surface of the patterned first semiconductor film 11'; or the etching depth can be greater than the thickness of the light-emitting film 12', but less than the sum of the thicknesses of the light-emitting film 12' and the first semiconductor film 11', etching away a portion of the patterned first semiconductor film 11'. This facilitates the formation of a good electrical connection between the subsequently formed first electrode 2 and the first semiconductor layer 11a.

[0213] For example, as shown in Figure 13(c), when the etching depth is greater than or equal to the sum of the thicknesses of the second semiconductor thin film 13' and the light-emitting thin film 12', and less than the sum of the thicknesses of the second semiconductor thin film 13', the light-emitting thin film 12' and the first semiconductor thin film 11', the surface of the patterned first semiconductor thin film can be exposed to form multiple second semiconductor patterns 13, multiple light-emitting patterns 12 and the first semiconductor layer 11a (for example, multiple first semiconductor patterns 11 in multiple epitaxial structures 1 are interconnected).

[0214] For example, the shapes and arrangements of the resulting multiple extensional structures 1 include various types, which can be selected and set according to actual needs.

[0215] For example, the aforementioned plurality of extensional structures 1 can be spaced apart along the first direction X, and each extensional structure 1 extends along the second direction Y. The orthographic projection shape of each extensional structure 1 on the first plane can be rectangular or strip-shaped.

[0216] For example, the aforementioned multiple extensional structures 1 can be arranged in an array. The shape of the orthographic projection of each extensional structure 1 onto the first plane can be a polygon (e.g., a triangle, rectangle, or hexagon).

[0217] Here, the shape of the second semiconductor pattern 13 and the shape of the light-emitting pattern 12 in the epitaxial structure 1 can be referred to the illustrative description in some of the above embodiments.

[0218] It should be noted that, considering the influence of the fabrication process, the angle between the edge of the epitaxial structure 1 and the first plane can be an acute angle, as shown in Figure 13(c), so that the cross-sectional shape of the epitaxial structure 1 is trapezoidal.

[0219] In other examples, in the above S200, a plurality of epitaxial structures 1 are formed on one side of the substrate, which may include: S210b to S240b.

[0220] As shown in Figure 13(a), S210b has a first semiconductor thin film 11', a light-emitting thin film 12', and a second semiconductor thin film 13' sequentially formed on one side of the substrate 8.

[0221] For example, the fabrication process and materials of the first semiconductor thin film 11', the light-emitting thin film 12', and the second semiconductor thin film 13' can be referred to the illustrative description in S210a above, and will not be repeated here.

[0222] As shown in Figures 14(d) and 14(e), a conductive thin film 3' is formed on the side of the second semiconductor thin film 13' away from the substrate 8.

[0223] For example, the above-mentioned conductive thin film 3' can be formed by sputtering deposition process.

[0224] For example, the material of the conductive thin film 3' can be, for example, Ni, silver (Ag), or aluminum (Al). The thickness of the conductive thin film 3' can range from 1 nm to 1000 nm.

[0225] For example, the thickness of the conductive thin film 3' can be 1 nm, 10 nm, 150 nm, 500 nm, 800 nm or 1000 nm, etc.

[0226] As shown in Figure 14(f), S230b is subjected to annealing of the conductive film 3' to form a plurality of dispersed conductive particles 31'.

[0227] For example, the annealing temperature range can be 100℃ to 500℃, and the annealing time range can be 10s to 1000s.

[0228] For example, the annealing temperature range can be 100℃, 200℃, 300℃, 410℃ or 500℃, and the annealing time range can be 10s, 100s, 300s, 550s, 860s or 1000s, etc.

[0229] Annealing the conductive film 3' can utilize the principle of solid dehumidification, transforming the conductive film 3' into multiple conductive particles 31'. These multiple conductive particles 31' can be dispersed relatively uniformly and have a relatively uniform particle size.

[0230] It should be noted that the particle size of conductive particles 31' can increase with the increase of the annealing temperature. Therefore, the desired particle size of conductive particles 31' can be controlled by controlling the annealing temperature.

[0231] For example, the particle size of the conductive particles 31' can range from 0.01 μm to 10 μm. The gap size between adjacent conductive particles 31' can range from 0.01 μm to 10 μm.

[0232] For example, the particle size of the conductive particles 31' can be 0.01 μm, 0.1 μm, 1 μm, 5 μm, or 10 μm, etc. The gap size between adjacent conductive particles 31' can be 0.01 μm, 0.1 μm, 1 μm, 5 μm, or 10 μm, etc.

[0233] S240b, as shown in Figure 14(g), using the aforementioned plurality of conductive particles 31' as masks, the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11' are patterned to form a first semiconductor pattern 11, a light-emitting pattern 12, and a second semiconductor pattern 13, thereby obtaining a plurality of epitaxial structures 1. Among them, at least two first semiconductor patterns 11 are interconnected to form a first semiconductor layer 11a.

[0234] For example, the process or etching depth for patterning the second semiconductor thin film 13', the light-emitting thin film 12' and the first semiconductor thin film 11' can be referred to the illustrative description in S220a above, and will not be repeated here.

[0235] For example, the shapes and arrangements of the resulting multiple extensional structures 1 are varied and can be selected and set according to actual needs.

[0236] For example, the aforementioned multiple epitaxial structures 1 can be arranged in an array. The shape of the orthographic projection of each epitaxial structure 1 onto the first plane can be circular or elliptical.

[0237] Here, the shape of the second semiconductor pattern 13 and the shape of the light-emitting pattern 12 in the epitaxial structure 1 can be referred to the illustrative description in some of the above embodiments.

[0238] Considering the fabrication process of the epitaxial structure 1, the particle size of the conductive particles 31' and the gap size between adjacent conductive particles 31', the included angle between the edge of the prepared epitaxial structure 1 and the first plane can be, for example, 90° or approximately 90°, as shown in Figure 14(g), so that the cross-sectional shape of the epitaxial structure 1 is a slant shape.

[0239] It should be noted that after the second semiconductor thin film 13', the light-emitting thin film 12' and the first semiconductor thin film 11' are patterned, the above-mentioned multiple conductive particles 31' can serve as multiple second electrodes 3.

[0240] In some other examples, in the above S200, a plurality of epitaxial structures 1 are formed on one side of the substrate, which may include: S210c to S230c.

[0241] S210c, as shown in FIG15(a), a first semiconductor thin film 11' is formed on the substrate 8. Alternatively, as shown in FIG16(a), a first semiconductor thin film 11' and a light-emitting thin film 12' are stacked on the substrate 8.

[0242] For example, the fabrication process and materials of the first semiconductor thin film 11' and the light-emitting thin film 12' can be referred to the illustrative description in S210a above, and will not be repeated here.

[0243] In this example, the first semiconductor thin film 11' can be referred to as the first semiconductor layer 11a. The first semiconductor layer 11a includes a plurality of first semiconductor patterns 11 of a plurality of epitaxial structures 1 to be formed.

[0244] As shown in Figures 15(b) and 16(b), in S220c, a defining layer 9 is formed on the substrate 1. This defining layer 9 has a plurality of openings K. The defining layer 9 is configured to define the epitaxial structure 1.

[0245] Here, when only the first semiconductor thin film 11' is formed on the substrate 8, the defining layer 9 can be located on the side of the first semiconductor thin film 11' away from the substrate 8, and the aforementioned plurality of openings K expose the first semiconductor thin film 11'. When both the first semiconductor thin film 11' and the light-emitting thin film 12' are formed on the substrate 8, the defining layer 9 can be located on the side of the light-emitting thin film 12' away from the substrate 8, and the aforementioned plurality of openings K expose the light-emitting thin film 12'.

[0246] For example, a defining film can be deposited using a deposition process, and then the defining film can be patterned using a photolithography process to form multiple openings K, thus obtaining the aforementioned defining layer 9.

[0247] For example, the structure of the aforementioned defined thin film can be a single-layer thin film formed of silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), or it can be a multilayer thin film formed of at least two of SiO2, SiN, and SiON stacked sequentially.

[0248] It should be noted that, considering the influence of the preparation process, the angle between the edge of the opening K of the defined layer 9 and the first plane can be an acute angle, as shown in Figures 15(b) and 16(b), so that the cross-sectional shape of the epitaxial structure 1 is trapezoidal.

[0249] As shown in Figure 15(c), in case S230c, when a first semiconductor thin film 11' is formed on the substrate 8, a light-emitting pattern 12 and a second semiconductor pattern 13 are stacked and formed in each opening K. Alternatively, as shown in Figure 16(c), when a first semiconductor thin film 11' and a light-emitting thin film 12' are formed on the substrate 8, a second semiconductor pattern 13 is formed in each opening K. Multiple epitaxial structures 1 are obtained.

[0250] For example, an MOCVD process can be used to form a light-emitting pattern 12 and a second semiconductor pattern 13 within the opening K, wherein the cross-sectional shape of the light-emitting pattern 12 and the second semiconductor pattern 13 is determined by the shape of the opening K; or only the second semiconductor pattern 13 can be formed, wherein the cross-sectional shape of the second semiconductor pattern 13 is determined by the shape of the opening K.

[0251] Here, after the defining layer 9 is formed, the opening K in the defining layer 9 can be used to define the arrangement, shape and size of the extensional structure 1.

[0252] For example, the shapes and arrangements of the resulting multiple extensional structures 1 are varied and can be selected and set according to actual needs.

[0253] For example, the aforementioned multiple extensional structures 1 can be spaced apart along the first direction X, and each extensional structure 1 extends along the second direction Y. The orthographic projection shape of each extensional structure 1 on the first plane can be a quadrilateral or a strip.

[0254] For example, the aforementioned multiple extensional structures 1 can be arranged in an array. The shape of the orthographic projection of each extensional structure 1 onto the first plane can be a polygon (e.g., a triangle, rectangle, or hexagon).

[0255] Here, the shape of the second semiconductor pattern 13 and the shape of the light-emitting pattern 12 in the epitaxial structure 1 can be referred to the illustrative description in some of the above embodiments.

[0256] It should be noted that when the light-emitting pattern 12 and the second semiconductor pattern 13 are stacked and formed within each opening K, the thickness of the defining layer 9 and the sum of the thicknesses of the light-emitting pattern 12 and the second semiconductor pattern 13 can be, for example, equal or approximately equal, so that the light-emitting pattern 12 and the second semiconductor pattern 13 are formed only within the opening K. When the second semiconductor pattern 13 is formed within each opening K, the thickness of the defining layer 9 and the subsequent thickness of the third semiconductor pattern 13 can be, for example, equal or approximately equal, so that the third semiconductor pattern 13 is formed only within the opening K1.

[0257] This example, by setting a demarcation layer 9, can avoid patterning the subsequently formed light-emitting pattern 12 and the second semiconductor pattern 13, or can avoid patterning the second semiconductor pattern 13. This simplifies the process of fabricating the LED chip 100 and avoids damage to the subsequently formed structure (i.e., the light-emitting pattern 12 and the second semiconductor pattern 13, or the second semiconductor pattern 13) due to patterning, thus affecting the light-emitting performance of the LED chip.

[0258] S300, at least one first electrode 2 is formed. The first electrode 2 is electrically connected to the first semiconductor layer 11a.

[0259] For example, the first electrode 2 can be formed using a photolithography process. The material of the first electrode 2 may include, for example, titanium (Ti), aluminum (Al), Ni, or Au.

[0260] It should be noted that, considering the influence of the fabrication process, the angle between the edge of the prepared epitaxial structure 1 and the first plane can be, for example, an acute angle, as shown in Figures 13(e), 14(c), 15(g) and 16(f), so that the cross-sectional shape of the epitaxial structure 1 is trapezoidal.

[0261] Here, there are multiple methods for forming the first electrode 2, which can be selected and set according to actual needs.

[0262] In some examples, after obtaining multiple extensional structures 1 in S210a to S220a above, S300 may include, for example, S310a.

[0263] S310a, as shown in Figure 13(e), a first electrode material thin film is formed on the side of the plurality of epitaxial structures 1 away from the substrate 8, and then the first electrode material thin film is patterned by photolithography to obtain the first electrode 2.

[0264] Regarding the shape and arrangement of the first electrode 2, please refer to the descriptions in the examples above, which will not be repeated here.

[0265] In other examples, in S210b to S240b above, before forming the conductive thin film 3' (i.e., S220b), S300 may include, for example, S310b to S320b.

[0266] S310b, as shown in FIG14(a), the second semiconductor thin film 13', the light-emitting thin film 12' and the first semiconductor thin film 11' are patterned to expose the surface of the portion of the first semiconductor thin film 11' corresponding to the first electrode 2 to be formed.

[0267] For example, the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11' can be patterned using a photolithography process.

[0268] The aforementioned photolithography process may include, for example, coating a photoresist on the side of the second semiconductor thin film 13' away from the substrate 8, then patterning the photoresist, and using the patterned photoresist as a mask to pattern the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11'; or, sequentially depositing silicon dioxide (SiO2) on the side of the second semiconductor thin film 13' away from the substrate 8, coating a photoresist, then patterning the photoresist, using the patterned photoresist as a mask to pattern the SiO2, and then using the patterned SiO2 to pattern the second semiconductor thin film 13', the light-emitting thin film 12', and the first semiconductor thin film 11'.

[0269] Here, during the patterning process of the second semiconductor thin film 13', the light-emitting thin film 12' and the first semiconductor thin film 11', the etching depth can be greater than or equal to the sum of the thicknesses of the second semiconductor thin film 13' and the light-emitting thin film 12', and less than the sum of the thicknesses of the second semiconductor thin film 13', the light-emitting thin film 12' and the first semiconductor thin film 11'.

[0270] S320b, as shown in Figure 14(c), forms a first electrode material thin film in the above structure, and then the first electrode material thin film is patterned by photolithography to obtain the first electrode 2.

[0271] The shape and arrangement of the first electrode 2 can be referred to in the above examples, and will not be repeated here.

[0272] In some other examples, after obtaining multiple extensional structures 1 in S210c to S230c, S300 may include, for example, S310c to S320c.

[0273] For example, as shown in FIG15(e), in the case where a first semiconductor thin film 11' is formed on the substrate 8 in the above S210c, the above S310c may include, for example, patterning the defining layer 9 and the first semiconductor thin film 11' to expose the surface of the portion of the first semiconductor thin film 11' corresponding to the first electrode 2 to be formed.

[0274] For example, the defining layer 9 and the first semiconductor thin film 11' can be patterned using a photolithography process.

[0275] Here, during the patterning of the defining layer 9 and the first semiconductor thin film 11', the etching depth may be greater than or equal to the thickness of the defining layer 9, and less than the sum of the thicknesses of the defining layer 9 and the first semiconductor thin film 11'.

[0276] For example, in the case where a first semiconductor thin film 11' and a light-emitting thin film 12' are formed on the substrate 8 in the above S210c, the above S310c may include, for example, patterning the defining layer 9, the light-emitting thin film 12' and the first semiconductor thin film 11' to expose the surface of the portion of the first semiconductor thin film 11' corresponding to the first electrode 2 to be formed.

[0277] For example, the defining layer 9, the light-emitting thin film 12', and the first semiconductor thin film 11' can be patterned using a photolithography process.

[0278] Here, during the patterning process of the defining layer 9, the light-emitting thin film 12' and the first semiconductor thin film 11', the etching depth can be greater than or equal to the sum of the thicknesses of the defining layer 9 and the light-emitting thin film 12', and less than the sum of the thicknesses of the defining layer 9, the light-emitting thin film 12' and the first semiconductor thin film 11'.

[0279] As shown in Figures 15(g) and 16(f), in the above structure, a first electrode material thin film is formed, and then the first electrode material thin film is patterned by photolithography to form the first electrode 2.

[0280] The shape and arrangement of the first electrode 2 can be referred to in the above examples, and will not be repeated here.

[0281] It should be noted that in some examples, the substrate 8 may have multiple chip regions. As shown in Figures 13(d), 14(b), 15(f) and 16(e), in the above-described S300, before forming the first electrode 2 (e.g., before S310a, S320b or S320c), the method for fabricating the LED chip may further include: further patterning the patterned first semiconductor thin film 11" to expose the substrate 8.

[0282] For example, the further patterned locations in the first semiconductor thin film 11' are the boundary locations of the aforementioned plurality of chip regions, and the exposed portion of the substrate 8 is in a grid pattern. This allows for the definition of the boundaries of the LED chip to be formed, facilitating subsequent segmentation.

[0283] S400, a plurality of second electrodes 3 are formed. Each second electrode 3 is electrically connected to at least one of the second semiconductor patterns 13 of the plurality of epitaxial structures 1.

[0284] For example, the material of the second electrode 3 may include Ti, Al, Ni, Au, copper (Cu), indium (In), tin (Sn), silver (Ag), or Sn alloys, etc.

[0285] Here, there are various methods for forming the second electrode 3, which can be selected and set according to actual needs.

[0286] In some examples, after the first electrode 2 is formed in S310a above, S400 may include, for example, S410a to S420a.

[0287] S410a, as shown in FIG13(f), a first insulating film is formed on the side of each epitaxial structure 1 away from the substrate 8. The first insulating film not only covers the exposed portions of the multiple epitaxial structures 1 and the substrate 8, but also lies within the gap between any two adjacent epitaxial structures 1. The first insulating film is then patterned to form vias that expose the surface of the second semiconductor pattern 13 of each epitaxial structure 1, thereby obtaining the first insulating layer 101.

[0288] For example, the first insulating film described above can be formed using a deposition process, and then patterned using a photolithography process. The first insulating film can be a single-layer film structure formed of SiO2, SiN, or SiON, or it can be a multilayer film structure formed by sequentially stacking at least two of SiO2, SiN, and SiON.

[0289] S420a, as shown in Figure 13(g), a second electrode material thin film is formed on the side of the first insulating layer 101 away from the substrate 8, and then the second electrode material thin film is patterned to obtain a plurality of second electrodes 3.

[0290] For example, the second electrode material film described above can be formed using a deposition process, and then the second electrode material film can be patterned using a photolithography process.

[0291] Regarding the shape and arrangement of the second electrode 3, please refer to the descriptions in the examples above, which will not be repeated here.

[0292] It should be noted that when the LED chip 100 includes a first electrode pin 4 and a second electrode pin 5, the aforementioned insulating film can also cover the first electrode 2. After patterning the first insulating film, a via exposing the first electrode 2 can be formed, and then after patterning the second electrode material film, a first electrode pin 4 electrically connected to the first electrode 2 can be formed.

[0293] Here, when the orthographic projection of the epitaxial structure 1 onto the first plane is a polygon, the second electrode 3 can serve as the second conductive pin 5. When the orthographic projection of the epitaxial structure 1 onto the first plane is a strip, the second electrode 3 can be an integral structure with the second electrode pin 5.

[0294] When the orthographic projection shape of the extensional structure 1 on the first plane is a strip, such as Figures 2-5 As shown, a second insulating layer 102 can also be formed on the side of the second electrode 3 away from the substrate 8, exposing the second electrode pin 5 and covering the second electrode 3 to form a protective layer.

[0295] In other examples, in S240b above, as shown in FIG14(f), after obtaining multiple epitaxial structures 1, multiple conductive particles 31' serving as masks can serve as multiple second electrodes 3.

[0296] It should be noted that, in the case where the LED chip 100 includes a first electrode pin 4 and a second electrode pin 5, the aforementioned plurality of conductive particles 31' can also serve as the second conductive pin 5. The first electrode 2 formed before S220b can also serve as the first conductive pin 4.

[0297] In some other examples, after the first electrode 2 is formed in S320c above, S400 may include, for example, S410c to S420c.

[0298] Here, step S410c (as shown in Figure 15(h)) can be referred to as S410a, and step S420c (as shown in Figures 15(i) and 16(g)) can be referred to as S420a. Further details will not be provided here.

[0299] The beneficial effects that can be achieved by the LED chip fabrication method provided in some embodiments of this disclosure are the same as the beneficial effects that can be achieved by the LED chip 100 provided in some embodiments above, and will not be repeated here.

[0300] It should be noted that the step numbers in the above preparation method (such as "S100", "S200", "S300" or "S400") are only for clearly indicating the content of each step, and are not a limitation on the order of steps in preparing the LED chip 100.

[0301] In some embodiments, in the above S200, the method for fabricating the LED chip may include, for example, forming a buffer layer 7 on one side of the substrate 8.

[0302] For example, as shown in FIG13(a), a buffer film 7' can be epitaxially grown on one side of the substrate 8 using an MOCVD process.

[0303] In this case, during the steps of defining the boundary of the LED chip to be formed and further patterning the patterned first semiconductor thin film 11' to expose the substrate 8, the buffer thin film 7' is also patterned simultaneously to obtain the buffer layer 7.

[0304] In some embodiments, in the above S200, the method for fabricating the LED chip may include, for example, forming an ohmic contact layer 6 on the side of the second semiconductor pattern 13 of each epitaxial structure 1 away from the substrate 8.

[0305] Here, there are several methods for forming the ohmic contact layer 6, which can be selected and set according to actual needs.

[0306] In some examples, as shown in FIG13(b), after S210a and before S220a, an ohmic contact film 6' is formed on the side of the second semiconductor film 13' away from the substrate 8. Then, during the patterning of the second semiconductor film 13', the light-emitting film 12' and the first semiconductor film 11', the ohmic contact film 6' is simultaneously patterned to form an ohmic contact layer 6.

[0307] For example, the ohmic contact film 6' can be formed by vapor deposition and then patterned by photolithography.

[0308] Here, considering the influence of the fabrication process and structure, the angle between the edge of the ohmic contact layer 6 and the first plane can be an acute angle, as shown in Figure 13(c), so that the cross-sectional shape of the epitaxial structure 1 is trapezoidal.

[0309] In other examples, after S210b and before S220b, an ohmic contact film 6' is formed on the side of the second semiconductor film 13' away from the substrate 8. Then, in S240b, during the patterning of the second semiconductor film 13', the light-emitting film 12', and the first semiconductor film 11', the ohmic contact film 6' is simultaneously patterned to form an ohmic contact layer 6.

[0310] For example, the ohmic contact film 6' can be formed by vapor deposition and then patterned by photolithography.

[0311] Here, considering the influence of the fabrication process and structure, the angle between the edge of the formed ohmic contact layer 6 and the first plane can be, for example, 90° or about 90°, as shown in Figure 14(g), so that the cross-sectional shape of the epitaxial structure 1 is rectangular.

[0312] In some other examples, as shown in Figures 15(d) and 16(d), after S230c above, an ohmic contact film 6' is formed on the side of the plurality of epitaxial structures 1 away from the substrate 8, and then the ohmic contact film 6' is patterned to form an ohmic contact layer 6.

[0313] For example, the ohmic contact film 6' can be formed by vapor deposition and then patterned by photolithography.

[0314] Here, considering the influence of the fabrication process and structure, the angle between the edge of the formed ohmic contact layer 6 and the first plane can be an acute angle, as shown in Figures 15(d) and 16(d), so that the cross-sectional shape of the epitaxial structure 1 is trapezoidal.

[0315] In some embodiments, after a plurality of LED chips 100 are formed on the substrate 8, the substrate 8 can be peeled off or thinned.

[0316] Some embodiments of this disclosure provide a display device 1000. For example... Figure 17 As shown, the display device 1000 includes: a driving backplate 200, and a plurality of LED chips 100 as described in any of the above embodiments.

[0317] In some examples, as shown in Figure 16, the driving backplane 200 may include a plurality of first pads P1 and a plurality of second pads P2. In the plurality of LED chips 100 described above, the first electrode 2 of each LED chip 100 may be electrically connected to a first pad P1, and the second electrode 3 of each LED chip 100 may be electrically connected to a second pad P2.

[0318] For example, in each LED chip 100, the number of first electrodes 2 is less than the number of second electrodes 3, and the number of first pads P1 electrically connected to the first electrodes 2 can be less than the number of second pads P2 electrically connected to the second electrodes 3.

[0319] For example, each LED chip 100 has a first electrode 2 and a plurality of second electrodes 3. In this case, each first pad P1 and the plurality of second pads P2 can correspond to each other and be grouped together, and can be electrically connected to one LED chip 100.

[0320] For example, the aforementioned driving backplane 200 is configured to transfer electrons to the first electrode 2 of the LED chip 100 electrically connected thereto via the first pad P1, and to transfer holes to one of the second electrodes 3 of the plurality of second electrodes 3 of the LED chip 100 electrically connected thereto via the second pad P2, such that electrons and holes recombine to emit light in the light-emitting pattern 12 in the corresponding epitaxial structure 1.

[0321] In some examples, where the LED chip 100 includes a first conductive pin 4 and a second conductive pin 5, the first electrode 2 of each LED chip 100 can be electrically connected to a first pad P1 via the first conductive pin 4, and the second electrode 3 of each LED chip 100 can be electrically connected to a second pad P2 via the second conductive pin 5.

[0322] The display device 1000 provided in some embodiments of this disclosure has the same beneficial effects as the LED chip 100 provided in some of the above embodiments, and will not be repeated here.

[0323] In some embodiments, the aforementioned driving backplate 200 may be, for example, the backplate in the backlight module of a liquid crystal display (LCD). In this case, the LED chip 100 can serve as a light source, and the display device 1000 can serve as the backlight module in the LCD, providing backlight for the image display of the LCD.

[0324] In other embodiments, the aforementioned driving backplane 200 may be, for example, a display backplane. In this case, the LED chip 100 may be part of a plurality of sub-pixels, and the display device 1000 may be an LED display device for image display. The display device 1000 may be, for example, a Mini LED display device or a Micro LED display device.

[0325] In some embodiments, the display device 1000 described above can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0326] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A light-emitting diode chip, characterized in that, The light-emitting diode chip includes: Multiple epitaxial structures; any two adjacent epitaxial structures in the multiple epitaxial structures have a gap between them; each epitaxial structure includes: a first semiconductor pattern, a light-emitting pattern, and a second semiconductor pattern stacked sequentially; the first semiconductor patterns of at least two epitaxial structures in the multiple epitaxial structures are interconnected to form a first semiconductor layer; the light-emitting patterns of at least two epitaxial structures in the multiple epitaxial structures are interconnected to form a light-emitting layer; At least one first electrode; the first electrode is electrically connected to the first semiconductor layer; and, A plurality of second electrodes; each second electrode is electrically connected to a second semiconductor pattern of at least one of the plurality of epitaxial structures.

2. The light-emitting diode chip according to claim 1, characterized in that, The first electrode and the plurality of second electrodes are disposed on the same side of the first semiconductor layer.

3. The light-emitting diode chip according to claim 1, characterized in that, The orthographic projection of the first electrode on the first plane is located within the orthographic projection range of the first semiconductor layer electrically connected to the first electrode on the first plane, and does not overlap with the orthographic projections of the plurality of epitaxial structures on the first plane; The first plane is a plane parallel to the first semiconductor layer.

4. The light-emitting diode chip according to claim 3, characterized in that, The orthographic projection of the second electrode onto the first plane and the orthographic projection of the second semiconductor pattern of the at least one epitaxial structure electrically connected to the second electrode onto the first plane at least partially overlap.

5. The light-emitting diode chip according to claim 1, characterized in that, The plurality of epitaxial structures are spaced apart along a first direction, and the epitaxial structures extend along a second direction; The first direction and the second direction intersect each other.

6. The light-emitting diode chip according to claim 5, characterized in that, The plurality of second semiconductor patterns in the plurality of epitaxial structures are spaced apart along the first direction, and the second semiconductor patterns extend along the second direction.

7. The light-emitting diode chip according to claim 6, characterized in that, The plurality of light-emitting patterns in the plurality of epitaxial structures are spaced apart along the first direction, and the light-emitting patterns extend along the second direction.

8. The light-emitting diode chip according to claim 1, characterized in that, The multiple epitaxial structures are arranged in an array.

9. The light-emitting diode chip according to claim 8, characterized in that, The multiple second semiconductor patterns in the multiple epitaxial structures are arranged in an array.

10. The light-emitting diode chip according to claim 9, characterized in that, The multiple light-emitting patterns in the multiple epitaxial structures are arranged in an array.

11. The light-emitting diode chip according to claim 8, characterized in that, The first electrode is located within the gap between at least two adjacent epitaxial structures in the plurality of epitaxial structures; The first electrode includes at least one first portion extending along a first direction and at least one second portion extending along a second direction.

12. The light-emitting diode chip according to any one of claims 5 to 10, characterized in that, The first electrode is disposed around the plurality of epitaxial structures.

13. The light-emitting diode chip according to any one of claims 1 to 11, characterized in that, In the plurality of epitaxial structures, the size of the gap between any two adjacent epitaxial structures ranges from 0.01 μm to 100 μm.

14. The light-emitting diode chip according to any one of claims 1 to 11, characterized in that, The light-emitting diode chip also includes: At least one first conductive pin; the conductive pin is located on the side of the first electrode away from the first semiconductor layer and is electrically connected to the first electrode; and, Multiple second conductive pins; each second conductive pin is electrically connected to the second electrode.

15. The light-emitting diode chip according to any one of claims 1 to 11, characterized in that, The light-emitting diode chip further includes an ohmic contact layer disposed between the second semiconductor pattern and a second electrode electrically connected thereto.

16. The light-emitting diode chip according to claim 15, characterized in that, The ohmic contact layer is either a light-transmitting ohmic contact layer or a reflective ohmic contact layer.

17. A method for fabricating a light-emitting diode chip, characterized in that, The preparation method includes: Provide substrate; Multiple epitaxial structures are formed on one side of the substrate; any two adjacent epitaxial structures have a gap between them; each epitaxial structure includes: a first semiconductor pattern, a light-emitting pattern, and a second semiconductor pattern stacked sequentially; the first semiconductor patterns of at least two of the multiple epitaxial structures are interconnected to form a first semiconductor layer; the light-emitting patterns of at least two of the multiple epitaxial structures are interconnected to form a light-emitting layer. At least one first electrode is formed; the first electrode is electrically connected to the first semiconductor layer; A plurality of second electrodes are formed; each second electrode is electrically connected to a second semiconductor pattern of at least one of the plurality of epitaxial structures.

18. A display device, characterized in that, The display device includes: A drive backplane; the drive backplane includes a plurality of connection pads, the plurality of connection pads including a plurality of first pads and a plurality of second pads; and, The plurality of light-emitting diode chips as described in any one of claims 1 to 16; each first electrode of the plurality of light-emitting diode chips is electrically connected to a first pad, and each second electrode of the plurality of light-emitting diode chips is electrically connected to a second pad.

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