Display substrate and display device

Abstract

A display substrate and a display device. In the display substrate, a first opening region includes a first opening and a first opening peripheral region surrounding the first opening; a second opening region is adjacent to the first opening region and includes a second opening and a second opening peripheral region surrounding the second opening; an inter-opening region is located between the first opening region and the second opening region, and at least one of the inter-opening region, the first opening peripheral region, and the second opening peripheral region includes a first virtual sub-pixel; a display region at least partially surrounds the first opening region, the second opening region, and the inter-opening region and includes sub-pixels. A first signal line extends along a first direction and includes a first portion passing through the first opening peripheral region, the inter-opening region, and the second opening peripheral region; the first portion passes through a first virtual sub-pixel; the first virtual sub-pixel includes a first compensation capacitor, a first plate of which is in the same layer as and electrically connected to the first portion of the first signal line, and in the same layer as the second plate of the storage capacitor; the second plate is in a different layer than and insulated from the first plate of the first compensation capacitor, and the second plate of the first compensation capacitor at least partially overlaps with the first plate of the first compensation capacitor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] Currently, the display screens of display devices are developing in the direction of large screens and full screens. Typically, display devices (such as mobile phones, tablet computers, etc.) have a camera device (or imaging device), which is usually arranged on a side outside the display area of ​​the display screen. However, since the installation of the camera device requires a certain frame position, it is not conducive to the full-screen and narrow-frame design of the display screen. For example, the camera device can be combined with the display area of ​​the display screen and overlapped together, and a position can be reserved for the camera device in the display area to maximize the display area of ​​the display screen. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first opening area, a second opening area, an area between openings, a display area, and a first signal line. The first opening area includes a first opening and a first opening peripheral area surrounding the first opening; the second opening area is adjacent to the first opening area along the first direction and includes a second opening and a second opening peripheral area surrounding the second opening; the area between openings is located between the first opening area and the second opening area, and at least one of the area between openings, the first opening peripheral area, and the second opening peripheral area includes a first virtual sub-pixel; the display area at least partially surrounds the first opening area, the second opening area, and the area between openings, and includes a plurality of pixels, each of the pixels includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, and the pixel circuit The present invention comprises: a transistor, a light-emitting element, and a storage capacitor, comprising an active layer, a gate, and a source and drain; the light-emitting element is connected to one of the source and drain electrodes of the transistor; the storage capacitor comprises a first plate and a second plate, the gate and the first plate of the storage capacitor being arranged in the same layer; a first signal line extending in a first direction, comprising a first portion passing through the first opening peripheral region, the inter-opening region, and the second opening peripheral region, and configured to provide a first display signal to the pixel circuit; a first portion of the first signal line passing through the first virtual sub-pixel, the first virtual sub-pixel comprising a virtual pixel circuit, the virtual pixel circuit comprising a first compensation capacitor, the first compensation capacitor comprising: a first plate and a second plate. The first plate is arranged in the same layer as the first portion of the first signal line and is electrically connected to the first signal line, and is arranged in the same layer as the second plate of the storage capacitor; the second plate is arranged in a different layer from the first plate of the first compensation capacitor and is insulated, wherein the orthographic projection of the second plate of the first compensation capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first compensation capacitor on the substrate.

[0004] At least one embodiment of the present disclosure further provides a display substrate, which includes a base substrate including a first opening area, a display area, a plurality of first signal lines, a plurality of second signal lines, and a first floating electrode. The first opening region includes a first opening and a first opening peripheral region surrounding the first opening; the display region at least partially surrounds the first opening region and includes: a first display region located on a first side of the first opening region; and a second display region located on a second side of the first opening region, wherein the first side and the second side are opposite to each other in a first direction, and the first display region and the second display region include a plurality of pixels; a plurality of first signal lines configured to provide first display signals to the plurality of pixels, the first signal lines extending along the first direction and passing through the first display region and the second display region; a plurality of second signal lines configured to provide second display signals to the plurality of pixels, the second signal lines extending along a second direction intersecting the first direction, portions of the plurality of second signal lines passing through the first opening peripheral region along the second direction, each of the plurality of second signal lines including a longitudinal winding portion located in the first opening peripheral region, wherein the longitudinal winding portion is partially disposed around the first opening; a longitudinal winding portion of the plurality of second signal lines that is closest to the first opening is an edge longitudinal winding portion, and the first floating electrode is disposed in the same layer as the edge longitudinal winding portion and is located on a side of the edge longitudinal winding portion that is adjacent to the first opening.

[0005] At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0007] Figure 1 is a planar schematic diagram of a display substrate;

[0008] Figure 2A A schematic plan view of a display substrate provided in one embodiment of the present disclosure;

[0009] Figure 2B for Figure 2A A partially enlarged schematic diagram including the first opening area and the second opening area;

[0010] Figure 2C for Figure 2A The diagram includes a partial enlarged schematic diagram of the first opening area and the area between the openings;

[0011] Figure 3A A schematic cross-sectional view of a sub-pixel in a display area of ​​a display substrate;

[0012] Figure 3B is another schematic cross-sectional view of a sub-pixel in a display area of ​​a display substrate;

[0013] Figure 4A A schematic diagram of a planar layout of a first virtual pixel circuit in a display substrate provided by an embodiment of the present disclosure;

[0014] Figure 4B For the Figure 4A Schematic cross-sectional view of line A2-B2 in FIG;

[0015] Figures 4C-4G A schematic diagram of various layers of a first virtual pixel circuit of a display substrate provided by an embodiment of the present disclosure;

[0016] Figure 4H A schematic diagram of a first plate of a first compensation capacitor of another display substrate provided by an embodiment of the present disclosure;

[0017] Figure 4I For the Figure 4A A schematic cross-sectional view of line A3-B3 in FIG;

[0018] Figure 4J is a partial view showing a substrate;

[0019] Figure 5A for Figure 2C An enlarged schematic diagram of the local C in FIG;

[0020] Figure 5B for Figure 2C An enlarged schematic diagram of the local D in FIG;

[0021] Figure 5C for Figure 2C An enlarged schematic diagram of the local E in FIG;

[0022] Figure 5D for Figure 2C An enlarged schematic diagram of the local F in FIG;

[0023] Figure 5E An enlarged schematic diagram of an area where the first signal line and the second signal line are to be layer-changed;

[0024] Figures 5F-5H Along Figure 5E Schematic cross-sectional view of lines A4-B4, A5-B5 and A6-B6;

[0025] Figure 6 An equivalent circuit diagram of a pixel circuit in an array substrate provided in one embodiment of the present disclosure;

[0026] Figure 7A A schematic diagram of a planar layout of a pixel circuit in an array substrate provided in one embodiment of the present disclosure;

[0027] Figure 7B-7K A schematic diagram of various layers of a pixel circuit of an array substrate provided in one embodiment of the present disclosure;

[0028] Figure 8A For the Figure 7A A schematic cross-sectional view of the A-A' line in FIG.

[0029] Figure 8B For the Figure 7A A schematic cross-sectional view of the BB' line in FIG.

[0030] Figure 9 yes Figure 6 The signal timing diagram of the working process of the pixel circuit shown;

[0031] Figure 10A is an enlarged schematic diagram of a first opening area of ​​a display substrate provided by one embodiment of the present disclosure;

[0032] Figure 10B is an enlarged schematic diagram of a first opening area of ​​another display substrate provided by an embodiment of the present disclosure;

[0033] Figure 10C is an enlarged schematic diagram of a first opening area of ​​another display substrate provided by an embodiment of the present disclosure;

[0034] Figure 11 yes Figure 10A An enlarged schematic diagram of the local H in FIG;

[0035] Figure 12 yes Figure 11 An enlarged schematic diagram of the local G in ;

[0036] Figure 13 is an enlarged schematic diagram of a part I in FIG16;

[0037] Figure 14 yes Figure 13 An enlarged schematic diagram of the local J in FIG.

[0038] Figure 15 is a schematic plan view of another display substrate according to an embodiment of the present disclosure;

[0039] Figure 16A A schematic planar layout diagram of a second virtual pixel circuit in a second virtual sub-pixel of a display substrate provided by an embodiment of the present disclosure;

[0040] Figures 16C-16FA schematic diagram of various layers of a second virtual pixel circuit of a display substrate provided by an embodiment of the present disclosure;

[0041] Figure 17 A schematic planar layout diagram of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which the invention belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0044] In the following description, when two or more components are referred to as being “integrally formed”, it means that these components are formed from at least the same material layer, for example, by performing the same patterning process on the same film layer, so that there is no interface between them and they are continuous.

[0045] Figure 1 FIG. 1 is a schematic plan view of a display substrate. Figure 1 As shown, the display substrate 10 includes a display area 101 and a peripheral area 102 surrounding the display area 101. The display area 101 is designed to be an irregular shape, for example, having a notch 103 on at least one side. The display substrate 10 can arrange devices such as cameras and distance sensors in the area of ​​the notch 103, thereby helping to achieve a narrow-frame design of the display substrate 10.

[0046] like Figure 1 As shown, the display area 101 includes a first display area 1011 and a second display area 1012 located on the left and right sides of the notch 103. The first display area 1011 and the second display area 1012 are at the same horizontal position relative to the bottom edge of the display area 101 (the lower edge in the figure), for example, they are driven by one or more scanning signal lines (gate lines) extending horizontally to the left and right in the figure. Of course, in some other embodiments, the first display area and the second display area may also be at different horizontal positions. For example, when the display screen using the display substrate is an irregular (non-rectangular or non-rectangular) display screen, in the irregular screen, for example, the first display area and the second display area are arranged along the curved edge of the display screen, then the first display area and the second display area may not be at the same horizontal position. Due to the presence of the notch 103, the number of pixels in the same row of pixels in the first display area 1011 and the second display area 1012 is greater than that in other parts of the display area 101 (for example, Figure 1 The number of pixels in a row of pixels in the middle of the first display area 1011 and the second display area 1012 is small. Therefore, in the display substrate 10, the number of pixels connected to the horizontally extending signal line used to provide display signals (e.g., scan signals) to the same row of pixels in the first display area 1011 and the second display area 1012 is different from the number of pixels connected to the signal line used to provide electrical signals (e.g., scan signals) to a row of pixels in other parts of the display area 101 except the first display area 1011 and the second display area 1012. Moreover, when the notch 103 is an irregular shape (e.g., a trapezoidal shape, a teardrop shape, etc.), the number of pixels in different rows of pixels in the first display area 1011 and the second display area 1012 may also be different. Therefore, in the display substrate 10, due to the different number of pixels in different rows of pixels, the loads of the signal lines connecting the different rows of pixels are different, and thus the speeds at which these signal lines transmit signals are different. The deviation between the actual display signal and the designed value is different, which affects the display effect of the display substrate.

[0047] For example, load compensation may be performed on the signal lines with different loads so that the loads of the signal lines are substantially the same, thereby reducing the adverse effect of the notch 103 on the display quality.

[0048] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first opening area, a second opening area, an area between openings, a display area, and a first signal line. The first opening area includes a first opening and a first opening peripheral area surrounding the first opening; the second opening area is adjacent to the first opening area along the first direction and includes a second opening and a second opening peripheral area surrounding the second opening; the area between openings is located between the first opening area and the second opening area, and at least one of the area between openings, the first opening peripheral area, and the second opening peripheral area includes a first virtual sub-pixel; the display area at least partially surrounds the first opening area, the second opening area, and the area between openings, and includes a plurality of pixels, each of the pixels includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, and the pixel circuit The present invention comprises: a transistor, a light-emitting element, and a storage capacitor, comprising an active layer, a gate, and a source and drain; the light-emitting element is connected to one of the source and drain electrodes of the transistor; the storage capacitor comprises a first plate and a second plate, the gate and the first plate of the storage capacitor being arranged in the same layer; a first signal line extending in a first direction, comprising a first portion passing through the first opening peripheral region, the inter-opening region, and the second opening peripheral region, and configured to provide a first display signal to the pixel circuit; a first portion of the first signal line passing through the first virtual sub-pixel, the first virtual sub-pixel comprising a virtual pixel circuit, the virtual pixel circuit comprising a first compensation capacitor, the first compensation capacitor comprising: a first plate and a second plate. The first plate is arranged in the same layer as the first portion of the first signal line and is electrically connected to the first signal line, and is arranged in the same layer as the second plate of the storage capacitor; the second plate is arranged in a different layer from the first plate of the first compensation capacitor and is insulated, wherein the orthographic projection of the second plate of the first compensation capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first compensation capacitor on the substrate.

[0049] At least one embodiment of the present disclosure further provides a display substrate, which includes a base substrate including a first opening area, a display area, a plurality of first signal lines, a plurality of second signal lines, and a first floating electrode. The first opening region includes a first opening and a first opening peripheral region surrounding the first opening; the display region at least partially surrounds the first opening region and includes: a first display region located on a first side of the first opening region; and a second display region located on a second side of the first opening region, wherein the first side and the second side are opposite to each other in a first direction, and the first display region and the second display region include a plurality of pixels; a plurality of first signal lines configured to provide first display signals to the plurality of pixels, the first signal lines extending along the first direction and passing through the first display region and the second display region; a plurality of second signal lines configured to provide second display signals to the plurality of pixels, the second signal lines extending along a second direction intersecting the first direction, portions of the plurality of second signal lines passing through the first opening peripheral region along the second direction, each of the plurality of second signal lines including a longitudinal winding portion located in the first opening peripheral region, wherein the longitudinal winding portion is partially disposed around the first opening; a longitudinal winding portion of the plurality of second signal lines that is closest to the first opening is an edge longitudinal winding portion, and the first floating electrode is disposed in the same layer as the edge longitudinal winding portion and is located on a side of the edge longitudinal winding portion that is adjacent to the first opening.

[0050] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present invention appears in more than one figure, the component is represented by the same reference numeral in each figure.

[0051] Figure 2A is a schematic plan view of a display substrate according to an embodiment of the present disclosure. Figure 2B for Figure 2A The figure includes a partially enlarged schematic diagram of the first opening area and the second opening area.

[0052] like Figure 2A and Figure 2BAs shown, the display substrate 20 includes a base substrate, and the base substrate includes a first opening area 202A, a second opening area 202B, an inter-opening area 2014, a display area 201 and a first signal line 23. The first opening area 202A includes a first opening 201A and a first opening peripheral area 203A surrounding the first opening 201A; the second opening area 202B is arranged adjacent to the first opening area 202A along the first direction R1, and includes a second opening 201B and a second opening peripheral area 203B surrounding the second opening 201B. The inter-opening area 2014 is located between the first opening area 202A and the second opening area 202B. The display area 201 at least partially surrounds the first opening area 202A, the second opening area 202B and the inter-opening area 2014, and includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and each of the sub-pixels includes a pixel circuit. As shown Figure 2B As shown, the first signal line 23 extends along the first direction R1, includes a first portion passing through the first opening peripheral area 202A, the inter-opening area 2014 and the second opening peripheral area 203B, and is configured to provide a first display signal to the pixel circuit.

[0053] For example, in Figure 2A and Figure 2B In the illustrated embodiment, the second opening region 202B and the first opening region 202A are arranged along a first direction R1. Thus, the inter-opening region 2014 is located between the first opening region 202A and the second opening region 202B in the first direction R1. Of course, in other embodiments, the second opening region 202B and the first opening region 202A may also be arranged along a second direction R2. In this case, the inter-opening region 2014 is located between the first opening region 202A and the second opening region 202B in the second direction R2. The presently disclosed embodiment does not limit the arrangement direction of the second opening region 202B and the first opening region 202A.

[0054] The display area 201 includes pixels arranged in an array, each pixel includes one or more sub-pixels, and also includes various signal lines for transmitting various electrical signals to the sub-pixels to realize the display function; the border area 204 includes various driving circuits, signal lines electrically connected to the sub-pixels, contact pads, etc., and the signal lines of the border area 204 are electrically connected (or formed as one) with the signal lines (such as gate lines, data lines, etc.) in the display area 201 to provide electrical signals (such as scanning signals, data signals, etc.) to the sub-pixels.

[0055] For example, the first opening 201A is configured to allow light from the display side of the display substrate to pass through to reach the camera and the distance sensor to achieve light sensing, thereby realizing functions such as image capture and distance sensing; for example, in the area corresponding to the first opening 201A, a camera, a distance sensor and other devices can be set on the back side of the display substrate (i.e., the side opposite to the display side), and the camera, the distance sensor, etc. are at least partially exposed through the first opening 201A.

[0056] For example, various signal lines from the border area 204 extend through the display area 201. When encountering the first opening area 201A, these signal lines pass through the first opening peripheral area 203A and bypass the first opening 201A, and then enter the display area 201 to provide electrical signals (such as scanning signals, data signals, etc.) to the sub-pixels passing through. Therefore, these signal lines do not need to be set in the first opening 201A to increase the light transmittance of the first opening 201A.

[0057] The display area 201 includes a first display area 2011 and a second display area 2012. The first display area 2011 is located on a first side of the first opening area 202A, and the second display area 2012 is located on a second side of the first opening area 202A, with the first side and the second side being opposite to each other in a first direction R1 (horizontal direction in the figure). For example, the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 are arranged in sequence along the first direction R1. The first display area 2011 and the second display area 2012 constitute a first pixel array. For example, the first pixel array includes a plurality of pixels arranged in an array, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.

[0058] by Figure 2BTaking the first signal line 2301 in the display as an example, the display substrate includes multiple first signal lines 2301 / 2302 / 2303 / 2304 / 2305 / 2306. The first signal line 2301 is configured to provide a first display signal to the first pixel array and sequentially passes through the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 along the first direction R1, thereby electrically connecting sub-pixels in the first display area 2011 and the second display area 2012 located on opposite sides of the first opening 201A. For example, the first display signal is provided to sub-pixels in the first display area 2011 and the second display area 2012 that are located at the same horizontal position as the sub-pixels in the first opening peripheral area 203A. In various embodiments, the first display signal can be any form of electrical signal, such as a gate scan signal, a light-emitting control signal, or a reset voltage signal. For example, multiple first signal lines 2301 / 2302 / 2303 / 2304 / 2305 / 2306 can provide one or more of scanning signals, light-emitting control signals, reset voltage signals, etc. to pixel circuits in the first display area 2011 and the second display area 2012.

[0059] For example, Figure 2A and Figure 2B As shown, the display substrate 20 further includes a third display area 2013. For example, the third display area 2013 includes a first portion 2013C located on a first side of the first display area 2011 and the second display area 2012 in the second direction R2, and a second portion 2013D located on a second side of the first display area 2011 and the second display area 2012 in the second direction R2. The first side of the first display area 2011 and the second side of the first display area 2011 and the second display area 2012 are opposite to each other in the second direction R2; the first portion 2013C and the second portion 2013D are both connected to the first display area 2011 and the second display area 2012.

[0060] For example, two edges 2013A and 2013B of the first portion 2013C of the third display area 2013, which are opposite to each other in the second direction R2, are aligned with an edge 2011A of the first display area 2011 extending along the second direction R2 and away from the first opening 201A, and an edge 2012A of the second display area 201 extending along the second direction R2 and away from the first opening 201A. The third display area 2013 includes multiple rows and columns of pixels. The display substrate 20 also includes multiple third signal lines 2307, which are located in the first portion 2013C and the second portion 2013D of the third display area 2013. Figure 2A and Figure 2BA third signal line 2307 located in the first portion 2031A of the third display area 2013 is shown as an example. The third signal line 2307 is configured to provide a third scanning signal to multiple rows of pixels in the third display area 2013 and extends along the first direction R1. For example, in this embodiment, the second signal line 24 sequentially passes through the second portion 2013D of the third display area 2013, the first opening peripheral region 203A, and the first portion 2013C of the third display area 2013 along the second direction R2, and is configured to provide a second display signal to multiple columns of pixels in the third display area 2013.

[0061] The third display area 2013 also includes a plurality of pixels, each pixel including a plurality of sub-pixels, and each sub-pixel including a pixel circuit. Each pixel of the third display area 2013 may have the same structure as each pixel of the first display area and the second display area. For example, in some embodiments, the number of pixels included in each row of pixels in the multiple rows and columns of sub-pixels in the third display area 2013 is substantially the same. At this time, the number of pixels electrically connected to the multiple third signal lines 2037 is substantially the same, so the multiple third signal lines 2037 have substantially the same load. For example, the number of pixels included in each row of pixels in the multiple rows and columns of pixels is greater than the number of pixels included in the first pixel row of the first pixel array, and greater than the number of pixels included in the second pixel row of the first pixel array. For example, after load compensation, the load of each first signal line 2301 / 2302 / 2303 / 2304 is basically the same as the load of multiple third signal lines 2037, and thus the signal transmission speed of each first signal line 2301 / 2302 / 2303 / 2304 is basically the same as that of each third signal line 2037, and the deviation between the actual display signal transmitted to the pixel circuit of the sub-pixel and the design value is basically consistent, thereby maintaining the display consistency of the display area 201 and improving the display effect of the display substrate 20.

[0062] like Figure 2B As shown, for example, the display substrate 20 further includes a first power line VDD, which is connected to the first voltage terminal and is configured to provide a first power supply voltage to the pixel circuit of one or more sub-pixels. For example, the first power line VDD includes a plurality of first sub-routes 2421 / 2422 extending along the first direction R1 and a plurality of second sub-routes 2423 / 2424 extending along the second direction R2. A first portion of the first sub-routes 2421 of the plurality of first sub-routes 2421 / 2422 is disconnected in the first opening area 202A, and a second portion of the first sub-routes 2422 of the plurality of first sub-routes 2421 / 2422 passes through the third display area. For example, in Figure 2BIn the embodiment, the first sub-routing 2422 runs through the first portion 2013C of the third display area 2013 along the first direction R1. The first portion of the second sub-routing 2423 among the plurality of second sub-routings 2423 / 2424 is disconnected at the first opening area 202A, and the second portion of the second sub-routing 2424 among the plurality of second sub-routings 2423 / 2424 sequentially runs through the first display area 2011 and the third display area 2013. For example, in this embodiment, the second portion 2013D of the third display area 2013, the first display area 2011, and the first portion 2013C of the third display area 2013 are sequentially run through. Alternatively, the second sub-routing 2424 runs through the second display area 2012 and the third display area 2013 sequentially. For example, in this embodiment, the second portion 2013D of the third display area 2013, the second display area 2012, and the first portion 2013C of the third display area 2013 are sequentially run through. The first sub-route 2421 of the first part and at least one second sub-route 2424 of the second part are electrically connected in the first display area 2011 and the second display area 2012 respectively, and the second sub-route 2423 of the first part and at least one first sub-route 2422 of the second part are electrically connected in the third display area 2013 to provide a first power supply voltage to the sub-pixels in each row and column of the first pixel array and the second pixel array.

[0063] The planar shape of the first opening area of ​​the display substrate provided in at least one embodiment of the present disclosure is not limited to a circle, and may also be a regular shape such as a rectangle, an ellipse, or a racetrack shape (for example, Figure 15 ), teardrop-shaped and other irregular shapes. In these cases, the setting principles and technical effects of the first signal line and the second signal line are the same or similar to those of the above circular example.

[0064] At least one of the inter-opening region 2014, the first opening peripheral region 203A, and the second opening peripheral region 203B includes a first virtual sub-pixel, for example, Figure 2C As shown, in this embodiment, the area between the openings 2014 includes the first virtual sub-pixel 11 as an example, that is, the first virtual sub-pixel 11 is located Figure 2C The structure of the first virtual sub-pixel will be described in detail later in the section A. Of course, the first virtual sub-pixel 11 may also be located in the first opening peripheral region 203A or / and the second opening peripheral region 203B.

[0065] The structure of the sub-pixels in the display area, such as the sub-pixel 12 in the portion B and the portion C in FIG. 3C , is introduced below.

[0066] Figure 3A FIG. 1 is a schematic cross-sectional view of a sub-pixel in a display area of ​​a display substrate. Figure 3AAs shown, the pixel circuit of each sub-pixel in the display area 201 of the display substrate 20 includes a transistor, which is described by taking a thin film transistor (TFT) as an example, as well as a light-emitting element 180 and a storage capacitor CST. The thin film transistor includes an active layer 120, a gate 121 and a source and drain electrode 122 / 123; the storage capacitor CST includes a first electrode plate CE1 and a second capacitor electrode plate CE2. The light-emitting element 180 includes a cathode 183, an anode 181 and a light-emitting layer 182 between the cathode 183 and the anode 181, and the anode 181 is electrically connected to one of the source and drain electrodes 122 / 123 of the thin film transistor TFT, such as the drain electrode 123. For example, the light-emitting element can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and accordingly, the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.

[0067] For example, Figure 3A As shown, the display area 201 further includes a first gate insulating layer 151 located between the active layer 120 and the gate electrode 121, a second gate insulating layer 152 located above the gate electrode 121, and an interlayer insulating layer 160. The second gate insulating layer 152 is located between the first electrode plate CE1 and the second capacitor electrode plate CE2, so that the first electrode plate CE1, the second gate insulating layer 152, and the second capacitor electrode plate CE2 constitute a storage capacitor CST. The interlayer insulating layer 160 covers the second capacitor electrode plate CE2.

[0068] For example, Figure 3A As shown, the display area 201 further includes an insulating layer 113 (such as a passivation layer) covering the pixel circuit and a first planarization layer 112. The display area 201 also includes a pixel definition layer 170 for defining a plurality of sub-pixels and spacers (not shown) on the pixel definition layer 170. Figure 3A As shown, in some embodiments, the insulating layer 113 is located above the source and drain 122 / 123 (for example, a passivation layer formed of materials such as silicon oxide, silicon nitride or silicon oxynitride), and a first planarization layer 112 is provided above the insulating layer 113. The anode 181 is electrically connected to the drain 123 through a via hole passing through the first planarization layer 112 and the insulating layer 113.

[0069] For example, Figure 3AAs shown, the first opening peripheral area 203A of the display substrate 20 further includes encapsulation layers 291, 292 and 293. The display area 201 further includes an encapsulation layer 190, and the encapsulation layer 190 includes a plurality of encapsulation sublayers 191 / 192 / 193. Of course, the encapsulation layer 190 is not limited to 3 layers, and can also be 2 layers, or 4 layers, 5 layers or more layers. For example, the first encapsulation layer 291 is arranged on the same layer as the first encapsulation sublayer 191 in the encapsulation layer 190, the second encapsulation layer 292 is arranged on the same layer as the second encapsulation sublayer 192 in the encapsulation layer 190, and the third encapsulation layer 293 is arranged on the same layer as the third encapsulation sublayer 193 in the encapsulation layer 190. For example, the first encapsulation layer 291 and the third encapsulation layer 293 can both include inorganic encapsulation materials, such as silicon oxide, silicon nitride or silicon oxynitride, and the second encapsulation layer 292 can include organic materials, such as resin materials. The multi-layer packaging structure of the display area 201 and the first opening peripheral area 203A can achieve a better packaging effect to prevent impurities such as water vapor or oxygen from penetrating into the interior of the display substrate 20 .

[0070] In some embodiments, as Figure 3A As shown, the display substrate further includes a buffer layer 111 located on the base substrate 210. The buffer layer 111 serves as a transition layer to prevent harmful substances in the base substrate 210 from invading the interior of the display substrate 20 and to increase the adhesion of the film layers in the display substrate 20 to the base substrate 210. For example, the material of the buffer layer 111 may include a single layer or a multilayer structure formed by insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0071] Figure 3B is another cross-sectional schematic diagram of a sub-pixel in the display area of ​​a display substrate. Figure 3A The display area shown is different from Figure 3B In the display area shown, the anode 181 of the light emitting element 180 is electrically connected to the drain 123 of the thin film transistor TFT via the switching electrode 171. At this time, the switching electrode 171 is covered with the second planarization layer 114, for example, the second planarization layer 114 is covered on the first planarization layer 112.

[0072] For example, in other embodiments, the display region of the display substrate may not have the insulating layer 113 and the second planarization layer 114 .

[0073] For example, in at least one embodiment of the present disclosure, the base substrate 210 may be a glass substrate, a quartz substrate, a metal substrate, or a resin substrate. For example, the material of the base substrate 210 may include an organic material, such as a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the base substrate 210 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

[0074] For example, the material of any one of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarizing layer 112, the pixel defining layer 170, and the spacer may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, or may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not specifically limit the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarizing layer 112, the pixel defining layer 170, and the spacer. For example, the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarizing layer 112, the second planarizing layer 114, the pixel defining layer 170, and the spacer may be the same or partially the same as each other, or may be different from each other, and the embodiments of the present disclosure do not limit this.

[0075] For example, Figure 2B As shown, the display substrate 20 may further include a barrier wall 28 located in the first opening peripheral region 203A and at least partially surrounding the first opening 201A. For example, in a direction perpendicular to the base substrate 210, the barrier wall 28 at least partially overlaps the first signal line and the second signal line. The barrier wall 28 can provide isolation and support in the first opening peripheral region 203A, maintaining the stability of the first opening 201A and protecting the photoelectric sensor device, such as the camera, within the first opening 201A. It also blocks harmful impurities, such as moisture and oxygen, from diffusing into the display area through the first opening 201A, thereby preventing these harmful impurities from degrading the pixel circuits in the display area.

[0076] Figure 4A A schematic diagram of a planar layout of a first virtual pixel circuit in a display substrate provided in an embodiment of the present disclosure is provided. For example, the first virtual pixel circuit is Figure 2C Local A in Figure 4B For the Figure 4A Schematic diagram of the cross section of line A2-B2 in FIG. Figures 4C-4G A schematic diagram of various layers of a first virtual pixel circuit of a display substrate provided in one embodiment of the present disclosure.

[0077] Combine Figures 2A-2C and Figures 4A-4B The first portion 2301A of the first signal line 2301 passes through the first virtual sub-pixel 11. The first virtual sub-pixel 11 includes a virtual pixel circuit, which includes a first compensation capacitor COM1. The first compensation capacitor COM1 includes a first plate CE11 and a second plate CE12. The first plate CE11 of the first compensation capacitor COM1 is disposed on the same layer as the first portion 2301A of the first signal line 2301 and is electrically connected to the first signal line 2301. It is also disposed on the same layer as the second plate CE2 of the storage capacitor CST. The second plate CE12 of the first compensation capacitor COM1 is disposed on a different layer from the first plate CE11 of the first compensation capacitor COM1 and is insulated from the first plate CE11 of the first compensation capacitor COM1. The orthographic projection of the second plate CE12 of the first compensation capacitor COM1 on the base substrate 210 at least partially overlaps with the orthographic projection of the first plate CE11 of the first compensation capacitor COM1 on the base substrate 210. The first compensation capacitor COM1 compensates for the load on the first signal line 2301, thereby reducing the display difference caused by the different loads on the first signal line connecting different rows of pixels due to the different number of pixels in different rows. This ensures that the display effect of the first display area 2011 and the second display area 2012 is consistent with the display effect of the pixel row in the display area 201 without the first opening area 202A, thereby improving the display quality. In addition, since the first electrode plate CE11 is arranged on the same layer as the second electrode plate CE2 of the storage capacitor CST, the first electrode plate CE11 can not only form a compensation capacitor with the metal layer located above it (in the direction away from the substrate), but also form a compensation capacitor with the semiconductor layer below it (in the direction close to the substrate). If the first electrode plate CE11 is arranged on the same layer as the above-mentioned gate 121, it will form a TFT with the semiconductor layer.

[0078] For example, Figure 4B and Figure 4E As shown, the first electrode plate CE11 of the first compensation capacitor COM1 and the first signal line 2301 are integrally formed.

[0079] For example, Figure 4BAs shown, the material of the second plate CE12 of the first compensation capacitor COM1 includes a semiconductor material and is a conductor, and is arranged in the same layer as the above-mentioned active layer 120. For example, the material of the second plate CE12 of the first compensation capacitor COM1 includes the same material as the active layer 120, such as a-Si, polysilicon, etc. For example, the second plate CE12 of the first compensation capacitor COM1 is heavily doped to enhance its conductivity so that it becomes a conductor. For example, this can be done at the same time as the active layer 120 is doped, because the second plate CE12 of the first compensation capacitor COM1 will not be blocked and heavy doping can be achieved. For example, the doping material is boron (B). When a voltage signal is applied to the second plate CE12, the semiconductor material is equivalent to a conductor, so it can serve as a capacitor plate, and the existing layers are fully utilized. It can be formed simultaneously with the active layer 120 through the same patterning process. The same patterning process refers to using the same mask template and performing the same exposure for patterning.

[0080] like Figures 4A-4B As shown, the virtual pixel circuit also includes a second compensation capacitor COM2, which includes a first plate CE21 and a second plate CE22. The first plate CE21 of the first compensation capacitor COM1 is reused as the first plate CE21 of the second compensation capacitor COM2; the second plate CE22 is arranged on a different layer from and insulated from the first plate CE21 of the second compensation capacitor COM2, and is arranged on the same layer as the source and drain electrodes 122 / 123. The orthographic projection of the second plate CE22 of the second compensation capacitor COM2 on the base substrate 210 at least partially overlaps with the orthographic projection of the first plate CE21 of the second compensation capacitor CE22 on the base substrate 210. The second compensation capacitor further compensates for the load on the first signal line 2301, thereby reducing display differences caused by different loads on the first signal line connecting different rows of pixels due to different numbers of pixels in different rows. This ensures that the display effects of the first display area 2011 and the second display area 2012 are consistent with the display effects of the pixel rows in the display area 201 without the first opening area 202A, thereby improving display quality. At the same time, the existing layer, ie the conductive layer where the source and drain electrodes 122 / 123 are located, is utilized, and the source and drain electrodes 122 / 123 can be formed by performing a single patterning process on the same film layer, thereby simplifying the manufacturing process of the display plate and saving costs.

[0081] For example, the second plate CE22 of the second compensation capacitor COM2 is electrically connected to the second plate CE12 of the first compensation capacitor COM1, so that the first compensation capacitor and the second compensation capacitor are connected in parallel, providing more effective compensation and a larger compensation range.

[0082] Figure 4H A schematic diagram of a first plate of a first compensation capacitor of another display substrate provided in one embodiment of the present disclosure. Figure 4HAs shown, the first plate CE11 of the first compensation capacitor COM1 includes a first extension portion 21 and a second extension portion 22. The first extension portion 21 is connected to the first portion 2301A of the first signal line 2303, extends from the first portion 2301A of the first signal line 2303, and is located on a first side of the first portion 2301A of the first signal line 2303 in a second direction R2. The second direction R2 intersects the first direction R1, for example, perpendicularly, but not limited to, thereto. The second extension portion 22 is connected to the first portion 2301A of the first signal line 2303, extends from the first portion 2301A of the first signal line 2303, and is located on a second side of the first portion 2301A of the first signal line 2303, opposite the first side in the second direction R2. This increases the area of ​​the first plate of the first compensation capacitor, thereby providing a wider compensation range as needed.

[0083] For example, the first extension portion 21 , the second extension portion 22 and the first portion 2301A of the first signal line 2303 are integrally formed.

[0084] For example, the display substrate further includes a first power line. The first power line is connected to the first voltage terminal, configured to provide the first power supply voltage to the above-mentioned pixel circuit, and is connected to the second electrode plate CE2 of the storage capacitor CST. The first power line includes: a plurality of first sub-routes extending along the first direction, and a plurality of second sub-routes extending along the second direction, and the plurality of second sub-routes are electrically connected to the plurality of first sub-routes. A first portion of the plurality of second sub-routes 2424 passes through the inter-opening area 2014 and passes through the first virtual sub-pixel 11. Figure 4F As shown, the second plate CE22 of the second compensation capacitor COM2 includes a first part CE221 and a second part CE222, the first part second sub-route 2424 is arranged on the same layer as the first part CE221 of the second plate of the second compensation capacitor and is electrically connected to serve as the second part CE222 of the second plate of the second compensation capacitor, and the first part second sub-route 2424 is electrically connected to the second plate CE12 of the first compensation capacitor COM1, thereby realizing the electrical connection between the second plate CE22 of the second compensation capacitor COM2 and the second plate CE12 of the first compensation capacitor COM1.

[0085] For example, the first portion of the second sub-trace 2424 and the second electrode plate CE22 of the second compensation capacitor COM2 are integrally formed.

[0086] Figure 4I For the Figure 4A A schematic cross-sectional view of the A3-B3 line in FIG. Figure 4IAs shown, the display substrate 20 further includes: a first insulating layer 151 (e.g., the first gate insulating layer) located between the second plate CE12 of the first compensation capacitor COM1 and the gate 121; a second insulating layer 152 (e.g., the second gate insulating layer) located between the gate 121 and the first plate CE11 of the first compensation capacitor COM1; and a third insulating layer 160 (e.g., the interlayer insulating layer) located between the first plate CE11 of the first compensation capacitor COM1 and the second plate CE22 of the second compensation capacitor COM2. The first portion of the second sub-trace 2424 is electrically connected to the second plate CE12 of the first compensation capacitor COM1 via a first via VH10 that penetrates the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160 and exposes the second plate CE12 of the first compensation capacitor COM1.

[0087] For example, Figure 2C As shown, the display substrate 20 further includes a plurality of second signal lines 24. The plurality of second signal lines 24 are configured to provide second display signals to the plurality of sub-pixels. A first portion of the plurality of second signal lines 2411 passes through the inter-opening region 2014 and the first virtual sub-pixel 11 along the second direction R2. Figure 4B The first portion of the second signal line 2411 is located on the side of the second electrode plate CE22 of the second compensation capacitor COM2 away from the substrate 210. Figure 4A and Figure 4B The first portion 21 of the second electrode plate CE22 of the second compensation capacitor COM2 has a hollow area H1, and the orthographic projection of the first portion of the second signal line 2411 of the first virtual sub-pixel 11 where the second electrode plate CE22 of the second compensation capacitor COM2 is located on the base substrate 210 at least partially overlaps with the hollow area H1, so as to reduce the overlapping area between the first portion of the second signal line 2411 and the second electrode plate CE22 of the second compensation capacitor COM2, reduce the capacitance formed by the overlap between the two, and thereby reduce the load on the first portion of the second signal line 2411.

[0088] For example, combined with Figure 4A and Figure 4B The second plate CE22 of the second compensation capacitor COM2 has multiple hollow regions H1 / H2. In this embodiment, two hollow regions H1 are used as an example. The multiple hollow regions are spaced apart from each other along the second direction R2. Thus, the load of the first portion of the second signal line 2411 can be adjusted in a gradient according to different needs.

[0089] For example, combined with Figure 4A and Figure 4FThe multiple hollow areas include an adjacent first hollow area H1 and a second hollow area H2. The length of the first hollow area H1 in the second direction R2 is different from the length of the second hollow area H2 in the second direction R2. The load of the first part of the second signal line 2411 can be adjusted differently according to the different load sizes of different parts of the first part of the second signal line 2411.

[0090] For example, combined with Figure 4A and Figure 4F The portion P of the second plate CE22 of the second compensation capacitor COM2 located between the first hollow area H1 and the second hollow area H2 is continuous along the first direction R1; the second plate CE22 of the second compensation capacitor COM2 includes a first edge and a second edge opposite to each other in the second direction R2, and at least one of the first edge and the second edge is disconnected by the hollow area.

[0091] For example, the first signal line includes a gate scan signal line and a reset signal line. For example, the first signal line 2303 is a gate scan signal line configured to provide a gate scan signal to a sub-pixel. Accordingly, the first display signal is a gate scan signal. The first signal line 2301 is a reset signal line configured to provide a reset voltage signal to a sub-pixel. Accordingly, the first display signal is a reset voltage signal. For example, the second signal line 24 is a data line configured to provide a data signal to a sub-pixel for controlling the grayscale of the sub-pixel's light emission.

[0092] For example, in some embodiments, in a first virtual sub-pixel 11, the second plate CE12 of the first compensation capacitor COM1 covers the entire first virtual sub-pixel 11, and the orthographic projection of the first plate CE11 of the first compensation capacitor COM1 on the base substrate 210 is located within the orthographic projection of the second plate CE12 of the first compensation capacitor COM1 on the base substrate 210. The size of the first compensation capacitor COM1 is smaller than the size of the second compensation capacitor COM2. Furthermore, the effective size of each plate of the first compensation capacitor COM1 and the second compensation capacitor COM2 can be adjusted as needed to adjust the size of the first compensation capacitor COM1 and the second compensation capacitor COM2.

[0093] For example, Figure 2A and 2B As shown, the display area 201 includes a first display area 2011 and a second display area 2012. The first display area 2011 is located on a side of the first opening area 202A away from the inter-opening area 2014; the second display area 2012 is located on a side of the second opening area 202B away from the inter-opening area 2014. The first display area 2011 and the second display area 2012 each include a plurality of pixels. Figure 4JAs shown, the first display area 2011 and the second display area 2012 comprise a plurality of pixel rows extending along a first direction R1, such as the first row, the second row, the third row, and so on. These plurality of pixel rows are separated by a first opening area 202A, an inter-opening area 2014, and a second opening area 202B. For example, the number of pixels in the first row of pixels differs from the number of pixels in the second row of pixels, and the number of first compensation capacitors in a first virtual pixel row corresponding to the first row of pixels differs from the number of first compensation capacitors in a second virtual pixel row corresponding to the second row of pixels, thereby equalizing the load on the first signal lines of pixels in different rows.

[0094] like Figure 2B As shown, the first signal line 2303 sequentially passes through the first display area 2011, the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the second display area 2012 along the first direction R1. The first signal line 2303 also includes a second portion 2303B passing through the first display area 2011 and a third portion 2303C passing through the second display area 2012. The second portion 2303B and the third portion 2303C are provided on the same layer as the gate 121. Therefore, the second portion 2303B and the first portion 2303A need to be switched layers, and the first portion 2303A and the third portion 2303C need to be switched layers.

[0095] Figure 5A for Figure 2C An enlarged schematic diagram of the local C in the figure. Figures 5B-5D They are Figure 2C The enlarged schematic diagram of local D, local E and local F in the figure is as follows: Figure 5E This is an enlarged schematic diagram of the area where the first signal line and the second signal line are switched layers. Figures 5F-5H Along Figure 5E Schematic cross-sectional view of the A4-B4 line, the A5-B5 line and the A6-B6 line.

[0096] Combine Figures 5A-5B and Figure 5EThe display substrate 20 further includes a first connection structure, for example, the first connection structure includes a first sub-connection structure 311 and a second sub-connection structure 312. For example, the first connection structure 311 / 312 is located in the first opening peripheral area 203A, for example, at the junction of the first opening peripheral area 203A and the first display area 2011, and is arranged in a different layer from the second portion 2303B / 2301B of the first signal line and the first portion 2303A / 2301A of the first signal line. The second portion 2303B / 2301B of the first signal line is electrically connected to the first connection structure 311 / 312, and the first portion 2303A / 2301A of the first signal line is electrically connected to the first connection structure 311 / 312, thereby achieving layer switching when the first signal line 2303 / 2301 enters the first opening peripheral area 203A from the first display area 2011.

[0097] For example, the first signal line 2303 is a gate scanning signal line, and the first signal line 2301 is a reset signal line. Figure 5E and Figure 5F The second part 2301B of the reset signal line and the first part 2301A of the reset signal line are set in different layers. The second part 2301B of the reset signal line is electrically connected to the second sub-connection structure 312 through the via VH11, and the first part 2301A of the reset signal line is electrically connected to the second sub-connection structure 312 through the via VH12, thereby realizing the electrical connection between the second part 2301B of the reset signal line and the first part 2301A of the reset signal line, thereby realizing the reset signal line 2301 is wired around the first opening after changing layers.

[0098] Similarly, combining Figure 5E and Figure 5G The second part 2303B of the gate scanning signal line and the first part 2303A of the gate scanning signal line are arranged in different layers. The second part 2303B of the gate scanning signal line is electrically connected to the first sub-connection structure 311 through the via VH13, and the first part 2303A of the gate scanning signal line is electrically connected to the first sub-connection structure 311 through the via VH14, thereby realizing the electrical connection between the second part 2303B of the gate scanning signal line and the first part 2303A of the gate scanning signal line, thereby realizing the gate scanning signal line 2303 is wired around the first opening after changing layers.

[0099] For example, the first connection structure and the second connection structure are provided in the same layer as the source and drain electrodes 122 / 123 .

[0100] The display substrate 20 also includes a second connection structure. For example, the second connection structure is located in the second opening peripheral region 203B, for example, at the junction of the second opening peripheral region 203B and the first display region. The second connection structure is disposed in a different layer from the first portion 2303A / 2301A of the first signal line and the third portion 2303C / 2301C of the first signal line. The first portion 2303A / 2301A of the first signal line is electrically connected to the second connection structure (not shown), and the third portion 2303C / 2301C of the first signal line is electrically connected to the second connection structure, thereby enabling the first signal line 2303 to switch layers again, i.e., switching layers when the first signal line 2303 enters the second display region 2012 from the second opening peripheral region 203B. For example, the second connection structure includes a third sub-connection structure and a fourth sub-connection structure, which are disposed corresponding to the gate scan signal line 2303 and the reset signal line 2301, respectively, to enable the gate scan signal line 2303 and the reset signal line 2301 to switch layers again. For example, the configuration of the third sub-connection structure and the fourth sub-connection structure may refer to the configuration of the first sub-connection structure and the second sub-connection structure. For example, in some embodiments, the third sub-connection structure and the fourth sub-connection structure are substantially symmetrical with the first sub-connection structure and the second sub-connection structure.

[0101] For example, Figure 5E As shown, the first gate line GLn and the second gate line GLn-1 that provide gate scan signals to the same row of sub-pixels 12 are switched layers through the same first sub-connection structure 311 to save space. For example, the reset signal line that provides reset voltage signals to multiple rows of sub-pixels can be switched layers through the same second connection structure 312 to save space. For example, the same second connection structure 312 is arranged in a zigzag pattern along the boundary between the first display area and the area surrounding the first opening to rationally utilize space and leave ample space for other structures such as the first connection structure and the second connection structure. Of course, in other embodiments, the switching layers can also be performed using multiple second connection structures 312 that are separated from each other.

[0102] Combine Figures 5C-5D and Figure 5EA portion of the second signal line 2410 passes from the display area into the area surrounding the first opening (the same applies to the second opening, using the first opening as an example), remaining located on the side of the source and drain electrodes 122 / 123 away from the base substrate 210, without undergoing a layer change. A portion of the second signal line 2412 passes from the display area into the area surrounding the first opening (the same applies to the second opening, using the first opening as an example). The second signal line 2412 includes a first portion 2412A that passes through the display area and a second portion 2412B that passes through the area surrounding the first opening 203A. The first portion 2412A of the second signal line 2412 is located on the side of the source and drain electrodes 122 / 123 away from the base substrate 210, while the second portion 2412B of the second signal line 2412 is provided on the same layer as the source and drain electrodes 122 / 123. Therefore, the second signal line 2412 requires a layer change.

[0103] Combine Figure 5E and Figure 5H The first portion 2412A of the second signal line 2412 is directly connected to the second portion 2412B of the second signal line 2412 through the via hole VH15 passing through the insulating layer 113, without the need to set up additional connecting electrodes, thereby simplifying the manufacturing process.

[0104] For example, the data line 2410 that does not change layers is adjacent to the data line 2412 that does change layers in the first direction.

[0105] Figure 6 This is an equivalent circuit diagram of a pixel circuit in an array substrate provided in one embodiment of the present disclosure. Figure 7A A schematic diagram of the planar layout of a pixel circuit in an array substrate provided in one embodiment of the present disclosure is provided. Figure 7A Take the layer structure of the pixel circuits in two adjacent sub-pixels as an example.

[0106] The data line 1 mentioned below is an example of the second signal line 24 .

[0107] Each of the plurality of sub-pixels 1030 includes a pixel circuit, which includes a light-emitting device, a storage capacitor CST, a driving transistor T1 (hereinafter referred to as a first transistor) and a data writing transistor T2 (hereinafter referred to as a second transistor), as well as a data line 1 and a first connection structure CP1. Each of the driving transistor T1 and the data writing transistor includes an active layer, a gate, a first electrode, and a second electrode. The driving transistor T1 is configured to control the light-emitting device to emit light, for example, to control the driving current that drives the light-emitting device to emit light. The data line 1 is connected to the first electrode of the data writing transistor T2 and is configured to provide the data writing transistor T2 with a data signal for controlling the display grayscale of the sub-pixel 1030. The data writing transistor T2 is configured to write the data signal to the gate of the driving transistor T1 in response to a first scanning signal applied to the gate of the data writing transistor T2. The first connection structure CP1 is connected to the gate of the driving transistor T1 and the first plate of the storage capacitor CST. The first connection structure CP1 and the data line 1 are arranged in different layers, that is, the first connection structure CP1 and the data line 1 are arranged in different layers, and an insulating layer exists between the first connection structure CP1 and the data line 1 in a direction perpendicular to the base substrate 210. Figure 6 and Figure 7A In the pixel circuit shown, if the first connection structure CP1 and the data line 1 are arranged in the same layer, the distance between the two is small, which will result in a large parasitic capacitance being formed between the first connection structure CP1 and the data line 1 in the horizontal direction. This phenomenon is particularly serious in high-resolution display panels. This parasitic capacitance will directly lead to an unsatisfactory display effect. Moreover, the parasitic capacitance formed between the first connection structure CP1 and the data line 1 is unstable because the data signal on the data line 1 is constantly changing during the display process. As the data signal is written into the gate of the driving transistor T1, that is, the data signal is written into the gate of the driving transistor T1, the parasitic capacitance is unstable. Figure 6 The N1 node in the circuit causes the N1 node signal to jump, thereby affecting the fluctuation of the current flowing through the N1 node and affecting the display effect. The first connection structure CP1 is Figure 6 Therefore, in the array substrate provided by the embodiment of the present disclosure, disposing the first connection structure CP1 and the data line 1 in different layers can reduce or avoid the formation of the parasitic capacitance between the two, thereby improving or avoiding the adverse effects on the display effect and achieving a more ideal display effect.

[0108] It should be noted that due to the pixel array arrangement, the aforementioned parasitic capacitance (hereinafter referred to as parasitic capacitance 1) forms between the data line 1 and the first connection structure CP1 corresponding to the same sub-pixel 1030. Parasitic capacitance (hereinafter referred to as parasitic capacitance 2) also forms between the data line 1 and the first connection structure CP1 corresponding to two adjacent sub-pixels. Simulations show that when the first connection structure CP1 and data line 1 are arranged on the same layer, the value of parasitic capacitance 1 can reach 0.07971fF, and the value of parasitic capacitance 2 can reach 0.05627fF. The crosstalk generated by these two factors on node N1 is 0.678%. A higher crosstalk value indicates greater interference and a greater adverse effect on the display.

[0109] In the array substrate provided by the embodiment of the present disclosure, the value of parasitic capacitance 1 is approximately 0.0321fF, and the value of parasitic capacitance 2 is up to 0.0242fF. The crosstalk degree generated by the two on the N1 node is 0.218%. This shows that the values ​​of parasitic capacitance 1 and parasitic capacitance 2 in the array substrate provided by the embodiment of the present disclosure are significantly reduced compared to the case where the two are arranged on the same layer, and the crosstalk degree generated on the N1 node is significantly reduced, thereby significantly improving the adverse effects caused by the display.

[0110] like Figure 6 As shown, in some embodiments, the pixel circuit includes multiple thin film transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, multiple signal lines connected to the multiple thin film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor CST. That is, the pixel circuit in this embodiment has a 7T1C structure. Accordingly, the multiple signal lines include gate lines GLn / GLn-1 (i.e., scan signal lines), a light emitting control line EM, a reset signal line RL, a data line DAT, and a first power line VDD. The gate lines GLn / GLn-1 may include a first gate line GLn and a second gate line GLn-1. For example, the first gate line GLn is used to transmit a gate scan signal, and the second gate line GLn-1 is used to transmit a reset voltage signal. The light emitting control line EM is used to transmit a light emitting control signal, for example, connected to a first light emitting control terminal EM1 and a second light emitting control terminal EM2. The gate of the fifth transistor T5 is connected to the first light-emitting control terminal EM1, or serves as the first light-emitting control terminal EM1, to receive the first light-emitting control signal; the gate of the sixth transistor T6 is connected to the second light-emitting control terminal EM2, or serves as the second light-emitting control terminal EM2, to receive the second light-emitting control signal.

[0111] It should be noted that the embodiments of the present disclosure include but are not limited to the pixel circuit of the above-mentioned 7T1C structure. The pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, etc., and the embodiments of the present disclosure are not limited to this.

[0112] For example, Figure 6 As shown, the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4. The first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5. The first drain D1 of the first thin film transistor T1 is electrically connected to the third source S3 of the third thin film transistor T3 and the sixth source S6 of the sixth thin film transistor T6.

[0113] For example, Figure 6 As shown, the second gate of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive a gate scan signal; the second source S2 of the second thin film transistor T2 is configured to be electrically connected to the data line DAT to receive a data signal; the second drain D2 of the second thin film transistor T2 is electrically connected to the first source S1 of the first thin film transistor T1.

[0114] For example, Figure 6 As shown, the third gate of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, the third source S3 of the third thin film transistor T3 is electrically connected to the first drain electrode D1 of the first thin film transistor T1, and the third drain D3 of the third thin film transistor T3 is electrically connected to the first gate of the first thin film transistor T1.

[0115] For example, Figure 6 As shown, the fourth gate of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset voltage signal, the fourth source S4 of the fourth thin film transistor T4 is configured to be electrically connected to the reset signal line RL to receive a reset voltage signal, and the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate of the first thin film transistor T1.

[0116] For example, Figure 6 As shown, the fifth gate of the fifth thin film transistor T5 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, the fifth source S5 of the fifth thin film transistor T5 is configured to be electrically connected to the first power line VDD to receive the first power signal, and the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.

[0117] For example, Figure 6As shown, the sixth gate of the sixth thin film transistor T6 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, the sixth source S6 of the sixth thin film transistor T6 is electrically connected to the first drain D1 of the first thin film transistor T1, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the light emitting device (for example Figure 6 The first display electrode (eg, Figure 6 Anode 181) is shown electrically connected. Figures 7A-7C The thin film transistor TFT in FIG. 1 is the sixth thin film transistor T6 .

[0118] For example, Figure 6 As shown, the seventh gate electrode of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal, and the seventh source electrode S7 of the seventh thin film transistor T7 is electrically connected to the first display electrode (eg Figure 6 The seventh drain electrode D7 of the seventh thin film transistor T7 is electrically connected to the reset signal line RL to receive a reset voltage signal. For example, the seventh drain electrode D7 of the seventh thin film transistor T7 can be electrically connected to the fourth source electrode S4 of the fourth thin film transistor T4 to achieve electrical connection with the reset signal line RL.

[0119] In this embodiment, the fourth transistor T4 and the seventh transistor T7 are reset transistors configured to provide a reset signal to the sub-pixel.

[0120] It should be noted that the reset voltage signal and the reset voltage signal may be the same signal.

[0121] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polycrystalline silicon thin film transistors. In the embodiments of the present disclosure, if the first electrode of any transistor is the source, then the second electrode is the drain; or, if the first electrode of any transistor is the drain, then the second electrode is the source. The source and drain of each transistor may be symmetrical in structure, so their source and drain may be physically indistinguishable. The source and drain of all or part of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0122] Figures 7B-7F This is a schematic diagram of various layers of a pixel circuit of an array substrate provided by an embodiment of the present disclosure. Figure 8A For the Figure 7A A schematic cross-sectional view of the A-A' line in FIG.

[0123] In some embodiments, as Figure 7AAs shown, the pixel circuit includes the above-mentioned thin film transistors T3, T4, T5, T6 and T7, a storage capacitor CST, a first gate line GLn connected to the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, a second gate line GLn-1, a light emitting control line EM, a reset signal line RL, a data line DAT and a first power line VDD.

[0124] Next, combine Figures 7A-7F and Figure 8A Specific features of the structure of the pixel circuit according to the embodiment of the present disclosure are described.

[0125] like Figure 7A and Figure 8A As shown, the data line 1 and the first connection structure CP1 both extend along the first direction, and the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210 are at least partially opposite to each other in the horizontal direction R2. This structure facilitates a compact pixel circuit structure. In this case, if the data line 1 and the first connection structure CP1 are arranged on the same layer, the parasitic capacitance between the two will be particularly significant. This arrangement not only improves or avoids the above-mentioned parasitic capacitance, but also achieves a compact pixel circuit structure, which is conducive to achieving high resolution of the array substrate. The horizontal direction R2 is parallel to the base substrate 210 and perpendicular to the first direction R1.

[0126] For example, the distance between the orthographic projection of the first connection structure CP1 on the substrate 210 and the orthographic projection of the data line 1 on the substrate 210 (the maximum distance between the edge of the orthographic projection of the first connection structure CP1 on the substrate 210 that is closest to the orthographic projection of the data line 1 on the substrate 210 and the edge of the orthographic projection of the data line 1 on the substrate 210 that is closest to the orthographic projection of the first connection structure CP1 on the substrate 210) is less than the horizontal dimension of a sub-pixel 1030, thereby further facilitating a compact pixel circuit structure. Even when the spacing between the first connection structure CP1 and the data line 1 in the horizontal direction R2 is very small, the aforementioned parasitic capacitance phenomenon does not occur. For example, the distance between the data line 1 and the first connection structure CP1 corresponding to the same sub-pixel 1030 is less than the horizontal dimension of the sub-pixel 1030 in the horizontal direction R2, and the distance between the data line 1 and the first connection structure CP1 in two adjacent sub-pixels is less than the horizontal dimension of the sub-pixel 1030 in the horizontal direction R2. For example, the horizontal dimension of a sub-pixel 1030 in the horizontal direction R2 is 30 μm to 90 μm.

[0127] Furthermore, for example, there is a gap between the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210. Alternatively, in some embodiments, there is substantially no gap between the orthographic projection of the first connection structure CP1 on the base substrate 210 and the orthographic projection of the data line 1 on the base substrate 210. In other words, they are substantially in contact, which is conducive to achieving high resolution. In this case, the array substrate provided by the embodiments of the present disclosure can also prevent the above-mentioned parasitic capacitance phenomenon.

[0128] For example, the pixel circuit includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer. Figure 7A A schematic layout diagram showing the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel circuit is shown.

[0129] Figure 7B The semiconductor layer of the pixel circuit is shown. For example, Figure 7B The semiconductor layer shown includes an active layer A1 of a first thin film transistor T1, an active layer A2 of a second thin film transistor T2, an active layer A3 of a third thin film transistor T3, an active layer A4 of a fourth thin film transistor T4, an active layer A5 of a fifth thin film transistor T5, an active layer A6 of a sixth thin film transistor T6, and an active layer A7 of a seventh thin film transistor T7. Figure 7B As shown, the semiconductor layer can be formed by patterning a semiconductor material layer. The semiconductor layer can be used to manufacture the above-mentioned active layer of each transistor, which may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor material (for example, indium gallium tin oxide (IGZO)), etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0130] In the array substrate provided in some embodiments of the present disclosure, a first insulating layer is formed on the semiconductor layer. Figure 7A 、 Figures 7B-7K The individual insulating layers are not shown. Figure 7B and Figure 8A The first insulating layer 151 of the pixel circuit is disposed on a side of the first conductive layer away from the base substrate 210 .

[0131] Figure 7C shows the first conductive layer of the pixel circuit, Figure 7G Schematic diagram of the stacking of the first conductive layer and the semiconductor layer is shown. The first conductive layer is located on the side of the semiconductor layer away from the base substrate 210. Figure 7C 、 Figure 7G and Figure 8AThe first insulating layer 151 is located between the active layer of each transistor and the first conductive layer. For example, the first conductive layer includes the first electrode CE1 of the storage capacitor CST, the first gate line GLn, the second gate line GLn-1, the light-emitting control line EM, and the gates of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7. Therefore, the active layers of the above-mentioned transistors are arranged on the same layer, and the gates of the above-mentioned transistors are arranged on the same layer as the first electrode CE1 of the storage capacitor CST. As a result, the first insulating layer 151 is located between the active layer of each transistor and the gates of each transistor and the first electrode CE1 of the storage capacitor CST. As can be seen, the gate of the driving transistor, i.e., the first transistor T1 (or the gates of each transistor), and the first electrode CE1 of the storage capacitor CST are located on the side of the active layer of the driving transistor (or the active layer of each transistor) away from the base substrate 210.

[0132] Combine Figures 7A-7C and Figure 7G As shown, the gates of the second thin-film transistor T2, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 are the portions where the first gate line GLn and the second gate line GLn-1 overlap with the semiconductor layer, respectively. In some embodiments, for example, the third thin-film transistor T3 may be a dual-gate thin-film transistor, one gate of the third thin-film transistor T3 may be the portion where the first gate line GLn overlaps with the semiconductor layer, and the other gate of the third thin-film transistor T3 may be a protrusion from the first gate line GLn. The gate of the first thin-film transistor T1 may be integrally formed with the first electrode plate CE1, i.e., the first electrode plate CE1 serves as the gate of the first thin-film transistor T1. For example, the fourth thin-film transistor T4 may be a dual-gate thin-film transistor, with both gates being the portions where the second gate line GLn-1 overlaps with the semiconductor layer.

[0133] For example, the gates of the thin film transistors are integrally formed with the corresponding first gate line GLn or second gate line GLn-1. In this embodiment, the first gate line GLn, the second gate line GLn-1, and the gates of the thin film transistors are disposed on the same layer as the first electrode plate CE1 of the storage capacitor CST and can be formed simultaneously through the same patterning process.

[0134] For example, Figure 7AAs shown, the array substrate 100 further includes a first power line VDD, which is connected to the first voltage terminal and the second plate CE2 of the storage capacitor CST and is configured to provide a first voltage to the light-emitting control transistor, namely, the first transistor T1. For example, the first power line VDD includes a first sub-trace 21 extending along a first direction R1 and a second sub-trace 22 extending along a second direction. The first direction R1 intersects the second direction, for example, the second direction is a transverse direction R2. The first sub-trace 21 is electrically connected to the second sub-trace 22.

[0135] Figure 7D shows the second conductive layer of the pixel circuit, Figure 7H Schematic diagram of the second conductive layer and the semiconductor layer after being stacked. The second conductive layer is located on the side of the first conductive layer away from the base substrate 210. For example, Figure 7D 、 Figure 7H and Figure 8A The second conductive layer of the pixel circuit includes the second plate CE2 of the storage capacitor CST, the reset signal line RL, and the second sub-line 22. It can be seen that the second sub-line 22 is arranged in the same layer as the second plate CE2 of the storage capacitor CST, and the second plate CE2 of the storage capacitor CST is located on the side of the gate of the driving transistor, namely the first transistor T1 (or the gates of each transistor), and the first plate CE1 of the storage capacitor CST, away from the active layer. For example, the second sub-line 22 and the second plate CE2 of the storage capacitor CST are integrally formed, and can be formed using the same patterning process. The second plate CE2 at least partially overlaps with the first plate CE1 to form the storage capacitor CST.

[0136] For example, in some embodiments, in combination Figure 7A and Figure 7D The second conductive layer may further include a light shielding portion 791. The orthographic projection of the light shielding portion 791 on the base substrate 210 covers at least a portion of the active layer of the second thin film transistor T2, the drain electrode of the third thin film transistor T3, and the active layer between the drain electrodes of the fourth thin film transistor T4, thereby preventing external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4. The light shielding portion 791 can be electrically connected to the first power line VDD through a via hole VH9 penetrating the insulating layer, as shown in FIG. Figure 7A and as shown in Figure 8C.

[0137] In at least one embodiment of the present disclosure, Figure 7A and Figure 7KAs shown, for example, in a sub-pixel, in the horizontal direction R2, the first connection structure CP1 is located between the first sub-line 21 and the data line 1 (the pixel circuit of the same sub-pixel as the first connection structure CP1 and the first sub-line 21). In this case, in the horizontal direction, there is no structure such as the first power line extending along the first direction R1 between the first connection structure CP1 and the data line 1, so the spacing between the first connection structure CP1 and the data line 1 is smaller, which will result in a more significant parasitic capacitance being formed between the first connection structure CP1 and the data line 1 in the horizontal direction. Therefore, in this case, in the array substrate provided by the embodiment of the present application, arranging the first connection structure CP1 and the data line 1 in different layers has a more significant effect of reducing the signal interference of the data line 1 on the first connection structure CP1.

[0138] In addition, compared with the situation where the first sub-route 21 is located between the first connection structure CP1 and the data line (the pixel circuit belonging to the same sub-pixel as the first connection structure CP1 and the first sub-route 21), the length of the first connection structure CP1 in the first direction R1 is smaller, and the width of the first connection structure CP1 in the horizontal direction R2 is also smaller. Therefore, the second conductive layer can also include the above-mentioned light-shielding portion 791 to block the active layer of the second thin-film transistor T2, the third thin-film transistor T3 and the fourth thin-film transistor T4. The second conductive layer can be used to achieve this purpose, thereby simplifying the manufacturing process of the array substrate.

[0139] For example, Figure 8A As shown, the array substrate 100 further includes a second insulating layer 152, which is located between the first plate CE1 of the storage capacitor CST and the second plate CE2 of the storage capacitor CST, that is, between the first conductive layer and the second conductive layer. Figures 7B-7F The second insulating layer 152 is also not shown.

[0140] The array substrate 100 further includes a second power line VSS. For example, the first power line VDD is a power line that provides a high voltage to the pixel circuit, and the second power line VSS is connected to the second voltage terminal. The second power line VSS is a power line that provides a low voltage (lower than the aforementioned high voltage) to the pixel circuit. Figure 6 In the illustrated embodiment, the first power line VDD provides a constant first power voltage, which is a positive voltage; the second power line VSS provides a constant second power voltage, which can be a negative voltage, etc. For example, in some examples, the second power voltage can be a ground voltage.

[0141] In some embodiments, for example, Figure 8A As shown, the data line 1 (DATA) is located on the side of the first connection structure CP1 away from the base substrate 210. In this case, for example, Figure 7Eshows the third conductive layer of the pixel circuit, Figure 7I FIG3 shows a schematic diagram of a stack of the third conductive layer and the semiconductor layer. The third conductive layer is located on the side of the second conductive layer away from the substrate 1. For example, Figure 7E and Figure 7I As shown, the third conductive layer of the pixel circuit includes a first connection structure CP1 and a first sub-line 21 of the first power line VDD, that is, the first connection structure CP1 and the first sub-line 21 are arranged on the same layer. Figure 8A As shown, the array substrate 100 further includes a third insulating layer 160 . The third insulating layer 160 is located between the second electrode plate CE2 of the storage capacitor CST and the first connection structure CP1 , that is, between the second conductive layer and the third conductive layer.

[0142] For example, the first sub-trace 21 is electrically connected to the second sub-trace 22 through a via hole (eg, via hole VH3 ) penetrating the third insulating layer 160 .

[0143] For example, combined with Figure 7A 、 Figure 7E and Figure 8A8C , the third conductive layer further includes a second connection structure CP2, a third connection structure CP3, and a fourth connection structure CP4. One end of the first connection structure CP1 is connected to the first electrode plate CE1 of the storage capacitor CST via a via (e.g., via VH5) that penetrates the second insulating layer 152 and the third insulating layer 160 and exposes a portion of the first electrode plate CE1 of the storage capacitor CST. The other end of the first connection structure CP1 is connected to the semiconductor layer via at least one via (e.g., via VH4) that penetrates the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160, for example, to the drain region of the semiconductor layer corresponding to the third thin film transistor T3. One end of the second connection structure CP2 is connected to the reset signal line RL through a via (e.g., via VH6) penetrating the third insulating layer 160. The other end of the second connection structure CP2 is connected to the semiconductor layer through at least one via (e.g., via VH7) penetrating the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160, for example, to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer. The third connection structure CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via (e.g., via VH8) penetrating the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160. The fourth connection structure CP4 is connected to the drain region of the fifth thin film transistor T5 in the semiconductor layer through at least one via (e.g., via VH2) penetrating the first insulating layer 151, the second insulating layer 152, and the third insulating layer 160. The fifth connection structure CP5 is connected to the drain region of the third thin film transistor T3 in the semiconductor layer through at least one via hole (eg, via hole VH1 ) penetrating the first insulating layer 151 , the second insulating layer 152 , and the third insulating layer 160 and exposing a portion of the semiconductor layer.

[0144] For example, Figure 7F shows the fourth conductive layer of the pixel circuit, Figure 7J shows a schematic diagram of the fourth conductive layer and the semiconductor layer after being stacked, Figure 7K Schematic diagram of the stacking of the fourth conductive layer, the third conductive layer and the semiconductor layer is shown. Figure 7A 、 Figure 7E-7F 、 Figure 7J-7K and Figure 8AAs shown, the fourth conductive layer is located on a side of the third conductive layer away from the base substrate 210. The fourth conductive layer includes a data line 1 (DATA), a sixth connection structure CP6, and a seventh connection structure CP7. The array substrate 100 also includes a fourth insulating layer 113, which is located between the third conductive layer and the fourth conductive layer, that is, between the first connection structure CP1 and the data line 1 (DATA). For example, the fourth insulating layer 113 is a flat layer. The via VH1 also penetrates the fourth insulating layer 113 to expose at least a portion of the fifth connection structure CP5. The data line 1 (DATA) is electrically connected to the fifth connection structure CP5 through the via VH1, thereby achieving electrical connection between the data line 1 (DATA) and the drain region of the third thin film transistor T3 in the semiconductor layer. For example, the seventh connection structure CP7 is in direct contact with the data line 1 to achieve electrical connection between the two. Since the line width of the data line 1 is relatively small, for example, it is significantly smaller than the line width of the first sub-line 21, the seventh connection structure CP7 can widen the portion of the data line 1 that needs to be connected to the semiconductor layer. For example, the entire structure of the data line 1 and the seventh connection structure CP7 is electrically connected to the fifth connection structure CP5 through the via VH1, thereby achieving electrical connection between the data line 1 (DATA) and the drain region of the third thin film transistor T3 in the semiconductor layer. For example, the seventh connection structure CP7 is integrally formed with the data line 1. For example, the via VH2 also penetrates the fourth insulating layer 113 to expose at least a portion of the fourth connection structure CP4, and the sixth connection structure CP6 is electrically connected to the fourth connection structure CP4 through the via VH2, thereby achieving connection between the sixth connection structure CP6 and the drain region of the corresponding fifth thin film transistor T5 in the active layer to serve as the drain of the fifth thin film transistor T5. For example, the sixth connection structure CP6 is used to connect to the anode of the light-emitting device (for example Figure 6 For example, in different sub-pixels 1030, for example, Figure 7A In the two adjacent sub-pixels 1030 shown, the shape, size and position of the sixth connection structure CP6 may not be exactly the same, so as to meet the requirements of the anode positions of the corresponding sub-pixels with different shapes. Figure 7A The shape, size, and position of the sixth connection structure CP6 in the left sub-pixel 1030 are different from those in the right sub-pixel 1030. This is because the positions of the anodes in the two sub-pixels are different. The shape, size, and position of the sixth connection structure CP6 extend in a direction intersecting the first direction R1 and the transverse direction R2, and the position of its upper end (the end not connected to the fourth connection structure CP4) is such that it is connected to the anode located at the upper end.

[0145] For example, the thickness of the fourth insulating layer 113 in a direction perpendicular to the base substrate 210 is greater than at least one of the thickness of the first insulating layer 151 in a direction perpendicular to the base substrate 210, the thickness of the second insulating layer 152 in a direction perpendicular to the base substrate 210, the thickness of the third insulating layer 160 in a direction perpendicular to the base substrate 210, and the thickness of the fourth insulating layer 113 in a direction perpendicular to the base substrate 210. This enhances the insulating effect of the fourth insulating layer 113 and better reduces or avoids parasitic capacitance between the data line 1 and the first connection structure CP1.

[0146] For example, the thickness of the fourth insulating layer 113 in a direction perpendicular to the base substrate 210 is several microns, for example, less than 5 μm to 10 μm. This thickness range can effectively reduce or avoid the parasitic capacitance between the data line 1 and the first connection structure CP1 without excessively increasing the size of the array substrate 100.

[0147] In the above embodiment, the first sub-routing 21 and the data line 1 are arranged on different layers. Since the spacing between the adjacent first sub-routing 21 and the data line 1 is relatively small, this design can avoid the generation of parasitic capacitance between the first sub-routing 21 and the data line, thereby preventing the parasitic capacitance from affecting the display effect. For example, the adjacent first sub-routing 21 and the data line 1 correspond to two adjacent sub-pixels respectively.

[0148] refer to Figure 7A and Figure 8A For example, the orthographic projection of the first connection structure CP1 on the base substrate 210 does not overlap with the orthographic projection of the data line 1 on the base substrate 210, and the orthographic projection of the first trace 21 on the base substrate 210 does not overlap with the orthographic projection of the data line 1 on the base substrate 210. Compared to the above situation where the signal lines overlap in a direction perpendicular to the base substrate 210, this solution of the embodiment of the present disclosure can better prevent crosstalk between the signals on these signal lines.

[0149] For example, to reduce the resistance of the data line and the first connection structure, the data line 1 and the first connection structure CP1 are both made of metal. For example, the fourth conductive layer forming the data line 1 uses a three-layer metal stacked structure Ti / Al / Ti.

[0150] Figure 8C shows the Figure 7A A schematic cross-sectional view of line BB' in FIG. The plurality of sub-pixels includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel. Figure 7A Two adjacent sub-pixels are shown, the first sub-pixel is Figure 7A The second sub-pixel is the left sub-pixel in the middle. Figure 7AThe sub-pixels on the right side, namely the first sub-pixel and the second sub-pixel, are adjacent in the horizontal direction; of course, in other embodiments, the first sub-pixel and the second sub-pixel may also be adjacent in the vertical direction, and the directions and positions of other structures can be adaptively adjusted. Figure 7A 、 Figure 7G As shown in Figure 8C , the first reset transistor T4 includes an active layer A4, a gate (the portion of GLn-1 that overlaps with the active layer A4), a first electrode (e.g., a source electrode), and a second electrode (e.g., a drain electrode). The second reset transistor T7 includes an active layer A7, a gate (the portion of gate line GLn-1 that overlaps with the active layer A7), a first electrode (e.g., a source electrode), and a second electrode (e.g., a drain electrode). The active layer of the first reset transistor T4 includes a channel region (the portion of the active layer A4 that overlaps with the gate line GLn-1) and an electrode region E1. The active layer A7 of the second reset transistor T7 includes a channel region (the portion of the active layer A7 that overlaps with the gate line GLn-1) and an electrode region E1. The first reset transistor T4 and the second reset transistor T7 share the same electrode region E1. For example, the second connection structure CP2 extends along the first direction R1 and includes a first end and a second end that are opposite to each other in the first direction R1. The second connection structure CP2 of the pixel circuit of the second subpixel is located in the channel region of the active layer of the first reset transistor T4 and the channel region of the active layer of the second reset transistor T7 in the pixel circuit of the first subpixel in the lateral direction R2, on a side of the channel region near the data line 1 of the pixel circuit of the first subpixel. The first end of the second connection structure CP2 is electrically connected to the reset signal line RL via a via VH6, and the second end of the second connection structure CP2 is electrically connected to the electrode region E1 of the active layer of the reset transistors (T4 and T7) in the pixel circuit of the second subpixel via a via VH7. Thus, the second connection structure CP2 constitutes the first electrode and the second electrode of the first reset transistor T4 and the second reset transistor T7.

[0151] Combine Figure 7A 、 Figure 7GAs shown in Figure 8C , the electrode region E1 of the active layer of the first reset transistor T4 and the second reset transistor T7 of the pixel circuit of the second subpixel extends laterally from the first subpixel into the adjacent second subpixel, and the orthographic projection of the electrode region E1 of the active layer of the first reset transistor T4 and the second reset transistor T7 of the pixel circuit of the second subpixel on the substrate at least partially overlaps with the orthographic projection of the data line 1 of the pixel circuit of the first subpixel on the substrate. That is, the electrode region E1 of the active layer of the first reset transistor T4 and the second reset transistor T7 intersects with the data line 1, allowing for more flexible and full utilization of the limited pixel area to form the desired semiconductor layer pattern that facilitates connection to other structures. Because the electrode region E1 of the active layer that overlaps with the projection of the data line 1 is relatively far from the second conductive layer where the data line 1 is located in a direction perpendicular to the substrate, the intersection of the two does not interfere with each other's signals.

[0152] It should be noted that in Figure 7A 、 Figure 7F 、 Figure 7J and Figure 7K Three data lines 1 are shown, and the three data lines 1 belong to the pixel circuits of three adjacent sub-pixels respectively; the data line 1 in the middle belongs to the pixel circuit of the first sub-pixel, and the data line 1 on the right belongs to the pixel circuit of the second sub-pixel.

[0153] Figure 9 for Figure 6 The signal timing diagram of the pixel circuit is shown below. Figure 9 The signal timing diagram shown is Figure 6 For example, the working principle of the pixel circuit shown in FIG. Figure 6 The first light control line EM1 and the second light control line EM2 are the same common light control line as an example. In other embodiments, the first light control line EM1 and the second light control line EM2 may also be different signal lines, providing different first light control signals and second light control signals respectively.

[0154] In addition, here Figure 9 The transistors shown are all P-type transistors. The gate of each P-type transistor is turned on when a low level is connected, and is turned off when a high level is connected. The following embodiments are the same and will not be repeated here.

[0155] like Figure 9 As shown, the working process of the pixel circuit includes three stages, namely the reset stage P1, the data writing and compensation stage P2 and the light emitting stage P3. The figure shows the timing waveform of each signal in each stage.

[0156] During the reset phase P1, the second gate line Gn-1 provides a reset signal Rst, and the fourth transistor T4 and the seventh transistor T7 are turned on by the low level of the reset signal. The reset signal (a low level signal, for example, which can be grounded or another low level signal) is applied to the first gate of the first transistor T1, and the reset signal is applied to the N4 node, thereby resetting the light-emitting element 180. This allows the light-emitting element 180 to be displayed in a black state and not emit light before the light-emitting phase P3, thereby improving the contrast and other display effects of the display device using this pixel circuit. At the same time, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off by the high level signals connected to them.

[0157] During the data writing and compensation phase P2, the first gate line GLn provides a scan signal Gn-1, the data line DAT provides a data signal Data, and the second transistor T2 and the third transistor T3 are turned on. Simultaneously, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off by the high-level signals connected to them. The data signal Data charges the first node N1 (i.e., charges the storage capacitor CST) after passing through the second transistor T2, the first transistor T1, and the third transistor T3. In other words, the potential of the first node N1 gradually increases. It is easy to understand that since the second transistor T2 is turned on, the potential of the second node N2 remains at Vdata. At the same time, according to the inherent characteristics of the first transistor T1, when the potential of the first node N1 increases to Vdata+Vth, the first transistor T1 is turned off, and the charging process ends. It should be noted that Vdata represents the voltage value of the data signal Data, and Vth represents the threshold voltage of the first transistor T1. Since the first transistor T1 is described as a P-type transistor in this embodiment, the threshold voltage Vth here can be a negative value.

[0158] After the data writing and compensation stage P2, the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is, the voltage information with the data signal Data and the threshold voltage Vth is stored in the storage capacitor CST, so as to provide grayscale display data and compensate for the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.

[0159] During the light-emitting phase P3, the light-emitting control line provides the light-emitting control signal EM, and the fifth and sixth transistors T5 and T6 are turned on by the low-level light-emitting control signal EM. The second, third, fourth, and seventh transistors T2, T3, T4, and T7 are turned off by the high-level voltages connected to them. Simultaneously, the potential of the first node N1 is Vdata + Vth, and the potential of the second node N2 is VDD, so the first transistor T1 also remains on during this phase. The anode and cathode of the light-emitting element 180 are connected to the first power supply voltage (high voltage) and the second voltage VSS (low voltage) provided by the first power supply line VDD, respectively. Consequently, the light-emitting element 180 emits light under the action of the drive current flowing through the first transistor T1.

[0160] For example, the display substrate further includes a third signal line extending along the first direction, including a first portion passing through the first opening peripheral region, the inter-opening region, and the second opening peripheral region, and configured to provide a third display signal to the pixel circuit. The first portion of the third signal line is disposed on the same layer as the gate electrode; for example, the third display signal is a light-emitting drive scanning signal (EM line).

[0161] For example, the display substrate further includes a second virtual sub-pixel, and the second virtual sub-pixel includes a second virtual pixel circuit as shown in FIG16. The second virtual pixel circuit includes a virtual semiconductor layer, which is disposed on the same layer as the active layer and is electrically connected to the first portion of the second sub-routing. The orthographic projection of the first portion of the third signal line on the base substrate at least partially overlaps with the orthographic projection of the virtual semiconductor layer on the base substrate to form a third compensation capacitor.

[0162] Figure 16A A schematic planar layout diagram of a second virtual pixel circuit in a second virtual sub-pixel (the virtual sub-pixel on the right side of the figure) in a display substrate provided by one embodiment of the present disclosure; Figure 16B For the Figure 16A A schematic cross-sectional view of line A3-B3 in FIG; Figures 16C-16F A schematic diagram of various layers of a second virtual pixel circuit of a display substrate provided in one embodiment of the present disclosure.

[0163] In some embodiments, for example, the inter-opening region 2014 further includes a second virtual sub-pixel, and the second virtual sub-pixel includes a second virtual pixel circuit, such as Figure 16A The second virtual pixel circuit includes a second compensation capacitor COM10, and the second compensation capacitor COM10 includes a first electrode plate CE10 and a second electrode plate CE20.

[0164] Figure 16D shows a structure of a second virtual pixel circuit located in the first conductive layer, Figure 16EThe structure of the second dummy pixel circuit located in the second conductive layer is shown.

[0165] Combine Figures 16A-16B and Figure 16D-16E The first plate CE10 of the fourth compensation capacitor COM10 is disposed on the same layer as the first signal line 2301, for example, both are located on the first conductive layer, and the first plate CE10 of the fourth compensation capacitor COM10 is electrically connected to the first signal line 2301. The orthographic projection of the first signal line 2301 on the base substrate 210 at least partially overlaps with the orthographic projection of the second plate CE20 of the fourth compensation capacitor COM10 on the base substrate 210.

[0166] like Figure 16D As shown, the first electrode CE10 of the fourth compensation capacitor COM10 includes a second main portion CE100 and a third extension portion CE101. The second main portion CE100 is located on a first side of the first signal line 2301 in the second direction R2. The third extension portion CE101 extends from the second main portion CE100 toward the first signal line 2301 in the second direction R2, is located on a first side of the first signal line 2301 in the second direction, and is located between the second main portion CE100 and the first signal line 2301. The second main portion CE100 is electrically connected to the first signal line 2301 via the third extension portion CE101. For example, the first electrode CE20 plate of the fourth compensation capacitor COM10 includes a fourth extension portion CE102, which extends from the first signal line 2301 toward a direction away from the second main body portion CE100, is located on the second side of the first signal line 2301 in the second direction R2 and is electrically connected to the first signal line 2301, and the second side of the first signal line 2301 is opposite to the first side of the first signal line 2301, thereby further increasing the area of ​​the first electrode plate CE10 of the fourth compensation capacitor COM10. If the area of ​​the second electrode plate of the fourth compensation capacitor COM10 is increased at the same time, the fourth compensation capacitor COM10 can be further increased to meet the requirements of different compensation degrees for the first signal line.

[0167] For example, the second main portion CE100, the third extension portion CE101, the first signal line 2301 and the fourth extension portion CE102 are integrally formed, so that these structures can be formed using the same patterning process, simplifying the manufacturing process of the display substrate.

[0168] Combine Figures 16A-16B and Figure 16EThe second plate CE20 of the fourth compensation capacitor COM10 includes a third main portion CE200 and a fifth extension portion CE201. The third main portion CE200 is located on a first side of the first signal line 2301 in the second direction R2. The fifth extension portion CE201 extends from the third main portion CE200 in the second direction R2 toward the first signal line 2301. The orthographic projection of the first signal line 2301 on the substrate 210 at least partially overlaps with the orthographic projection of the fifth extension portion CE201 on the substrate 210.

[0169] For example, Figure 16B As shown, the orthographic projection of the first plate CE10 of the fourth compensation capacitor COM10 on the base substrate 210 is located within the orthographic projection of the second plate CE20 of the fourth compensation capacitor COM10 on the base substrate 210, so as to maximize the utilization of the area of ​​the first plate CE10 of the fourth compensation capacitor COM10 and form the required size of the fourth compensation capacitor using limited space.

[0170] For example, Figure 16E As shown, a portion 7921 of the second electrode plate CE20 of the fourth compensation capacitor COM10 may be located in the same position and pattern as the light shielding portion in the pixel circuit of the display area to maintain etching uniformity.

[0171] For example, the second virtual sub-pixel includes a second virtual semiconductor layer, and the second virtual semiconductor layer is located on a side of the first electrode plate of the fourth compensation capacitor close to the base substrate. Figure 16C The pattern of the second virtual sub-pixel is shown. Figure 16C The right side is in the virtual sub-pixel A02. Figure 16A and Figure 16C As shown, the second virtual semiconductor layer includes a first portion AP21 and a second portion AP22 that are spaced apart and not connected to each other. The first portion AP21 is located on a first side of the first signal line 2301, and the second portion AP22 is located on a second side of the first signal line 2301. The orthographic projection of the first signal line 2301 on the base substrate 210 does not overlap with the orthographic projection of the first virtual semiconductor layer on the base substrate 210. As a result, no actual thin-film transistors exist in the second virtual pixel circuit, and no display function is implemented. For example, the orthographic projection of the fourth compensation capacitor COM10 on the base substrate 210 does not overlap with the orthographic projection of the first virtual semiconductor layer on the base substrate.

[0172] Figure 16F The structure of the second virtual pixel circuit located in the third conductive layer is shown. Figures 16A-16B 、 Figure 16E and Figure 16FThe second virtual pixel circuit includes a second transfer electrode CP10, and the second transfer electrode CP10 is arranged in the same layer as the first transfer electrode of the first virtual pixel circuit and the first connection portion CP1 of the pixel circuit in the display area, for example, both are located in the third conductive layer, and are electrically connected to the second plate CE20 of the fourth compensation capacitor COM10. For example, the second transfer electrode CP10 is electrically connected to the second plate CE20 of the fourth compensation capacitor COM10 through the via VH40 and the via VH50 to maintain etching uniformity here and at other locations such as the display area of ​​the display substrate.

[0173] For example, combined with Figures 16A-16B and Figure 16E The second plate CE20 of the fourth compensation capacitor COM10 is connected to the first power line VDD through the via VH40 and the via VH50, for example, connected to the first trace 2424 of the first power line VDD, so as to provide the first power supply voltage to the second plate CE20 of the fourth compensation capacitor COM10 to form the fourth compensation capacitor COM10.

[0174] For example, the second portion AP22 of the second virtual semiconductor layer is configured to be fed with an electrical signal through the second virtual pixel circuit; the first portion AP21 of the first virtual semiconductor layer has a first end P21 and a second end P22 opposite to each other in the first direction R1, the second end P22 is configured to be fed with the electrical signal through the second virtual pixel circuit, the first end P21 is connected to the second end P22, so that the electrical signal from the second end P2 can be transmitted to the first end P21, preventing signal drift caused by no signal input to the first end P21. For example, Figure 16A As shown, the second end P22 is electrically connected to the second sub-track 2424 of the first power line VDD, for example, by a via VH20, so that the first power voltage from the second sub-track 2424 of the first power line VDD is transmitted to the second end P22 and the first end P21. The structure of the first power line VDD is not limited to Figures 16A-16F In the case of FIG, it is sufficient to connect the first power line VDD to the second terminal P22.

[0175] For example, Figure 16A As shown, the positive projection of the first part of the third signal line, such as the light-emitting scanning signal line EM, on the base substrate 210 at least partially overlaps with the positive projection of the virtual semiconductor layer on the base substrate 210 to form a third compensation capacitor to compensate for the load of the third signal line and obtain a more uniform display effect.

[0176] Of course, the second virtual pixel structure is not limited to Figures 16A-16F The situation shown, Figures 16A-16FIn the embodiment, the data line and the source / drain electrodes 122 / 123 are on the same layer. For example, when the data line is located on the side of the source / drain electrodes 122 / 123 away from the base substrate, the dummy semiconductor layer can also be arranged to overlap with a third signal line, such as the light-emitting scanning signal line EM, to form a third compensation capacitor. This is not limited in the present embodiment.

[0177] In such Figure 2B and Figure 2C In the illustrated embodiment, the second opening region 202B and the first opening region 202A are arranged along the first direction R1. Thus, the inter-opening region 2014 is located between the first opening region 202A and the second opening region 202B in the first direction R1. The first display region 2011 is located on a side of the first opening region 202A away from the inter-opening region 2014, and the second display region 2012 is located on a side of the second opening region 202B away from the inter-opening region 2014. In this case, the first display region 2011 is located on a first side of the first opening region 202A, and the second display region 2012 is located on a second side of the second opening region 201B. That is, the first display region, the first opening region, the inter-opening region, the second opening region, and the second display region are arranged in sequence along the first direction. For the first opening region 202A and the second opening region 201B, respectively, the first display region 2011 is located on a first side of the first opening region 202A, and the second display region 2012 is located on a second side of the first opening region 202A, with the first side and the second side being opposite to each other in the first direction R1. The first signal line 23 sequentially passes through the first display region 2011, the first opening peripheral region 203A, the inter-opening region 2014, the second opening peripheral region 203B, and the second display region 2012 along the first direction R1.

[0178] like Figure 2B As shown, the first signal line 2301 includes a first lead portion E1A1 / E2A2 located in the first opening peripheral area 203A (ie, taking a first signal line as an example, for example, the first lead portion is Figure 2B The straight line segment E1A1 and the straight line segment E2A2 in the first opening peripheral area 203A and the lateral winding portion A1A2 (ie, the lateral winding portion is Figure 2B The second signal line 24 is configured to provide a second display signal to the first pixel array, and passes through the first opening peripheral area 203A along a second direction R2 intersecting the first direction R1, including a longitudinal winding portion C1C2 located in the first opening peripheral area 203A, that is, the longitudinal winding portion is Figure 2BThe curved segment C1C2 in the longitudinal winding portion C1C2 is partially disposed around the first opening 201A. The orthographic projections of the first lead portion E1A1 / E2A2 on the substrate and the orthographic projections of the second signal line 24 on the substrate have first overlapping regions S1 / S2, respectively, i.e., the regions where they intersect. The orthographic projections of the lateral winding portion A1A2 on the substrate and the orthographic projections of the longitudinal winding portion C1C2 on the substrate have second overlapping regions. For example, the two overlap at segments A1C1 and D1A2. The second overlapping region is the region represented by A1C1 and D1A2. In this way, due to the formation of the first overlapping area and the second overlapping area, a compensation capacitor is formed between the first signal line 2301 and the second signal line 24 that overlap each other in a direction perpendicular to the base substrate, compensating for the load on the first signal line, thereby reducing the display difference caused by the different loads of the first signal lines connecting different rows of pixels due to the different number of pixels in different rows of pixels in the first pixel array, so that the display effect of the first display area 2011 and the second display area 2012 is consistent with the display effect of the pixel row in the display area 201 where the first opening area 202A is not provided, thereby improving the display quality. At the same time, the above-mentioned routing method can also reduce the arrangement space of the first signal line and the second signal line, and minimize the area occupied by the first opening peripheral area 203A as much as possible. Therefore, for example, when the under-screen camera function is realized through the first opening area 202A, the influence of the first opening area 202A on the display effect of the area is reduced, or, in other embodiments, when the first opening peripheral area 203A is located in the border area 204, the width of the border area 204 can also be reduced, thereby helping to achieve a narrow border and large screen design of the display substrate 20. For example, Figure 2B As shown, the orthographic projection of the lead portion E1A1 of the first signal line 2301 on the substrate substrate has a first overlapping region with the orthographic projection of the longitudinal winding portion of the second signal line 24 on the substrate substrate. That is, each of the plurality of first signal lines sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead portion and a transverse winding portion located in the first opening peripheral area. The transverse winding portion partially surrounds the first opening, and the first lead portion is connected to the transverse winding portion. The orthographic projections of the transverse winding portions of the plurality of first signal lines on the substrate substrate respectively have overlapping regions with the orthographic projections of the longitudinal winding portions of the plurality of second signal lines on the substrate substrate.

[0179] Figure 17 A schematic planar layout diagram of a second virtual pixel circuit in a second virtual sub-pixel in a display substrate provided by an embodiment of the present disclosure. Figure 17 and Figure 16AThe main difference is that the data line DATA is located on the side of the source and drain electrodes 122 / 123 away from the substrate, and the relative position of the data line DATA to the first power line VDD in the first direction is different. Figure 16A .

[0180] Figure 10A This is an enlarged schematic diagram of a first opening area of ​​a display substrate provided by one embodiment of the present disclosure. Figure 10A and Figures 2B-2C The difference is that the display substrate also includes a first floating electrode 41 / 42. The longitudinal winding portion of the plurality of second signal lines closest to the first opening 201A is the edge longitudinal winding portion 2401 / 2402. The first floating electrode 41 / 42 is disposed on the same layer as the edge longitudinal winding portion and is located on the side of the edge longitudinal winding portion 2401 / 2402 closest to the first opening 201A. The first floating electrode 41 / 42 is disposed on the same layer as the edge longitudinal winding portion and is located on the side of the edge longitudinal winding portion 2401 / 2402 closest to the first opening 201A. This prevents differences in etching properties of the edge longitudinal winding portion and improves etching uniformity. The first floating electrode does not carry any electrical signals and does not interfere with other surrounding signal lines.

[0181] For example, as shown in FIG10 , a plurality of pixels include a first pixel column and a second pixel column extending along a second direction R2, respectively. A first opening 201A has a first side and a second side opposing each other in the first direction R2, as well as a third side and a fourth side opposing each other in the second direction R2. The display substrate includes two longitudinal edge winding portions arranged corresponding to the first opening 201A. The two longitudinal edge winding portions include: an edge winding portion configured to provide a second display signal to the first pixel column, the edge winding portion providing the second display signal to the first pixel column partially surrounding the first opening on a first side of the first opening; and an edge winding portion configured to provide a second display signal to the second pixel column, the edge winding portion providing the second display signal to the second pixel column partially surrounding the first opening on a second side of the first opening. The first floating electrode includes a first portion 41 and a second portion 42. The first portion 41 is located on a side of the longitudinal edge winding portion providing the second display signal to the first pixel column that is closer to the first opening 201A. The second portion 42 is located on a side of the longitudinal edge winding portion providing the second display signal to the second pixel column that is closer to the first opening 201A.

[0182] For example, the line width and extension direction of the first floating electrode and the edge longitudinal winding portion are substantially the same, so as to further increase the etching uniformity of the edge longitudinal winding portion.

[0183] For example, there is a first interval between two adjacent second signal lines among the multiple second signal lines. For example, there is a first interval between the longitudinal winding portions of two adjacent second signal lines. The interval between the first floating electrode and the edge longitudinal winding portion is basically equal to the first interval, so as to further increase the etching uniformity of the edge longitudinal winding portion.

[0184] For example, in some embodiments, Figure 10A As shown, the first portion 41 of the first floating electrode and the second portion 42 of the first floating electrode are spaced apart from each other. Figure 10B and Figure 10C As shown, the first portion 41 of the first floating electrode and the second portion of the first floating electrode are integrally formed.

[0185] For example, Figure 10B As shown, the overall planar shape of the first portion 41 of the first floating electrode and the second portion 42 of the first floating electrode is an open ring surrounding the first opening 201A. The opening of the open ring can better release the accumulated charge and avoid signal interference with the surrounding signal lines. Of course, in some embodiments, for example, Figure 10C As shown, the planar shape of the entire structure formed by the first portion 41 of the first floating electrode and the second portion 42 of the first floating electrode may also be a closed ring.

[0186] Figure 11 yes Figure 10A Figure 16 is an enlarged schematic diagram of a local H in Figure 11 An enlarged schematic diagram of the local G in Figure 13 is an enlarged schematic diagram of a part I in FIG16 , Figure 14 yes Figure 13 Schematic diagram of an enlarged portion J in FIG. The display substrate further includes a second floating electrode. The horizontal winding portion of the plurality of first signal lines closest to the first opening 201A is an edge horizontal winding portion. The second floating electrode is disposed on the same layer as the edge horizontal winding portion and on a different layer from the first floating electrode. The second floating electrode is located on one side of the edge horizontal winding portion near the first opening. The orthographic projection of the second floating electrode on the base substrate 210 overlaps with the orthographic projection of the first floating electrode on the base substrate 210. This avoids differences in etching properties of the edge horizontal winding portion and improves etching uniformity. Similar to the first floating electrode, the second floating electrode and the edge horizontal winding portion have substantially the same line width and extension direction, further improving etching uniformity of the edge horizontal winding portion.

[0187] For example, there is a second interval between two adjacent second signal lines among the multiple first signal lines. For example, there is a second interval between the lateral winding portions of two adjacent first signal lines. The interval between the second floating electrode and the edge lateral winding portion is basically equal to the second interval, so as to further increase the etching uniformity of the edge lateral winding portion.

[0188] For example, the first signal lines include a plurality of gate scanning signal lines and a plurality of reset signal lines. Figure 13 As shown, the gate scan signal line 2303A (in this case, the first portion 2303A of the gate scan signal line) and the reset signal line 2301A (in this case, the first portion 2301A of the gate scan signal line) are arranged in different layers. Furthermore, the horizontal winding portions 2303A-1 of the gate scan signal line 2303A and the horizontal winding portions 2301A-1 of the reset signal line 2301A are arranged alternately in the second direction. The gate scan signal line 2303A closest to the first opening 201A among the multiple gate scan signal lines 2303A is an edge gate scan signal line 2303A-0, and the reset signal line closest to the first opening 201A among the multiple reset signal lines 2301A is an edge reset signal line 2301A-0. The second floating electrode includes a first sub-floating electrode 511 and a second sub-floating electrode 512. The first sub-floating electrode 511 is arranged on the same layer as the gate scanning signal line and is located on the side of the edge gate scanning signal line 2303A close to the first opening 201A; the second sub-floating electrode 512 is arranged on the same layer as the reset signal line 2301A-0 and is located on the side of the edge reset signal line 2301A-0 close to the first opening 201A; the edge gate scanning signal line 2303A-0 is farther away from the first opening 201A than the edge reset signal line 2301A-0, and the first sub-floating electrode 511 is farther away from the first opening 201A than the second sub-floating electrode 512. The orthographic projection of the first floating electrode on the substrate has at least an overlapping area with the first sub-floating electrode, which can solve the problem of etching uniformity of the edge reset signal line 2301A-0 and the edge reset signal line 2301A-0. Alternatively, the edge reset signal line 2301A-0 is farther away from the first opening 201A than the edge gate scan signal line 2303A-0, the second sub-floating electrode 512 is farther away from the first opening 201A than the first sub-floating electrode 511, and the orthographic projection of the first floating electrode on the substrate has at least an overlapping area with the second sub-floating electrode, which can also solve the problem of etching uniformity of the edge reset signal line 2301A-0 and the edge reset signal line 2301A-0.

[0189] In some embodiments, for example, Figure 13As shown, the portion of the plurality of second signal lines includes a first portion of second signal lines 2410 and a second portion of second signal lines 2412. The first portion of second signal lines 2410 and the second portion of second signal lines 2412 are disposed in different layers and alternately arranged in the first direction. The layers of the first portion of second signal lines 2410 and 2412 are described above. The second signal line closest to the first opening in the first portion of second signal lines 2410 is an edge first sub-data signal line, and the second signal line closest to the first opening in the second portion of second signal lines 2412 is an edge second sub-data signal line. The orthographic projection of the longitudinal winding portion of each second signal line in the first portion of second signal lines on the substrate 210 overlaps with the orthographic projection of the transverse winding portion of a gate drive scan signal line on the substrate. The orthographic projection of the longitudinal winding portion of each second signal line in the second portion of second signal lines on the substrate overlaps with the orthographic projection of the transverse winding portion of each reset signal line on the substrate. The first floating electrode includes a third sub-floating electrode 411 and a fourth sub-floating electrode 412. The third sub-floating electrode 411 is arranged on the same layer as the first part of the second signal line 2410 and is located on the side of the edge first sub-data signal line close to the first opening; the fourth sub-floating electrode 412 is arranged on the same layer as the second part of the second signal line 2412 and is located on the side of the edge second sub-data signal line close to the first opening 201A; the orthographic projection of the third sub-floating electrode 411 on the base substrate has an overlapping area with the first sub-floating electrode 511, and the orthographic projection of the fourth sub-floating electrode 412 on the base substrate has an overlapping area with the second sub-floating electrode 512.

[0190] For example, the first part of the second signal line 2410 (here referring to its longitudinal winding portion) is arranged on the same layer as the source and drain 122 / 123, and the second part of the second signal line 2412 (here referring to its longitudinal winding portion) is located on the side of the first part of the second signal line 2410 away from the substrate; multiple gate scanning signal lines are arranged on the same layer as the second plate of the storage capacitor, and multiple reset signal lines are arranged on the same layer as the first plate CE1 of the storage capacitor CST; or, the multiple gate scanning signal lines are arranged on the same layer as the first plate CE1 of the storage capacitor CST, and the multiple reset signal lines are arranged on the same layer as the second plate CE2 of the storage capacitor CST.

[0191] In the above embodiment, the gate scanning signal line and the reset signal line are both arranged in a winding manner at the first opening, rather than being disconnected at the first opening.

[0192] For example, in some embodiments, the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, wherein the gate scan signal lines and the reset signal lines are arranged in different layers. Each gate scan signal line sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead portion and a transverse winding portion located in the first opening peripheral area, wherein the transverse winding portion partially surrounds the first opening, and the first lead portion is connected to the transverse winding portion. Each reset signal line includes a first portion and a second portion. The first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction and is separated from the first portion by the first opening area. That is, the gate scan signal line is wound around the first opening, and the reset signal line is disconnected at the first opening.

[0193] For example, in some embodiments, the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, wherein the gate scan signal lines and the reset signal lines are arranged in different layers. Each reset signal line sequentially passes through the first display area, the first opening peripheral area, and the second display area along the first direction, and includes a first lead portion and a transverse winding portion located in the first opening peripheral area, wherein the transverse winding portion partially surrounds the first opening, and the first lead portion is connected to the transverse winding portion. Each gate scan signal line includes a first portion and a second portion. The first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction and is separated from the first portion by the first opening area. That is, the reset signal line is wound around the first opening, and the gate scan signal line is disconnected at the first opening.

[0194] For example, in some embodiments, the plurality of first signal lines include a plurality of gate scan signal lines and a plurality of reset signal lines, the gate scan signal lines and the reset signal lines being arranged in different layers; each gate scan signal line includes a first portion and a second portion. The first portion passes through the first display area along the first direction; the second portion passes through the second display area along the first direction and is separated from the first portion by the first opening area; and each reset signal line includes a first portion and a second portion, the first portion passing through the first display area along the first direction; the second portion passing through the second display area along the first direction and being separated from the first portion by the first opening area. That is, both the gate scan signal lines and the reset signal lines are disconnected at the first opening.

[0195] When the gate scan signal line and / or the reset signal line is disconnected at the first opening, a double-sided driving method can be used to load driving signals to the disconnected signal lines from both sides of the substrate in the first direction. For details, refer to conventional technology.

[0196] For example, in some embodiments, the display substrate may further include an outer floating electrode. Among the longitudinal winding portions of the plurality of second signal lines, the longitudinal winding portion farthest from the first opening is the outer edge longitudinal winding portion, and the outer floating electrode is disposed in the same layer as the outer edge longitudinal winding portion and is located on a side of the outer edge longitudinal winding portion farthest from the first opening, so as to increase etching uniformity of the outer edge longitudinal winding portion.

[0197] For example, each of the second signal lines of the part of the plurality of second signal lines also includes a second lead portion. The second lead portion extends along the second direction and is connected to the longitudinal winding portion. The arrangement density of the second lead portion is greater than the arrangement density of the longitudinal winding portion. The line width of the second lead portion is substantially equal to the line width of the longitudinal winding portion. Due to the difference in arrangement density and the limitation of the etching process, the design line width of the second lead portion is made smaller than the design line width of the longitudinal winding portion in the manufacturing process, so that the final line widths of the two formed are substantially equal. Alternatively, if there is no difference in the design line width, the line width of the second lead portion is smaller than the line width of the longitudinal winding portion.

[0198] At least one embodiment of the present disclosure provides a display device comprising any of the aforementioned display substrates. The display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other device having a display function, and the embodiments of the present disclosure are not limited thereto.

[0199] The structure, function, and technical effects of the display device provided by the embodiment of the present disclosure can refer to the corresponding description of the display substrate provided by the above embodiment of the present disclosure, and will not be repeated here.

[0200] For example, the display device provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, and the embodiments of the present disclosure are not limited thereto.

[0201] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, wherein: The display substrate comprises: A substrate, comprising: a first opening region comprising a first opening and a first opening peripheral region surrounding the first opening; a second opening region, disposed adjacent to the first opening region along a first direction, and comprising a second opening and a second opening peripheral region surrounding the second opening; an inter-opening region, located between the first opening region and the second opening region, wherein at least one of the inter-opening region, the first opening peripheral region, and the second opening peripheral region includes a first virtual sub-pixel; A display area at least partially surrounds the first opening area, the second opening area, and the inter-opening area, and includes a plurality of pixels, each of the pixels includes a plurality of sub-pixels, wherein the display area includes: a first display area located on a side of the first opening area away from the inter-opening area; and a second display area located on a side of the second opening area away from the inter-opening area, wherein both the first display area and the second display area include the plurality of pixels, the first display area and the second display area as a whole include a plurality of pixel rows extending along a first direction, the plurality of pixel rows being interrupted by the whole formed by the first opening area, the inter-opening area, and the second opening area, and the plurality of pixel rows including different numbers of sub-pixels; wherein each of the sub-pixels includes a pixel circuit, and the pixel circuit includes: A transistor including an active layer, a gate, and a source and drain; a light emitting element connected to one of the source and drain of the transistor; and A storage capacitor, comprising a first plate and a second plate, wherein the gate and the first plate of the storage capacitor are arranged in the same layer; and A first signal line extends along a first direction, includes a first portion passing through the first opening peripheral area, the inter-opening area, and the second opening peripheral area, and is configured to provide a first display signal to the pixel circuit, wherein the first portion of the first signal line passes through the first virtual sub-pixel, the first virtual sub-pixel includes a virtual pixel circuit, the virtual pixel circuit includes a first compensation capacitor, and the first compensation capacitor includes: a first electrode plate, disposed in the same layer as the first portion of the first signal line and electrically connected to the first signal line, and disposed in the same layer as the second electrode plate of the storage capacitor; and a second electrode plate, provided in a different layer from and insulated from the first electrode plate of the first compensation capacitor, wherein an orthographic projection of the second electrode plate of the first compensation capacitor on the substrate at least partially overlaps with an orthographic projection of the first electrode plate of the first compensation capacitor on the substrate; There are multiple first signal lines, each of which is configured to provide the first display signal to the pixel circuits of the multiple pixel rows. The compensated loads of the multiple first signal lines are substantially the same.

2. The display substrate according to claim 1, wherein The first plate of the first compensation capacitor includes: a first extending portion connected to the first portion of the first signal line, extending from the first portion of the first signal line and located on a first side of the first portion of the first signal line in a second direction, wherein the second direction intersects the first direction; The second extension portion is connected to the first portion of the first signal line, extends from the first portion of the first signal line, and is located on a second side of the first portion of the first signal line opposite to the first side in the second direction.

3. The display substrate according to claim 2, wherein: The first extension portion, the second extension portion, and the first portion of the first signal line are integrally formed.

4. The display substrate according to claim 1, wherein: The second electrode plate of the first compensation capacitor includes a semiconductor material and is provided in the same layer as the active layer.

5. The display substrate according to claim 1, wherein The virtual pixel circuit further includes a second compensation capacitor, and the second compensation capacitor includes: a first plate, wherein the first plate of the first compensation capacitor is reused as the first plate of the second compensation capacitor; and The second electrode plate is arranged in a different layer and insulated from the first electrode plate of the second compensation capacitor, and is arranged in the same layer as the source and drain, wherein the orthographic projection of the second electrode plate of the second compensation capacitor on the base substrate at least partially overlaps with the orthographic projection of the first electrode plate of the second compensation capacitor on the base substrate. The display substrate according to claim 5 , wherein: The second plate of the second compensation capacitor is electrically connected to the second plate of the first compensation capacitor.

7. The display substrate according to claim 6, wherein: The display substrate further includes a first power line, wherein the first power line is connected to a first voltage terminal, configured to provide a first power supply voltage to the pixel circuit, and is connected to the second plate of the storage capacitor, and the first power line includes: a plurality of first sub-routes extending along the first direction; and A plurality of second sub-routes extend along a second direction intersecting the first direction and are electrically connected to the plurality of first sub-routes, wherein: A first part of the multiple second sub-routes passes through the area between the openings and through the first virtual sub-pixel, and the second plate of the second compensation capacitor includes a first part and a second part. The first part of the second sub-routes and the first part of the second plate of the second compensation capacitor are arranged in the same layer and are electrically connected to serve as the second part of the second plate of the second compensation capacitor, and the first part of the second sub-routes are electrically connected to the second plate of the first compensation capacitor.

8. The display substrate according to claim 7, further comprising: a first insulating layer, located between the second plate of the first compensation capacitor and the gate; a second insulating layer, located between the gate and the first plate of the first compensation capacitor; as well as The third insulating layer is located between the first plate of the first compensation capacitor and the second plate of the second compensation capacitor, wherein: The first portion of the second sub-routing is electrically connected to the second plate of the first compensation capacitor through a first via hole that penetrates the first insulation layer, the second insulation layer, and the third insulation layer and exposes the second plate of the first compensation capacitor.

9. The display substrate according to claim 7, wherein: The second sub-wire of the first portion and the second electrode plate of the second compensation capacitor are integrally formed.

10. The display substrate according to claim 7, wherein: The display substrate further includes: a plurality of second signal lines configured to provide second display signals to the plurality of sub-pixels, wherein a first portion of the plurality of second signal lines passes through the inter-opening region and the first dummy sub-pixel along the second direction, and the first portion of the second signal lines is located on a side of the second plate of the second compensation capacitor away from the base substrate; The first part of the second plate of the second compensation capacitor has a hollow area, and the orthographic projection of the first part of the second signal line of the first virtual sub-pixel where the second plate of the second compensation capacitor is located on the base substrate at least partially overlaps with the hollow area.

11. The display substrate according to claim 10, wherein: The second electrode plate of the second compensation capacitor has a plurality of hollow areas, and the plurality of hollow areas are arranged at intervals from each other along the second direction.

12. The display substrate according to claim 11, wherein: The plurality of hollow areas include a first hollow area and a second hollow area that are adjacent to each other, and a length of the first hollow area in the second direction is different from a length of the second hollow area in the second direction.

13. The display substrate according to claim 12, wherein: A portion of the second electrode plate of the second compensation capacitor located between the first hollow area and the second hollow area is continuous along the first direction; The second electrode plate of the second compensation capacitor includes a first edge and a second edge opposite to each other in the second direction, and at least one of the first edge and the second edge is disconnected by the hollow area.

14. The display substrate according to claim 10, wherein: In the first virtual sub-pixel, the second electrode plate of the first compensation capacitor covers the entire first virtual sub-pixel, and the orthographic projection of the first electrode plate of the first compensation capacitor on the substrate is located within the orthographic projection of the second electrode plate of the first compensation capacitor on the substrate; The first compensation capacitor is smaller than the second compensation capacitor.

15. The display substrate according to claim 1, wherein The first signal line passes through the first display area, the first opening peripheral area, the inter-opening area, the second opening peripheral area and the second display area in sequence along the first direction. The first signal line also includes a second part passing through the first display area and a third part passing through the second display area. The second part and the third part are arranged in the same layer as the gate.

16. The display substrate according to claim 15, wherein: The display substrate further includes: a first connection structure, located in a peripheral area of ​​the first opening and disposed in a different layer from the second portion of the first signal line and the first portion of the first signal line, wherein the second portion of the first signal line is electrically connected to the first connection structure, and the first portion of the first signal line is electrically connected to the first connection structure; and The second connection structure is located in the peripheral area of ​​the second opening and is arranged in a different layer from the first part of the first signal line and the third part of the first signal line, wherein the first part of the first signal line is electrically connected to the second connection structure, and the third part of the first signal line is electrically connected to the second connection structure.

17. The display substrate according to claim 16, wherein: The first connection structure and the second connection structure are arranged in the same layer as the source and drain.

18. The display substrate according to any one of claims 1 to 17, wherein: The first signal line is a gate scanning signal line, and the first display signal is a gate scanning signal.

19. The display substrate according to any one of claims 7 to 17, wherein: The display substrate further comprises: a third signal line extending along the first direction, including a first portion passing through the first opening peripheral area, the inter-opening area, and the second opening peripheral area, configured to provide a third display signal to the pixel circuit, wherein the first portion of the third signal line is provided in the same layer as the gate; The virtual pixel circuit includes: A virtual semiconductor layer is arranged in the same layer as the active layer and is electrically connected to the second sub-line of the first part, wherein the orthographic projection of the first part of the third signal line on the base substrate at least partially overlaps with the orthographic projection of the virtual semiconductor layer on the base substrate to form a third compensation capacitor.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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