A floating point multiplier-accumulator

Abstract

The present invention discloses a floating-point multiplier and adder, which realizes the floating-point multiplication and addition operation in the form of A*B+C. The floating-point multiplier and adder adopts a three-stage pipeline method to realize the floating-point multiplication and addition operation. The first pipeline beat completes the floating-point multiplication, the second pipeline beat completes the addition, and the third pipeline beat completes the rounding operation and exception judgment, and outputs the final result. Advantages: The floating-point multiplier and adder of the present invention realizes the multiplication and addition operation of single and double precision floating points, and supports the three-stage pipeline architecture of non-normalized numbers.

Description

Technical Field

[0001] The invention relates to the technical field of chip design, in particular to a floating-point multiplier-adder. Background Art

[0002] Currently, in high-performance DSPs, floating-point multipliers and adders are an important part of achieving high-performance computing. Technologies related to the present invention include floating-point multipliers, floating-point adders, floating-point multipliers and adders, etc. Among the existing technologies, some only support single-precision operations, some have low operating frequencies, some have too many pipeline stages, some do not support non-normalized numbers, and some have too bloated structures and poor timing. Summary of the invention

[0003] The present invention proposes a floating-point multiplier-adder, and the technical solution adopted is:

[0004] A floating-point multiplier and adder implements a floating-point multiplication and addition operation in the form of A*B+C. The floating-point multiplier and adder uses a three-stage pipeline to implement the floating-point multiplication and addition operation. The first pipeline beat completes the floating-point multiplication, the second pipeline beat completes the addition, and the third pipeline beat completes the rounding operation and exception judgment, and outputs the final result.

[0005] The first pipeline beat includes a sign bit processing module, an exponential preprocessing module, a 161-bit right shift module, a negation module, a partial product generation module, and a Wallace compression tree module.

[0006] The sign bit processing module determines the sign bit to be corrected according to the operation code and the sign bits of the three operands. The sign bit of fs*ft and the coincidence bit of fr of the output result of the sign bit processing module are sent to the sign bit judgment module of the third pipeline beat. The valid subtraction indication signal of the output result of the sign bit processing module is sent to the negation module; wherein fs, ft and fr refer to A, B and C in A*B+C respectively;

[0007] The exponential preprocessing module and the 161-bit right shift module constitute an exponential top-level module. The exponential preprocessing module in the exponential top-level module simultaneously inputs the exponential bits of the three operands, calculates the intermediate exponential result, and provides it to the exponential calculation module in the second pipeline beat for exponential calculation. At the same time, the exponential preprocessing module calculates the number of right shift bits required for fr according to the exponent of fs*ft+fr, and provides it to the 161-bit right shift module. The 161-bit right shift module simultaneously inputs the result right shift bit of the exponential preprocessing module and the mantissa bit of fr to right shift the mantissa of fr;

[0008] The negation module determines whether to negate the mantissa of fr after the right shift according to the valid subtraction indication signal provided by the sign bit processing module, the lower 106 bits of fr output by the negation module are sent to the 106-bit 3:2 compressor in the second pipeline beat, the higher 55 bits of the mantissa fr output by the negation module are simultaneously sent to the leading zero prediction module and the 161-bit carry look-ahead adder in the second pipeline beat, and the 3-bit rounding signal output by the negation module is sent to the 164-bit left shift module in the second pipeline beat;

[0009] The partial product generation module and the Wallace compression tree module constitute a multiplication module. The partial product generation module simultaneously inputs the mantissa of fs and the mantissa of ft to perform multiplication of two floating-point mantissas. The output of the partial product generation module is sent to the Wallace compression tree module for compression to generate two sets of data: 106-bit sum and 106-bit carry.

[0010] The second pipeline beat includes a leading zero prediction module, an exponent calculation module, a 106-bit 3:2 compressor, a 161-bit carry-lookahead adder and a 164-bit left shift module, and the 106-bit 3:2 compressor, the 161-bit carry-lookahead adder and the 164-bit left shift module constitute an addition module;

[0011] The 106-bit sum, 106-bit carry, the high 55-bit number of the mantissa fr output by the negation module, and the low 106-bit number of fr output by the negation module generated by the first pipeline beat are input into the leading zero prediction module together, and the prediction result of the leading zero prediction module is output to the 164-bit left shift module for left shifting;

[0012] The result of the intermediate index of the first pipeline beat and the prediction result of the leading zero prediction module are input into the index calculation module to correct the intermediate index, and the output result of the index calculation module is sent to the index post-processing module of the third pipeline beat;

[0013] The 106-bit 3:2 compressor in the addition module simultaneously inputs the 106-bit sum generated by the first pipeline beat, the 106-bit carry and the lower 106-bit number of fr output by the negation module for compression, and the output result of the 106-bit 3:2 compressor is sent to the 161-bit carry-lookahead adder;

[0014] The 161-bit carry-lookahead adder in the addition module simultaneously inputs the output result of the 106-bit 3:2 compressor and the high 55 bits of the mantissa fr output by the negation module for addition, and the output result of the 161-bit carry-lookahead adder is sent to the 164-bit left shift module, and the final result sign bit of the output result of the 161-bit carry-lookahead adder is sent to the leading zero prediction module and the sign bit judgment module in the third pipeline beat respectively;

[0015] The 164-bit left shift module simultaneously inputs the left shift bit number of the leading zero prediction module, the output result of the 161-bit carry lookahead adder and the 3-bit rounding signal output by the negation module, the 164-bit left shift module shifts the output result of the 161-bit carry lookahead adder according to the left shift bit number output by the leading zero prediction module, and the output result of the 164-bit left shift module is sent to the absolute value module of the third pipeline beat;

[0016] The third pipeline beat includes a sign bit judgment module, a special value processing module, an absolute value module, a rounding judgment module, a 53-bit adder, a MUX selection module, an exponential post-processing module and a data selection module.

[0017] The sign bit judgment module simultaneously inputs the operation code, the rounding mode, the sign bit of fs*ft and the coincidence bit of fr in the first pipeline beat, and the final result sign bit in the second pipeline beat, and the sign bit output by the sign bit judgment module is sent to the data selection module;

[0018] The special value processing module simultaneously inputs the special value indication signal of fs*ft, the special value indication signal of fs, the special value indication signal of ft, the special value indication signal of fr and the rounding mode, and the output result of the special value processing module is sent to the data selection module; the exception information obtained by the special value processing module is output as the exception judgment;

[0019] The absolute value module determines whether to take the absolute value of the output result of the 164-bit left shift module of the second pipeline beat of the input 110 bits according to the sign bit. The valid data in the output result of the absolute value module determines whether an addition operation is required according to the rounding mode, sign bit, round bit and sticky bit. The valid data that needs to be added is sent to the 53-bit adder, and the valid data that does not need to be added is sent to the MUX selection module. The data that needs to be rounded in the output result of the absolute value module is sent to the rounding judgment module, and the rounding judgment module inputs the rounding mode. The rounding judgment module performs rounding judgment on the discarded part of the data and sends its output result to the MUX selection module.

[0020] The MUX selection module selects the data using the rounding result of the input data, and the high 53 bits of the output result are simultaneously sent to the exponential post-processing module and the data selection module;

[0021] The exponential post-processing module simultaneously inputs the exponential result of the second pipeline beat and the high 53-bit data of the output result of the MUX selection module, and the exponent output by the exponential post-processing module is sent to the data selection module;

[0022] The data selection module simultaneously inputs the sign bit output by the sign bit judgment module, the output result of the special value processing module, the exponent output by the exponential post-processing module, the mantissa output by the MUX selection module and the special value defined in the IEEE754 standard, and selects the final result output.

[0023] In the preferred embodiment of the technical solution of the present invention, the partial product generation module in the multiplication module adopts booth coding in the radix-4 mode, and the Wallace compression tree module in the multiplication module adopts a CSA4:2 compressor.

[0024] In the preferred embodiment of the technical solution of the present invention, the shift order function in the exponential top module includes exponent difference calculation and mantissa right shift.

[0025] The exponent difference calculation is that the exponent preprocessing module offsets fr to the left by 56 bits, and then calculates the difference d between the exponents of fr and fs*ft. The calculated difference d is sent to the 161-bit right shift module to shift the exponents of fr and fs*ft to be consistent, and then add them;

[0026] When the floating point number is a double precision floating point number, d = exp(fs)+exp(ft)-exp(fr)-967;

[0027] When the floating point number is a single-precision floating point number, d = exp(fs)+exp(ft)-exp(fr)-71;

[0028] The mantissa right shifts the operand fr right according to the difference d calculated by the exponent difference, and the shifted digits are reserved for the following module rounding.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The floating-point multiplier and adder of the present invention can realize single-precision floating-point number and double-precision floating-point number multiplication and addition operations, and supports denormalized numbers.

[0031] 2. The floating-point multiplier and adder of the present invention can run at 2.5 GHz under TSMC 12 nm process, and can better meet the computing requirements of high-performance DSP processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a flow chart of the three-beat pipeline of the floating-point multiplier-adder of the present invention.

[0033] Figure 2 This is a block diagram of a CSA4:2 compressor used in Wallace tree compression of the Mul_top part in an embodiment of the present invention.

[0034] Figure 3 It is a flow chart of the add_top part in the embodiment of the present invention.

[0035] Figure 4 This is a flow chart of the third pipeline beat part in an embodiment of the present invention.

[0036] Figure 5 4 is a flow chart of a leading zero prediction module in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is described in detail below, but the protection scope of the present invention is not limited to the embodiments.

[0038] To make the content of the present invention more clearly understood, the following Figure 1 -Attached Figure 5 The specific implementation manner is further described.

[0039] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] like Figure 1 As shown, a floating-point multiplier and adder proposed in the present invention implements a floating-point multiplication and addition operation in the form of A*B+C. The floating-point multiplier and adder adopts a three-stage pipeline method to implement the floating-point multiplication and addition operation. The first pipeline beat completes the floating-point multiplication, the second pipeline beat completes the addition, and the third pipeline beat completes the rounding operation and exception judgment, and outputs the final result.

[0041] like Figure 1 As shown, the floating-point multiplier and adder of this embodiment has the function of inputting three operands A, B, and C, performing the operation of A*B+C on the three operands, and outputting the result of the operation after three clock cycles. A, B, and C can be positive or negative, and can be both normalized and denormalized. The + sign of A*B+C can also be replaced by a - sign, and the IEEE754-2008 standard is adopted.

[0042] like Figure 1 As shown, the floating-point multiplier and adder of this embodiment adopts three-stage pipeline division, and the input is three floating-point operands A, B, and C. When the number is normalized, the hidden bit of the mantissa is filled with a 1, and when the number is denormalized, the hidden bit of the mantissa is filled with a 0 to make the data complete.

[0043] like Figure 1As shown, the floating-point multiplier and adder of this embodiment uses a three-beat pipeline to implement floating-point calculation operations. Considering that there is a one-beat data cache time between the floating-point instruction issuing unit fpu_rs and fmac, which is used to receive data bypassed by other execution units, the abnormal judgment of the three input source data is placed in the data cache beat. In the figure (fs represents A in A*B+C, ft represents B, and fr represents C).

[0044] like Figure 1 As shown, the first pipeline beat includes a sign bit processing module, an exponent preprocessing module, a 161-bit right shift module, a negation module, a partial product generation module and a Wallace compression tree module.

[0045] The sign bit processing module determines the sign bit to be corrected according to the operation code and the sign bits of the three operands. The sign bit of fs*ft and the coincidence bit of fr of the output result of the sign bit processing module are sent to the sign bit judgment module of the third pipeline beat, and the valid subtraction indication signal of the output result of the sign bit processing module is sent to the inversion module; wherein fs, ft and fr refer to A, B and C in A*B+C respectively.

[0046] The exponential preprocessing module and the 161-bit right shift module constitute an exponential top-level module. The exponential preprocessing module in the exponential top-level module simultaneously inputs the exponent bits of the three operands, calculates the intermediate exponent results, and provides them to the exponential calculation module in the second pipeline beat for exponential calculation. At the same time, the exponential preprocessing module calculates the number of right shift bits required for fr according to the exponent of fs*ft+fr, and provides it to the 161-bit right shift module. The 161-bit right shift module simultaneously inputs the number of right shift bits resulting from the exponential preprocessing module and the mantissa bits of fr to right shift the mantissa of fr.

[0047] The inversion module determines whether to invert the mantissa of fr after the right shift according to the valid subtraction indication signal provided by the sign bit processing module. The lower 106 bits of fr output by the inversion module are sent to the 106-bit 3:2 compressor in the second pipeline beat, and the upper 55 bits of the mantissa fr output by the inversion module are simultaneously sent to the leading zero prediction module and the 161-bit carry look-ahead adder in the second pipeline beat. The 3-bit rounding signal output by the inversion module is sent to the 164-bit left shift module in the second pipeline beat.

[0048] The partial product generation module and the Wallace compression tree module constitute a multiplication module. The partial product generation module simultaneously inputs the mantissa bits of fs and the mantissa bits of ft to perform multiplication operations on two floating-point mantissas. The output of the partial product generation module is sent to the Wallace compression tree module for compression to generate two sets of data, a 106-bit sum and a 106-bit carry. The two sets of data, a 106-bit sum and a 106-bit carry, are generated and added to obtain the multiplication result, and the high-bit overflow is discarded.

[0049] The multiplication module in the first pipeline beat - Mul_top, includes partial product generation and Wallace tree compression. This module is responsible for completing the multiplication operation of two floating-point mantissas, using booth encoding and then Wallace tree compression, and finally obtaining 106-bit sum and 106-bit Co. The two sets of data are added to get the multiplication result, and the high-bit overflow can be discarded.

[0050] Booth encoding uses radix-4. For the input multipliers X and Y, first expand X to {X, 1'b0}, then perform 3-bit encoding. If the high bits are not enough to form 3 bits, they are padded with zeros. The lowest 3 bits are {X1, X0, 1'B0}, and then {X3, X2, X1}. The lowest bit of the current encoding coincides with the highest bit of the previous encoding. In this module, source_b_i is booth encoded, so the final result is 27 54-bit partial products.

[0051] like Figure 3 As shown in the figure, when performing Wallace tree compression, the CSA4:2 compressor is uniformly used. A total of four levels of structures are used to implement the 27 partial products generated by double-precision floating-point numbers. In order to simplify the structure, the single-precision floating-point numbers are directly expanded into 53-bit data, and encoded and calculated according to double-precision data. The first partial product is sign-extended (!S, S, S), the 2nd to 26th partial products are sign-extended (1, !S), and the last partial product is not extended.

[0052] like Figure 3 As shown, it should be noted that the addition of two 106-bit data may result in a 107-bit result, the highest bit of which is an overflow bit and should be discarded when predicting the leading zero.

[0053] The exponential top module in the first pipeline beat - exp_top, the exp_top part has two modules, one is the exponential preprocessing module, and the other is the 161-bit right shift module. The exponential preprocessing module is responsible for calculating the exponential difference and the intermediate exponential result. The intermediate exponent is the estimated exponential result, which will be corrected by the following modules. The 161-bit right shift module is responsible for right shifting the mantissa.

[0054] Therefore, when calculating the addition of A*B+C, the exponent of C must be adjusted to be consistent with the exponent of A*B before they can be added, and the corresponding mantissa also needs to be shifted.

[0055] The shift order function in the exponential top-level module of this embodiment includes exponent difference calculation and mantissa right shift. The exponent difference calculation is that the exponent preprocessing module offsets fr to the left by 56 bits, calculates the difference d between the exponents of fr and fs*ft, and sends the calculated difference d to the 161-bit right shift module to shift the exponents of fr and fs*ft to be consistent, and then add; when the floating point number is a double-precision floating point number, d= exp(fs)+exp(ft)-exp(fr)-967;

[0056] When the floating point number is a single-precision floating point number, d = exp(fs)+exp(ft)-exp(fr)-71;

[0057] The mantissa right shifts the operand fr right according to the difference d calculated by the exponent difference, and the shifted digits are reserved for the following module rounding.

[0058] In this embodiment, exponent difference calculation: the exponent difference calculation function calculates the difference d between the exponents of C and A*B after offsetting C to the left by 56 bits. The calculated d is sent to the shift module, and the exponents of fr and fs*ft are shifted to be consistent, and then added. Originally, the decimal point of fr and the decimal point of fs*ft are in the same position. fr is offset to the left by 56 bits, which is equivalent to expanding the mantissa by 56 times, so the exponent of fr should be reduced by 56 accordingly. Therefore, the exponent of fr after offset is exp(fr)-56. The final exponent difference d=exp(fs*ft)-exp(fr)+56. exp(fs*ft) is exp(fs)+exp(ft)-1023. 1023 is subtracted because both exp(fs) and exp(ft) contain the bias exponent 1023, but only one bias is needed in the result exponent, so the extra 1023 is subtracted. The final exponent difference d=exp(fs)+exp(ft)-exp(fr)-967 (double precision); d=exp(fs)+exp(ft)-exp(fr)-71 (single precision). In single precision, the operand fr is biased 56 bits to the left and remains unchanged, while the subtracted bias is 127. The reason for subtracting the exponent of fr from the exponent of fs*ft instead of the other way around is to ensure that d is greater than zero, so the shift can be directly shifted. When d is less than zero, fs*ft can be directly rounded.

[0059] Shift: The function of shift is to shift the operand fr according to the exponent difference d, and keep three shifted bits for rounding of the following module. Shift can be done directly using the shift operator.

[0060] The detailed design of the shift-to-order function in this embodiment is as follows:

[0061] Data placement: The shift-to-order function is divided into two parts, one for the exponent difference calculation and the other for the right shift module. In the previous operation, the decimal points of the operands ft and fs*ft were aligned, and then the exponents were aligned by left or right shift according to the exponent difference, and finally fr and fs*ft were added to get the final result. Because the implementation of the function that can be shifted left and right will cause a large waste of resources, the improved structure is to offset fr to the left by 56 bits (that is, expand the mantissa of fr by 56 bits) and then only perform the right shift operation, and the left shift shifter can be removed. The reason for using only a 56-bit offset is that when fr is larger than fs*ft and exceeds 56 bits, the result of fs*ft is too small and can be rounded directly. No addition operation is required, and only rounding operation is required.

[0062] The detailed design scheme of the exponential difference calculation function in this embodiment is as follows:

[0063] The most important thing about the exponential difference calculation function is to calculate the difference of the exponents. In addition, it will also give an indication signal of data rounding and a signal whether the shift exceeds 53 bits (this signal is required when judging leading zeros).

[0064] First, let's look at the process of exponential difference calculation: the values ​​that need to be input are the exponents of the three operands exp(fs), exp(ft), and exp(fr), plus the indication signal indicating whether it is single-precision data or double-precision data, single_double. After the exponent of operand fr is input, it is first negated because d=exp(fs*ft)-exp(fr)+56 needs to take the complement of fr, but the complement plus one operation is not performed first. The plus one operation is performed when the two-bit adder outputs, and the three exponents are sent to the 11-bit CSA3:2 (3:2 compressor, a module that converts three-bit data of the same weight into a base bit and a carry bit). The result is the 11-bit base bit sum and the 11-bit carry bit of the higher weight. We send the lower two bits of the base bit sum[1:0] and the lower one bit of the carry bit to the end with zero {carry[0],1'b0} to the two-bit adder to calculate the final result. In addition to the lower two bits of the compressor, the two-bit adder also adds two extra 1s. When one of the 1s is exp(fr) negated and added, the other 1 is the 1 of the last two bits of -967 (double precision) or -71 (single precision). Among them, -967 and -71 are defined as 12-bit wide data. The lower two bits are sent to the two-bit adder, and the upper ten bits are sent to the second-level CSA3:2. The output of the two-bit adder is three bits, two bits of the original bit and one bit of the carry bit. The two bits of the original bit are directly output and sent to the 161-bit shifter for shifting, and the one bit of the carry bit is sent to the next-level two-bit adder for addition.

[0065] The remaining 9-bit standard and 10-bit carry of the first-stage compressor are sent to the next-stage compressor, and the high-bit standard is expanded by one 0 to make 10 bits. The high ten bits of -967 (double precision) or -71 (single precision) are sent to the compressor for compression to obtain the new compressed 10-bit standard and carry. The low two bits of the standard, the low two bits of the carry with a zero at the end, and the carry of the two-bit adder of the previous stage are sent to the two-bit adder, and the two-bit standard of the result is sent to the 161-bit shifter. The carry bit is used to select the result of the next-stage 4-bit double adder. The input of the four-bit double adder is sum and carry. For the next four bits, it simultaneously calculates the results of sum and carry, and the results of sum and carry with 1-bit carry in the low bit. The final result is selected by the carry bit of the two-bit adder to output the four-bit standard to the 161-bit shifter, and the carry bit is used to select the result of the next-stage 4-bit double adder. At this point, all the shift data required by the 161-bit shifter has been calculated (because 161 is only 8 bits when converted to binary). The upper four bits of the compressor are sent to the 4-bit double adder to calculate the two results of carry and no carry, and the result is selected by the carry of the previous level. The result of the 4-bit double adder of the last level is used for rounding judgment. Because the 3:2 compressor is used in the calculation, each bit of it is a carry-preserving adder, so the carry bit that should have overflowed to the sign bit when calculating the complement is retained, and the overflow generated by the first-level 10-bit compressor is retained and enters the second-level compressor, so the overflow bit of the two-level 3:2 compressor must be specially processed in the highest 4-bit double adder.

[0066] First consider the first case. When the result of the first-stage compressor is a positive number, it should overflow to the 12th bit and cancel out the sign bit of the inverse of fr. However, the calculation enters the second-stage compressor, so a 1 should be subtracted from the 12th bit. When the result is a negative number, all bit widths should be expanded to 13 bits. The 13th bit is supplemented with 1 for the sign bit (the result is negative), and the 12th bit is supplemented with 1 (complement code is supplemented with 1, obtained by inverse fr). However, there is no bit expansion when it is sent to the compressor, so 1 is subtracted from the 12th bit in the final four-bit double adder to make up for the error. The second stage of the compressor is for the same reason as the first stage. When it is a positive number, the carry and sign bit should be canceled, and when it is a negative number, the sign bit should be supplemented, so 1 is subtracted from the 13th bit to make up for it.

[0067] Two 2-bit adders, two 4-bit adders, and the carry bit of the last 4-bit adder total 13 bits. When put together, they form the 13-bit exponent difference d, with the 13th bit being the sign bit. When d <= 0, fs * ft is rounded; when d >= 163, fr is rounded; when 0 < d < 163, normal shifting is performed. Rounding is done after shifting 163 bits because ground and round bits need to be left after the result of AB. Finally, the exponent difference calculation function also gives a signal indicating whether the shift exceeds 53 bits (directly judged by d > 53).至此指数差计算功能设计完成。

[0068] In this embodiment, the detailed design scheme of the shifting module:

[0069] The mantissa fr input to the shifting module is 53 bits, and it can be shifted right by at most 163 bits. If it exceeds 163 bits, fr can be rounded. So the total bit width of the shift is 161 + 2 (round, stick) + 53 (the shifted out fr = 216 bits. Originally, for the last 53 bits shifted out, all are taken or a single extern_stick_bit bit is generated, and then the 53 bits shifted out plus extern_stick_bit total 54 bits are taken or an extern_stick_bit is generated. So finally, a total of 217 bits of data are shifted.

[0070] The final output result splits the high 161 bits into 55-bit msb and 106-bit lsb for output.

[0071] In the first pipeline stage of this embodiment, intermediate exponent calculation: The role of the intermediate exponent calculation function is to output the expected value of the exponent and send it to the leading zero module for exponent compensation after leading zero shifting.

[0072] The detailed design scheme of the intermediate exponent calculation function is as follows:

[0073] The role of the intermediate exponent calculation function is to calculate the exponent of fs * ft and add 3 (the reason for adding 3 is related to leading zero shifting. Please refer to the leading zero module for the reason of adding 3), or the value of fs * ft + 56. Because when fs * ft and fr are placed in the entire 161-bit shifting format, the exponent is basically determined. fs * ft is placed in the lower 106 bits, with the decimal point scaled between the 104th and 105th bits, and its value is exp(fs * ft). Since the exponent of a certain bit in the 161 bits is determined, the exponents of other bits are just increased or decreased by a few bits. For example, the exponent between the 161st and 160th bits is exp(fs * ft) + 56.

[0074] When calculating the intermediate exponent, it is necessary to distinguish whether it is a single-precision exponent or a double-precision exponent, because the offset of single-precision is 127 bits, the offset of double-precision is 1023 bits, and the number of bits of the final fr offset to the left is 56 bits, so the final exponent offset of double precision is 967 and the final exponent offset of single precision is 71. The intermediate exponent is compressed with a first-level 3:2 compressor, and the sum and carry are added together to get the final result. At the same time, the two results of exp(fs*ft+3) and exp(fs*ft+56) are calculated, and the final exponent result is selected according to whether the shift signal is normal and whether the shift exceeds 53 bits.

[0075] like Figure 1 As shown, the second pipeline beat includes a leading zero prediction module, an exponent calculation module, a 106-bit 3:2 compressor, a 161-bit carry lookahead adder and a 164-bit left shift module. The 106-bit 3:2 compressor, the 161-bit carry lookahead adder and the 164-bit left shift module constitute an addition module - add_top.

[0076] like Figure 1 As shown, the 106-bit sum, 106-bit carry, the high 55 bits of the mantissa fr output by the inversion module, and the low 106 bits of fr output by the inversion module generated by the first pipeline beat are input into the leading zero prediction module together, and the prediction result of the leading zero prediction module is output to the 164-bit left shift module for left shift.

[0077] The result of the intermediate index of the first pipeline beat and the prediction result of the leading zero prediction module are input into the index calculation module to correct the intermediate index, and the output result of the index calculation module is sent to the index post-processing module of the third pipeline beat.

[0078] The 106-bit 3:2 compressor in the addition module simultaneously inputs the 106-bit sum generated by the first pipeline beat, the 106-bit carry and the lower 106 bits of fr output by the inversion module for compression, and the output result of the 106-bit 3:2 compressor is sent to the 161-bit carry-lookahead adder.

[0079] The 161-bit carry-lookahead adder in the addition module simultaneously inputs the output result of the 106-bit 3:2 compressor and the high 55 bits of the mantissa fr output by the inversion module for addition, and the output result of the 161-bit carry-lookahead adder is sent to the 164-bit left shift module, and the final result sign bit of the output result of the 161-bit carry-lookahead adder is sent to the leading zero prediction module and the sign bit judgment module in the third pipeline beat respectively.

[0080] The 164-bit left shift module simultaneously inputs the left shift bit number of the leading zero prediction module, the output result of the 161-bit carry lookahead adder and the 3-bit rounding signal output by the negation module. The 164-bit left shift module shifts the output result of the 161-bit carry lookahead adder according to the left shift bit number output by the leading zero prediction module, and the output result of the 164-bit left shift module is sent to the absolute value module of the third pipeline beat.

[0081] like Figure 3 As shown, in the second pipeline beat of this embodiment, the addition module - add_top, which mainly completes the addition operation of the multiplication result and the fr mantissa after the order, and performs a left shift operation on the addition result. First, the three input data are compressed into two groups of data using a CSA3:2 compressor, and then the two groups of data are added using a carry-ahead adder to obtain an addition result. Finally, according to the leading zero prediction result sent by the leading zero prediction module, it is shifted to the left to obtain an addition result with the highest bit being 1. At this time, there is still a 1-bit error, and a 2-bit error is added to compensate in the last beat.

[0082] like Figure 3 As shown in the figure, when inputting, since the data compression process is different from that of normal data when there is denormal data in fs*ft, different CSA3:2 compressors are used respectively, and then the correct data is selected and sent to the 161-bit carry-ahead adder. The addition result sends the sign bit to the LZA (leading zero prediction) module to select the positive and negative coding trees, and the result is sent to the shifter. Finally, the addition result is shifted to the left in the left shifter according to the input value. The entire timing is about 340ps before the mux selection is added, and some optimization can be performed later.

[0083] Furthermore, in the addition module - add_top in the second pipeline beat of this embodiment, if the addition result is a negative number, no absolute value operation is performed in this beat.

[0084] Furthermore, in the addition module - add_top within the second pipeline beat of this embodiment, when one of the two input multipliers is the minimum non-normalized data, the valid data of the multiplication result is in the lower 53 bits. At this time, if the exponent of the addend is smaller than the exponent of the multiplication result, it is necessary to shift the mantissa of the addend out of the data and retain 3 more bits for rounding precision protection.

[0085] like Figure 1 As shown, the third pipeline beat of this embodiment includes a sign bit judgment module, a special value processing module, an absolute value module, a rounding judgment module, a 53-bit adder, a MUX selection module, an exponential post-processing module and a data selection module.

[0086] like Figure 3As shown, in the third pipeline beat of this embodiment, this module mainly completes the sign bit, exponent and mantissa rounding processing of the multiplication and addition result, and at the same time performs output special value judgment, and finally selects to output the final result and exception information.

[0087] The sign bit judgment module simultaneously inputs the operation code, rounding mode, the sign bit of fs*ft and the coincidence bit of fr in the first pipeline beat, and the final result sign bit in the second pipeline beat. The sign bit output by the sign bit judgment module is sent to the data selection module.

[0088] The special value processing module simultaneously inputs the special value indication signal of fs*ft, the special value indication signal of fs, the special value indication signal of ft, the special value indication signal of fr and the rounding mode, and the output result of the special value processing module is sent to the data selection module; the exception information obtained by the special value processing module is output as the exception judgment.

[0089] The absolute value module determines whether to take the absolute value of the output result of the 164-bit left shift module of the second pipeline beat of the input 110 bits according to the sign bit. The valid data in the output result of the absolute value module determines whether an addition operation is required according to the rounding mode, sign bit, round bit and sticky bit. The valid data that needs to be added is sent to the 53-bit adder, and the valid data that does not need to be added is sent to the MUX selection module. The data that needs to be rounded in the output result of the absolute value module is sent to the rounding judgment module, and the rounding judgment module inputs the rounding mode. The rounding judgment module performs rounding judgment on the discarded part of the data and sends its output result to the MUX selection module.

[0090] The MUX selection module selects data using the result of rounding and carrying, and the high 53 bits of the output result are simultaneously sent to the exponential post-processing module and the data selection module.

[0091] The exponential post-processing module simultaneously inputs the exponential result of the second pipeline beat and the high 53-bit data of the output result of the MUX selection module, and the exponent output by the exponential post-processing module is sent to the data selection module.

[0092] The data selection module simultaneously inputs the sign bit output by the sign bit judgment module, the output result of the special value processing module, the exponent output by the exponential post-processing module, the mantissa output by the MUX selection module and the special value defined in the IEEE754 standard, and selects the final result output.

[0093] like Figure 4As shown, in this embodiment, the leading zero prediction module in the second pipeline beat is used to predict the number of zeros generated in front of the first-level fs*ft multiplication result minus fr, and then send the number of zeros generated to the left shift module for left shifting. After the shift, the fixed bit is intercepted and rounded to obtain the final result. The leading zero prediction algorithm (LZA) is only for subtraction, so addition must be specially processed. The leading zero prediction module contains the leading zero detection module (LZD). The leading zero prediction algorithm is divided into two parts, one is the leading zero prediction of the final result, and the other is the leading zero detection of the predicted result. Therefore, LZA expands the prediction part of the leading zero of the result compared to LZD. The leading zero module is also responsible for adjusting the intermediate exponent result according to the number of leading zeros and sending out three expected exponents.

[0094] like Figure 5 As shown, the detailed design scheme of the leading zero module of this embodiment is as follows:

[0095] Leading zero module design idea: Leading zero prediction is only required for subtraction and only when subtraction will produce a large number of zeros. Leading zero prediction is not required in other cases. Next, let's discuss under what circumstances leading zero prediction is required after fr shifts.

[0096] When fr is a normalized number and the first bit after fr is shifted is in the first 54 bits of the 161-bit shifter, even if the results of AB are all 1, fr only needs to borrow 1 bit from the integer bit to meet the requirement of subtraction borrow. When the first bit after fr is shifted is at the 55th bit to the end, borrowing forward may result in a long string of 0s, so leading zero prediction is performed.

[0097] When fr is in the first 54 bits after right shift, the number of leading zeros may be the number of shifted bits or the number of shifted bits + 1, and the 1 in the number of shifted bits + 1 is generated by borrowing. From the 55th bit to the end, leading zero prediction is required. The current solution is to take the first 108 bits of 161 bits of data when the number of right shifted bits of fr is less than or equal to 53, and take the last 108 bits of data when fr is more than 53 bits right shifted. Because when fr is less than or equal to 53 bits right shifted, the result of fs*ft is directly added or subtracted from the decimal part of fr, and has no effect on the integer bit. fr can be directly moved back to the first bit of 161 bits. It should be noted that when adding, the result of fs*ft is added to fr, and there may be a carry, so when outputting the number of left shifts, one less bit needs to be shifted. Whether there is a carry error is determined by the following module. When subtracting, there is a borrow error. When outputting the number of left shifts, only the 0 generated by the right shift of fr is removed. By default, there is no borrow. Whether there is a 0 generated by borrowing is determined by the following module.

[0098] When the number of right shifts of fr is greater than 53 and leading zero prediction is required for subtraction, when adding, because the first 1 positions of sum, carry and fr are flush or only differ by one or two digits, the addition of the three numbers may have a two-digit carry error, so there are two digits of carry by default, and the result of sum, carry and fr is taken and shifted left by two digits to perform leading zero detection. When fr is shifted right by 54 digits, there is only one carry by default, because the first 1 positions of fr, sum and carry differ greatly, and there is only one carry. When leading zero prediction is performed during subtraction, the first 1 position is predicted by generating an intermediate variable encoding. The encoding value of the intermediate variable only cares about the position of the first 1, and does not care about the result of the value after the first 1. The leading zero prediction will get a value of the number of leading zeros with a one-digit error. This value can only be one digit less, so the leading zero position is shifted left first. Whether there is a one-digit error is determined by the subsequent module. When shifting left, only the last 108 bits are taken for shifting. When the first bit is 108, the shifting stops. The 53 bits before the 161th bit are discarded because they are all 0 and do not need to be shifted. After the shift, the exponent must not be less than the IEEE754 standard, so the exponent must be paid attention to while shifting. The minimum exponent is 1, so the leading zero and the exponent must be compared. When the exponent is large, the leading zero is shifted. When there are too many leading zeros, the exponent can only be shifted to 1 and the shifting cannot continue.

[0099] When taking the first 108 digits, because the exponent of fr is standardized, there is no need to worry about the exponent being less than zero. When taking the last 108 digits, the decimal point is placed after the first digit of the 108th digit by default. Now we need to consider whether the exponent is still less than 0 and needs to be shifted right when the decimal point is placed after the first digit of the 108th digit. We will discuss three cases:

[0100] When fr is much larger than the exponent of fs*ft, the first 108 bits are directly taken.

[0101] When the exponent of fr is much smaller than that of fs*ft, and the first digit of fr is behind the first digit of fs*ft, because the exponent of fr is greater than 0, and because fs*ft is greater than fr, it is guaranteed that the exponents behind the first digit of the last 108 digits are also greater than 1.

[0102] When fr is only 1, 2, or 3 digits larger than fs*ft, in order to make the exponent of the first bit of 108 smaller, the exponent of fr must also be the minimum value 1. Because the minimum exponent of fr is 1, which is greater than zero, and the exponent of the first bit of 108 is greater than the exponent of fr, the exponent of the first bit of 108 must be greater than 1. Therefore, the subsequent leading zero shift module only needs to be shifted left, and no right shift is required.

[0103] When one of fs and ft is a denormalized number, a large number of 0s will be generated in front of the product of fs*ft. The first-stage compressor will generate sum and carry. The sum and carry are added, causing a large number of 1s in front to overflow and generate a large number of zeros. However, the sum and carry are sent to the leading zero prediction module, and no overflow is generated when they are added. As a result, there are a lot of 1s in front of sum and carry, which interfere with the leading zero prediction and make it impossible to predict the leading zero. Therefore, sum and carry need to be processed to remove all the 1s that should have overflowed in front.

[0104] When two numbers are multiplied, there will be a carry in the integer position. Only when a normalized number and a denormalized number are multiplied will a string of zeros appear in front of the result. When two denormalized numbers are multiplied, they are rounded directly.

[0105] When a normalized number is multiplied by a denormalized number, the number of leading zeros in the product is the number of leading zeros in the denormalized number or the number of leading zeros in the denormalized number minus 1. Therefore, the leading zero detection is performed on the denormalized number in fs or ft at the first level, and a sequence is generated. The number of leading zeros in this sequence is the same as the number of leading zeros in the denormalized number, and the following bits are all 1, a total of 53 bits. This sequence is called a selection window. The window is padded with 1 in front and zero in the back, a total of 108 bits, covering the sum and carry. The window generated at the first level is called a medium window, and the middle window is padded with 3 1s in front, which are groundbit, round bit, and carry bit. Subtracting a 1 from the front of the middle window is called a small window, and adding a 1 to the front is called a large window. The role of the small window is to cover the result when there is a carry in the fs*ft product. The role of the large window is when the first 1 position of the fs*ft product result is the carry from sum and carry, and when sum and carry are not added, there is no carry, and the corresponding first position should be covered to ensure that it is 0. The leading zero of the fs*ft product result just discussed can only be the number of leading zeros of the denormalized number or the corresponding minus 1. This is discussed for the result. Sum and carry are intermediate variables. It is possible that a carry will be generated after addition to get the correct leading zero, so sum and carry need a large window to cover one more bit. The bit that generates a carry when sum and carry are added must be that sum and carry are both 1 in that bit, so sum and carry are bitwise ANDed, and the first 1 position is the position that generates the carry. First use the small window and the result of the bitwise AND, then use the medium window, and finally use the large window. If the result of the bitwise AND is not 0, the length of the corresponding window is the length of the overflow bit. Because sum and carry sometimes have all-1 overflow bits and sometimes not, we need to judge whether there is an all-1 overflow. Because when a normalized number is multiplied by a denormalized number, the carry bit of the 106th bit must not be a data bit, and the result of the multiplication of fs*ft must be 0, so we can use the 106th bit to judge whether there is an all-1 overflow. Take out the 106th bit of sum and carry and OR them. If it is 1, it means there is an all-1 overflow bit, and if it is 0, it means there is no all-1 overflow bit.

[0106] The parts not involved in the present invention are the same as the prior art or can be implemented by using the prior art.

[0107] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes in form and details may be made without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A floating-point multiplier-adder, realizing a floating-point multiplication-addition operation in the form of A*B+C, characterized in that: The floating-point multiplier-adder implements floating-point multiplication and addition operations in a three-stage pipeline mode. The first pipeline beat completes floating-point multiplication, the second pipeline beat completes addition, and the third pipeline beat completes rounding operations and exception judgments, and outputs the final result. The first pipeline beat includes a sign bit processing module, an exponential preprocessing module, a 161-bit right shift module, a negation module, a partial product generation module, and a Wallace compression tree module. The sign bit processing module determines the sign bit to be corrected according to the operation code and the sign bits of the three operands. The sign bit of fs*ft and the coincidence bit of fr of the output result of the sign bit processing module are sent to the sign bit judgment module of the third pipeline beat. The valid subtraction indication signal of the output result of the sign bit processing module is sent to the negation module; wherein fs, ft and fr refer to A, B and C in A*B+C respectively; The exponential preprocessing module and the 161-bit right shift module constitute an exponential top-level module. The exponential preprocessing module in the exponential top-level module simultaneously inputs the exponential bits of the three operands, calculates the intermediate exponential result, and provides it to the exponential calculation module in the second pipeline beat for exponential calculation. At the same time, the exponential preprocessing module calculates the number of right shift bits required for fr according to the exponent of fs*ft+fr, and provides it to the 161-bit right shift module. The 161-bit right shift module simultaneously inputs the result right shift bit of the exponential preprocessing module and the mantissa bit of fr to right shift the mantissa of fr; The negation module determines whether to negate the mantissa of fr after the right shift according to the valid subtraction indication signal provided by the sign bit processing module, the lower 106 bits of fr output by the negation module are sent to the 106-bit 3:2 compressor in the second pipeline beat, the higher 55 bits of the mantissa fr output by the negation module are simultaneously sent to the leading zero prediction module and the 161-bit carry look-ahead adder in the second pipeline beat, and the 3-bit rounding signal output by the negation module is sent to the 164-bit left shift module in the second pipeline beat; The partial product generation module and the Wallace compression tree module constitute a multiplication module. The partial product generation module simultaneously inputs the mantissa of fs and the mantissa of ft to perform multiplication of two floating-point mantissas. The output of the partial product generation module is sent to the Wallace compression tree module for compression to generate two sets of data: 106-bit sum and 106-bit carry. The second pipeline beat includes a leading zero prediction module, an exponent calculation module, a 106-bit 3:2 compressor, a 161-bit carry-lookahead adder and a 164-bit left shift module, and the 106-bit 3:2 compressor, the 161-bit carry-lookahead adder and the 164-bit left shift module constitute an addition module; The 106-bit sum, 106-bit carry, the high 55-bit number of the mantissa fr output by the negation module, and the low 106-bit number of fr output by the negation module generated by the first pipeline beat are input into the leading zero prediction module together, and the prediction result of the leading zero prediction module is output to the 164-bit left shift module for left shifting; The result of the intermediate index of the first pipeline beat and the prediction result of the leading zero prediction module are input into the index calculation module to correct the intermediate index, and the output result of the index calculation module is sent to the index post-processing module of the third pipeline beat; The 106-bit 3:2 compressor in the addition module simultaneously inputs the 106-bit sum generated by the first pipeline beat, the 106-bit carry and the lower 106-bit number of fr output by the negation module for compression, and the output result of the 106-bit 3:2 compressor is sent to the 161-bit carry-lookahead adder; The 161-bit carry-lookahead adder in the addition module simultaneously inputs the output result of the 106-bit 3:2 compressor and the high 55 bits of the mantissa fr output by the negation module for addition, and the output result of the 161-bit carry-lookahead adder is sent to the 164-bit left shift module, and the final result sign bit of the output result of the 161-bit carry-lookahead adder is sent to the leading zero prediction module and the sign bit judgment module in the third pipeline beat respectively; The 164-bit left shift module simultaneously inputs the left shift bit number of the leading zero prediction module, the output result of the 161-bit carry lookahead adder and the 3-bit rounding signal output by the negation module, the 164-bit left shift module shifts the output result of the 161-bit carry lookahead adder according to the left shift bit number output by the leading zero prediction module, and the output result of the 164-bit left shift module is sent to the absolute value module of the third pipeline beat; The third pipeline beat includes a sign bit judgment module, a special value processing module, an absolute value module, a rounding judgment module, a 53-bit adder, a MUX selection module, an exponential post-processing module and a data selection module. The sign bit judgment module simultaneously inputs the operation code, the rounding mode, the sign bit of fs*ft and the coincidence bit of fr in the first pipeline beat, and the final result sign bit in the second pipeline beat, and the sign bit output by the sign bit judgment module is sent to the data selection module; The special value processing module simultaneously inputs the special value indication signal of fs*ft, the special value indication signal of fs, the special value indication signal of ft, the special value indication signal of fr and the rounding mode, and the output result of the special value processing module is sent to the data selection module; the exception information obtained by the special value processing module is output as the exception judgment; The absolute value module determines whether to take the absolute value of the output result of the 164-bit left shift module of the second pipeline beat of the input 110 bits according to the sign bit. The valid data in the output result of the absolute value module determines whether an addition operation is required according to the rounding mode, sign bit, round bit and sticky bit. The valid data that needs to be added is sent to the 53-bit adder, and the valid data that does not need to be added is sent to the MUX selection module. The data that needs to be rounded in the output result of the absolute value module is sent to the rounding judgment module, and the rounding judgment module inputs the rounding mode. The rounding judgment module performs rounding judgment on the discarded part of the data and sends its output result to the MUX selection module. The MUX selection module selects the data using the rounding result of the input data, and the high 53 bits of the output result are simultaneously sent to the exponential post-processing module and the data selection module; The exponential post-processing module simultaneously inputs the exponential result of the second pipeline beat and the high 53-bit data of the output result of the MUX selection module, and the exponent output by the exponential post-processing module is sent to the data selection module; The data selection module simultaneously inputs the sign bit output by the sign bit judgment module, the output result of the special value processing module, the exponent output by the exponential post-processing module, the mantissa output by the MUX selection module and the special value defined in the IEEE754 standard, and selects the final result output.

2. The floating-point multiplier-adder according to claim 1, wherein: The partial product generation module in the multiplication module adopts radix-4 booth coding, and the Wallace compression tree module in the multiplication module adopts CSA4:2 compressor.

3. The floating-point multiplier-adder according to claim 1, wherein: The shift-to-order function in the exponential top-level module includes exponent difference calculation and right shift of the mantissa. The exponent difference calculation is that the exponent preprocessing module offsets fr to the left by 56 bits, calculates the difference d between the exponents of fr and fs*ft, and sends the calculated difference d to the 161-bit right shift module to shift the exponents of fr and fs*ft to be consistent, and then add them; When the floating point number is a double precision floating point number, d = exp(fs)+exp(ft)-exp(fr)-967; When the floating point number is a single-precision floating point number, d = exp(fs)+exp(ft)-exp(fr)-71; The mantissa right shifts the operand fr right according to the difference d calculated by the exponent difference, and the shifted digits are reserved for the following module rounding.

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