A spaceborne computer detection system

Abstract

The present application provides a satellite computer detection system, comprising an onboard computer and a single-board test board, the single-board test board comprising a plurality of first data interfaces and a core controller; the core controller being configured to simulate various environmental status signals of the onboard computer in an operating mode, transmit the corresponding environmental status signals to the onboard computer via the first data interface, and determine whether an abnormality has occurred in the onboard computer based on a data feedback signal received from the onboard computer; and the onboard computer being configured to process the environmental status signals to obtain a data feedback signal. The present application can simulate the entire onboard computer in different operating states and can test various application functions of the onboard computer via the single-board test board, thereby improving test efficiency and reducing test costs while accelerating the process of troubleshooting incorrect designs and abnormal conditions during the onboard computer design process.

Description

Technical Field

[0001] The present application relates to the field of spacecraft technology, and in particular to a spaceborne computer detection system. Background Art

[0002] Onboard computers typically refer to the core control systems of electronic systems onboard spacecraft such as satellites. They perform tasks such as operational support, mission planning, and data scheduling during the satellite's in-orbit operation. Due to the diverse mission types and high data complexity of satellite electronic systems, onboard computers typically have complex data interfaces with diverse speed requirements and signal types. Furthermore, the same data interface may include multiple different data protocols.

[0003] As for the traditional testing method for onboard computers, different external tools are usually used to perform tests according to the requirements and data conventions of different interfaces on the onboard computers. This testing method consumes more resource and equipment costs and has low testing efficiency. In addition, with the current development of digital circuits, the integration of circuits in onboard computers has become higher and the mainboard area has decreased, resulting in an increase in the density of onboard computer interface lines and an increase in the difficulty of testing a single interface. In the process of completing and processing onboard tasks, various interface data linkages will occur. Therefore, the method of using traditional external tools to detect the connection of a single interface cannot fully simulate the working status of the entire onboard computer. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a satellite computer detection system, which can simulate the entire satellite computer in different working conditions and can test various application functions of the satellite computer through a single-board test board. While improving the test efficiency and reducing the test cost, it also speeds up the progress of detecting incorrect designs and abnormal conditions during the design process of the satellite computer.

[0005] The embodiment of the present application provides a satellite computer detection system, the satellite computer detection system includes a satellite computer and a single-board test board, the single-board test board includes multiple first data interfaces and a core controller, the first data interface is connected to the second data interface of the satellite computer in a stacked plug-in manner; wherein,

[0006] The core controller is configured to simulate various environmental status signals of the onboard computer in a working mode, send the corresponding environmental status signals to the onboard computer through the first data interface, and determine whether an application function of the onboard computer is abnormal based on a received data feedback signal sent by the onboard computer;

[0007] The onboard computer is used to process the environmental status signal to obtain the data feedback signal, and send the data feedback signal to the core controller through the second data interface.

[0008] Furthermore, the first data interface includes at least one of the following interfaces:

[0009] First RS422 interface, first CAN bus interface, first AD interface, DA interface, USB interface.

[0010] Furthermore, the second data interface includes a second AD interface, the environmental status signal includes a temperature simulation signal; the application function includes a temperature control function, wherein,

[0011] The core controller is configured to send the temperature simulation signal to the onboard computer via the second AD interface, and determine whether the temperature control function of the onboard computer is abnormal based on the received temperature feedback signal sent by the onboard computer;

[0012] The onboard computer is used to process the temperature simulation signal to obtain the temperature feedback signal.

[0013] Furthermore, the core controller is configured to send the temperature simulation signal to the onboard computer using the second AD interface, including:

[0014] The core controller is used to send the temperature simulation signal to the second AD interface of the onboard computer through the DA interface, and send the temperature simulation signal to the onboard computer through the second AD interface.

[0015] Furthermore, the second data interface further includes a second CAN bus interface and a second RS422 interface, and the environmental status signal further includes a CAN bus analog signal; wherein,

[0016] The core controller is configured to send the CAN bus analog signal to the onboard computer using the second CAN bus interface, and determine whether the second CAN bus interface and the second RS422 interface of the onboard computer are abnormal based on a received package feedback signal sent by the onboard computer;

[0017] The onboard computer is used to process the CAN bus analog signal to obtain a packaged feedback signal, and send the packaged feedback signal to the core controller through a serial port data interface.

[0018] Furthermore, the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the onboard computer are abnormal according to the following steps:

[0019] performing subpackaging and parsing processing on the received packaged feedback signal sent by the onboard computer to generate a parsed feedback signal;

[0020] Determining whether the analysis feedback signal and the CAN bus analog signal are consistent based on the tag information of the analysis feedback signal and the tag information of the CAN bus analog signal;

[0021] If so, it is determined that both the second CAN bus interface and the second RS422 interface are normal.

[0022] Furthermore, the environmental status signal also includes a voltage simulation signal, and the application function includes a voltage detection function; wherein,

[0023] The core controller is configured to send the voltage analog signal to the onboard computer using the second AD interface, and determine whether the voltage detection function of the onboard computer is abnormal based on the received voltage feedback signal sent by the onboard computer;

[0024] The onboard computer is used to process the voltage analog signal to obtain the voltage feedback signal.

[0025] Furthermore, the voltage feedback signal is a voltage signal including a flag bit fed back by the onboard computer via the second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:

[0026] Whether the voltage detection function of the onboard computer is abnormal is determined based on the digital information and position information of the mark bit.

[0027] Furthermore, the single-board test board also includes a resistor voltage divider circuit, which is connected to the first AD interface and is used to simulate voltage simulation signals of different voltage values corresponding to the onboard computer in the working mode.

[0028] Furthermore, the USB interface is connected to an external terminal device; wherein,

[0029] The USB interface is used to send data feedback signals to an external terminal device;

[0030] The external terminal device is used to draw a detection waveform diagram based on the data feedback signal received from the USB interface.

[0031] Compared with the prior art, the onboard computer detection system provided in the embodiments of the present application can simulate the entire onboard computer in different working states, and can test various application functions of the onboard computer through a single-board test board. While improving test efficiency and reducing test costs, it speeds up the progress of detecting incorrect designs and abnormal conditions during the design process of the onboard computer.

[0032] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A structural block diagram of a detection system for onboard computing provided in an embodiment of the present application is shown;

[0035] Figure 2 A structural block diagram of a USB interface design in a detection system for onboard computing provided by an embodiment of the present application is shown;

[0036] Figure 3 A structural block diagram of a resistor voltage divider circuit in a detection system for onboard computing provided by an embodiment of the present application is shown;

[0037] Figure 4 A structural block diagram of a single-board test board in a satellite-based computing detection system provided in an embodiment of the present application is shown.

[0038] In the picture:

[0039] 10-Onboard computer detection system; 100-Single-board test board; 110-Core controller; 111-Programmable control chip; 1111-Microcontroller; 1112-Logic resource processing sub-chip; 112-Level matching chip; 120-First data interface; 130-Resistor voltage divider circuit; R1-First resistor; R2-Second resistor; U-Power supply; 200-Onboard computer; 210-Second data interface. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work falls within the scope of protection of the present application.

[0041] First of all, research has found that the traditional testing method for onboard computers in the existing technology usually uses different external tools to perform tests according to the requirements and data conventions of different interfaces on the onboard computer. This testing method consumes more resource and equipment costs and has low testing efficiency. In addition, with the current development of digital circuits, the integration of circuits in onboard computers has become higher and the mainboard area has decreased, resulting in an increase in the density of onboard computer interface lines and an increase in the difficulty of testing a single interface. In the process of completing and processing onboard tasks, the onboard computer will have various interface data linkages. Therefore, the method of using traditional external tools to detect the connection of a single interface cannot fully simulate the working status of the entire onboard computer.

[0042] Based on this, an embodiment of the present application provides a satellite computer detection system that can simulate the entire satellite computer in different working conditions, and can test various application functions of the satellite computer through a single-board test board. While improving test efficiency and reducing test costs, it also speeds up the progress of detecting incorrect designs and abnormal conditions during the design process of the satellite computer.

[0043] See also Figure 1 , Figure 1 This is a structural block diagram of a satellite-borne computer detection system provided in an embodiment of the present application. Figure 1 As shown in , the onboard computer detection system 10 provided in an embodiment of the present application includes an onboard computer 200 and a single-board test board 100, the single-board test board 100 includes multiple first data interfaces 120 and a core controller 110, and the first data interface 120 is connected to the second data interface 210 of the onboard computer 200 in a stacked plug-in manner.

[0044] In the above-mentioned specific embodiment, the onboard computer 200 in the onboard computer detection system 10 is the core control system on the spacecraft, and the single-board test board 100 included in the onboard computer detection system 10 can detect the configuration data of each interface in the onboard computer 200 and the functional data of each interface, as well as the processing configuration data of the onboard computer 200 when performing different flight missions, and the single-board test board 100 itself has independent operation and programmable conditions. Compared with the onboard computer 200, the single-board test board 100 is equivalent to a lower-level machine inspection device actively controlled by the onboard computer, and the specific connection method is: the onboard computer is stacked and plugged into the first data interface 120 of the single-board test board 100 through the second data interface 210, which facilitates data interaction between the onboard computer and the single-board test board 100.

[0045] In the above, the single-board test board 100 designs the corresponding data flow according to the actual usage scenario, and sends various environmental status signals of the simulated on-board computer 200 in the working mode to the on-board computer 200 through various types of first data interfaces 120, which is used to simulate the data interaction process between the real application subsystem and the on-board computer 200 during satellite operation, and judge whether there are any abnormalities in the configuration data of the on-board computer 200 and the functional data of the second interface according to the status performance of the on-board computer 200 and the task processing results in the above simulation process.

[0046] Here, the size of the single-board test board 100 is designed to be stacked and plugged in according to the actual size of the onboard computer 200. Therefore, the single-board test board 100 can simulate the actual installation conditions of the onboard computer 200 and can perform various related environmental tests together with the onboard computer 200 to facilitate acceptance testing.

[0047] Among them, the onboard computer 200 is used to ensure the operating status, mission planning and data scheduling of the spacecraft during its on-orbit operation, and the second data interface 210 in the onboard computer 200 includes at least a second RS422 interface, a second CAN bus interface and a second AD interface, etc., and the mission working mode of the onboard computer 200 includes multiple situations in which the second data interface 210 is linked.

[0048] Here, a specific embodiment is given to illustrate the task working mode of multiple second data interfaces 210 being linked, as shown below:

[0049] For example, after the second CAN bus interface packages the received task data and receives a data sending instruction, it is necessary to transmit the above-mentioned packaged task data from the second RS422 interface in a specific format and parse the received data according to the interface protocol of the second RS422 interface. In this way, the logic value of certain OC ports will be changed, that is, the second RS422 interface in the embodiment provided by the present application, where the OC port is an output comparison port, which is an output for the pin. It can be set to count and output a high level or a low level, which is mainly used to output pulses.

[0050] Among them, the core controller is used to simulate various environmental status signals of the onboard computer 200 in the working mode, and send the corresponding environmental status signals to the onboard computer 200 through the first data interface 120, and determine whether the application function of the onboard computer 200 is abnormal based on the data feedback signal received from the onboard computer 200.

[0051] In the above specific implementation manner, the core controller 110 in the single-board test board 100 is implemented using an FPGA SoC chip. The core controller has both FPGA logic resources and microcontroller 1111 processing resources. The single-board test board 100 designs and simulates various environmental status signals of the external application stand-alone device in the working mode of the onboard computer 200 through the internal microcontroller 1111 processing resources, and designs functional algorithms corresponding to the relevant environmental status signals. The various environmental status signals representing various types of functional data are sent by the microcontroller 1111 to the logic resource processing sub-chip 1112 inside the single-board test board 100, and the various environmental status signals are sent by the logic resource processing sub-chip 1112 to the onboard computer 200 via the first data interface 120.

[0052] The FPGA SoC chip can meet the logic implementation and data calculation of many first data interface 120 functions, and the parallel timing design capability of the FPGA can coordinate the data communication functions and data flows of each first data interface 120, and the microcontroller 1111 in the core controller can calculate the data according to the algorithm, so that the onboard computer detection system 10 in this application is more adaptable with the support of the core controller 110, and realizes more specific simulation of various environmental status signals of the onboard computer 200 in the working mode. Among them, the microcontroller 1111 in the embodiment provided in this application can select an ARM hard-core controller.

[0053] In the above, the core controller is also used to receive data feedback signals sent by the onboard computer 200, and determine whether various application functions of the onboard computer 200 are abnormal based on the data feedback signals and the functional algorithm edited by the microcontroller 1111 inside the core controller.

[0054] Preferably, the first data interface 120 includes at least one of the following interfaces: a first RS422 interface, a first CAN bus interface, a first AD interface, a DA interface, and a USB interface.

[0055] Here, the second data interface 210 of the onboard computer 200 includes a second RS422 interface, a second CAN bus interface and a second AD interface. The first RS422 interface in the first data interface 120 of the single-board test board 100 is stacked and plugged with the second RS422 interface in the second data interface 210 of the onboard computer 200. The first CAN bus interface in the first data interface 120 of the single-board test board 100 is stacked and plugged with the second CAN bus interface in the second data interface 210 of the onboard computer 200. The DA interface and the first AD interface in the first data interface 120 of the single-board test board 100 are both stacked and plugged with the second AD interface in the second data interface 210 of the onboard computer 200. The USB interface in the first data interface 120 of the single-board test board 100 is connected to an external terminal device, wherein the USB interface is used to send a data feedback signal to an external terminal device; and the external terminal device is used to draw a detection waveform based on the data feedback signal received from the USB interface.

[0056] In the above-mentioned process of designing the single-board test board 100, due to the consideration of user portability and the actual use of equipment in satellites (such as spacecraft, etc.), the single-board test board 100 and the on-board computer 200 are connected using a stacking plug-in connection, and the stacking plug-in connection is also the installation method of electronic products in satellites.

[0057] Here, some of the first data interface 120 connection nodes of the single-board test board 100 are connected through on-board plug-in contacts. By adopting a single-board installation method, the various nodes used on the satellite can be fully contacted, and in addition to the above-mentioned functional coverage test, comprehensive testing can also be performed on the physical interface and electrical standards.

[0058] Among them, the hardware design of the USB interface is to implement the communication protocol using the USB 2.0 communication protocol driver chip. The embodiment provided in this application selects the FTDI FT232H controller chip as the communication protocol driver chip, and implements USB 2.0 high-speed data communication through the FTDI FT232H controller chip. The controller supports up to 480Mbps.

[0059] like Figure 2 As stated, Figure 2 This is a structural block diagram of a USB interface design in a detection system for onboard computing provided in an embodiment of the present application. Figure 2 In the FT232H controller chip, a 12MHz crystal oscillator provides the chip operating clock. The protocol used during communication is pre-programmed through an external directly connected electrically programmable read-only memory (EEPROM). The USB 2.0 data interface is brought out from the DP and DM pins of the FT232H controller chip. These two signals are connected to the communication connector to complete the external connection to the USB 2.0 interface.

[0060] Thus, when using the FT232H to drive USB 2.0, it is necessary to configure the FT232H to the FT245 mode synchronous FIFO interface to convert USB 2.0 serial data into 8-bit wide encoded data. When using this mode, the main signals are shown in Table 1:

[0061] Table 1 FT232H and star sensor main control chip connection signal table

[0062]

[0063] Here, the read operation driver design for the FT232H chip in Table 1 is as follows:

[0064] When the chip outputs RXF# low, a read operation can be performed. Before the RD# signal becomes low, the FPGA SoC system can set OE# to low, making the signal direction of the data bus driver output, so that the FPGA SoC side can read data; after OE# is low, the first data byte begins to appear on the data. Once all the data has been read, the chip will drive RXF# high. After RXF# is high, all data appearing on the data bus is invalid and should be ignored.

[0065] The FT232H chip write operation driver design is as follows:

[0066] When TXE# is low, the write operation can be started. When the write data operation is valid, WR# changes from high to low. As long as TXE# remains low, the write operation can be performed continuously on each clock. The FPGA SoC resource chip driver must monitor the TXE# and WR# signals to check whether the receiver has received the data. When both are not low, the data cannot be received by the data bus, and all data appearing on the data bus is invalid.

[0067] Here, the above-mentioned USB 2.0 drive signal is controlled by the core controller in the single-board test board 100 and the data signal is collected and read. After the external terminal device receives the data feedback signal and performs auxiliary analysis, the external terminal device performs auxiliary analysis on the data feedback signal, provides dynamic analysis data, and draws a waveform diagram to facilitate the tester to view it more intuitively.

[0068] The onboard computer 200 is configured to process the environmental status signal to obtain the data feedback signal, and send the data feedback signal to the core controller via the second data interface 210 .

[0069] In the above specific implementation manner, the onboard computer 200 is used to process the environmental status signal simulated by the single-board test board, wherein the processing methods include but are not limited to judgment processing, calculation processing, packaging processing and design processing. After processing, the obtained data feedback signal is sent to the core controller through the second data interface 210.

[0070] Preferably, the second data interface 210 includes a second AD interface, and the environmental status signal includes a temperature simulation signal; the application function includes a temperature control function, wherein the core controller is used to use the second AD interface to send the temperature simulation signal to the onboard computer 200, and determine whether the temperature control function of the onboard computer 200 is abnormal based on the received temperature feedback signal sent by the onboard computer 200.

[0071] The onboard computer 200 is used to process the temperature simulation signal to obtain the temperature feedback signal.

[0072] In the above, when the temperature control function of the onboard computer 200 needs to be detected in the embodiment provided by the present application, the onboard computer detection system 10 needs to simulate an external temperature control application subsystem. At this time, the microcontroller 1111 of the core controller simulates a first temperature digital signal, and converts the first temperature digital signal into a first analog signal through the DA conversion controller in the logic resource processing sub-chip 1112, and sends the first analog signal to the second AD interface of the onboard computer 200 through the DA interface. The onboard computer 200 converts the first analog signal into a first digital signal via AD, and the first analog signal is converted into a first data signal via AD. At this time, the onboard computer 200 determines whether the first data signal is higher than a preset low temperature threshold. If it is greater than the preset low temperature threshold, the onboard computer 200 starts heating and outputs the heating temperature feedback signal to the microcontroller 1111 in the detection system through the second AD interface. At this time, the microcontroller 1111 simulates a second temperature digital signal (the second temperature digital signal is greater than the preset low temperature threshold of the onboard computer 200, and The onboard computer 200 receives a second temperature digital signal (less than a preset high temperature threshold of the onboard computer 200) and sends the second temperature digital signal to the onboard computer 200. If, after processing, the onboard computer 200 continuously outputs a temperature feedback signal to the detection system to continue heating, it is said that the temperature control function of the onboard computer 200 is abnormal at this point. Then, the microcontroller 1111 of the core controller simulates a third temperature digital signal and converts the third temperature digital signal into a third analog signal via the DA conversion controller in the logic resource processing sub-chip 1112. The third analog signal is then sent to the second AD interface of the onboard computer 200 via the DA interface. The onboard computer 200 converts the third analog signal into a third digital signal (the third digital signal is higher than the preset high temperature threshold) via the DA interface. The third analog signal is then converted into a third data signal via the DA interface. At this point, if the onboard computer 200 determines whether the third data signal is higher than the preset low temperature threshold and outputs a temperature feedback signal to the detection system to stop heating, the detection system determines that the temperature control function of the onboard computer 200 is normal based on the temperature feedback signal.

[0073] Here, the detection system performs timing analysis on the level and PWM waveform of the temperature feedback signal. If the analysis result is different from the working status result represented by the temperature feedback signal sent by the onboard computer 200 to the detection system, it is determined that the temperature control function of the onboard computer 200 is abnormal.

[0074] Among them, the temperature control function of the onboard computer 200 is specifically as follows: after the onboard computer 200 receives a temperature simulation signal lower than a preset low temperature threshold, the temperature simulation signal is heated to determine that the working mode of the onboard computer 200 is a heating state; if the temperature simulation signal is higher than the preset high temperature threshold, the onboard computer 200 determines to stop heating the temperature simulation signal and determines that the working mode of the onboard computer 200 is a stop heating state.

[0075] Preferably, the second data interface 210 further includes a second CAN bus interface and a second RS422 interface, and the environmental status signal further includes a CAN bus analog signal; wherein,

[0076] The core controller is used to use the second CAN bus interface to send the CAN bus analog signal to the onboard computer 200, and determine whether the second CAN bus interface and the second RS422 interface of the onboard computer 200 are abnormal based on the received packaged feedback signal sent by the onboard computer 200; the onboard computer 200 is used to process the CAN bus analog signal to obtain a packaged feedback signal, and send the packaged feedback signal to the core controller through the serial port data interface.

[0077] In the above, when the second CAN bus interface and the second RS422 interface of the onboard computer 200 need to be detected in the embodiment provided by this application, the simplest case is:

[0078] First, connect the first CAN bus interface of the first data interface 120 in the detection system to the first CAN bus interface of the second data interface 210 in the onboard computer 200, and connect the first RS422 interface of the first data interface 120 in the detection system to the second RS422 interface of the second data interface 210 in the onboard computer 200. If the second CAN bus interface or the second RS422 interface of the onboard computer 200 can successfully send the corresponding data feedback signal, it means that there is no abnormality in the functional design of the second CAN bus interface or the second RS422 interface of the onboard computer 200.

[0079] Here, during the mission processing of the onboard computer 200, in addition to the basic data transmission and forwarding functions, the second CAN bus interface and the second RS422 interface may also be used for interface linkage. For example, to transmit the telemetry and remote control environment status signal received via the second CAN bus to a single ground device, the second CAN bus and the second RS422 interface may need to be connected in series for linkage detection. The following example illustrates this:

[0080] For example, if the single-board test board 100 needs to send the simulated temperature measurement signals of 100 thermal controllers to the onboard computer 200 through the second AD interface on the onboard computer 200, the onboard computer 200 will send the processed data feedback signal to the data transmission system after performing a series of processing and complex calculation and judgment processing of the onboard computer 200. The signal channel between the onboard computer 200 and the data transmission system is strictly one-to-one. Therefore, at this time, the single-board test board 100 needs to simulate the data transmission system and receive the corresponding type of data feedback signal one-to-one through the first RS422 interface on the single-board test board 100, and send it to the ground receiving station after receiving it, so as to realize the detection of the linkage of the first data interface 120 in the onboard computer 200.

[0081] Preferably, the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the onboard computer 200 are abnormal according to the following steps:

[0082] The received packaged feedback signal sent by the onboard computer 200 is packaged and parsed to generate a parsed feedback signal.

[0083] In the above, the onboard computer 200 will package the received CAN bus analog signal and send the packaged data feedback signal to the single-board test board 100. The single-board test board 100 will then subpackage and parse the packaged data feedback signal to generate a parsed feedback signal and analyze the specific content on the back of the parsed feedback signal.

[0084] According to the tag information of the analysis feedback signal and the tag information of the CAN bus analog signal, it is determined whether the analysis feedback signal and the CAN bus analog signal are consistent.

[0085] If so, it is determined that both the second CAN bus interface and the second RS422 interface are normal.

[0086] In the above, if the single board test board 100 determines that the content of the analyzed feedback signal is consistent with the content of the CAN bus analog signal after labeling the CAN bus analog signal and the analyzed feedback signal, it is determined that the second CAN bus interface and the second RS422 interface are both normal.

[0087] Here, if the single-board test board 100 determines that the content of the analyzed feedback signal is inconsistent with the content of the CAN bus analog signal after labeling the CAN bus analog signal and the analyzed feedback signal, it is determined that there is an abnormality in the second CAN bus interface and the second RS422 interface. At this time, according to the actual situation, the second CAN bus interface or the second RS422 interface is reset, designed and debugged.

[0088] Preferably, the environmental status signal also includes a voltage simulation signal, and the application function includes a voltage detection function; wherein the core controller is used to send the voltage simulation signal to the onboard computer 200 using the second AD interface, and determine whether the voltage detection function of the onboard computer 200 is abnormal based on the received voltage feedback signal sent by the onboard computer 200; the onboard computer 200 is used to process the voltage simulation signal to obtain the voltage feedback signal.

[0089] In the above description, the function of the onboard computer 200 to detect whether the power supply is abnormal is specifically as follows:

[0090] The second AD interface of the onboard computer 200 typically collects a V reference voltage value. That is, when the second AD interface performs analog signal quantization transmission, the full scale is 5V. Therefore, in the hardware design of the onboard computer 200, the voltage values of the above-mentioned multiple power supplies (the voltage values of the power supplies are typically 28V, 12V, and 5V, etc.) are divided by the first resistor and the second resistor to obtain a 3V voltage, and the 3V voltage is connected to the input end of the second AD interface. When the second AD interface of the onboard computer 200 receives the 3V voltage, it is considered that the corresponding high voltage value is also correct, because the high voltage value actually used for power supply and the collected voltage value are divided by resistors. When the absolute value of the difference between the collected voltage value and the 3V voltage value exceeds the preset voltage value of the onboard calculation, it is considered that the onboard computer 200 has detected a power supply abnormality of the power supply.

[0091] When the single-board test board 100 in the embodiment provided herein needs to test the stand-alone power supply function of the onboard computer 200, the single-board test board 100 first transmits the voltage analog signal corresponding to the 3V voltage analog signal output by the chip to the DA interface via the DA interface. At this time, the second AD interface of the onboard computer 200 obtains the quantized value of the analog signal. The onboard computer 200 determines whether the voltage meets the normal working state according to the threshold deviation judgment method and sends a voltage feedback signal through the second CAN bus interface. If the voltage feedback signal at this time is a preset mark symbol representing normal power supply, the single-board test board 100 determines that the voltage detection function of the onboard computer 200 is normal. If the single-board test board 100 outputs a voltage analog signal with a large deviation of 3V, the onboard computer 200 also generates the quantized voltage value corresponding to the voltage analog signal according to the threshold deviation judgment method. If the voltage feedback signal at this time is a preset mark symbol representing normal power supply, the single-board test board 100 determines that the voltage detection function of the onboard computer 200 is abnormal.

[0092] Preferably, the voltage feedback signal is a voltage signal including a flag bit fed back by the onboard computer 200 via the second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:

[0093] Whether the voltage detection function of the onboard computer 200 is abnormal is determined based on the digital information and position information of the mark bit.

[0094] In the above, the mark bit is the bit indicating the working condition of the power supply in the table, and the mark bit can be customized. For example, the mark bit can be set to the last bit of the voltage feedback signal according to the digital information and position information, such as using "0" to indicate that the voltage detection function is abnormal, using "1" to indicate that the voltage detection function is abnormal, and using "0" to indicate that the voltage detection function is normal.

[0095] Preferably, the single-board test board 100 further includes a resistor voltage divider circuit 130, the resistor voltage divider circuit 130 is connected to the first AD interface, and the resistor voltage divider circuit 130 is used to simulate voltage analog signals of different voltage values corresponding to the onboard computer 200 in the working mode, such as Figure 3 As shown, Figure 3 This is a structural block diagram of a resistor divider circuit in a detection system for onboard computing provided in an embodiment of the present application. The resistor divider circuit 130 includes a first resistor R1, a second resistor R2, and a power supply U. The positive terminal of the power supply U is connected in series with the first resistor R1 and the second resistor R2 and then grounded. The negative terminal of the power supply U is grounded. The end where the first resistor R1 and the second resistor R2 are connected is connected to the first AD interface.

[0096] The onboard computer detection system 10 provided in the embodiment of the present application, compared with the prior art, uses a single-board test board to simulate various environmental status signals of the card onboard computer 200 in the working mode, thereby realizing the simulation of the entire onboard computer 200 in different working states, and testing of various interfaces of the onboard computer 200, avoiding the need to use different external tools to perform a single interface test. While improving test efficiency and reducing test costs, it speeds up the progress of troubleshooting incorrect designs and abnormal conditions during the design process of the onboard computer 200.

[0097] See also Figure 4 , Figure 4 This is a structural block diagram of a single-board test board 100 in a detection system for onboard computing provided by another embodiment of the present application. Figure 4 As shown in , the single-board test board 100 provided in the embodiment of the present application includes:

[0098] The onboard computer detection system 10 includes an onboard computer 200 and a single-board test board 100. The single-board test board 100 includes multiple first data interfaces 120 and a core controller. The first data interface 120 is stacked and plug-in connected to the second data interface 210 of the onboard computer. The core controller includes a programmable control chip 111 and a level matching chip 112. The programmable control chip 111 includes a microcontroller 1111 and a logic resource processing sub-chip 1112.

[0099] The level matching chip 112 is used to match the corresponding first data interface 120 to obtain various environmental status signals of the simulated onboard computer 200 in the working mode from the programmable control chip 111.

[0100] The microcontroller 1111 adopts an ARM hard-core microcontroller 1111, wherein the logic resource processing sub-chip 1112 includes a CAN controller, a serial port controller, an LVDS interface controller, a DA conversion controller, an AD conversion controller and a USB interface timing, and the corresponding level matching chip 112 includes a CAN bus transceiver, an RE422 level matching chip 112, a DA conversion chip, an AD conversion chip and a USB protocol chip.

[0101] The RE422 level matching chip 112 adopts the MAX3488ESA RS422 differential level protocol chip to convert the single-ended serial communication interface into an RS422 interface. The CAN bus transceiver adopts the TJA1040T chip, the AD conversion chip adopts the ADS8344 chip, and the DA conversion chip adopts the DAC80508 chip.

[0102] Compared with the prior art, the single-board test board 100 in the embodiment provided in the present application can simulate the various environmental status signals of the onboard computer 200 in the working mode, thereby realizing the test of each interface of the onboard computer 200 under different working states, avoiding the need to use different external tools to test a single interface. While improving the test efficiency and reducing the test cost, it speeds up the progress of troubleshooting incorrect designs and abnormal conditions during the design process of the onboard computer 200.

[0103] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system described above can refer to the corresponding process in the aforementioned system embodiment, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed system can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple subsystems or modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some communication interface, which can be electrical, mechanical or other forms.

[0104] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0105] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0106] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A satellite-borne computer detection system, characterized in that: The onboard computer detection system includes an onboard computer and a single-board test board, the single-board test board includes multiple first data interfaces and a core controller, the first data interface is connected to the second data interface of the onboard computer in a stacked plug-in manner, and the second data interface includes a second CAN bus interface and a second RS422 interface; wherein, The core controller is configured to simulate various environmental status signals of the onboard computer in a working mode, send the corresponding environmental status signals to the onboard computer through the first data interface, and determine whether an application function of the onboard computer is abnormal based on a received data feedback signal sent by the onboard computer; The onboard computer is configured to process the environmental status signal to obtain the data feedback signal, and send the data feedback signal to the core controller via the second data interface; the environmental status signal includes a CAN bus analog signal; The core controller is further configured to send the CAN bus analog signal to the onboard computer using the second CAN bus interface, and determine whether the second CAN bus interface and the second RS422 interface of the onboard computer are abnormal based on the received package feedback signal sent by the onboard computer; The onboard computer is further configured to process the CAN bus analog signal to obtain a packaged feedback signal, and send the packaged feedback signal to the core controller via a serial data interface; The core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the onboard computer are abnormal according to the following steps: performing subpackaging and parsing processing on the received packaged feedback signal sent by the onboard computer to generate a parsed feedback signal; Determining whether the analysis feedback signal and the CAN bus analog signal are consistent based on the tag information of the analysis feedback signal and the tag information of the CAN bus analog signal; If so, it is determined that both the second CAN bus interface and the second RS422 interface are normal.

2. The onboard computer detection system according to claim 1, characterized in that: The first data interface includes at least one of the following interfaces: First RS422 interface, first CAN bus interface, first AD interface, DA interface, USB interface.

3. The onboard computer detection system according to claim 1, characterized in that: The second data interface includes a second AD interface, the environmental status signal includes a temperature simulation signal; the application function includes a temperature control function; wherein, The core controller is configured to send the temperature simulation signal to the onboard computer via the second AD interface, and determine whether the temperature control function of the onboard computer is abnormal based on the received temperature feedback signal sent by the onboard computer; The onboard computer is used to process the temperature simulation signal to obtain the temperature feedback signal.

4. The onboard computer detection system according to claim 3, characterized in that: The core controller is configured to send the temperature simulation signal to the onboard computer using the second AD interface, including: The core controller is used to send the temperature simulation signal to the second AD interface of the onboard computer through the DA interface, and send the temperature simulation signal to the onboard computer through the second AD interface.

5. The onboard computer detection system according to claim 3, characterized in that: The environmental status signal also includes a voltage simulation signal, and the application function includes a voltage detection function; wherein, The core controller is configured to send the voltage analog signal to the onboard computer using the second AD interface, and determine whether the voltage detection function of the onboard computer is abnormal based on the received voltage feedback signal sent by the onboard computer; The onboard computer is used to process the voltage analog signal to obtain the voltage feedback signal.

6. The onboard computer detection system according to claim 5, characterized in that: The voltage feedback signal is a voltage signal including a flag bit fed back by the onboard computer via the second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps: Whether the voltage detection function of the onboard computer is abnormal is determined based on the digital information and position information of the mark bit.

7. The onboard computer detection system according to claim 2, characterized in that: The single-board test board also includes a resistor voltage divider circuit, which is connected to the first AD interface and is used to simulate voltage simulation signals of different voltage values corresponding to the onboard computer in the working mode.

8. The onboard computer detection system according to claim 2, characterized in that: The USB interface is connected to an external terminal device; wherein, The USB interface is used to send data feedback signals to an external terminal device; The external terminal device is used to draw a detection waveform diagram based on the data feedback signal received from the USB interface.

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