Semiconductor device

Abstract

A semiconductor device capable of improving heat dissipation characteristics is provided. When a first surface of a first member is viewed in plan, at least one switching circuit including a switch is arranged inside the first surface. A second member is joined in surface contact with the first surface of the first member. The second member includes a plurality of transistors of a compound semiconductor system constituting a high-frequency amplification circuit. A first conductor protrusion protrudes from the second member to an opposite side of the first member side. The first member includes a circuit element arranged between the high-frequency amplification circuit and the at least one switching circuit when viewed in plan, and the circuit element does not constitute the switching circuit.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] RF front-end modules, which integrate high-frequency signal transmission and reception functions, are assembled in electronic devices used for mobile communications, satellite communications, and other applications. An RF front-end module includes: a monolithic microwave integrated circuit (MMIC) with high-frequency amplification capabilities, a control IC for controlling the high-frequency amplification circuit, a switching IC, a duplexer, etc.

[0003] Patent Document 1 discloses a miniaturized high-frequency module by stacking a control IC on an MMIC. The high-frequency module disclosed in Patent Document 1 includes an MMIC mounted on a module substrate and a control IC stacked on the MMIC. The electrodes of the MMIC, the electrodes of the control IC, and the electrodes on the module substrate are electrically connected by wire bonding.

[0004] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0303971.

[0005] In high-frequency amplifier circuits, heterojunction bipolar transistors (HBTs) are used, for example. During operation, HBTs generate collector losses and thus heat. This heat causes a temperature rise in the HBT, which in turn increases the collector current. If this positive feedback condition is met, it can lead to thermal runaway of the HBT. To avoid thermal runaway of the HBT, the upper limit of its output power is limited.

[0006] To achieve high output in high-frequency amplifier circuits, it is preferable to improve the heat dissipation characteristics from semiconductor devices, including HBTs. However, the high-frequency module disclosed in Patent Document 1 does not meet the recent demands for high output in high-frequency amplifier circuits. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor device that can improve heat dissipation characteristics.

[0008] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0009] The first component has a first surface, and when viewed from above, at least one switch circuit including a switch is disposed inside the first surface.

[0010] The second component, which is in surface contact with the first surface of the first component, includes a plurality of transistors constituting a compound semiconductor system for a high-frequency amplifier circuit; and

[0011] The first conductor protrusion protrudes from the second component to the side opposite to the first component.

[0012] The first component includes circuit elements, which, when viewed from above, are disposed between the high-frequency amplifier circuit and the at least one switching circuit, and do not constitute the at least one switching circuit.

[0013] Two heat transfer paths are formed: one from multiple transistors through the interface between the first and second components to the first component, and the other from the second component through the first conductor protrusion to the module substrate on which the semiconductor device is mounted. Therefore, the heat dissipation characteristics from the transistors can be improved. Furthermore, a circuit element that does not constitute a switching circuit is arranged between the high-frequency amplifier circuit and at least one switching circuit, thereby improving the insulation between the high-frequency amplifier circuit and the switching circuit. Attached Figure Description

[0014] Figure 1 This is a block diagram of a high-frequency module including the semiconductor device of the first embodiment.

[0015] Figure 2 This is a top view showing the positional relationship of the circuit components of the high-frequency module of the semiconductor device including the first embodiment.

[0016] Figure 3 This is a schematic cross-sectional view of the semiconductor device of the first embodiment.

[0017] Figure 4A This is an equivalent circuit diagram of each of the plurality of units constituting the power stage amplifier circuit of the semiconductor device of the first embodiment. Figure 4B It is a schematic cross-sectional view of a unit that constitutes a power stage amplifier circuit formed in the second component.

[0018] Figure 5A This is a schematic diagram showing the top view of the arrangement of the constituent elements of the semiconductor device according to the first embodiment. Figure 5B This is a top-view diagram showing the arrangement of multiple transistors that make up a power stage amplifier circuit.

[0019] Figure 6A and Figure 6B It is a schematic diagram used to illustrate the area between two circuits.

[0020] Figures 7A to 7F The accompanying drawing is a cross-sectional view of a semiconductor device during the manufacturing process.

[0021] Figures 8A to 8C The attached figure is a cross-sectional view of a semiconductor device during the manufacturing process. Figure 8D This is a cross-sectional view of the completed semiconductor device.

[0022] Figure 9 This is a schematic diagram showing the top view of the configuration of the constituent elements of the semiconductor device of the second embodiment.

[0023] Figure 10 This is a schematic cross-sectional view of the semiconductor device of the second embodiment.

[0024] Figure 11 This is a schematic diagram showing the top view of the configuration of each component of the semiconductor device according to the third embodiment.

[0025] Figure 12 This is a top view schematic diagram showing the configuration of the constituent elements of a modified semiconductor device according to the third embodiment.

[0026] Explanation of reference numerals in the attached figures

[0027] 20…High-frequency module; 21…Module substrate; 30…Semiconductor device; 31…First component; 31A…First surface; 32…Second component; 32B…Third component; 41, 41B…Output switching circuit; 42, 42B…Transmission control circuit; 43, 43B…Input switching circuit; 44…Charge pump circuit; 45…Other circuits; 47…Switching circuit; 50, 50B…High-frequency amplifier circuit; 51, 51B…Power stage amplifier circuit; 52, 52B…Driver stage amplifier circuit Large circuit; 53, 53B… bias circuit; 54, 54B… input matching circuit; 55… area where multiple transistors are distributed; 56, 56B… interstage matching circuit; 61, 61B… wiring; 62, 62B, 63… pads; 64, 64B… wiring; 67… interlayer insulating film; 68… protective film; 70… duplexer; 71… low noise amplifier; 72… antenna switch; 73… band selection switch; 74… output terminal selection switch; 75… receiver control circuit; 7 6… Output matching circuit; 82, 82B, 82C, 82E… Conductor protrusions; 82P… Cu pillars; 82S… Solder layer; 83… Conductor protrusion; 101… Substrate semiconductor layer; 101A… Conductive region; 101B… Component separation region; 102B… Base layer; 102C… Collector layer; 102E… Emitter layer; 103B… Base electrode; 103C… Collector; 103E… Emitter electrode; 104B… Base wiring; 104BB… Base bias Wiring; 104C…Collector wiring; 104E…Emitter wiring; 105E…Emitter wiring; 105RF…High-frequency signal input wiring; 111, 112…Interlayer insulating film; 200…Main substrate; 201…Release layer; 204…Connector support; 210…Substrate; 311…Substrate; 312…Multilayer wiring structure; 313, 313B…Metal pattern; 314, 314B…Through hole; 315, 316…Wiring; 317…First component protective film. Detailed Implementation

[0028] [First Embodiment]

[0029] Reference Figures 1 to 8DThe semiconductor device of the first embodiment will be described with reference to the accompanying drawings. The semiconductor device of the first embodiment described below is a high-frequency power amplifier.

[0030] Figure 1 This is a block diagram of a high-frequency module 20 including the semiconductor device 30 of the first embodiment. The high-frequency module 20 includes the semiconductor device 30 of the first embodiment, an output matching circuit 76, multiple duplexers 70, an antenna switch 72, two receiving band selection switches 73, two low-noise amplifiers 71, a receiving output terminal selection switch 74, and a receiving control circuit 75. These circuit components are flip-chip mounted on the module substrate. The high-frequency module 20 has the function of transmitting and receiving in frequency division duplex (FDD) mode.

[0031] Semiconductor device 30 includes a first component 31 and a second component 32 coupled to the first component 31. For example, the first component 31 is made of an elemental semiconductor system, and the second component 32 is made of a compound semiconductor system. The first component 31 has an input switching circuit 43, a transmission control circuit 42, and an output switching circuit 41. The second component 32 has a two-stage high-frequency amplifier circuit 50 consisting of a power stage amplifier circuit 51 and a driver stage amplifier circuit 52, a bias circuit 53, an input matching circuit 54, and an inter-stage matching circuit 56. The driver stage amplifier circuit 52 is the primary amplifier circuit, and the power stage amplifier circuit 51 is the final stage amplifier circuit. Figure 1 In the circuit, a relatively light shaded line is marked on the circuit set in the first component 31, and a relatively dark shaded line is marked on the circuit set in the second component 32.

[0032] The bias circuit 53 supplies bias current to the power stage amplifier circuit 51 and the driver stage amplifier circuit 52 according to the control signal from the transmitting control circuit 42.

[0033] The two input contacts of the input switch circuit 43 are connected to the high-frequency signal input terminals IN1 and IN2 respectively, which are located on the module substrate. High-frequency signals are input from the two high-frequency signal input terminals IN1 and IN2. The input switch circuit 43 selects one of the two input contacts and inputs the high-frequency signal input to the selected contact to the driver stage amplifier circuit 52 via the input matching circuit 54.

[0034] The high-frequency signal amplified in the driver stage amplifier circuit 52 is input to the power stage amplifier circuit 51 via the interstage matching circuit 56. The high-frequency signal amplified in the power stage amplifier circuit 51 is input to one input contact of the output switching circuit 41 via the output matching circuit 76. The output switching circuit 41 selects one contact from multiple output contacts and outputs the high-frequency signal amplified in the high-frequency amplifier circuit 50 from the selected output contact.

[0035] Two of the multiple output contacts of the output switching circuit 41 are connected to auxiliary output terminals PAAUX1 and PAAUX2 respectively, which are provided on the module substrate. The other six contacts are connected to the transmit input ports of multiple duplexers 70 prepared for each frequency band. The output switching circuit 41 has the function of selecting one duplexer 70 from the multiple duplexers 70 prepared for each frequency band.

[0036] Antenna switch 72 has multiple contacts on the circuit side and two contacts on the antenna side. Two of the multiple contacts on the circuit side of antenna switch 72 are connected to the transmit signal input terminals TRX1 and TRX2, respectively. The other six contacts on the circuit side are connected to the input / output shared ports of multiple duplexers 70. The two contacts on the antenna side are connected to antenna terminals ANT1 and ANT2, respectively. Antennas are connected to antenna terminals ANT1 and ANT2, respectively.

[0037] Antenna switch 72 connects two antenna-side contacts to two contacts selected from a plurality of contacts on the circuit side. When communicating using a single frequency band, antenna switch 72 connects one contact on the circuit side to one contact on the antenna side. The high-frequency signal, amplified in high-frequency amplifier circuit 50 and passed through duplexer 70 for the corresponding frequency band, is transmitted from the antenna connected to the selected antenna-side contact.

[0038] Each of the two receiving band selection switches 73 has four input contacts and one output contact. Three of the four input contacts of each of the two band selection switches 73 are connected to the receiving output port of the duplexer 70. The remaining contact of each of the two band selection switches 73 is connected to the auxiliary input terminals LNAAUX1 and LNAAUX2, respectively.

[0039] The output contacts of the two receiver band selection switches 73 are respectively connected to the two low-noise amplifiers 71. The two receiver band selection switches 73 respectively enable the received signal that has passed through the duplexer 70 to be input to the low-noise amplifier 71.

[0040] The two circuit-side contacts of the output terminal selection switch 74 are connected to the output ports of the two low-noise amplifiers 71, respectively. The three terminal-side contacts of the output terminal selection switch 74 are connected to the receive signal output terminals LNAOUT1, LNAOUT2, and LNAOUT3, respectively. The received signal amplified in the low-noise amplifier 71 is output from the receive signal output terminal selected by the output terminal selection switch 74.

[0041] Power supply voltages are applied to the power stage amplifier circuit 51 and the driver stage amplifier circuit 52 from the power supply terminals VCC1 and VCC2 located on the module substrate, respectively.

[0042] The transmit control circuit 42 is connected to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1. The transmit control circuit 42 controls the bias circuit 53, the input switch circuit 43, and the output switch circuit 41 based on the control signal provided to the control signal terminal SDATA1.

[0043] The receiver control circuit 75 is connected to the power supply terminal VIO2, the control signal terminal SDATA2, and the clock terminal SCLK2. The receiver control circuit 75 controls the low-noise amplifier 71, the receiver band selection switch 73, and the output terminal selection switch 74 based on the control signal provided to the control signal terminal SDATA2.

[0044] The module substrate also includes a power supply terminal VBAT and a drain voltage terminal VDD2. Power is supplied from the power supply terminal VBAT to the bias circuit 53 and the transmission control circuit 42. The power supply voltage is applied to the low-noise amplifier 71 from the drain voltage terminal VDD2.

[0045] Figure 2 This diagram shows the top-view positional relationship of the circuit components of the high-frequency module 20, which includes the semiconductor device of the first embodiment. The semiconductor device 30, multiple duplexers 70, a low-noise amplifier 71, an antenna switch 72, and other surface-mount passive components are mounted on the module substrate 21. The first component 31 of the semiconductor device 30 is larger than the second component 32 in top view and includes the second component 32.

[0046] The output matching circuit 76 is composed of passive components such as inductors disposed within the module substrate and capacitors surface-mounted on the module substrate. The inductors constituting the output matching circuit 76 are positioned to overlap with the semiconductor device 30 when viewed from above. Alternatively, the output matching circuit 76 may be composed of integrated passive components.

[0047] Figure 3 This is a schematic cross-sectional view of the semiconductor device 30 according to the first embodiment. The first component 31 includes a substrate 311, a multilayer wiring structure 312 disposed thereon, and a first component protective film 317 covering the surface of the multilayer wiring structure 312. The substrate 311 includes a semiconductor portion of an elemental semiconductor system. For example, a silicon substrate or a silicon-on-insulator (SOI) substrate is used as the substrate 311. Output switch circuit 41 ( Figure 1 ), Transmitting control circuit 42 ( Figure 1 ) and input switch circuit 43 ( Figure 1 It is composed of semiconductor elements formed on the surface layer of substrate 311 and wiring within the multilayer wiring structure 312. Figure 3In the diagram, the area where the input switch circuit 43 is formed is enclosed by a dashed line and shown. The outermost surface of the first component 31 is referred to as the first surface 31A. An opening is provided in a portion of the first component protective film 317, and a metal film 318 is filled in the opening. The upper surfaces of the first component protective film 317 and the metal film 318 correspond to the first surface 31A.

[0048] The second component 32 is joined to the first surface 31A of the first component 31 in contact. Furthermore, in a top view, at least a portion of the second component 32 overlaps with at least a portion of the metal film 318, and the second component 32 is in contact with the surface of the metal film 318. A [missing information - likely a component name or structure] is formed on the second component 32. Figure 1 The diagram shows a power stage amplifier circuit 51, a driver stage amplifier circuit 52, a bias circuit 53, an input matching circuit 54, and an interstage matching circuit 56. Figure 3 In the image, the area where the input matching circuit 54 is configured is surrounded by a dashed line and shown.

[0049] An interlayer insulating film 67 is disposed on the first surface 31A to cover the second component 32. Multiple openings are provided at predetermined locations on the interlayer insulating film 67. Pads 62 and 63, and wiring 61 are disposed on the interlayer insulating film 67. The wiring layer with pads 62 and 63 and wiring 61 is sometimes referred to as a rewiring layer. The wiring 61 within the rewiring layer is sometimes referred to as rewiring.

[0050] Wiring 61 connects the circuit formed in the second component 32 and the circuit formed in the first component 31 through an opening in the interlayer insulating film 67. For example, wiring 61 connects to the input switch circuit 43 via wiring 315 within the multilayer wiring structure 312 through an opening in the interlayer insulating film 67, and connects to the input matching circuit 54 through another opening in the interlayer insulating film 67. In addition to wiring 61, several other wirings are arranged within the rewiring layer. The wirings within the rewiring layer are used, for example, for... Figure 1 The connection between the transmission control circuit 42 and the bias circuit 53 is shown.

[0051] Pad 62 is included in the second component 32 when viewed from above and is connected to the circuit formed in the second component 32. Another pad 63 is disposed on the outside of the second component 32 when viewed from above and is connected to the input switch circuit 43 formed in the first component 31 via wiring 316 in the multilayer wiring structure 312.

[0052] A protective film 68 is disposed on the interlayer insulating film 67 to cover the redistribution layer. The protective film 68 has openings that expose a portion of the upper surface of each of the pads 62 and 63. Conductor protrusions 82 and 83 are disposed on the pads 62 and 63, respectively. The conductor protrusion 82 includes a Cu pillar 82P connected to the pad 62 and a solder layer 82S disposed on the upper surface of the Cu pillar 82P. This type of conductor protrusion 82 is referred to as a Cu pillar bump.

[0053] Furthermore, to improve contact tightness, a bump under-metal layer can be disposed on the bottom surface of the Cu pillar 82P. The other conductor protrusion 83 also has the same stacked structure as conductor protrusion 82. Alternatively, Au bumps, solder ball bumps, or conductor pillars erected on pads can be used instead of Cu pillar bumps in conductor protrusions 82, 83, etc. Like Au bumps, bumps without a solder layer are also called pillars. Conductor pillars erected on pads are also called terminals.

[0054] Conductor protrusion 82, for example, is used for Figure 1 The diagram shows the connection between power supply terminal VCC1 and power stage amplifier circuit 51, the connection between power supply terminal VCC2 and drive stage amplifier circuit 52, and the connection between power stage amplifier circuit 51 and output matching circuit 76. Furthermore, the conductor protrusion 82 is used to connect the grounding conductor within the second component 32 to the grounding conductor of the module substrate.

[0055] Conductor protrusion 83, for example, is used for Figure 1 The connections shown include the input switch circuit 43 and the high-frequency signal input terminals IN1 and IN2, the transmission control circuit 42 and the power supply terminal VIO1, the control signal terminal SDATA1 and the clock terminal SCLK1, the output switch circuit 41 and the output matching circuit 76, and the multiple duplexers 70.

[0056] At least one layer of metal pattern 313 and multiple vias 314 are disposed within the multilayer wiring structure 312. The multiple vias 314 connect the metal patterns 313 to each other, or to the metal film 318 and the metal pattern 313, in the thickness direction. The multiple metal patterns 313 overlap with a portion of the second component 32 when viewed from above. The metal pattern 313 disposed on the bottommost wiring layer is connected to the substrate 311 via the multiple vias 314. The metal pattern 313 is not electrically connected to any circuit of the first component 31. The metal film 318, the metal pattern 313, and the vias 314 function as heat transfer paths from the second component 32 to the substrate 311. Additionally, the conductor protrusion 82, in addition to functioning as a current path, also functions as a heat transfer path from the second component 32 to the module substrate.

[0057] Figure 4AIt is the power stage amplifier circuit 51 constituting the semiconductor device 30 of the first embodiment. Figure 1 The equivalent circuit diagrams of each of the multiple units of the power stage amplifier circuit 51 are shown. The power stage amplifier circuit 51 is composed of multiple units connected in parallel. Furthermore, the driver stage amplifier circuit 52 ( Figure 1 It also has the same circuit structure as the power stage amplifier circuit 51. However, the number of units constituting the driver stage amplifier circuit 52 is less than the number of units constituting the power stage amplifier circuit 51.

[0058] Each unit includes a transistor Q, an input capacitor Cin, and a ballast resistor Rb. The base of transistor Q is connected to the high-frequency signal input wiring 105RF via the input capacitor Cin. Furthermore, the base of transistor Q is connected to the base bias wiring 104BB via the ballast resistor Rb. The emitter of transistor Q is grounded. The collector of transistor Q is connected to the collector wiring 104C. A power supply voltage is applied to the collector of transistor Q via the collector wiring 104C, and an amplified high-frequency signal is output from the collector.

[0059] Figure 4B It constitutes the power stage amplifier circuit 51 formed in the second component 32. Figure 1 This is a schematic cross-sectional view of one unit of the first component 31. The second component 32 includes a substrate semiconductor layer 101. The substrate semiconductor layer 101 is in surface contact with the first component 31, thereby bonding the second component 32 to the first component 31. The substrate semiconductor layer 101 is divided into a conductive region 101A and a device separation region 101B. GaAs is used, for example, in the substrate semiconductor layer 101. The conductive region 101A is formed of n-type GaAs, and the device separation region 101B is formed by implanting insulating impurity ions into the n-type GaAs layer.

[0060] A transistor Q is disposed on a conductive region 101A. The transistor Q includes a collector layer 102C, a base layer 102B, and an emitter layer 102E, sequentially stacked from the conductive region 101A. The emitter layer 102E is disposed on a portion of the base layer 102B. As an example, the collector layer 102C is formed of n-type GaAs, the base layer 102B is formed of p-type GaAs, and the emitter layer 102E is formed of n-type InGaP. That is, the transistor Q is a heterojunction bipolar transistor. Other compound semiconductor devices can also be used as the transistor Q.

[0061] A base electrode 103B is disposed on the base layer 102B and is electrically connected to the base layer 102B. An emitter electrode 103E is disposed on the emitter layer 102E and is electrically connected to the emitter layer 102E. A collector electrode 103C is disposed on the conductive region 101A. The collector electrode 103C is electrically connected to the collector layer 102C via the conductive region 101A.

[0062] An interlayer insulating film 111 is disposed on the substrate semiconductor layer 101 to cover the transistor Q, collector 103C, base electrode 103B, and emitter electrode 103E. The interlayer insulating film 111 is formed, for example, from an inorganic insulating material such as SiN. Openings are provided at various predetermined locations on the interlayer insulating film 111.

[0063] An emitter wiring 104E, a base wiring 104B, a collector wiring 104C, and a base bias wiring 104BB are disposed on the interlayer insulating film 111. A ballast resistor element Rb is also disposed on the interlayer insulating film 111. The emitter wiring 104E is connected to the emitter electrode 103E through an opening in the interlayer insulating film 111. The base wiring 104B is connected to the base electrode 103B through other openings in the interlayer insulating film 111. The collector wiring 104C is connected to the collector electrode 103C through other openings in the interlayer insulating film 111.

[0064] The base wiring 104B extends into the region where no transistor Q is configured, and its front end overlaps with one end of the ballast resistor element Rb. At the overlap, the base wiring 104B and the ballast resistor element Rb are electrically connected. The other end of the ballast resistor element Rb overlaps with the base bias wiring 104BB. At the overlap, the ballast resistor element Rb and the base bias wiring 104BB are electrically connected.

[0065] A second interlayer insulating film 112 is disposed on the interlayer insulating film 111 to cover the emitter wiring 104E, base wiring 104B, base bias wiring 104BB, and ballast resistor element Rb of the first layer. The second interlayer insulating film 112 is also formed of an inorganic insulating material such as SiN.

[0066] A second layer of emitter wiring 105E and a high-frequency signal input wiring 105RF are disposed on the interlayer insulating film 112. The second layer of emitter wiring 105E is connected to the first layer of emitter wiring 104E through an opening in the interlayer insulating film 112. A portion of the high-frequency signal input wiring 105RF overlaps with the first layer of base wiring 104B when viewed from above. An input capacitor Cin is formed in the overlapping area.

[0067] A third interlayer insulating film 67 is configured to cover the emitter wiring 105E and the high-frequency signal input wiring 105RF of the second layer. The third interlayer insulating film 67 is formed, for example, of an organic insulating material such as polyimide. Furthermore, the third interlayer insulating film 67... Figure 3 It extends to the first component 31 as shown.

[0068] Pads 62 are disposed on the interlayer insulating film 67 of the third layer. Pads 62 are connected to the emitter wiring 105E of the second layer through openings provided in the interlayer insulating film 67.

[0069] Figure 5A This is a schematic diagram showing the top view of the configuration of each component of the semiconductor device 30 according to the first embodiment. In the top view, the second component 32 is included in the first component 31.

[0070] Looking at the first surface 31A of the first component 31 from above ( Figure 3 In this configuration, the first surface 31A contains an input switch circuit 43, a transmission control circuit 42, an output switch circuit 41, a charge pump circuit 44, and other circuits 45. These other circuits 45 include, for example, an electrostatic protection circuit, a fuse circuit, and a temperature compensation circuit. Figure 5A In the diagram, the area of ​​the first component 31 where these circuits are arranged is marked with a relatively dark shaded line sloping downwards to the right. Furthermore, "area where circuits are arranged" means an area that, when viewed from above, includes multiple circuit elements such as active and passive components that constitute the circuit, as well as the wiring that connects these circuit elements to each other.

[0071] The second component 32 is equipped with a two-stage high-frequency amplifier circuit 50 (driver stage amplifier circuit 52 and power stage amplifier circuit 51), a bias circuit 53, an input matching circuit 54, and an inter-stage matching circuit 56. Figure 5A In the middle, the area of ​​the second component 32 where these circuits are configured is marked with a relatively light shaded line that slopes upward to the right.

[0072] The input switching circuit 43 and the input matching circuit 54 are connected via wiring 61 in the rewiring layer. Figure 3 They are interconnected. The transmit control circuit 42 and the bias circuit 53 are interconnected through other wiring 64 in the rewiring layer.

[0073] The charge pump circuit 44 repeatedly switches on and off via a periodic clock signal, thereby reversing the polarity of the voltage applied to the capacitor and boosting the input voltage. For example... Figure 1As shown, the output switch circuit 41 is a switch that connects and disconnects high-frequency signals between one input contact and multiple output contacts. Thus, the charge pump circuit 44, which includes the switch for connecting and disconnecting, and the output switch circuit 41 are collectively referred to as the switch circuit 47. The charge pump circuit 44 and the output switch circuit 41 are arranged adjacent to each other.

[0074] Viewed from above, the charge pump circuit 44 and the output switch circuit 41 are spaced apart from the second component 32. The input switch circuit 43 and other circuits 45 overlap with the second component 32 when viewed from above.

[0075] Viewed from above, a transmission control circuit 42 is disposed in the region between the high-frequency amplifier circuit 50 formed in the second component 32 and the switching circuit 47 disposed in the first component 31. That is, at least one circuit element that does not constitute the switching circuit 47 is disposed in the region between the high-frequency amplifier circuit 50 and the switching circuit 47 in the first component 31. The circuit element that does not constitute the switching circuit 47 includes, for example, active components, passive components, fuses, etc., formed in the first component 31.

[0076] Figure 5B This represents the multiple transistors Q that constitute the power stage amplifier circuit 51. Figure 4A , Figure 4B A top-view diagram of the configuration of the multiple transistors Q. Each of the multiple transistors Q includes a collector layer 102C and a base layer 102B. In top view, the outer periphery of the collector layer 102C and the outer periphery of the base layer 102B are approximately aligned. The emitter layer 102E (… Figure 4B When viewed from above, it is contained within the base layer 102B. Each transistor Q, when viewed from above, is in one direction (in... Figure 5B The transistors Q have an elongated shape in the vertical direction. The long sides of each transistor Q are parallel, and the transistors Q are aligned in a direction orthogonal to the long side direction (in the vertical direction). Figure 5B Arranged and configured in the left-right direction.

[0077] Multiple transistors Q are distributed within region 55. Region 55, in which multiple transistors Q are distributed, is defined, for example, as the smallest convex polygon containing multiple transistors Q when viewed from above.

[0078] Alternatively, multiple columns of transistors Q can be arranged in a direction orthogonal to the direction in which the transistors Q are arranged. In this case, the smallest convex polygon containing all the transistors Q included in the multiple transistor columns can be defined as the region 55 where the multiple transistors Q are distributed.

[0079] like Figure 5AAs shown, a region 55 containing multiple transistors Q is arranged within the power stage amplifier circuit 51. Conductor protrusions 82E and 82C are connected to the emitters and collectors of the multiple transistors Q, respectively. Viewed from above, the emitter conductor protrusion 82E encompasses the region 55 containing the multiple transistors Q. The circuit block constituting the power stage amplifier circuit also includes... Figure 4A and Figure 4B The input capacitor Cin and the ballast resistor element Rb are shown.

[0080] Next, refer to Figure 6A and Figure 6B The section explains the "region between two circuits".

[0081] Figure 6A and Figure 6B This is a schematic diagram used to illustrate the region between two circuits. When the shortest line segment Lmin, which connects the multiple circuit elements contained in the first circuit A1 and the multiple circuit elements contained in the second circuit A2, is moved in a direction orthogonal to line segment Lmin, the region traversed by line segment Lmin is marked as Lpass. Figure 6A This represents an example where multiple line segments Lmin exist. Figure 6B This represents an example where only one line segment Lmin exists.

[0082] The region AB within region Lpass, in which at least one of the first circuit A1 and the second circuit A2 is arranged in a direction orthogonal to line segment Lmin, is defined as the region between the first circuit A1 and the second circuit A2. Figure 6A , Figure 6B (The area marked with a shaded line). When the first circuit A1 and the second circuit A2 are respectively configured in multiple separate areas, the "area between the two circuits" is defined for each separate area.

[0083] Next, refer to Figures 7A to 8D The accompanying drawings illustrate the method for manufacturing the semiconductor device 30 of the first embodiment. Figures 7A to 8C The attached figure is a cross-sectional view of the semiconductor device 30 during the manufacturing process. Figure 8D This is a cross-sectional view of the completed semiconductor device 30.

[0084] like Figure 7A As shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 is formed on the device forming layer 202. Figure 4B The second component 32 shown includes transistor Q, a first wiring layer, a second wiring layer, etc. These circuit elements and wiring layers are formed using conventional semiconductor processes. Figure 7AThe element structure formed on the element forming layer 202 is omitted from the description. At this stage, the element forming layer 202 is not separated into individual second components 32.

[0085] Next, as Figure 7B As shown, a resist pattern (not shown) is used as an etching mask to form the element forming layer 202. Figure 5A ) and release layer 201. In this stage, element forming layer 202 ( Figure 5A It is separated into each second component 32.

[0086] Next, as Figure 7C As shown, a connecting support 204 is attached to the separated second component 32. Thus, multiple second components 32 are interconnected via the connecting support 204. Furthermore, it is also possible to... Figure 7B The resist pattern remaining in the pattern forming process, which is used as an etching mask, is located between the second component 32 and the connecting support 204.

[0087] Next, as Figure 7D As shown, the release layer 201 is selectively etched onto the mother substrate 200 and the second component 32. As a result, the second component 32 and the connecting support 204 are peeled off from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with an etching resistance different from either the mother substrate 200 or the second component 32 is used as the release layer 201.

[0088] like Figure 7E As shown, a structure is prepared to be formed on the first component 31 ( Figure 3 The input switch circuit 43 and the multilayer wiring structure 312 () Figure 3 The substrate 210, etc. At this stage, the substrate 210 is not separated into individual first components 31.

[0089] like Figure 7F As shown, the second component 32 is bonded to the substrate 210. The bonding between the second component 32 and the substrate 210 is formed by van der Waals bonds or hydrogen bonds. Alternatively, the second component 32 can be bonded to the substrate 210 via electrostatic bonding, covalent bonding, eutectic alloy bonding, etc. For example, if a portion of the surface of the substrate 210 is formed of Au, the second component 32 can be brought into close contact with the Au region and pressure applied to bond the two together.

[0090] Next, as Figure 8A As shown, the connecting support 204 is peeled off from the second component 32. After peeling off the connecting support 204, as... Figure 8B As shown, an interlayer insulating film 67 and a redistribution layer are formed on the substrate 210 and the second component 32. The redistribution layer includes wiring 61, pads 62, and 63. Figure 3 )wait.

[0091] Next, as Figure 8C As shown, a protective film 68 is formed on the redistribution layer, and an opening is formed at a predetermined position on the protective film 68. Then, conductor protrusions 82 are formed within the openings and on the protective film 68. Simultaneously with the formation of the conductor protrusions 82, other conductor protrusions 83 are also formed. Figure 3 )wait.

[0092] Finally, as Figure 8D As shown, substrate 210 is cut. This yields semiconductor device 30.

[0093] Next, the superior effects of the first embodiment will be explained.

[0094] In the first embodiment, as Figure 3 As shown, a heat transfer path is formed from the second component 32 toward the first component 31. The second component 32 is in surface contact with the first component 31, thus the second component 32 and the first component 31 are thermally coupled through low thermal resistance. Furthermore, a metal pattern 313 and a via 314 are disposed within the multilayer wiring structure 312 directly below the second component 32, therefore, compared to a structure where the entire area of ​​the multilayer wiring structure 312 directly below the second component 32 is formed of insulating material, the thermal resistance of the heat transfer path from the second component 32 to the substrate 311 is lower. In addition, the metal pattern 313 is not electrically connected to any circuit block of the first component 31, so the metal pattern 313, which functions as a heat transfer path, does not affect the operation of the circuit blocks of the first component 31. Alternatively, the metal pattern 313 can be electrically connected to a ground conductor within the first component 31.

[0095] Heat conducted from the second component 32 to the first component 31 diffuses within the first component 31. The heat diffused within the first component 31 radiates outwards from its surface. When the semiconductor device 30 is covered with molding resin in a mounted state on a module substrate, heat is conducted from the first component 31 to the molding resin.

[0096] Furthermore, the conductor protrusion 82 functions as a heat transfer path from the second component 32 to the module substrate. Thus, heat dissipation occurs through two paths: the heat transfer path from the second component 32 towards the module substrate and the heat transfer path from the second component 32 towards the first component 31. Therefore, the heat dissipation characteristics from the second component 32 can be improved. To achieve a sufficiently improved heat dissipation characteristic, it is preferable to use a semiconductor with a higher thermal conductivity than the compound semiconductor formed in the semiconductor element of the substrate 311 of the first component 31, such as elemental semiconductors like Si or Ge. Additionally, as the semiconductor element formed in the second component 32, for amplifying high-frequency signals, it is preferable to use a compound semiconductor-based semiconductor element with a higher electron mobility than the semiconductor portion of the substrate 311 of the first component 31.

[0097] In the second component 32, the region 55 where the multiple transistor Qs of the power stage amplifier circuit 51 are distributed is... Figure 5A It is particularly prone to generating heat. In order to reduce the heat generated from the region 55 where multiple transistors Q are distributed to the substrate 311 of the first component 31 ( Figure 3 The thermal resistance of the heat transfer path is preferably contained in the metal pattern 313 in a region 55 where multiple transistors Q are distributed when viewed from above. Figure 3 The metal pattern 313 is configured in a manner that allows for the arrangement of multiple transistor Q regions 55, which, when viewed from above, are contained within the metal film 318. Figure 3 The metal film 318 is configured in a manner that allows for the preparation of metal films.

[0098] Additionally, in the first embodiment, the second component 32 ( Figure 5A The second component 32 overlaps with the input switch circuit 43 of the first component 31 and other circuits 45. Therefore, compared with the case where the second component 32 does not overlap with any circuit of the first component 31, the top view size of the semiconductor device 30 can be reduced.

[0099] Furthermore, in the first embodiment, the switching circuit 47 and the high-frequency amplifier circuit 50 are spaced apart in the in-plane direction, thus improving the insulation between the high-frequency amplifier circuit 50 and the switching circuit 47. For example, it is possible to suppress noise generated in the output switching circuit 41 and the charge pump circuit 44 from mixing into the high-frequency signal amplified or amplified in the high-frequency amplifier circuit 50. In addition, it is possible to suppress the direct coupling of high-order harmonics of the high-frequency signal amplified by the power stage amplifier circuit 51 to the output switching circuit 41 without being affected by the output matching circuit 76. Figure 1 ) Filtering situation.

[0100] Furthermore, while the input switch circuit 43 and the driver stage amplifier circuit 52 are configured close to each other, problems are less likely to arise from placing the switch circuit 47 and the high-frequency amplifier circuit 50 close together for the following reasons. Impedance matching on the input side of the driver stage amplifier circuit 52 is achieved through the input switch circuit 43 and the input matching circuit 54. Therefore, high insulation is not required between the input switch circuit 43 and the driver stage amplifier circuit 52. Additionally, the signal level through the input switch circuit 43 is sufficiently lower than the signal level through the output switch circuit 41. Therefore, the negative voltage generated by the charge pump circuit 44 is not used in the input switch circuit 43. In this case, the need to improve the insulation of the input switch circuit 43 from other circuits is lower compared to the output switch circuit 41.

[0101] The high-frequency amplifier circuit 50 and the switching circuit 47 are arranged apart from each other, and the transmission control circuit 42 is arranged between them. Therefore, even if the high-frequency amplifier circuit 50 and the switching circuit 47 are arranged apart from each other, the semiconductor device 30 will not be enlarged.

[0102] Furthermore, in the first embodiment, the charge pump circuit 44 and the output switch circuit 41 are arranged adjacent to each other. The output switch circuit 41 is activated by the negative voltage generated in the charge pump circuit 44. By arranging the charge pump circuit 44, which generates the negative voltage that activates the output switch circuit 41, near the output switch circuit, malfunctions of the switch can be suppressed. In addition, by shortening the wiring connecting the two, the interference of noise from surrounding circuits into the output switch circuit 41 via the wiring can be suppressed.

[0103] Next, a variation of the first embodiment will be described.

[0104] In the first embodiment ( Figure 3 In this structure, the metal film 318 of the first component 31, multiple metal patterns 313 within the multilayer wiring structure 312, and multiple vias 314 are present. Figure 3 The heat transfer path formed by the metal film 318, the metal pattern 313, and the multiple vias 314 may not necessarily need to contact the second component 32 and the substrate 311. For example, the heat transfer path formed by the multiple metal patterns 313 and the multiple vias 314 can also be thermally coupled to the second component 32 and the substrate 311 via the insulating film. In this case, the insulating film functions as part of the heat transfer path from the second component 32 to the substrate 311. Alternatively, the metal film 318 may not be provided, and the entire area of ​​the first surface 31A may be set as the first component protective film 317. In this case, the portion of the first component protective film 317 that contacts the second component 32 mainly functions as a heat transfer path.

[0105] Furthermore, without the metal pattern 313 and via 314, the thermal resistance of the heat transfer path from the second component 32 to the substrate 311 becomes higher. However, if sufficient output of the power stage amplifier circuit 51 can be ensured, the metal pattern 313 and via 314 may not be necessary. In this case, the insulating film included in the multilayer wiring structure 312 functions as a heat transfer path.

[0106] In the first embodiment ( Figure 5A In this circuit, a transmission control circuit 42 is configured between the high-frequency amplifier circuit 50 and the switching circuit 47. However, circuit elements that do not constitute the switching circuit 47 can also be configured. Preferably, the circuit configured between the high-frequency amplifier circuit 50 and the switching circuit 47 is one that is less prone to generating noise compared to the charge pump circuit 44 and the output switching circuit 41. Alternatively, a circuit that does not operate during the operation of the high-frequency amplifier circuit 50 can be configured between the high-frequency amplifier circuit 50 and the switching circuit 47. Examples of such circuits include electrostatic discharge protection circuits, temperature compensation circuits, and fuse circuits.

[0107] In the first embodiment, the semiconductor device 30 is mounted on a high-frequency module 20 in a frequency division duplex (FDD) configuration. Figure 1 It can be used in high-frequency modules that operate in time-division duplex (TDD) mode, but it can also be used in other high-frequency modules that operate in time-division duplex (TDD) mode.

[0108] When the semiconductor device 30 is mounted in a TDD-type high-frequency module, a transmit / receive switching switch is used as the output switching circuit 41. Figure 1 The transmit / receive switch has two contacts and a common terminal. One of the two contacts is connected via an output matching circuit 76. Figure 1 One contact is connected to the power stage amplifier circuit 51, and the other contact is connected to the low-noise amplifier 71 used to amplify the received signal. Figure 1 ) connect, or via the receiving band selection switch 73 ( Figure 1 ) is connected to the low-noise amplifier 71. A common terminal is connected to the antenna terminal via a filter. When using a transmit / receive switch as the output switch circuit 41, similar to the first embodiment, in the output switch circuit 41 ( Figure 5A A transmission control circuit 42 is configured between the high-frequency amplifier circuit 50 and the high-frequency amplifier circuit 50.

[0109] [Second Embodiment]

[0110] Next, refer to Figure 9 and Figure 10 The semiconductor device of the second embodiment will be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figures 1 to 8D The semiconductor device of the first embodiment described in the accompanying drawings has the same structure, which is omitted from the description.

[0111] Figure 9 This is a schematic diagram showing the top view of the arrangement of the constituent elements of the semiconductor device 30 according to the second embodiment. Figure 9 Zhongyu Figure 5A Similarly, the area of ​​the first component 31 where the circuits are arranged is marked with a relatively dark shaded line sloping downward to the right, while the area of ​​the second component 32 where the circuits are arranged is marked with a relatively light shaded line sloping upward to the right.

[0112] Semiconductor device 30 in the first embodiment ( Figure 5A In the first embodiment, a second component 32 is attached to the first component 31. However, in the semiconductor device 30 of the second embodiment, a third component 32B is also attached to the first component 31 in addition to the second component 32. The structure of the second component 32 is the same as that of the second component 32 in the semiconductor device 30 of the first embodiment. The third component 32B is similar to the second component 32, including: a two-stage high-frequency amplifier circuit 50B comprising a power stage amplifier circuit 51B and a driver stage amplifier circuit 52B, a bias circuit 53B, an input matching circuit 54B, and an inter-stage matching circuit 56B.

[0113] Similar to the first component 31 of the semiconductor device 30 in the first embodiment, the first component 31 is provided with an input switch circuit 43, a transmission control circuit 42, and an output switch circuit 41 for the second component 32. It is also provided with an input switch circuit 43B, a transmission control circuit 42B, and an output switch circuit 41B for the third component 32B. A charge pump circuit 44 shared by the second component 32 and the third component 32B is also provided. Furthermore, similar to the first embodiment, other circuits 45 are provided in the first component 31.

[0114] Viewed from above, an output switch circuit 41B for a third component 32B is disposed between the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41 for the second component 32. The output switch circuit 41 for the second component 32 is disposed between the high-frequency amplifier circuit 50B of the third component 32B and the output switch circuit 41B for the third component 32B.

[0115] Other circuits 45 and an output switch circuit 41B for the third component 32B are arranged between the charge pump circuit 44 and the high-frequency amplifier circuit 50B of the second component 32.

[0116] That is, the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41 of the second component 32 are arranged apart from each other. Similarly, the high-frequency amplifier circuit 50B of the third component 32B and the output switch circuit 41B of the third component 32B are also arranged apart from each other.

[0117] The input matching circuit 54B of the third component 32B and the input switching circuit 43B used in the third component 32B are interconnected through wiring 61B in the redistribution layer. The bias circuit 53B of the third component 32B and the transmit control circuit 42B used in the third component 32B are interconnected through wiring 64B in the redistribution layer.

[0118] The high-frequency amplifier circuit 50 of the second component 32 and the high-frequency amplifier circuit 50B of the third component 32B operate in different frequency bands. One high-frequency amplifier circuit 50 and the other high-frequency amplifier circuit 50B operate selectively and do not operate simultaneously.

[0119] Figure 10 This is a schematic cross-sectional view of the semiconductor device 30 according to the second embodiment. In addition to the second component 32, the third component 32B is also in contact with and bonded to the first surface 31A of the first component 31. Like the second component 32, the third component 32B is provided with pads 62B, conductor protrusions 82B, wiring 61B, a metal film 318B, at least one layer of metal pattern 313B, and a plurality of vias 314B. The conductor protrusions 82B protrude from the third component 32B. The metal film 318B, the metal pattern 313B within the multilayer wiring structure 312, and the plurality of vias 314B overlap with the third component 32B when viewed from above. The wiring 61B within the rewiring layer interconnects the input matching circuit 54B of the third component 32B and the input switching circuit 43B for the third component 32B formed in the first component 31.

[0120] Next, the superior effects of the second embodiment will be explained.

[0121] In the second embodiment, similarly to the first embodiment, the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41 of the second component 32 are arranged spaced apart from each other, thus improving the insulation between them. Similarly, the insulation between the high-frequency amplifier circuit 50B of the third component 32B and the output switch circuit 41B of the third component 32B can be improved.

[0122] In the second embodiment, an output switch circuit 41B for the third component 32B is disposed near the high-frequency amplifier circuit 50 of the second component 32, and an output switch circuit 41 for the second component 32 is disposed near the high-frequency amplifier circuit 50B of the third component 32B. However, the high-frequency amplifier circuit 50 and the high-frequency amplifier circuit 50B do not operate simultaneously. Therefore, even if electromagnetic coupling occurs between the high-frequency amplifier circuit 50 and the output switch circuit 41B, and between the high-frequency amplifier circuit 50B and the output switch circuit 41B, which are disposed close to each other, the operation of the high-frequency amplifier circuit 50 and the high-frequency amplifier circuit 50B will not be substantially affected by these electromagnetic couplings.

[0123] Furthermore, the third component 32B is in contact with the surface of the first component 31, and a conductor protrusion 82B is also provided relative to the third component 32B, thereby improving the heat dissipation characteristics from the third component 32B.

[0124] [Third Embodiment]

[0125] Next, refer to Figure 11 The semiconductor device of the third embodiment will be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figure 9 and Figure 10 The semiconductor device of the second embodiment described herein has the same structure, which is omitted from the description.

[0126] Figure 11 This is a schematic diagram showing the top view of the arrangement of the constituent elements of the semiconductor device 30 according to the third embodiment. Figure 11 Zhongyu Figure 9 Similarly, the area of ​​the first component 31 where the circuits are arranged is marked with a relatively dark shaded line sloping downward to the right, while the area of ​​the second component 32 where the circuits are arranged is marked with a relatively light shaded line sloping upward to the right.

[0127] In the third embodiment, similarly to the second embodiment, the second component 32 and the third component 32B are in surface contact with and joined to the first component 31. The structure of the second component 32 and the third component 32B is the same as that of the semiconductor device 30 in the second embodiment. Figure 9 , Figure 10 The second component 32 and the third component 32B have the same structure.

[0128] The first component 31 is equipped with a transmission control circuit 42 and an output switch circuit 41 for the second component 32, and a transmission control circuit 42B and an output switch circuit 41B for the third component 32B. The input switch circuit 43 configured in the first component 31 is shared by the second component 32 and the third component 32B.

[0129] The wiring 61 and 64 of the rewiring layer are the same as in the second embodiment, connecting the circuit of the second component 32 and the circuit of the first component 31. Wiring 61B and 64B connect the circuit of the third component 32B and the circuit of the first component 31.

[0130] In the third embodiment, a transmission control circuit 42 for the second component 32 is disposed between the high-frequency amplification circuit 50 of the second component 32 and the output switching circuit 41 for the second component 32. This positional relationship is different from that of the semiconductor device 30 in the first embodiment. Figure 5A The positional relationship is the same. In addition, a transmission control circuit 42B for the third component 32B is arranged between the high-frequency amplifier circuit 50B of the third component 32B and the output switching circuit 41B for the third component 32B.

[0131] A transmission control circuit 42 for the second component 32 and a transmission control circuit 42B for the third component 32B are disposed between the charge pump circuit 44 and the high-frequency amplifier circuit 50 of the second component 32. A transmission control circuit 42 for the second component 32 and a transmission control circuit 42B for the third component 32B are also disposed between the charge pump circuit 44 and the high-frequency amplifier circuit 50B of the third component 32B.

[0132] Furthermore, a transmission control circuit 42 for the second component 32 and a transmission control circuit 42B for the third component 32B are respectively arranged between the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41B of the third component 32B, and between the high-frequency amplifier circuit 50B of the third component 32B and the output switch circuit 41B of the second component 32B.

[0133] Next, the superior effects of the third embodiment will be explained.

[0134] In the third embodiment, similarly to the second embodiment, the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41 of the second component 32 are arranged separately from each other, thereby improving the insulation between them. Similarly, the insulation between the high-frequency amplifier circuit 50B of the third component 32B and the output switch circuit 41B of the third component 32B can be improved.

[0135] Second embodiment ( Figure 9In the first embodiment, the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41B of the third component 32B are arranged close to each other. In contrast, in the third embodiment, the high-frequency amplifier circuit 50 of the second component 32 and the output switch circuit 41B of the third component 32B are arranged spaced apart. Therefore, the insulation between the high-frequency amplifier circuit 50 and the output switch circuit 41B can be improved. Similarly, the insulation between the high-frequency amplifier circuit 50B and the output switch circuit 41B can be improved. Therefore, it is possible to obtain an excellent effect where electromagnetic interference between the two is less likely to occur even when the high-frequency amplifier circuit 50 of the second component 32 and the high-frequency amplifier circuit 50B of the third component 32B operate simultaneously.

[0136] Next, refer to Figure 12 A variation of the third embodiment will be described.

[0137] Figure 12 This is a top view schematic diagram showing the arrangement of the constituent elements of the semiconductor device 30 in a modified example of the third embodiment. Figure 12 Zhongyu Figure 11 Similarly, the area of ​​the first component 31 where the circuits are arranged is marked with a relatively dark shaded line sloping downward to the right, while the area of ​​the second component 32 where the circuits are arranged is marked with a relatively light shaded line sloping upward to the right.

[0138] In the third embodiment, a second component 32 and a third component 32B are joined to the first component 31, and driver stage amplifier circuits 52 and 52B, power stage amplifier circuits 51 and 51B are respectively formed in the second component 32 and the third component 32B. In contrast, in this modified example, a second component 32 is joined to the first component 31, and two driver stage amplifier circuits 52 and 52B, two power stage amplifier circuits 51 and 51B, two input matching circuits 54 and 54B, and two bias circuits 53 and 53B are formed in the second component.

[0139] At least a portion of the input switch circuit 43 formed in the first component 31 is positioned outside the second component 32 when viewed from above. Wiring 61, 61B within the rewiring layer is connected to the input switch circuit 43 outside the second component 32 when viewed from above. As in this variation, a dual-system amplifier circuit can also be formed in a single second component 32.

[0140] It goes without saying that the above embodiments are illustrative, and partial substitutions or combinations of the structures shown in different embodiments are possible. The same effects caused by the same structures in multiple embodiments are not mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, various changes, improvements, and combinations will be apparent to those skilled in the art.

Claims

1. A semiconductor device comprising: A first component has a first surface, and when viewed from above, at least one switching circuit including a switch is disposed inside the first surface. The second component is surface-contactly bonded to the first surface of the first component and includes a plurality of transistors constituting a compound semiconductor system for a high-frequency amplifier circuit. as well as The first conductor protrusion extends from the second component to the opposite side of the first component. The first component includes circuit elements that, when viewed from above, are positioned between the high-frequency amplifier circuit and the at least one switching circuit, but do not constitute the at least one switching circuit.

2. The semiconductor device according to claim 1, wherein, The at least one switching circuit includes: Charge pump circuit; and The output switching circuit switches the high-frequency signal output from the high-frequency amplifier circuit to one output contact selected from multiple output contacts. The charging pump circuit and the output switch circuit are configured adjacent to each other.

3. The semiconductor device according to claim 2, wherein, The semiconductor device also includes: The third component, which is in surface contact with and coupled to the first component, includes a plurality of other transistors of a compound semiconductor system constituting other high-frequency amplifier circuits. and The second conductor protrusion extends from the third component to the side opposite to the first component. The first component further includes an output switching circuit for the third component, which switches the high-frequency signal output from the high-frequency amplification circuit of the third component to one output contact selected from a plurality of output contacts. When viewed from above, the output switch circuit for the third component is disposed between the high-frequency amplification circuit of the second component and the output switch circuit for the second component, and the output switch circuit for the second component is disposed between the high-frequency amplification circuit of the third component and the output switch circuit for the third component.

4. The semiconductor device according to claim 3, wherein, The high-frequency amplification circuit of the second component and the high-frequency amplification circuit of the third component operate in different frequency bands.

Images