Solid-state imaging device and electronic equipment

Abstract

A light detection device includes: a photoelectric conversion unit, which is configured to generate photoelectric charges; a first charge holding unit, which includes a first capacitor element and holds the photoelectric charges generated by the photoelectric conversion unit; a second charge holding unit, which is configured to hold the photoelectric charges transferred from the first charge holding unit; a first transistor, which is arranged on a wiring connecting the first charge holding unit and the second charge holding unit to transfer the photoelectric charges held in the first charge holding unit to the second charge holding unit; and a second transistor, which is configured to cause a pixel signal of a voltage value corresponding to the charge amount of the photoelectric charges held in the second charge holding unit to appear on a signal line.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and an electronic device. Background Art

[0002] In recent years, solid-state imaging elements such as CMOS (complementary metal oxide semiconductor) image sensors (CIS: CMOS image sensors) have become very common and are being used in various fields instead of film-type imaging devices. Instead of film-type imaging devices, solid-state imaging elements are used in normal imaging of visible light, and are also widely used for imaging of non-visible light such as ultraviolet rays, infrared rays, X-rays, and gamma rays. In addition, in an imaging device having a photoelectric conversion film, a pixel circuit that performs global shutter drive for holding photoelectric charges through a floating diffusion (FD: Floating Diffusion) is known. This pixel circuit may be referred to as a pixel circuit of an FD retention type global shutter (GS).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] JP 2011-130364 A Summary of the Invention

[0007] [Technical Issues]

[0008] However, when an FD retention type GS pixel circuit is designed with PN junction capacitance and wiring capacitance, the upper limit of the SN capacitance (the capacitance of the sense node (SN) that serves as a diffusion layer for accumulating photoelectric charge) is approximately 10fF, and it is difficult to ensure a sufficient amount of saturation charge. If the SN capacitance has insufficient saturation charge, the characteristics of the CMOS image sensor may deteriorate.

[0009] Therefore, the present disclosure provides a light detection device such as a solid-state imaging device and an electronic device for improving the characteristics of a CMOS image sensor.

[0010] [Technical solution to the problem]

[0011] According to at least some embodiments of the present disclosure, a solid-state imaging device includes: a photoelectric conversion unit configured to generate photoelectric charges; a first charge holding unit including a first capacitor element and holding the photoelectric charges generated by the photoelectric conversion unit; a second charge holding unit configured to hold the photoelectric charges transferred from the first charge holding unit; a first transistor arranged on a wiring connecting the first charge holding unit and the second charge holding unit to transfer the photoelectric charges held in the first charge holding unit to the second charge holding unit; and a second transistor configured to cause a pixel signal having a voltage value corresponding to the charge amount of the photoelectric charges held in the second charge holding unit to appear on a signal line.

[0012] According to certain embodiments of the present disclosure, a light detection device is provided. The light detection device includes: a photoelectric conversion region configured to generate photoelectric charges; a sensing node connected to the photoelectric conversion region, the sensing node including a first capacitor and holding the photoelectric charges generated by the photoelectric conversion region; a floating diffusion configured to hold the photoelectric charges transferred from the sensing node; a first transistor between the sensing node and the floating diffusion, the first transistor configured to selectively connect the sensing node to the floating diffusion to transfer the photoelectric charges held in the sensing node to the floating diffusion; and a second transistor between the floating diffusion and a signal line, the second transistor configured to selectively cause a pixel signal having a voltage value corresponding to the charge amount of the photoelectric charges held in the floating diffusion to appear on the signal line.

[0013] According to other embodiments of the present disclosure, an electronic device is provided. The electronic device includes: a pixel array in which a plurality of pixels are arranged in row and column directions; a drive circuit configured to drive a pixel to be read out from the plurality of pixels; and a processing circuit configured to read out a pixel signal from the pixel to be read out driven by the drive circuit. Each of the plurality of pixels includes: a photoelectric conversion region configured to generate photoelectric charges; a sensing node including a first capacitor element and holding the photoelectric charges generated by the photoelectric conversion region; a floating diffusion including a second capacitor element and holding the photoelectric charges transferred from the first charge holding unit; a first transistor between the sensing node and the floating diffusion, wherein the first transistor is configured to selectively transfer the photoelectric charges held in the sensing node to the floating diffusion; and a second transistor between the floating diffusion and a signal line, wherein the second transistor is configured to selectively cause a pixel signal having a voltage value corresponding to the charge amount of the photoelectric charges held in the second charge holding unit to appear on the signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] [ Figure 1 ]

[0015] Figure 1 is a block diagram illustrating a schematic configuration example of an electronic device according to an embodiment of the present disclosure.

[0016] [ Figure 2 ]

[0017] Figure 2 is a block diagram illustrating a schematic configuration example of an image sensor according to an embodiment of the present disclosure.

[0018] [ Figure 3 ]

[0019] Figure 3 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0020] [ Figure 4 ]

[0021] Figure 4 is a cross-sectional view of a pixel circuit according to an embodiment of the present disclosure.

[0022] [ Figure 5 ]

[0023] Figure 5 is a graph showing the relationship between the saturation charge number and the total capacitance of the SN.

[0024] [ Figure 6 ]

[0025] Figure 6 is a graph showing the relationship between the capacitance of the FD and random noise.

[0026] [ Figure 7 ]

[0027] Figure 7 is a diagram showing a design example of FD and SN.

[0028] [ Figure 8 ]

[0029] Figure 8 is a diagram showing a layout of a pixel circuit according to an embodiment of the present disclosure.

[0030] [ Figure 9 ]

[0031] Figure 9 is a diagram showing the arrangement of a plurality of pixel circuits.

[0032] [ Figure 10 ]

[0033] Figure 10 This is a layout diagram when a P-well tap and an N-well tap are shared.

[0034] [ Figure 11 ]

[0035] Figure 11 is a diagram showing a first example of another arrangement of a plurality of pixel circuits.

[0036] [ Figure 12A ]

[0037] Figure 12A is a diagram showing a second example of another arrangement of a plurality of pixel circuits.

[0038] [ Figure 12B ]

[0039] Figure 12B is a diagram showing a third example of another arrangement of a plurality of pixel circuits.

[0040] [ Figure 13 ]

[0041] Figure 13 is a diagram showing another example of the layout of a pixel circuit.

[0042] [ Figure 14 ]

[0043] Figure 14 is a circuit diagram of a pixel circuit according to Modification 1 of the embodiment of the present disclosure.

[0044] [ Figure 15 ]

[0045] Figure 15 is a circuit diagram of a pixel circuit according to Modification 2 of the embodiment of the present disclosure.

[0046] [ Figure 16 ]

[0047] Figure 16 is a circuit diagram of a pixel circuit according to Modification 3 of the embodiment of the present disclosure.

[0048] [ Figure 17 ]

[0049] Figure 17 is a circuit diagram of a pixel circuit according to Modification 4 of the embodiment of the present disclosure.

[0050] [ Figure 18A ]

[0051] Figure 18A is a diagram showing a planar configuration of a light receiving element.

[0052] [ Figure 18B ]

[0053] Figure 18B It shows that along Figure 18A FIG. 1 is a diagram of a cross-sectional structure taken along line BB′.

[0054] [ Figure 19 ]

[0055] Figure 19 is a diagram showing a cross-sectional configuration of another light receiving element.

[0056] [ Figure 20 ]

[0057] Figure 20 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0058] [ Figure 21 ]

[0059] Figure 21 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0060] [ Figure 22 ]

[0061] Figure 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0062] [ Figure 23 ]

[0063] Figure 23 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION

[0064] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the same parts are represented by the same reference numerals, and thus repeated descriptions will be omitted.

[0065] Note that the description will be given in the following order.

[0066] 1. Example

[0067] 2. Application Examples

[0068] 3. Application of mobile objects

[0069] 4. Application of endoscopic surgical system

[0070] 1. Example

[0071] The structure of electronic equipment

[0072] Figure 11 is a block diagram showing a schematic configuration example of an electronic device according to an embodiment of the present disclosure. Figure 1 As shown, the electronic device 100 includes, for example, an imaging lens 101 , an image sensor 102 , a processor 103 and a storage unit 104 .

[0073] The imaging lens 101 is an example of an optical system that converges incident light and forms an image on the light-receiving surface of the image sensor 102. The light-receiving surface may be a surface of the image sensor 102 on which photoelectric conversion elements are arranged. The image sensor 102 performs photoelectric conversion on the incident light and generates image data. The image sensor 102 also performs predetermined signal processing on the generated image data, such as noise removal and white balance adjustment.

[0074] The storage unit 104 includes, for example, a flash memory, a dynamic random access memory (DRAM), and a static random access memory (SRAM), and records image data such as image data input from the image sensor 102 .

[0075] The processor 103 is configured using, for example, a central processing unit (CPU), and may include, for example, an application processor for executing an operating system and various application software, a graphics processing unit (GPU), and a baseband processor. For example, the processor 103 performs various processes on image data such as image data input from the image sensor 102 and image data read from the storage unit 104 as needed, displays the image data to a user, and transmits the image data to the outside via a predetermined network.

[0076] Image sensor structure

[0077] Figure 2 This is a block diagram illustrating an example schematic configuration of an image sensor according to an embodiment of the present disclosure. Image sensor 102 is a CMOS image sensor. A CMOS image sensor is an image sensor produced by applying or partially utilizing a CMOS process. For example, image sensor 102 is formed as a backside-illuminated image sensor. Image sensor 102 is an example of a "solid-state imaging device."

[0078] The image sensor 102 according to this embodiment has, for example, a stacked structure in which a semiconductor chip including a pixel array unit 121 and a semiconductor chip including peripheral circuits are stacked. The peripheral circuits include, for example, a vertical drive circuit 122, a column processing circuit 123, a horizontal drive circuit 124, and a system control unit 125.

[0079] The image sensor 102 further includes a signal processing unit 126 and a data storage unit 127. The signal processing unit 126 and the data storage unit 127 may be provided on the same semiconductor chip as the peripheral circuit, or may be provided on another semiconductor chip.

[0080] The pixel array unit 121 has a structure in which unit pixels (hereinafter sometimes simply referred to as "pixels") 120 are arranged in a two-dimensional grid pattern (i.e., a matrix pattern) in the row and column directions. Each unit pixel has a photoelectric conversion element that generates and accumulates charge corresponding to the amount of light received. The row direction refers to the direction in which pixels in a pixel row are arranged (horizontally in the figure), and the column direction refers to the direction in which pixels in a pixel column are arranged (vertically in the figure). The detailed circuit configuration and pixel structure of the pixel 120 will be described below.

[0081] In the pixel array unit 121, regarding the matrix pixel array, a pixel drive line LD is arranged along the row direction for each pixel row, and a vertical signal line VSL is arranged along the column direction for each pixel column. The pixel drive line LD transmits a drive signal for driving when reading a signal from a pixel. Figure 2 In the embodiment, although the pixel drive line LD is shown as one wiring line, it is not limited to one. One end of the pixel drive line LD is connected to the output end of the vertical drive circuit 122 corresponding to each row.

[0082] The vertical drive circuit 122 is composed of, for example, a shift register and an address decoder, and drives each pixel 120 of the pixel array unit 121, for example, all pixels simultaneously or in units of rows. In other words, the vertical drive circuit 122, together with the system control unit 125 for controlling the vertical drive circuit 122, constitutes a drive unit that controls the operation of each pixel 120 of the pixel array unit 121. Although the specific configuration of the vertical drive circuit 122 is not shown, the vertical drive circuit generally includes two scanning systems, a readout scanning system and a sweep scanning system.

[0083] The readout scanning system selectively scans pixels 120 of pixel array unit 121 in order, row by row, to read out signals from pixels 120. The signals read out from pixels 120 are analog signals. The cleanup scanning system performs a cleanup scan on the readout row on which the readout scanning system performs the readout scan, one exposure time in advance of the readout scan.

[0084] The sweep scan system clears unnecessary charge from the photoelectric conversion elements of the pixels 120 in the readout row, thereby resetting the photoelectric conversion elements. The sweep scan system then clears (resets) unnecessary charge, thereby performing a so-called electronic shutter operation. The electronic shutter operation here refers to an operation that discards the charge in the photoelectric conversion elements and initiates a new exposure (starts charge accumulation).

[0085] The signal read out by the readout scanning system's readout operation corresponds to the amount of light received immediately before the readout operation or after the electronic shutter operation. The period from the readout timing of the immediately preceding readout operation or the clearing timing of the electronic shutter operation to the readout timing of the current readout operation is the charge accumulation period (also referred to as the exposure period) in the pixel 120.

[0086] The signal output from each pixel 120 of the pixel row selectively scanned by the vertical drive circuit 122 is input to the column processing circuit 123 through each vertical signal line VSL of each pixel column. The column processing circuit 123 performs predetermined signal processing on the signal output from each pixel 120 of the selected row through the vertical signal line VSL of each pixel column of the pixel array unit 121, and temporarily holds the pixel signal after the signal processing.

[0087] Specifically, the column processing circuit 123 performs at least noise removal processing, such as correlated double sampling (CDS) processing or double data sampling (DDS) processing as signal processing. For example, the CDS processing removes fixed pattern noise inherent to the pixel, such as reset noise and threshold variation of the amplifier transistor in the pixel 120. For example, the column processing circuit 123 also has an analog-to-digital (AD) conversion function, and converts the analog pixel signal read out from the photoelectric conversion element into a digital signal, and outputs the digital signal.

[0088] For example, the horizontal drive circuit 124 is composed of a shift register and an address decoder, and sequentially selects readout circuits (hereinafter referred to as pixel circuits) corresponding to pixel columns of the column processing circuit 123. Selective scanning by the horizontal drive circuit 124 allows pixel signals processed by the column processing circuit 123 for each pixel circuit to be sequentially output.

[0089] For example, the system control unit 125 is configured by a timing generator for generating various timing signals, and drives and controls the vertical driving circuit 122 , the column processing circuit 123 , and the horizontal driving circuit 124 based on various timings generated by the timing generator.

[0090] The signal processing unit 126 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing circuit 123. The data storage unit 127 temporarily stores data necessary for the signal processing in the signal processing unit 126.

[0091] Note that the image data output from the signal processing unit 126 may be subjected to predetermined processing by the processor 103 in the electronic device 100 on which the image sensor 102 is mounted, or may be transmitted to the outside via a predetermined network, for example.

[0092] Configuration of a pixel circuit according to an embodiment of the present disclosure

[0093] Figure 3 1 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure. The pixel 120 has Figure 3 The pixel circuit 1 shown is shown. The pixel 120 having the pixel circuit 1 is an example of a “solid-state imaging device”.

[0094] The pixel circuit 1 includes a photoelectric conversion film (also referred to as a photoelectric conversion unit) 10, a reset (RST) transistor 11, an amplifier (AMP) transistor 12, and a select (SEL) transistor 13. The pixel circuit 1 also includes a transfer (TRG) transistor 14 and a discharge (OFG) transistor 15. The pixel circuit 1 also includes a sense node (SN) 21 of a diffusion layer serving as the source of the transfer transistor 14 and the drain of the discharge transistor 15, and an FD (floating diffusion) 20 serving as a floating diffusion layer. In addition, the pixel circuit 1 according to this embodiment has capacitors 16 and 17. The pixel circuit 1 according to this embodiment is a pixel circuit of an FD retention type global shutter (GS).

[0095] The photoelectric conversion film 10 according to the present embodiment is a photoelectric conversion film in which holes formed using a compound semiconductor such as InGaAs are used as carriers for photoelectric conversion. For example, the photoelectric conversion film 10 may also be formed using a compound semiconductor such as indium arsenide antimony (InAsSb), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), or germanium (Ge), quantum (Q) dots, or an organic compound.

[0096] The output terminal of the photoelectric conversion film 10 according to this embodiment is connected to a SN 21, which is connected to the source of the discharge transistor 15, the source of the transfer transistor 14, and a capacitor 16. The discharge transistor 15 has a source connected to the SN 21 and a drain connected to the low-voltage power supply VDR. The transfer transistor 14 has a source connected to the SN 21 and a drain connected to the FD 20. The output terminal of the FD 20 is connected to the source of the reset transistor 11, the gate of the amplifier transistor 12, and a capacitor 17. The drain of the reset transistor 11 is connected to the low-voltage power supply VDR. The drain of the amplifier transistor 12 is connected to the voltage power supply VDD. Furthermore, the source of the amplifier transistor 12 is connected to the drain of the select transistor 13. The source of the select transistor 13 is connected to the output signal line. Capacitor 16 is connected to the output terminal of the photoelectric conversion film 10. Capacitor 17 is connected to the FD 20.

[0097] As described above, the output terminal of the photoelectric conversion film 10 is connected to the SN 21. The photoelectric conversion film 10 outputs holes as photoelectric conversion carriers from the output terminal. For example, the photoelectric conversion film 10 has a p-type impurity region, and the p-type impurity region is connected to the SN 21.

[0098] As described above, the SN 21 is connected to the output terminal of the photoelectric conversion film 10, the source of the discharge transistor 15, and the source of the transfer transistor 14. The SN 21 also includes the capacitor 16, which is a high-capacitance element. Any of a MOS capacitor, a capacitor having a metal-insulator-metal (MIM) structure in which an insulator is sandwiched by metal, or a capacitor having a three-dimensional MIM structure can be used as the SN 21. The SN 21 is an example of a "first charge retention unit."

[0099] As described above, capacitor 16 has one terminal connected to SN 21 and the other terminal connected to voltage source VDD. Capacitor 16 accumulates and holds the charge output from photoelectric conversion film 10. In other words, capacitor 16 increases the total capacitance of SN 21 to ensure the required saturation charge. Capacitor 16 is an example of a "first capacitive element."

[0100] The SN 21 including the capacitor 16 has a total capacitance that is the sum of the following four capacitances. Hereinafter, the total capacitance of the SN 21 including the capacitor 16 is simply referred to as the "total capacitance of the SN 21." One of the total capacitances of the SN 21 is the wiring capacitance of each wiring connected to the photoelectric conversion film 10, the discharge transistor 15, the transfer transistor 14, and the capacitor 16. Another of the total capacitances of the SN 21 is the diffusion capacitance serving as a diffusion layer. Still another of the total capacitances of the SN 21 is the capacitance of the capacitor 16. Still another of the total capacitances of the SN 21 is the InGaAs capacitance, which is the capacitance of the InGaAs forming the photoelectric conversion film 10. Figure 3In FIG, the wiring capacitance, diffusion capacitance, and InGaAs capacitance of the SN 21 excluding the capacitance of the capacitor 16 are represented as capacitance 18. In other words, the total capacitance of the SN 21 is the capacitance of the capacitor 16 plus the capacitance 18. The capacitance of the SN 21 including the capacitor 16 is, for example, 10 fF (femtofarad) or greater.

[0101] The capacitance of capacitor 16 is greater than the other capacitors that contribute to the total capacitance of SN 21. For example, the capacitance of capacitor 16 is one order of magnitude greater than the other capacitors that contribute to the total capacitance of SN 21. In other words, the capacitance of capacitor 16 becomes the dominant component of the capacitance of SN 21.

[0102] Therefore, by adding the capacitor 16, the saturation capacitance of the SN 21 increases. By increasing the saturation charge amount of the SN 21 to a desired value, noise can be reduced, thereby improving the characteristics of the image sensor 102 including the pixel circuit 1.

[0103] When the discharge transistor 15 is turned on, the charge held by the SN 21 including the capacitor 16 is discharged to the low voltage power supply VDR. On the other hand, when the transfer transistor 14 is turned on, the charge held by the SN 21 including the capacitor 16 is transferred to the FD 20.

[0104] Discharge transistor 15 is a PMOS transistor. As described above, discharge transistor 15 has a source connected to SN21 and a drain connected to the low-voltage power supply VDR. Furthermore, the gate of discharge transistor 15 is connected to the discharge control signal line. When a voltage equal to or lower than the threshold voltage is applied to the gate, discharge transistor 15, a PMOS transistor, turns on. On the other hand, when a voltage greater than the threshold voltage is applied to the gate, discharge transistor 15 turns off. When discharge transistor 15 is on, the charge held in photoelectric conversion film 10 and capacitor 16 is discharged to the low-voltage power supply VDR, resetting photoelectric conversion film 10. Discharge transistor 15 is an example of a "fifth transistor."

[0105] The transfer transistor 14 is also a PMOS transistor. As described above, the transfer transistor 14 has a source connected to the output terminal of the photoelectric conversion film 10 and a drain connected to the FD 20. Furthermore, the gate of the transfer transistor 14 is connected to the transmission signal line. When a voltage equal to or lower than the threshold voltage is applied to the gate by a signal transmitted from the transmission signal line, the PMOS transfer transistor 14 turns on. Furthermore, when a voltage greater than the threshold voltage is applied to the gate, the transfer transistor 14 turns off. When the transfer transistor 14 is on, the charge generated by the photoelectric conversion film 10 and accumulated in the capacitor 16 is transferred to the FD 20. The transfer transistor 14 is an example of a "fourth transistor."

[0106] As described above, the FD 20 is connected to the drain of the transfer transistor 14, the source of the reset transistor 11, and the gate of the amplifier transistor 12. The FD 20 also includes the capacitor 17, which is a high-capacitance element. Any of a MOS capacitor, a capacitor having an MIM structure, or a capacitor having a three-dimensional MIM structure can be used as the FD 20. The FD 20 is an example of a "second charge holding unit."

[0107] As described above, capacitor 17 has one terminal connected to FD 20 and the other terminal connected to voltage supply VDD. Capacitor 17 accumulates and holds the charge transferred from SN 21. In other words, capacitor 17 increases the total capacitance of FD 20 to ensure the required saturation charge. Capacitor 17 is an example of a "second capacitive element."

[0108] The FD 20 including the capacitor 17 has the sum of the following four capacitances as a total capacitance. Hereinafter, the total capacitance of the FD 20 including the capacitor 17 is simply referred to as the "total capacitance of the FD 20". One of the total capacitances of the FD 20 is the wiring capacitance of each wiring connected to the reset transistor 11, the amplifying transistor 12, the transfer transistor 14, and the capacitor 17. Another of the total capacitances of the FD 20 is the diffusion capacitance used as a diffusion layer. Still another of the total capacitances of the FD 20 is the capacitance of the capacitor 17. Still another of the total capacitances of the FD 20 is the AMP capacitance, which is the gate capacitance of the amplifying transistor. Figure 3 , the wiring capacitance, diffusion capacitance, and AMP capacitance excluding the capacitance of the capacitor 17 in the total capacitance of the FD 20 are represented as capacitance 19. In other words, the total capacitance of the FD 20 is the capacitance of the capacitor 17 plus the capacitance 19.

[0109] The capacitance of capacitor 17 is larger than other capacitances forming the total capacitance of FD 20. For example, the capacitance of capacitor 17 is one order of magnitude larger than other capacitances forming the total capacitance of FD 20. In other words, the capacitance of capacitor 17 becomes the main component of the capacitance of FD 20.

[0110] The total capacitance of FD 20 matches the total capacitance of SN 21. In other words, the capacitances of capacitor 16 and capacitor 17 are determined so that the value obtained by adding the other capacitances of SN 21 and the capacitance of capacitor 16 substantially matches the value obtained by adding the other capacitances of FD 20 and the capacitance of capacitor 17.

[0111] By setting the total capacitance of FD 20 and the total capacitance of SN 21 to substantially the same value, noise in pixel circuit 1 can be minimized. However, when capacitors 16 and 17 are not provided, it is difficult to match the total capacitances due to differences in the manufacturing processes of FD 20 and SN 21. In particular, when capacitors 16 and 17 are not provided, the main component of the total capacitance of FD 20 is wiring capacitance, while the main component of the total capacitance of SN 21 is InGaAs capacitance. Since wiring capacitance and InGaAs capacitance have no correlation, the wiring capacitance and InGaAs capacitance may change in opposite directions, with one increasing while the other decreases. In this case, the difference between the total capacitance of FD 20 and the total capacitance of SN 21 increases, and noise may increase.

[0112] Therefore, in the pixel circuit 1 according to this embodiment, capacitor 17 and capacitor 16, each having a larger capacitance than the other capacitance, are arranged in the FD 20 and the SN 21, respectively. Therefore, the capacitance of capacitor 17 and the capacitance of capacitor 16 become the main components of the total capacitance of the FD 20 and the main components of the total capacitance of the SN 21, respectively, thereby reducing the influence of manufacturing variations and thereby matching the total capacitance of the FD 20 with the total capacitance of the SN 21. Therefore, the characteristics of the image sensor 102 including the pixel circuit 1 can be stabilized.

[0113] When the transfer transistor 14 is turned on, the FD 20 including the capacitor 17 transfers the charge held by the SN 21 including the capacitor 16, and accumulates and holds the transferred charge. The FD 20 applies a voltage generated by the charge held in the capacitor 17, for example, to the gate of the amplifier transistor 12. The FD 20 turns on the amplifier transistor 12 by applying a voltage equal to or higher than the threshold voltage to the gate of the amplifier transistor 12. When the reset transistor 11 is turned on, the charge held by the FD 20 including the capacitor 17 is discharged to the low-voltage power supply VDR, and the FD 20 is reset.

[0114] The reset transistor 11 is a PMOS transistor. As described above, the source of the reset transistor 11 is connected to the path connected to the FD 20, and the drain is connected to the low-voltage power supply VDR. Furthermore, the gate of the reset transistor 11 is connected to the reset signal line. When a voltage equal to or lower than the threshold voltage is applied to the gate, the reset transistor 11 turns on. On the other hand, when a voltage greater than the threshold voltage is applied to the gate, the reset transistor 11 turns off. When the reset transistor 11 turns on, the charge accumulated in the FD 20 is discharged to the low-voltage power supply VDR, resetting the FD 20 including the capacitor 17. The reset transistor 11 is an example of a "first transistor."

[0115] The amplifier transistor 12 is an N-type MOS transistor (NMOS). As described above, the gate of the amplifier transistor 12 is connected to a path connected to the FD 20, the source is connected to the voltage supply VDD, and the drain is connected to the source of the selection transistor 13. When a voltage equal to or higher than the threshold voltage is applied to the gate by the charge output from the FD 20, the amplifier transistor 12 turns on. Alternatively, when a voltage less than the threshold voltage is applied to the gate, the amplifier transistor 12 turns off. When the amplifier transistor 12 is on, it outputs the current input from the voltage supply VDD to the selection transistor 13. In other words, the amplifier transistor 12 outputs a signal based on the charge held in the FD 20 to the selection transistor 13. The amplifier transistor 12 is an example of a "second transistor" and an "image generation unit."

[0116] The selection transistor 13 is an NMOS. As described above, the source of the selection transistor 13 is connected to the drain of the amplifier transistor 12, and the drain is connected to the output signal line. In addition, the gate of the selection transistor 13 is connected to the selection signal line. Since the selection transistor 13 is an NMOS, when a voltage equal to or greater than the threshold voltage is applied to the gate, the selection transistor is turned on. In addition, when a voltage less than the threshold voltage is applied to the gate, the selection transistor 13 is turned off. When the selection transistor 13 is turned on, the selection transistor outputs the signal output from the amplifier transistor 12 as a pixel signal to the output signal line. In other words, the selection transistor 13 controls the selection of the pixel during readout by determining whether the pixel signal is output from the pixel circuit 1. The selection transistor 13 is an example of a "third transistor."

[0117] Figure 4 is a cross-sectional view of a pixel circuit according to an embodiment of the present disclosure. Figure 4 The total capacitance of FD 20 and SN 21 is described uniformly. Figure 4 As shown, the pixel circuit 1 according to the present embodiment has a P-well arranged on an N-Sub which is an N-type semiconductor substrate and an N-well arranged in a portion of the P-well.

[0118] Reset transistor 11, transfer transistor 14, and discharge transistor 15 have their sources and drains arranged on an N-well, which is an N-type diffusion region. In other words, reset transistor 11, transfer transistor 14, and discharge transistor 15 share a diffusion layer. In this case, the source of reset transistor 11 and the drain of transfer transistor 14 use a shared N-type diffusion region. Additionally, the source of transfer transistor 14 and the source of discharge transistor 15 use a shared N-type diffusion region.

[0119] Furthermore, the photoelectric conversion film 10 and the capacitor 16 are connected to wiring extending from the SN 21. Figure 4In the embodiment, the photoelectric conversion film 10 includes, for example, a passivation layer, a transparent electrode layer, an InP (indium phosphide) layer, an InGaAs layer, a Ti-W (titanium-tungsten) layer, and a diffusion layer. The terminals extending from the diffusion layer have electrodes. The diffusion layer and the electrodes can be electrically connected via multiple wirings. The electrodes are also arranged via multiple wirings in the wirings extending from the SN 21. The electrodes extending from the diffusion layer of the photoelectric conversion film 10 and the electrodes connected to the wirings extending from the SN 21 are directly bonded. The electrodes are formed of a metal such as copper or a conductive material.

[0120] Furthermore, the amplifier transistor 12 and the select transistor 13 have their sources and drains arranged on a P-well, which is a P-type diffusion region. In other words, the amplifier transistor 12 and the select transistor 13 share a diffusion layer. In this case, the drain of the amplifier transistor 12 and the source of the select transistor 13 use a shared P-type diffusion region.

[0121] The FD 20 includes wiring for connecting the drain of the transfer transistor 14 and the gate of the amplification transistor 12. The capacitor 17 is connected to the FD 20.

[0122] Furthermore, the capacitance of each of FD 20 and SN 21 will be described. Figure 4 In the figure, each capacitor is represented by maintaining the approximate position of each capacitor by the portion surrounded by the single-dot chain line and the double-dot chain line.

[0123] The total capacitance of FD 20 includes wiring capacitance 201, diffusion capacitance 202, electrostatic capacitance 203, and AMP capacitance 204. Wiring capacitance 201 is the capacitance of the wiring extending from FD 20. Diffusion capacitance 202 is the capacitance of the diffusion layer connected to FD 20. Electrostatic capacitance 203 is the capacitance of capacitor 17. AMP capacitance 204 is the capacitance of the gate of amplifier transistor 12.

[0124] The total capacitance of SN 21 includes wiring capacitance 211, diffusion capacitance 212, electrostatic capacitance 213, and InGaAs capacitance 214. Wiring capacitance 211 is the capacitance of the wiring extending from SN 21. Diffusion capacitance 212 is the capacitance of the diffusion layer of SN 21. Electrostatic capacitance 213 is the capacitance of capacitor 17. InGaAs capacitance 214 is the capacitance of the InGaAs layer in photoelectric conversion film 10.

[0125] The electrostatic capacitance 213 is determined so that the saturation charge number of the SN 21 is a desired value. In addition, the electrostatic capacitance 203 is determined so that the value obtained by adding the wiring capacitance 201, the diffusion capacitance 202, the electrostatic capacitance 203, and the AMP capacitance 204 substantially matches the value obtained by adding the wiring capacitance 211, the diffusion capacitance 212, the electrostatic capacitance 213, and the InGaAs capacitance 214.

[0126] Now, a method of determining the electrostatic capacitances 203 and 213 will be described. In the image sensor 102, the amount of saturation charge (Qs) of the SN 21, the conversion efficiency (CGConversion Gain), and the random noise (RN: Random Noise) are expressed by the following mathematical formula 1.

[0127] [Mathematical formula 1]

[0128]

[0129] Among them, C SN is the total capacitance of SN 21. C FD is the total capacitance of the FD 20. Vtop is the voltage in the photoelectric conversion film 10. VDR is Figure 3 The voltage of the medium / low voltage power supply VDR. q is the charge per electron. k is the Boltzmann constant. T is the temperature.

[0130] As shown in Mathematical Formula 1, the amount of saturation charge depends on C SN . Figure 5 is a graph showing the relationship between the saturation charge number and the total capacitance of the SN. Figure 5 In the graph, the vertical axis represents the saturation charge count, and the horizontal axis represents the voltage of the photoelectric conversion film. In other words, as the voltage of the photoelectric conversion film 10 increases, the saturation charge count gradually accumulates. The greater the total capacitance of the SN 21, the greater the saturation charge count per voltage. Therefore, the total capacitance of the SN 21 is determined to achieve the desired saturation charge count. For example, the electrostatic capacitance 203 is determined so that when the voltage of the photoelectric conversion film 10 is a predetermined value, the saturation capacitance of the SN 21 becomes 100,000. The electrostatic capacitance of the capacitor 16 is determined so that the SN 21 has a predetermined saturation capacitance.

[0131] Furthermore, the relationship between the capacitance of the FD 20 and the random noise is obtained by the mathematical formula in which the random noise is expressed by the number of charges in Mathematical Formula 1. Figure 6 is a graph showing the relationship between the capacitance of the FD and random noise. Figure 6In the graph, the vertical axis represents noise, and the horizontal axis represents the capacitance of FD 20. Both the kTC noise in the D phase and the kTC noise in the P phase are represented by curve 301. The sum of the noise is then calculated by squaring, adding, and averaging the noise, and is represented by curve 302. The random noise is minimized at the minimum point in curve 302. When the capacitance of SN 21 and the capacitance of FD 20 are designed to be the same value, curve 302 reaches its minimum value. Therefore, the electrostatic capacitance of capacitor 17 is determined so that the capacitance of FD 20 matches the capacitance of SN 21.

[0132] Figure 7 The total capacitance of each of the FD 20 and the SN 21 determined by the above-described method is shown. Figure 7 is a diagram showing a design example of FD and SN. Figure 7 The values ​​shown are approximate. For example, the total capacitance of SN 21 is composed of 2.5E-15 wiring capacitance, 3.6E-16 diffusion capacitance, and 3.2E-15 InCaAs capacitance. Therefore, in this case, to obtain the desired saturation level, the electrostatic capacitance of capacitor 16 is determined to be 2.0E-14. In this case, the total capacitance of SN 21 is 2.6E-14.

[0133] On the other hand, in the FD capacitance, which is the total capacitance of FD 20, the wiring capacitance is 2.2E-15, the diffusion capacitance is 3.6E-16, and the AMP capacitance is 4.5E-16. Therefore, in this case, in order to reduce random noise, the electrostatic capacitance of capacitor 17 is determined to be 2.5E-14 so that the total capacitance of FD 20 and the total capacitance of SN 21 substantially match each other. In this case, the total capacitance of FD 20 is 2.8E-14, which substantially matches the total capacitance of SN 21 (i.e., 2.6E-14). The InGaAs capacitance included in the other capacitances of SN 21 other than capacitor 16 has a relatively large value relative to the other capacitances of FD 20 other than capacitor 17. Therefore, when the total capacitance of FD 20 and the total capacitance of SN 21 are designed to substantially match, the capacitance of capacitor 16 is preferably smaller than the capacitance of capacitor 17.

[0134] In addition, if Figure 7 As shown, the main component of the total capacitance of the FD 20 is the electrostatic capacitance of the capacitor 17, and the main component of the total capacitance of the SN 21 is the electrostatic capacitance of the capacitor 16. Since the electrostatic capacitance of each of the capacitors 16 and 17 is larger than the other capacitances included in the total capacitance of the FD 20 and the total capacitance of the SN 21, the influence of the manufacturing variation of the pixel circuit 1 is absorbed by the electrostatic capacitance of the capacitors 16 and 17, and the total capacitance of the FD 20 and the total capacitance of the SN 21 substantially match each other.

[0135] Operation of the pixel circuit according to the embodiment of the present disclosure

[0136] Now, we will explain Figure 3 The flow of pixel signal generation in the pixel circuit 1 is shown. First, the discharge transistor 15 becomes conductive, resetting the photoelectric conversion film 10 and the SN 21 with the capacitor 16. Then, when the discharge transistor 15 turns off, the charge generated in the photoelectric conversion film 10 is transferred to the SN 21 with the capacitor 16 and accumulated therein. The operations from resetting the photoelectric conversion film 10 to accumulating charge in the SN 21 with the capacitor 16 are performed simultaneously in all pixels 120 arranged in the pixel array unit 121. Thus, a global shutter is implemented. Note that the period from resetting the photoelectric conversion film 10 to accumulating charge in the capacitor 16 corresponds to the exposure period.

[0137] Next, the reset transistor 11 becomes conductive to reset the FD 20 having the capacitor 17. Then, the reset transistor 11 is turned off and the transfer transistor 14 is turned on. Therefore, the charge accumulated in the SN 21 having the capacitor 16 is transferred to the FD 20 and is accumulated and held in the FD 20 having the capacitor 17.

[0138] The amplifier transistor 12 generates a pixel signal corresponding to the charge held in the FD 20 having the capacitor 17. The select transistor 13 then becomes conductive, allowing the pixel signal generated by the amplifier transistor 12 to be output to the output signal line. The operations from resetting the FD 20 to outputting the pixel signal are sequentially performed for each pixel circuit 1 arranged in the pixel array. The pixel signal outputs are processed in all pixel circuits 1 in the pixel array to generate a frame of pixel signals as one screen.

[0139] Will refer to Figure 8 , further illustrating the layout of the pixel circuit 1. Figure 8 is a diagram showing a layout of a pixel circuit according to an embodiment of the present disclosure.

[0140] The pixel circuit 1 has a P-well 31 and an N-well 32. The N-well 32 is arranged on the P-well 31. The amplifier transistor 12 and the select transistor 13 are both NMOS transistors and are preferably arranged linearly on the P-well 31 to share diffusion layers such as the SN 21 and the FD 20. The reset transistor 11, the transfer transistor 14, and the discharge transistor 15 are PMOS transistors and are preferably arranged linearly on the N-well 32 to share diffusion layers. The linearly arranged amplifier transistor 12 and select transistor 13, as well as the linearly arranged reset transistor 11, transfer transistor 14, and discharge transistor 15, are arranged in parallel in the longitudinal direction.

[0141] Each pixel 120 has a lattice shape, and capacitors 16 and 17 are arranged in the remaining area of ​​the frame of each pixel 120, excluding the area where the reset transistor 11 to the discharge transistor 15 are arranged. As described above, the capacitance of capacitor 16 can be greater than that of capacitor 17, and the area occupied by capacitor 16 in the layout is smaller than that of capacitor 17. SN 21 is connected to wiring electrically connected to the photoelectric conversion film 10. On the other hand, FD 20 is connected to the gate of amplifier transistor 12. As described above, since FD 20 is connected to amplifier transistor 12, capacitor 17, which serves as the capacitance of FD 20, is positioned as a high-capacitance element close to amplifier transistor 12. In other words, capacitor 17 is arranged near amplifier transistor 12. This simplifies wiring and suppresses the generation of noise such as crosstalk. Furthermore, capacitor 16, which serves as the capacitance of SN 21, is arranged in the remaining area. In other words, capacitor 16 is arranged side by side with the reset transistor 11, transfer transistor 14, and discharge transistor 15 arranged in series. For example, the longitudinal direction of the capacitor 17 is arranged in a direction orthogonal to the longitudinal direction of the capacitor 16 .

[0142] Furthermore, a P-well tap 18 is arranged on the P-well 31. The P-well tap 18 is arranged on opposite sides of the amplifying transistor 12, holding the selecting transistor 13 in between. The P-well tap 18 is connected to a power supply.

[0143] Reset transistor 11 is arranged near amplifying transistor 12. Reset transistor 11, transfer transistor 14, and discharge transistor 15 are arranged in this order. Furthermore, N-well tap 19 is arranged on N-well 32. N-well tap 19 is arranged near P-well tap 18. N-well tap 19 is connected to a power supply. Capacitor 16 is arranged near transfer transistor 14 and discharge transistor 15. Capacitor 16 is then connected to SN 21, which has no other connected elements on N-well 32. Furthermore, contact 30 is arranged side by side between capacitors 16 and 17 to shield the in-pixel capacitance. Contact 30 is an example of a "shielding member."

[0144] Figure 9 is a diagram showing the arrangement of a plurality of pixel circuits. Figure 9 As shown, with Figure 8 The pixel circuit 1 of the illustrated layout can have a 2×2 mirror image arrangement. Figure 9 Four N-well taps 19 are shown in FIG. Figure 10 As shown, four N-well taps 19 can be shared as one N-well tap 19, thereby improving layout efficiency. Figure 10This is a layout diagram when the P-well tap and the N-well tap are shared. However, in the pixel circuit 1 according to the present embodiment having two floating nodes (FD 20 and SN 21), since the symmetry of the parasitic capacitance is important, four N-well taps 19 are provided without intentionally sharing the four N-well taps.

[0145] The pixel circuit 1 can also be used with Figure 9 The arrangement shown can be set up in different arrangements. For example, Figure 9 In FIG. 1 , when viewed from the front, the N-well tap 19 is arranged in an H-shaped manner, but as shown in FIG. Figure 11 As shown, the N-well tap 19 is integrated into an N-well tap arranged in the center, and when viewed from the front, the linearly arranged reset transistor 11, transfer transistor 14 and discharge transistor 15 can be arranged in an I-shaped manner, so that the longitudinal direction of these transistors is arranged into two rows on the upper side and two rows on the lower side. Figure 11 1 is a diagram showing another example of the arrangement of a plurality of pixel circuits. In this case, the layout efficiency can also be improved by sharing the N-well tap 19. Alternatively, as Figure 12A and Figure 12B As shown, can be arranged in parallel Figure 9 The pixel circuit 1 shown is unchanged in its direction. Figure 12A is a diagram showing a second example of another arrangement of a plurality of pixel circuits. Figure 12B 2 is a diagram showing a third example of another arrangement of a plurality of pixel circuits. This arrangement can reduce noise.

[0146] Figure 13 This is also a diagram showing another example of the layout of the pixel circuit. Regarding the arrangement of the transistors and the capacitors 16 and 17, Figure 13 The layout shown is similar to Figure 8 The layout shown is the same as that shown in FIG. However, in this case, capacitors 16 and 17, which serve as floating nodes, are covered by first metal 310. This allows electrical shielding of signal lines routed with a second metal or more. In this case, the Si-side power supply wiring for capacitors 16 and 17 can be shared.

[0147] Operation and Effect

[0148] As described above, the pixel circuit 1 according to this embodiment is an FD retention type GS and has the photoelectric conversion film 10 using holes as photoelectric conversion carriers. In the pixel circuit 1 according to this embodiment, the capacitors 16 and 17, which are high-capacitance elements compared to other capacitances, are arranged in the FD 20 and the SN 21.

[0149] Therefore, the pixel circuit 1 according to this embodiment can increase the saturation charge number Qs. By making the total capacitance of FD 20 and the total capacitance of SN 21 substantially match each other, random noise can also be minimized. In particular, when capacitor 16 is not provided, SN 21 does not become a photodiode (PD) of an ideal transfer type, and it is difficult to achieve the elimination of kTC noise through correlated double sampling (CDS). On the other hand, by providing capacitor 16, SN 21 can be close to the PD of the ideal transfer type, and kTC noise can be eliminated. Therefore, the dynamic range of pixel circuit 1 can be widely ensured, and image quality can be improved.

[0150] Furthermore, since capacitors 16 and 17 are the main components of the total capacitance of FD 20 and the total capacitance of SN 21, the capacitances serving as the main components can be balanced, and robustness against manufacturing variations can be ensured. Furthermore, since the main components are the electrostatic capacitances of the capacitors, the likelihood of capacitances varying in the same direction increases, and the risk of characteristic variations can be reduced.

[0151] Modification 1 of the embodiment of the present disclosure

[0152] Figure 14 FIG. 1 is a circuit diagram of a pixel circuit according to a modification example 1 of the embodiment of the present disclosure. Figure 14 As shown in FIG, the pixel circuit 1 according to this modification is different from the embodiment of the present disclosure in that the reset transistor 11 and the transfer transistor 14 are NMOS. Figure 14 Not shown Figure 3 Capacitors 18 and 19 are shown.

[0153] The reset transistor 11, the amplifying transistor 12, the selecting transistor 13, and the transferring transistor 14 are NMOS transistors, while the discharging transistor 15 is PMOS transistor.

[0154] Furthermore, in this modification, SN 21 is provided with capacitor 16, which is a high-capacitance element. FD 20 is provided with capacitor 17, which is also a high-capacitance element. In this case, the total capacitance of SN 21 is determined to ensure the required saturation charge, and capacitor 16 has an electrostatic capacitance that is a predetermined value for the total capacitance of SN 21. Capacitor 17 also has an electrostatic capacitance that substantially matches the total capacitance of FD 20 and the total capacitance of SN 21.

[0155] As described above, in the pixel circuit 1 of this variation, a PMOS transistor is used for the discharge transistor 15. Furthermore, the capacitor 16 is arranged in the SN 21, and the capacitor 17 is arranged in the FD 20. Even with this configuration, the saturation charge Qs can be increased, random noise can be reduced, and a wide dynamic range can be ensured for the pixel circuit 1, thereby improving image quality. Furthermore, robustness against manufacturing variations can be ensured, and the risk of characteristic variations can be reduced.

[0156] In this case, since it becomes difficult for the reset transistor 11, transfer transistor 14, and discharge transistor 15 to share a diffusion layer, layout efficiency is lower than that of the pixel circuit 1 according to the second embodiment. However, since no overflow path is formed adjacent to the FD 20, sunspot resistance is improved. In addition, since the amplifier transistor 12 and the select transistor 13 are NMOS transistors, the pixel circuit 1 according to this modification is compatible with peripheral circuits using NMOS transistors.

[0157] Modification 2 of the embodiment of the present disclosure

[0158] Figure 15 : is a circuit diagram of a pixel circuit according to a second variation of the embodiment of the present disclosure. Figure 15 As shown in FIG, the pixel circuit 1 according to the modification is different from the embodiment of the present disclosure in that the reset transistor 11 is an NMOS. Figure 15 Not shown Figure 3 Capacitors 18 and 19 are shown.

[0159] The reset transistor 11, the amplifying transistor 12, and the selecting transistor 13 are NMOS transistors, while the transfer transistor 14 and the discharging transistor 15 are PMOS transistors.

[0160] Furthermore, in this modification, SN 21 is provided with capacitor 16, which is a high-capacitance element. FD 20 is provided with capacitor 17, which is also a high-capacitance element. In this case, the total capacitance of SN 21 is determined to ensure the required saturation charge, and capacitor 16 has an electrostatic capacitance that is a predetermined value for the total capacitance of SN 21. Capacitor 17 also has an electrostatic capacitance that substantially matches the total capacitance of FD 20 and the total capacitance of SN 21.

[0161] As described above, in the pixel circuit 1 according to this variation, both the discharge transistor 15 and the transfer transistor 14 use PMOS transistors. Furthermore, capacitor 16 is arranged in the SN 21, and capacitor 17 is arranged in the FD 20. Even with this configuration, the saturation charge Qs can be increased, random noise can be reduced, and a wide dynamic range can be ensured for the pixel circuit 1, thereby improving image quality. Furthermore, robustness against manufacturing variations can be ensured, and the risk of characteristic variations can be reduced.

[0162] In this case, since it becomes difficult for the reset transistor 11, the transfer transistor 14, and the discharge transistor 15 to share the diffusion layer, the layout efficiency is lower than that of the pixel circuit 1 according to the second embodiment. However, since the amplification transistor 12 and the selection transistor 13 are NMOS, the pixel circuit 1 according to this modification is compatible with peripheral circuits using NMOS.

[0163] Modification 3 of the embodiment of the present disclosure

[0164] Figure 16 : is a circuit diagram of a pixel circuit according to a third variation of the embodiment of the present disclosure. Figure 16 As shown in FIG. 1 , the pixel circuit 1 according to this modification is different from the embodiment of the present disclosure in that the amplifying transistor 12 is a PMOS. Figure 16 Not shown Figure 3 Capacitors 18 and 19 are shown.

[0165] The selection transistor 13 is an NMOS transistor. On the other hand, the reset transistor 11, the amplification transistor 12, the transfer transistor 14, and the discharge transistor 15 are PMOS transistors.

[0166] Furthermore, in this modification, SN 21 is provided with capacitor 16, which is a high-capacitance element. FD 20 is provided with capacitor 17, which is also a high-capacitance element. In this case, the total capacitance of SN 21 is determined to ensure the required saturation charge, and capacitor 16 has an electrostatic capacitance that is a predetermined value for the total capacitance of SN 21. Capacitor 17 also has an electrostatic capacitance that substantially matches the total capacitance of FD 20 and the total capacitance of SN 21.

[0167] As described above, in the pixel circuit 1 according to this variation, PMOS transistors are used for the reset transistor 11, the amplifying transistor 12, the transfer transistor 14, and the discharge transistor 15. Furthermore, the capacitor 16 is arranged in the SN 21, and the capacitor 17 is arranged in the FD 20. Even with this configuration, the saturation charge Qs can be increased, random noise can be reduced, and a wide dynamic range can be ensured for the pixel circuit 1, thereby improving image quality. Furthermore, robustness against manufacturing variations can be ensured, and the risk of characteristic variations can be reduced.

[0168] In this case, since it becomes difficult to share a diffusion layer between the amplifier transistor 12 and the selection transistor 13, the layout efficiency is lower than that of the pixel circuit 1 according to the second embodiment. However, since the amplifier transistor 12 is a PMOS, a peripheral circuit is also required to cope with the configuration change using the PMOS.

[0169] Modification 4 of the embodiment of the present disclosure

[0170] Figure 17 : is a circuit diagram of a pixel circuit according to a fourth variation of the embodiment of the present disclosure. Figure 17 As shown in FIG, the pixel circuit 1 according to this modification is different from the embodiment of the present disclosure in that the amplifying transistor 12 and the selecting transistor 13 are PMOS transistors. Figure 17 Not shown Figure 3 Capacitors 18 and 19 are shown.

[0171] The reset transistor 11 , the amplifying transistor 12 , the selecting transistor 13 , the transferring transistor 14 , and the discharging transistor 15 are all PMOS.

[0172] Furthermore, in this modification, SN 21 is provided with capacitor 16, which is a high-capacitance element. FD 20 is provided with capacitor 17, which is also a high-capacitance element. In this case, the total capacitance of SN 21 is determined to ensure the required saturation charge, and capacitor 16 has an electrostatic capacitance that is a predetermined value for the total capacitance of SN 21. Capacitor 17 also has an electrostatic capacitance that substantially matches the total capacitance of FD 20 and the total capacitance of SN 21.

[0173] In this case, Figure 8 In the illustrated layout of the pixel circuit 1, the reset transistor 11, the amplifier transistor 12, the select transistor 13, the transfer transistor 14, the discharge transistor 15, and the capacitors 16 and 17 are arranged on the N-well. In this case, if the N-well tap 19 is provided, the P-well tap 18 can be omitted. As described above, in the pixel circuit 1 according to this variation, since only one N-well tap 19 is required, layout efficiency can be improved compared to the pixel circuits 1 according to the second embodiment and its variations 1 to 3.

[0174] As described above, in the pixel circuit 1 according to this variation, PMOS transistors are used for the reset transistor 11, the amplifier transistor 12, the select transistor 13, the transfer transistor 14, and the discharge transistor 15. Furthermore, capacitor 16 is arranged in the SN 21, and capacitor 17 is arranged in the FD 20. Even with this configuration, the saturation charge Qs can be increased, random noise can be reduced, and a wide dynamic range can be ensured for the pixel circuit 1, thereby improving image quality. Furthermore, robustness against manufacturing variations can be ensured, and the risk of characteristic variations can be reduced.

[0175] In the pixel circuit 1 according to this variation, since all MOS transistors are PMOS, they can be formed by arranging the source and drain electrodes on an N-well provided on a P-type diffusion layer. This simplifies the manufacturing process of the pixel circuit and reduces manufacturing costs.

[0176] In this case, since the reset transistor 11, the amplifier transistor 12, the selection transistor 13, the transfer transistor 14, and the discharge transistor 15 can share a diffusion layer, the layout efficiency is higher than that of the second embodiment. However, since the amplifier transistor 12 and the selection transistor 13 are PMOS transistors, peripheral circuits are also required to cope with the structural changes using PMOS transistors.

[0177] 2. Application Examples

[0178] Next, a configuration example to which the pixel circuit 1 described in each embodiment above can be applied will be described. Figure 18A is a diagram showing a planar configuration of a light receiving element. Figure 18B It shows that along Figure 18A For example, each pixel circuit 1 described in each embodiment and each modification example can be applied to Figure 18A and Figure 18B The light receiving element shown.

[0179] The light receiving element 501 is applied to, for example, an infrared sensor using a compound semiconductor material such as a III-V semiconductor, and has a photoelectric conversion function for light having a wavelength in, for example, the visible region (e.g., 380 nm to 780 nm) to the short infrared region (e.g., 780 nm to 2400 nm). Figure 18B As shown, the light receiving element 501 is provided with a plurality of light receiving unit regions P (pixels P) arranged two-dimensionally, for example.

[0180] The light receiving element 501 is applied to, for example, an infrared sensor using a compound semiconductor material such as a Group III-V semiconductor, and has a photoelectric conversion function for light having a wavelength in the visible region (e.g., 380 nm to 780 nm) to the short infrared region (e.g., 780 nm to 2400 nm). The light receiving element 501 is provided with, for example, a plurality of light receiving unit regions P (pixels P) arranged two-dimensionally.

[0181] like Figure 18A As shown, the light receiving element 501 has an element region R1 located at the center and a peripheral region R2 provided outside and surrounding the element region R1. The light receiving element 501 has a conductive film 515B extending from the element region R1 toward the peripheral region R2. The conductive film 515B has an opening in a region facing the center of the element region R1.

[0182] The light receiving element 501 has a laminated structure of an element substrate 510 and a readout circuit substrate 520. One surface of the element substrate 510 is a light incident surface (light incident surface S1), and the surface opposite to the light incident surface S1 (the other surface) is a bonding surface (bonding surface S2) with the readout circuit substrate 520.

[0183] The element substrate 510 includes, in order from the position closest to the readout circuit substrate 520, a wiring layer 510W, a first electrode 511, a semiconductor layer 510S (first semiconductor layer), a second electrode 515, and a passivation film 516. The surface and end surface (side surface) of the semiconductor layer 510S facing the wiring layer 510W are covered with an insulating film 517. The readout circuit substrate 520 is a so-called readout integrated circuit (ROIC), and includes a wiring layer 520W and a multilayer wiring layer 522C in contact with the bonding surface S2 of the element substrate 510, and a semiconductor substrate 521 facing the element substrate 510 via the wiring layer 520W and the multilayer wiring layer 522C.

[0184] The element substrate 510 has a semiconductor layer 510S in the element region R1. In other words, the area where the semiconductor layer 510S is provided is the element region R1 of the light receiving element 501. In the element region R1, the area exposed from the conductive film 515B (the area facing the opening of the conductive film 515B) is the light receiving area. In the element region R1, the area covered by the conductive film 515B is the optical black (OPB) area R1B. The OPB area R1B is provided in a manner surrounding the light receiving area. The OPB area R1B is used to obtain a black level pixel signal. The element substrate 510 has a buried layer 518 and an insulating film 517 in the peripheral region R2. The peripheral region R2 is provided with through holes H1 and H2, which penetrate the element substrate 510 and reach the readout circuit substrate 520. In the light receiving element 501, light enters the semiconductor layer 510S from the light incident surface S1 of the element substrate 510 through the passivation film 516, the second electrode 515 and the second contact layer 514. The signal charges photoelectrically converted in the semiconductor layer 510S move through the first electrode 511 and the wiring layer 510W, and are read out by the readout circuit substrate 520. The configuration of each portion will be described below.

[0185] The wiring layer 510W is provided so as to span the element region R1 and the peripheral region R2, and has a bonding surface S2 with the readout circuit substrate 520. In the light receiving element 501, the bonding surface S2 of the element substrate 510 is provided in both the element region R1 and the peripheral region R2, and the bonding surface S2 of the element region R1 and the bonding surface S2 of the peripheral region R2 form, for example, the same plane. As will be described below, in the light receiving element 501, the bonding surface S2 of the peripheral region R2 is formed by providing a buried layer 518.

[0186] Wiring layer 510W includes, for example, contact electrodes 519E and dummy electrodes 519ED in interlayer insulating films 519A and 519B. For example, interlayer insulating film 519B is disposed on the readout circuit substrate 520 side, while interlayer insulating film 519A is disposed on the first contact layer 512 side. These interlayer insulating films 519A and 519B are stacked. Interlayer insulating films 519A and 519B are made of, for example, an inorganic insulating material. Examples of such inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2). Interlayer insulating films 519A and 519B can be made of the same inorganic insulating material.

[0187] The contact electrode 519E is, for example, provided in the element region R1. The contact electrode 519E electrically connects the first electrode 511 and the readout circuit substrate 520, and the contact electrode 519E is provided for each pixel P in the element region R1. Adjacent contact electrodes 519E are electrically separated by the buried layer 518 and the interlayer insulating films 519A and 519B. The contact electrode 519E is formed, for example, by a copper (Cu) pad and is exposed on the joint surface S2. The dummy electrode 519ED is, for example, provided in the peripheral region R2. The dummy electrode 519ED is connected to the dummy electrode 522ED of the wiring layer 520W described below. By providing the dummy electrode 519ED and the dummy electrode 522ED, the strength of the peripheral region R2 can be improved. For example, the dummy electrode 519ED is formed using the same process as the contact electrode 519E. The dummy electrode 519ED is formed, for example, by a copper (Cu) pad and is exposed on the joint surface S2.

[0188] The first electrode 511, disposed between the contact electrode 519E and the semiconductor layer 510S, is an electrode (anode) that provides a voltage for reading out signal charges generated in the photoelectric conversion layer 513 (hereinafter, for convenience, it will be assumed that the signal charges are holes, and whether holes or electrons are described). This first electrode 511 is provided for each pixel P in the element region R1. The first electrode 511 is provided so as to fill the opening of the insulating film 517 and to contact the semiconductor layer 510S (more specifically, the diffusion region 512A described below). The first electrode 511 is, for example, larger than the opening of the insulating film 517, and a portion of the first electrode 511 is disposed in the buried layer 518. In other words, the upper surface of the first electrode 511 (the surface of the semiconductor layer 510S) is in contact with the diffusion region 512A, and a portion of the lower surface and side surfaces of the first electrode 511 are in contact with the buried layer 518. Adjacent first electrodes 511 are electrically separated by the insulating film 517 and the buried layer 518.

[0189] The first electrode 511 is made of, for example, any one of titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), and aluminum (Al), or an alloy containing at least one of these elements. The first electrode 511 can be a single-layer film made of these constituent materials, or can be a stacked film formed by combining two or more materials. For example, the first electrode 511 is composed of a stacked film of titanium and tungsten. The thickness of the first electrode 511 is, for example, tens to hundreds of nanometers.

[0190] The semiconductor layer 510S includes, for example, a first contact layer 512, a photoelectric conversion layer 513, and a second contact layer 514, from a position close to the wiring layer 510W. The first contact layer 512, the photoelectric conversion layer 513, and the second contact layer 514 have the same planar shape, and the end faces of these layers are arranged in the same position in a plan view.

[0191] For example, the first contact layer 512 is provided so as to be common to all pixels P and is arranged between the insulating film 517 and the photoelectric conversion layer 513. The first contact layer 512 electrically separates adjacent pixels P and is provided with, for example, a plurality of diffusion regions 512A. By using a compound semiconductor material having a larger band gap than the compound semiconductor material constituting the photoelectric conversion layer 513 for the first contact layer 512, dark current can be suppressed. For example, n-type InP (indium phosphide) can be used for the first contact layer 512.

[0192] The diffusion regions 512A provided in the first contact layer 512 are spaced apart from each other. The diffusion regions 512A are arranged for each pixel P, and the first electrode 511 is connected to each diffusion region 512A. The diffusion region 512A is also provided in the OPB region R1B. The diffusion region 512A reads out the signal charge generated in the photoelectric conversion layer 513 of each pixel P, and the diffusion region 512A contains, for example, p-type impurities. P-type impurities include, for example, Zn (zinc). Therefore, a pn junction interface is formed between the diffusion region 512A and the first contact layer 512 outside the diffusion region 512A, and adjacent pixels P are electrically separated from each other. The diffusion region 512A is provided, for example, in the thickness direction of the first contact layer 512, and is also provided on a portion of the thickness direction of the photoelectric conversion layer 513.

[0193] The photoelectric conversion layer 513 located between the first electrode 511 and the second electrode 515, more specifically, between the first contact layer 512 and the second contact layer 514, is, for example, set to be common to all pixels P. The photoelectric conversion layer 513 absorbs light of a predetermined wavelength and generates signal charges, and the photoelectric conversion layer 513 is made of, for example, a compound semiconductor material such as an i-type III-V semiconductor. The compound semiconductor materials constituting the photoelectric conversion layer 513 include, for example, indium gallium arsenide (InGaAs), indium arsenide antimony (InAsSb), indium arsenide (InAs), indium antimonide (InSb), and mercury cadmium damascene (HgCdTe). The photoelectric conversion layer 513 can be composed of germanium (Ge). In the photoelectric conversion layer 513, for example, light with a wavelength in the visible region to the short infrared region is photoelectrically converted.

[0194] For example, the second contact layer 514 is provided in common to all pixels P. The second contact layer 514 is provided between the photoelectric conversion layer 513 and the second electrode 515, and the second contact layer 514 contacts the photoelectric conversion layer and the second electrode. The second contact layer 514 is a region that transfers charges discharged from the second electrode 515, and the second contact layer 514 is made of, for example, a compound semiconductor containing n-type impurities. For example, n-type InP (indium phosphide) can be used for the second contact layer 514.

[0195] For example, the second electrode 515 is provided on the second contact layer 514 (light incident side) and contacts the second contact layer 514 as an electrode common to each pixel P. The second electrode 515 (cathode) discharges charges that are not used as signal charges for the charges generated in the photoelectric conversion layer 513. For example, when holes are read out from the first electrode 511 as signal charges, electrons can be discharged, for example, through the second electrode 515. The second electrode 515 is formed of a conductive film that can transmit incident light such as infrared light. For example, the second electrode 515 can use ITO (Indium Tin Oxide) or ITiO (In2O3-TiO2). For example, the second electrode 515 can be provided in a lattice shape to divide adjacent pixels P. The second electrode 515 can use a conductive material with low light transmittance.

[0196] The passivation film 516 covers the second electrode 515 from the light incident surface S1 side. The passivation film 516 may have an anti-reflection function. The passivation film 516 may be made of, for example, silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and tantalum oxide (Ta2O3). The passivation film 516 has an opening 516H in the OPB region R1B. Figure 18A As shown, the opening 516H is formed in a frame shape surrounding the light receiving area. In a plan view, the opening 516H may be, for example, a square or circular hole. The opening 516H of the passivation film 516 electrically connects the conductive film 515B to the second electrode 515.

[0197] The insulating film 517 is provided between the first contact layer 512 and the buried layer 518, covers the end surface of the first contact layer 512, the end surface of the photoelectric conversion layer 513, the end surface of the second contact layer 514, and the end surface of the second electrode 515, and is in contact with the passivation film 516 in the peripheral region R2. The insulating film 517 includes a material such as silicon oxide (SiO X ) or an oxide such as aluminum oxide (Al2O3). The insulating film 517 can be composed of a stacked structure composed of multiple films. For example, the insulating film 517 can be made of a silicon (Si)-based insulating material such as silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), silicon nitride (SiN), and silicon carbide (SiC). The thickness of the insulating film 517 is, for example, tens of nanometers to hundreds of nanometers.

[0198] The conductive film 515B is provided from the OPB region R1B to the through hole H1 of the peripheral region R2. The conductive film 515B contacts the second electrode 515 at the opening 516H of the passivation film 516 provided in the OPB region R1B, and contacts the wiring (wiring 522CB described below) of the readout circuit substrate 520 via the through hole H1. Therefore, a voltage is supplied from the readout circuit substrate 520 to the second electrode 515 through the conductive film 515B. The conductive film 515B serves as a voltage supply path to the second electrode 515, serves as a light shielding film, and forms the OPB region R1B. The conductive film 515B is made of, for example, a metal material containing tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), or copper (Cu). A passivation film may be provided on the conductive film 515B.

[0199] An adhesive layer B may be provided between the end of the second contact layer 514 and the second electrode 515. As will be described below, the adhesive layer B is used to form the light receiving element 501 and to bond the semiconductor layer 510S to the temporary substrate. The adhesive layer B is made of, for example, tetraethoxysilane (TEOS) or silicon oxide (SiO2). For example, the adhesive layer B is provided to be wider than the end face of the semiconductor layer 510S, and the adhesive layer B and the semiconductor layer 510S are covered by a buried layer 518. An insulating film 517 is provided between the adhesive layer B and the buried layer 518.

[0200] The buried layer 518 fills the step between the temporary substrate and the semiconductor layer 510S during the manufacturing process of the light receiving element 501. Although described in detail below, in this embodiment, the formation of the buried layer 518 can suppress the occurrence of defects during the manufacturing process caused by the step between the semiconductor layer 510S and the temporary substrate 533.

[0201] For example, the buried layer 518 in the peripheral region R2 is provided between the wiring layer 510W and the insulating film 517, and between the wiring layer 510W and the passivation film 516, and the thickness of the buried layer 518 is equal to or greater than the thickness of the semiconductor layer 510S. Here, since the buried layer 518 is provided so as to surround the semiconductor layer 510S, a region (peripheral region R2) surrounding the semiconductor layer 510S is formed. Therefore, the joint surface S2 with the readout circuit substrate 520 can be provided in the peripheral region R2. If the joint surface S2 is formed in the peripheral region R2, the thickness of the buried layer 518 may be reduced. However, preferably, the buried layer 518 covers the semiconductor layer 510S in the thickness direction, and the entire end surface of the semiconductor layer 510S is covered by the buried layer 518. Since the buried layer 518 covers the entire end surface of the semiconductor layer 510S via the insulating film 517, it can effectively reduce the infiltration of moisture into the semiconductor layer 510S. The buried layer 518 of the element region R1 is provided between the semiconductor layer 510S and the wiring layer 510W and covers the first electrode 511 .

[0202] The surface of the buried layer 518 on the bonding surface S2 side is flattened, and the wiring layer 510W is provided on the surface of the flattened buried layer 518 in the peripheral region R2. For example, the buried layer 518 may be made of a material such as silicon oxide (SiO X ), silicon nitride (SiN), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), and silicon carbide (SiC) and other inorganic insulating materials.

[0203] During the manufacturing process of the light receiving element 501, after forming the buried layer 518, a wiring layer 510W including interlayer insulating films 519A and 519B and a contact electrode 519E is formed above the buried layer 518. The readout circuit substrate 520 including the wiring layer 520W is stacked on the element substrate 510 including the wiring layer 510W to form the light receiving element 501. At this time, the contact electrode 519E of the wiring layer 510W is connected to the contact electrode 522E of the wiring layer 520W. The contact electrodes 519E and 522E have, for example, Cu pads and are connected to each other by direct bonding of the Cu pads. When the contact electrode 519E is formed by chemical mechanical polishing (CMP), the buried layer 518 arranged below the copper film to be polished must have a hardness that can withstand stress during the polishing process. In addition, in order to directly bond the Cu pads of the contact electrodes 519E and 522E to each other, the element substrate 510 and the readout circuit substrate 520 are required to be formed very flat. Therefore, the buried layer 518 arranged below the copper film preferably has a hardness that can withstand stress during the polishing process. Specifically, the material of the buried layer 518 is preferably a material with a hardness higher than that of the sealant material or the organic material arranged around the bare die in a typical semiconductor package. Materials with such high hardness include, for example, inorganic insulating materials. The buried layer 518 can be formed by depositing the inorganic insulating material, for example, by chemical vapor deposition (CVD), sputtering, or coating.

[0204] The buried layer 518 is provided with through holes H1 and H2 that pass through the buried layer 518. The through holes H1 and H2 pass through the wiring layer 510W together with the buried layer 518 and reach the readout circuit substrate 520. Figure 18A As shown, the through holes H1 and H2 have, for example, a rectangular planar shape, and a plurality of through holes H1 and H2 are provided to surround the element region R1. The through hole H1 is provided closer to the element region R1 than the through hole H2, and the sidewalls and bottom surface of the through hole H1 are covered with the conductive film 515B. The through hole H1 connects the second electrode 515 (conductive film 515B) to the wiring (wiring 522CB described below) of the readout circuit substrate 520, and the through hole H1 is provided to pass through the passivation film 516, the buried layer 518, and the wiring layer 510W.

[0205] For example, the through hole H2 is arranged at a position closer to the chip end E than the through hole H1. The through hole H2 passes through the passivation film 516, the buried layer 518 and the wiring layer 510W, and reaches the pad electrode (the pad electrode 522P described below) of the readout circuit substrate 520. The light receiving element 501 is electrically connected to the outside through the through hole H2. The through holes H1 and H2 may not reach the readout circuit substrate 520. For example, the through holes H1 and H2 may reach the wiring of the wiring layer 510W, and the wiring may be connected to the wiring 522CB and the pad electrode 522P of the readout circuit substrate 520. The through holes H1 and H2 may pass through the adhesive layer B.

[0206] The holes and electrons generated in the photoelectric conversion layer 513 are read out from the first electrode 511 and the second electrode 515. To perform the readout operation at high speed, the distance between the first electrode 511 and the second electrode 515 is preferably sufficient for photoelectric conversion, but not too far from each other. In other words, the thickness of the element substrate 510 is preferably reduced. For example, the distance between the first electrode 511 and the second electrode 515 or the thickness of the element substrate 510 is 10 μm or less, preferably 7 μm or less, and more preferably 5 μm or less.

[0207] The semiconductor substrate 521 of the readout circuit substrate 520 faces the element substrate 510 via the wiring layer 520W and the multilayer wiring layer 522C. The semiconductor substrate 521 is made of silicon (Si), for example. A plurality of transistors are provided near the surface of the semiconductor substrate 521 (the surface on the wiring layer 520W side). For example, a readout circuit (Read Out Circuit) is constructed for each pixel P using a plurality of transistors. As the readout circuit, the pixel circuit 1 described in each embodiment and each modification can be used. The wiring layer 520W has, for example, an interlayer insulating film 522A and an interlayer insulating film 522B in sequence from the element substrate 510 side, and the interlayer insulating films 522A and 522B are stacked. For example, a contact electrode 522E and a dummy electrode 522ED are provided in the interlayer insulating film 522A. The multilayer wiring layer 522C is provided so as to face the element substrate 510 via the wiring layer 520W. For example, a pad electrode 522P and a plurality of wirings 522CB are provided in the multilayer wiring layer 522C. The interlayer insulating films 522A and 522B are made of, for example, an inorganic insulating material. Examples of such inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2).

[0208] The contact electrode 522E electrically connects the first electrode 511 and the wiring 522CB and is provided for each pixel P in the element region R1. The contact electrode 522E contacts the contact electrode 519E on the bonding surface S2 of the element substrate 510. Adjacent contact electrodes 522E are electrically separated by an interlayer insulating film 522A.

[0209] The dummy electrode 522ED, disposed in the peripheral region R2, contacts the dummy electrode 519ED on the bonding surface S2 of the element substrate 510. For example, the dummy electrode 522ED is formed using the same process as the contact electrode 522E. The contact electrode 522E and the dummy electrode 522ED are formed, for example, from copper (Cu) pads and are exposed on the surface of the readout circuit substrate 520 facing the element substrate 510. In other words, for example, a CuCu bond is formed between the contact electrode 519E and the contact electrode 522E, and between the dummy electrode 519ED and the dummy electrode 522ED. This allows for miniaturization of the pixel P.

[0210] The wiring 522CB connected to the contact electrode 519E is connected to a transistor provided near the surface of the semiconductor substrate 521, and the first electrode 511 of each pixel P is connected to the readout circuit. For example, the wiring 522CB connected to the conductive film 515B via the through hole H1 is connected to a predetermined potential. Therefore, one charge (e.g., hole) generated in the photoelectric conversion layer 513 is read out from the first electrode 511 to the readout circuit via the contact electrodes 519E and 522E, while the other charge (e.g., electron) generated in the photoelectric conversion layer 513 is discharged from the second electrode 515 to a predetermined potential via the conductive film 515B.

[0211] The pad electrode 522P provided in the peripheral region R2 is electrically connected to the outside. A through hole H2 passing through the element substrate 510 and reaching the pad electrode 522P is provided near the chip end E of the light receiving element 501, and the light receiving element is electrically connected to the outside through the through hole H2. For example, the connection is made by methods such as wire bonding or bumps. For example, a predetermined potential can be provided from an external terminal arranged in the through hole H2 to the second electrode 515 through the through hole H2, the wiring 522CB of the readout circuit substrate 520, and the conductive film 515B. As a result of the photoelectric conversion in the photoelectric conversion layer 513, the signal voltage read out from the first electrode 511 can be read out to the readout circuit of the semiconductor substrate 521 through the contact electrodes 519E and 522E, and output to the external terminal arranged in the through hole H2 through the readout circuit. The signal voltage can be output to the external terminal, for example, through other circuits included in the readout circuit substrate 520 and the readout circuit. Other circuits are, for example, a signal processing circuit and an output circuit.

[0212] Preferably, the readout circuit substrate 520 is thicker than the element substrate 510. For example, the readout circuit substrate 520 is preferably more than 2 times, preferably more than 5 times, and more preferably more than 10 times thicker than the element substrate 510. Alternatively, the thickness of the readout circuit substrate 520 is, for example, more than 100 μm, more than 150 μm, or more than 200 μm. The readout circuit substrate 520 having such a large thickness ensures the mechanical strength of the light receiving element 501. Note that the readout circuit substrate 520 may include only a semiconductor substrate 521 for forming a circuit, or may include a substrate such as a support substrate in addition to the semiconductor substrate 521 for forming a circuit.

[0213] Figure 19 is a diagram showing a cross-sectional configuration of another light receiving element. For example, each pixel circuit 1 described in each embodiment and each modification can be applied to Figure 19 The light receiving element shown.

[0214] exist Figure 19 , each pixel 602 in the pixel array region is divided into a normal pixel 602A or a discharge pixel 602B according to the difference in reset transistor control. However, since the normal pixel 602A and the discharge pixel 602B have the same pixel structure, the pixel structure is simply described as pixel 602. Note that the discharge pixel 602B is arranged at the outermost side of the pixel array region.

[0215] A capacitor, a reset transistor, an amplifier transistor, and a readout circuit for a selection transistor in each pixel 602 are formed for each pixel on a semiconductor substrate 612 made of, for example, a single crystal material such as single crystal silicon (Si).

[0216] On the upper side of the semiconductor substrate 612 on which light is incident, an N-type semiconductor thin film 641 is formed over the entire surface of the pixel array area. The N-type semiconductor thin film 641 is made of a compound semiconductor having an InGaP, InAlP, InGaAs, InAlAs or chalcopyrite structure. A compound semiconductor having a chalcopyrite structure is a material capable of obtaining a high light absorption coefficient and high sensitivity over a wide wavelength range, and is preferably used for the N-type semiconductor thin film 641 for photoelectric conversion. This compound semiconductor having a chalcopyrite structure is composed of elements surrounding group IV elements such as Cu, Al, Ga, In, S and Se; examples of these elements include CuGaInS series mixed crystals, CuAlGaInS series mixed crystals and CuAlGaInSSe series mixed crystals. The pixel circuit 1 described in each embodiment and each modified example can be applied to a readout circuit arranged on the semiconductor substrate 612.

[0217] In addition to the above compound semiconductors, for example, amorphous silicon (Si), germanium (Ge), quantum dot photoelectric conversion films, and organic photoelectric conversion films can be used as the material of the N-type semiconductor film 641. Here, the N-type semiconductor film 641 can use an InGaAs compound semiconductor.

[0218] On the lower side of the N-type semiconductor thin film 641 on the semiconductor substrate 612 side, a high-concentration P-type layer 642 constituting a pixel electrode is formed for each pixel. Between the high-concentration P-type layers 642 formed for each pixel, an N-type layer 643 is formed of a compound semiconductor such as InP, for example, as a pixel separation region for separating each pixel 602. The N-type layer 643 serves not only as a pixel separation region but also as a dark current prevention region.

[0219] On the other hand, by using a compound semiconductor such as InP used as a pixel separation region, an N-type layer 644 having a higher concentration than that of the N-type semiconductor film 641 is further formed on the upper surface of the N-type semiconductor film 641 on the light incident side. The high-concentration N-type layer 644 serves as a blocking layer for preventing reverse flow of charges generated in the N-type semiconductor film 641. Compound semiconductors such as InGaAs, InP, or InAlAs can be used as the material of the high-concentration N-type layer 644.

[0220] An antireflection film 645 is formed on the high-concentration N-type layer 644 as a barrier layer. For example, the material of the antireflection film 645 can be silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or titanium oxide (TiO2).

[0221] Either the high-concentration N-type layer 644 or the anti-reflection film 645 serves as the upper electrode on the upper side of the electrodes that sandwich the N-type semiconductor film 641 in the vertical direction, and a predetermined voltage Va is applied to the high-concentration N-type layer 644 or the anti-reflection film 645 serving as the upper electrode.

[0222] A color filter 646 and an on-chip lens 647 are further formed on the anti-reflection film 645. The color filter 646 is a filter that transmits any one of red (R) light, green (G) light, and blue (B) light (wavelength light), and is arranged in the pixel array area in a so-called Bayer array, for example.

[0223] A passivation layer 651 and an insulating layer 652 are formed below the high-concentration P-type layer 642 constituting the pixel electrode and the N-type layer 643 serving as the pixel isolation region. Connecting electrodes 653A and 653B and a bump electrode 654 are formed to penetrate the passivation layer 651 and the insulating layer 652. The connecting electrodes 653A and 653B and the bump electrode 654 electrically connect the high-concentration P-type layer 642 constituting the pixel electrode to the capacitor 622 for accumulating charge.

[0224] The normal pixel 602A and the discharge pixel 602B are constructed as described above and have the same pixel structure. However, the control method of the reset transistor of the normal pixel 602A and the discharge pixel 602B is different.

[0225] In the normal pixel 602A, the reset transistor is turned on and off based on a reset signal according to, for example, the charge generation period (light reception period) of the photoelectric conversion unit and the reset period of the potential of the capacitor before the start of light reception. In the discharge pixel 602B, the reset transistor is always on. Therefore, the charge generated in the photoelectric conversion unit is discharged to the ground, and a constant voltage Va is always applied to the discharge pixel 602B.

[0226] 3. Application of mobile objects

[0227] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, or a robot.

[0228] Figure 20 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0229] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 20 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0230] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 controls: a drive force generating device, such as an internal combustion engine or a drive motor, for generating the vehicle's drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and control devices, such as a brake system, for generating the vehicle's braking force.

[0231] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In these cases, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from a portable device that replaces a key. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, and lights.

[0232] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection or distance detection processing on pedestrians, vehicles, obstacles, signs, or letters on the road surface.

[0233] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output this electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0234] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver has fallen asleep.

[0235] Based on the information outside and inside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for implementing advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, vehicle-to-vehicle distance-based tracking, vehicle speed maintenance, vehicle collision warning, or vehicle lane departure warning.

[0236] In addition, the microcomputer 12051 is also capable of controlling the driving force generating device, steering mechanism, braking device, etc. based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control for realizing automatic driving that enables the vehicle to drive autonomously without relying on the driver's operational control.

[0237] Based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 controls the headlights according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for glare prevention, such as switching the high beam to the low beam.

[0238] The sound and image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify information to passengers on the vehicle or outside the vehicle. Figure 20 In the example of FIG, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0239] Figure 21 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0240] exist Figure 21 , the vehicle 12100 has camera units 12101 , 12102 , 12103 , 12104 , and 12105 as the camera unit 12031 .

[0241] For example, camera units 12101, 12102, 12103, 12104, and 12105 are located at locations including the front nose, rearview mirrors, rear bumper, rear doors, and the upper portion of the windshield inside the vehicle 12100. Camera unit 12101 located at the front nose and camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located at the rearview mirrors primarily capture images from the sides of vehicle 12100. Camera unit 12104 located at the rear bumper or rear door primarily captures images from the rear of vehicle 12100. For example, the front images captured by camera units 12101 and 12105 are primarily used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0242] Notice, Figure 21 The figure shows examples of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, which are located on the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located on the rear bumper or rear door. For example, by superimposing the image data acquired by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 as viewed from above is obtained.

[0243] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0244] For example, microcomputer 12051 uses distance information obtained from imaging units 12101-12104 to determine the distance to each three-dimensional object within imaging ranges 12111-12114 and how this distance changes over time (relative speed to vehicle 12100). This allows it to identify the three-dimensional object closest to vehicle 12100 on its path and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., greater than or equal to 0 km / h) as the leading vehicle. Furthermore, microcomputer 12051 can pre-set the inter-vehicle distance to be maintained ahead of the leading vehicle and execute automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). This enables cooperative control aimed at autonomous driving, such as autonomous driving, independent of driver input.

[0245] For example, microcomputer 12051 can classify three-dimensional object data regarding three-dimensional objects based on distance information obtained from camera units 12101-12104, extracting three-dimensional objects such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, or utility poles, and use this extracted data to automatically avoid obstacles. For example, microcomputer 12051 can distinguish obstacles around vehicle 12100 into those visible to the driver of vehicle 12100 and those that are visually difficult to identify. Microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk equals or exceeds a set value, indicating a possible collision, microcomputer 12051 can output a warning to the driver via audio speaker 12061 or display unit 12062, or execute forced deceleration or evasive steering via drive system control unit 12010, thereby assisting driving to avoid a collision.

[0246] At least one of the imaging units 12101-12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether the pedestrian exists in the images captured by the imaging units 12101-12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which function as infrared cameras; and determining whether the pedestrian is a pedestrian by performing pattern matching on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline to emphasize the identified pedestrian. Furthermore, the audio and video output unit 12052 may control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0247] As described above, an example of a vehicle control system to which the technology of the present disclosure can be applied has been described. The technology of the present disclosure can be applied to the camera unit 12031 in the above-mentioned configuration. Specifically, Figure 3 and Figures 11 to 14 The pixel 120 of the pixel circuit 1 shown can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a wide dynamic range can be ensured, the risk of characteristic variation can be suppressed, and a more visible captured image can be obtained, thereby reducing driver fatigue.

[0248] 4. Application of endoscopic surgical system

[0249] The technology according to the present disclosure may also be applied to endoscopic surgical systems.

[0250] Figure 22 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0251] Figure 22 The figure shows a state where a surgeon (doctor) 11131 is performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy therapy tool 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices used for endoscopic surgery are installed.

[0252] Endoscope 11100 includes: a barrel 11101, a region of which has a predetermined length from a distal end thereof is inserted into a body cavity of a patient 11132; and a camera 11102 connected to a proximal end of barrel 11101. In the illustrated example, endoscope 11100 is configured as a so-called rigid endoscope having a rigid barrel 11101, but endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0253] An opening is provided at the distal end of the lens barrel 11101, and an objective lens is mounted in this opening. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the distal end of the lens barrel via a light guide extending within the lens barrel 11101. This light is then irradiated via the objective lens onto an observation target in the body cavity of the patient 11132. Note that the endoscope 11100 may correspond to a direct-viewing endoscope, a fluoroscopic endoscope, or a side-viewing endoscope.

[0254] The camera head 11102 includes an optical system and an imaging element. Light reflected from an observation target (observation light) is focused onto the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element, generating an electrical signal corresponding to the observation light—that is, an image signal corresponding to the observed image. This image signal is transmitted as raw data to the camera control unit (CCU) 11201.

[0255] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), and the like, and integrally controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera 11102 and performs various image processing such as development processing (demosaicing) on ​​the image signals for displaying an image based on the image signals.

[0256] Under the control of the CCU 11201 , the display device 11202 displays an image based on an image signal image-processed by the CCU 11201 .

[0257] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when imaging, for example, a surgical site.

[0258] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs an instruction for changing the imaging conditions of the endoscope 11100 (e.g., the type of irradiation light, magnification, and focal length).

[0259] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for purposes such as cauterization and cutting of tissue and sealing of blood vessels. The pneumoperitoneum device 11206 delivers gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of view of the endoscope 11100 and the surgeon's working space. The recorder 11207 is a device capable of recording various surgical information. The printer 11208 is a device capable of printing various surgical information in various formats, such as text, images, and charts.

[0260] Note that the light source device 11203 that provides irradiation light to the endoscope 11100 when imaging the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of an LED and a laser light source. When the white light source is composed of a combination of RGB laser light sources, the light source device 11203 can adjust the white balance of the captured image because the output intensity and output timing of each color (each wavelength) can be controlled with high precision. In this case, the object to be observed is irradiated with laser light from each of the RGB laser light sources in a time-division manner, and the drive of the imaging element of the camera 11102 is controlled in synchronization with the irradiation timing, so that images corresponding to R, G, and B, respectively, can be captured in a time-division manner. According to this method, a color image can be obtained even when a color filter is not provided in the imaging element.

[0261] Furthermore, the light source device 11203 can be controlled to change the output light intensity at predetermined time intervals. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the light intensity change, acquiring images in a time-division manner, and then synthesizing the images, it is possible to produce a high dynamic range image without so-called underexposure or overexposure.

[0262] Furthermore, the light source device 11203 can be configured to provide light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in human tissue and illuminating light in a narrower band than the band of illumination light used in ordinary observation (i.e., white light), so-called narrowband imaging is performed to image predetermined tissues, such as blood vessels in the surface layer of a mucosa, with high contrast. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by illuminating fluorescence generated by excitation light. In fluorescence observation, human tissue can be irradiated with excitation light and fluorescence from the tissue can be observed (autofluorescence observation), or an agent such as indocyanine green (ICG) can be locally injected into human tissue and the tissue can be irradiated with excitation light corresponding to the fluorescence wavelength of the agent to obtain a fluorescence image. The light source device 11203 can be configured to provide narrowband light and / or excitation light corresponding to such special light observation.

[0263] Figure 23 It shows Figure 22 A block diagram of an example of the functional configuration of the camera 11102 and CCU 11201 is shown.

[0264] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0265] The lens unit 11401 is an optical system provided at a portion connected to the lens barrel 11101. Observation light obtained from the distal end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 is constructed by combining a plurality of lenses (including a zoom lens and a focus lens).

[0266] The imaging unit 11402 includes an imaging element. The number of imaging elements included in the imaging unit 11402 can be one (a so-called single-board system) or multiple (a so-called multi-board system). For example, in the case where the imaging unit 11402 is composed of a multi-board system, image signals corresponding to R, G, and B, respectively, can be generated by each imaging element, and these signals can be combined to obtain a color image. Alternatively, the imaging unit 11402 can be configured to include a pair of imaging elements for respectively acquiring a right-eye image signal and a left-eye image signal corresponding to a three-dimensional (3D) display. When performing 3D display, the surgeon 11131 can more accurately grasp the depth of living tissue in the surgical site. When the imaging unit 11402 is configured as a multi-board system, a plurality of lens units 11401 can be provided corresponding to each imaging element.

[0267] In addition, the imaging unit 11402 does not have to be provided in the camera head 11102. For example, the imaging unit 11402 can be provided just behind the objective lens in the lens barrel 11101.

[0268] The drive unit 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0269] The communication unit 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits an image signal obtained from the imaging unit 11402 to the CCU 11201 through the transmission cable 11400 as raw data.

[0270] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0271] Note that the above-mentioned imaging conditions such as the frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 is equipped with a so-called automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function.

[0272] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0273] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0274] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication or optical communication.

[0275] The image processing unit 11412 performs various image processing on the image signal transmitted from the camera 11102 as raw data.

[0276] The control unit 11413 performs various controls related to imaging the surgical site, etc. through the endoscope 11100 and displaying the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0277] Furthermore, based on the image signal processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site, etc. In this case, the control unit 11413 can utilize various image recognition technologies to identify various objects in the captured image. For example, by detecting the shape and color of the edges of objects included in the captured image, the control unit 11413 can identify surgical tools such as forceps, specific living body parts, bleeding, and mist during the use of the energy therapy tool 11112. When the captured image is displayed on the display device 11202, the control unit 11413 can use the recognition results to overlay and display various surgical assistance information on the image of the surgical site. When this overlay and display of surgical assistance information is presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, allowing the surgeon 11131 to perform surgery more safely and reliably.

[0278] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electric signal cable corresponding to electric signal communication, an optical fiber corresponding to optical communication, or a composite cable corresponding to electric communication and optical communication.

[0279] Here, in the illustrated example, although communication is performed by wire using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed wirelessly.

[0280] As described above, an example of an endoscopic surgery system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the endoscope 11100 and the imaging unit 11402 of the camera 11102 in the above-mentioned structure. Specifically, Figure 3 and Figures 11 to 14 The pixel 120 of the illustrated pixel circuit 1 can be applied to the endoscope 11100 and the imaging unit 11402 of the camera 11102. By applying the technology according to the present disclosure to the endoscope 11100 and the imaging unit 11402 of the camera 11102, a wide dynamic range can be ensured, the risk of characteristic variations can be suppressed, and a clearer image of the surgical site can be obtained, allowing the surgeon to accurately confirm the surgical site.

[0281] Although an endoscopic surgical system is described here as an example, the technology according to the present disclosure can be applied to a microsurgery system, for example.

[0282] Although the embodiments of the present disclosure are described above, the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present disclosure. Components across different embodiments and variations can also be appropriately combined.

[0283] The effects described here are merely examples and are not limited thereto, and other effects may be provided.

[0284] Note that the present technology can also have the following configurations. (1)

[0286] A light detection device comprising:

[0287] a photoelectric conversion region configured to generate photoelectric charges;

[0288] a sensing node, wherein the sensing node is connected to the photoelectric conversion region, includes a first capacitive element, and holds the photoelectric charge generated by the photoelectric conversion region;

[0289] a floating diffusion configured to hold the photoelectric charges transferred from the sensing node;

[0290] a first transistor between the sensing node and the floating diffusion, wherein the first transistor is configured to selectively connect the sensing node to the floating diffusion to transfer photoelectric charges held in the sensing node to the floating diffusion; and

[0291] a second transistor between the floating diffusion and a signal line, wherein the second transistor is configured to selectively cause a pixel signal having a voltage value corresponding to a charge amount of photoelectric charges held in the floating diffusion to appear on the signal line. (2)

[0293] The light detection device according to (1), wherein a first capacitance of the sensing node is approximately equal to a second capacitance of the floating diffusion. (3)

[0295] The photodetection device according to (1) or (2), wherein the capacitance of the first capacitive element is 10 fF (femtofarad) or greater. (4)

[0297] The light detection device according to any one of (1) to (3), wherein the floating diffusion includes a second capacitive element. (5)

[0299] The light detection device according to (4), wherein the capacitance of the first capacitance element is smaller than the capacitance of the second capacitance element. (6)

[0301] The light detection device according to (4) or (5), wherein an occupied area of ​​the first capacitive element is smaller than an occupied area of ​​the second capacitive element. (7)

[0303] The light detection device according to any one of (4) to (6), wherein the first capacitance element is arranged near the first transistor, and the second capacitance element is arranged at a position other than a position where the first transistor, the second transistor, and the first capacitance element are provided. (8)

[0305] The light detection device according to any one of (4) to (7), wherein a shielding member for shielding the first capacitive element and the second capacitive element is arranged between the first capacitive element and the second capacitive element. (9)

[0307] A light detection device according to any one of (1) to (8), wherein the first capacitive element includes any one of a metal oxide semiconductor (MOS) capacitor, a capacitor having a metal insulator metal (MIM) structure in which an insulator is sandwiched between metals, and a capacitor having a three-dimensional MIM structure. (10)

[0309] A light detection device according to any one of (4) to (9), wherein the second capacitive element includes any one of a metal oxide semiconductor (MOS) capacitor, a capacitor having a metal insulator metal (MIM) structure in which an insulator is sandwiched between metals, and a capacitor having a three-dimensional MIM structure. (11)

[0311] The light detection device according to any one of (1) to (10), further comprising:

[0312] a third transistor disposed on a wiring connecting the floating diffusion and a constant-voltage power supply to discharge the photoelectric charge held by the floating diffusion to the constant-voltage power supply; and

[0313] A fourth transistor is arranged on a wiring connecting the second transistor and the signal line to switch the connection between the second transistor and the signal line. (12)

[0315] The light detection device according to any one of (1) to (11) further includes a fifth transistor arranged on a wiring connecting the sensing node and the constant-voltage power supply to discharge the photoelectric charge held by the sensing node to the constant-voltage power supply. (13)

[0317] A light detection device according to any one of (1) to (12), wherein the photoelectric conversion region includes any one of indium gallium arsenide (InGaAs), indium arsenide antimony (InAsSb), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots or organic compounds. (14)

[0319] The light detection device according to any one of (1) to (13), wherein the electrode connected to the photoelectric conversion region and the electrode connected to the sensing node are directly joined and electrically conductive. (15)

[0321] The light detection device according to any one of (1) to (14), wherein the terminal connected to the photoelectric conversion region and the terminal connected to the sensing node are connected and electrically conductive via a bump electrode. (16)

[0323] The light detection device according to (4), wherein at least a portion of the first capacitive element and at least a portion of the second capacitive element are formed by a first wiring layer. (17)

[0325] The light detection device according to (16), wherein the first wiring layer is provided between the photoelectric conversion region and the sensing node. (18)

[0327] The light detection device according to (16), wherein the first capacitive element and the second capacitive element are connected to a first voltage source. (19)

[0329] The light detection device according to any one of (1) to (15), wherein the photoelectric conversion region has a p-type impurity region connected to the sensing node. (20)

[0331] An electronic device comprising:

[0332] A pixel array, wherein a plurality of pixels are arranged in row and column directions;

[0333] a driving circuit configured to drive a pixel to be read out among the plurality of pixels; and

[0334] a processing circuit configured to read out pixel signals from pixels to be read out that are driven by the driving circuit,

[0335] Each of the plurality of pixels includes:

[0336] a photoelectric conversion region configured to generate photoelectric charges;

[0337] a sensing node including a first capacitive element and holding the photoelectric charge generated by the photoelectric conversion region;

[0338] a floating diffusion that includes a second capacitance element and holds the photoelectric charge transferred from the first charge holding unit;

[0339] a first transistor disposed between the sensing node and the floating diffusion, wherein the first transistor is configured to selectively transfer photoelectric charges held in the sensing node to the floating diffusion; and

[0340] a second transistor between the floating diffusion and the signal line, wherein the second transistor is configured to selectively cause a pixel signal having a voltage value corresponding to a charge amount of the photoelectric charges held in the second charge holding unit to appear on the signal line. (twenty one)

[0342] A solid-state imaging device comprising:

[0343] a photoelectric conversion unit configured to generate photoelectric charges;

[0344] a first charge holding unit including a first capacitance element and holding photoelectric charges generated by the photoelectric conversion unit;

[0345] a second charge holding unit configured to hold the photoelectric charges transferred from the first charge holding unit;

[0346] a first transistor arranged on a wiring connecting the first charge holding unit and the second charge holding unit to transfer the photoelectric charge held in the first charge holding unit to the second charge holding unit; and

[0347] A second transistor configured to cause a pixel signal of a voltage value corresponding to a charge amount of the photoelectric charge held in the second charge holding unit to appear on the signal line. (twenty two)

[0349] The solid-state image pickup device according to (21), wherein a first capacitance of the first charge holding unit is similar to a second capacitance of the second charge holding unit. (twenty three)

[0351] The solid-state imaging device according to (21) or (22), wherein the capacitance of the first capacitive element is 10 fF (femtofarad) or more. (twenty four)

[0353] The solid-state image pickup device according to any one of (21) to (23), wherein the second charge holding unit includes a second capacitive element. (25)

[0355] The solid-state imaging device according to (24), wherein the capacitance of the first capacitance element is smaller than the capacitance of the second capacitance element. (26)

[0357] The solid-state imaging device according to (24) or (25), wherein an occupied area of ​​the first capacitive element is smaller than an occupied area of ​​the second capacitive element. (27)

[0359] A solid-state imaging device according to any one of (24) to (26), wherein the first capacitor is arranged near the first transistor, and the second capacitor is arranged at a position other than a position where the first transistor, the second transistor, and the first capacitor are provided. (28)

[0361] The solid-state image pickup device according to any one of (24) to (27), wherein a shielding member for shielding the first capacitive element and the second capacitive element is arranged between the first capacitive element and the second capacitive element. (29)

[0363] A solid-state imaging device according to any one of (21) to (28), wherein the first capacitive element includes any one of a metal oxide semiconductor (MOS) capacitor, a capacitor having a metal insulator metal (MIM) structure in which an insulator is sandwiched between metals, and a capacitor having a three-dimensional MIM structure. (30)

[0365] A solid-state imaging device according to any one of (24) to (29), wherein the second capacitance element includes any one of a metal oxide semiconductor (MOS) capacitor, a capacitor having a metal insulator metal (MIM) structure in which an insulator is sandwiched between metals, and a capacitor having a three-dimensional MIM structure. (31)

[0367] The solid-state imaging device according to any one of (21) to (30), further comprising:

[0368] a third transistor arranged on a wiring connecting the second charge holding unit and a constant-voltage power supply to discharge the photoelectric charge held by the second charge holding unit to the constant-voltage power supply; and

[0369] A fourth transistor is arranged on a wiring connecting the second transistor and the signal line to switch the connection between the second transistor and the signal line. (32)

[0371] The solid-state imaging device according to any one of (21) to (31) further includes a fifth transistor, which is arranged on a wiring connecting the first charge holding unit and the constant-voltage power supply to discharge the photoelectric charge held by the first charge holding unit to the constant-voltage power supply. (33)

[0373] A solid-state imaging device according to any one of (21) to (32), wherein the photoelectric conversion unit includes any one of indium gallium arsenide (InGaAs), indium arsenide antimony (InAsSb), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots or organic compounds. (34)

[0375] The solid-state image pickup device according to any one of (21) to (33), wherein an electrode connected to the photoelectric conversion unit and an electrode connected to the first charge holding unit are directly joined and electrically conductive. (35)

[0377] The solid-state imaging device according to any one of (21) to (34), wherein a terminal connected to the photoelectric conversion unit and a terminal extending from the first charge holding unit are connected and electrically conductive via a bump electrode. (36)

[0379] The solid-state image pickup device according to any one of (21) to (32), wherein the photoelectric conversion unit has a p-type impurity region connected to the first charge holding unit. (37)

[0381] An electronic device comprising:

[0382] A pixel array unit, wherein a plurality of pixels are arranged in row and column directions;

[0383] a driving circuit configured to drive a pixel to be read out among the plurality of pixels;

[0384] a processing circuit configured to read out pixel signals from pixels to be read out that are driven by the drive circuit; and

[0385] a control unit configured to control the driving circuit and the processing circuit,

[0386] Each of the plurality of pixels includes:

[0387] a photoelectric conversion unit configured to generate photoelectric charges;

[0388] a first charge holding unit including a first capacitance element and holding photoelectric charges generated by the photoelectric conversion unit;

[0389] a second charge holding unit including a second capacitive element and holding the photoelectric charge transferred from the first charge holding unit;

[0390] a first transistor arranged on a wiring connecting the first charge holding unit and the second charge holding unit to transfer the photoelectric charge held in the first charge holding unit to the second charge holding unit; and

[0391] A second transistor configured to cause a pixel signal of a voltage value corresponding to a charge amount of the photoelectric charge held in the second charge holding unit to appear on the signal line.

[0392] [Reference Signs List]

[0393] 1 Pixel Circuit

[0394] 10 Photoelectric conversion film

[0395] 11 Reset transistor

[0396] 12 Amplifier transistor

[0397] 13 Select transistor

[0398] 14 Pass transistor

[0399] 15 Discharge transistor

[0400] 16,17 Capacitors

[0401] 100 electronic devices

[0402] 101 Imaging Lens

[0403] 102 Image Sensor

[0404] 103 processor

[0405] 104 storage units

[0406] 120 pixels

[0407] 121 pixel array unit

[0408] 122 vertical drive circuit

[0409] 123 column processing circuit

[0410] 124 horizontal drive circuit

[0411] 125 System Control Unit

[0412] 126 Signal Processing Unit

[0413] 127 data storage units.

Claims

1. A light detection device, comprising: a photoelectric conversion region configured to generate photoelectric charges; a sensing node, wherein the sensing node is connected to the photoelectric conversion region, the sensing node includes a first capacitive element, and holds the photoelectric charge generated by the photoelectric conversion region; a floating diffusion configured to hold the photoelectric charges transferred from the sensing node; a first transistor between the sensing node and the floating diffusion, wherein the first transistor is configured to selectively connect the sensing node to the floating diffusion to transfer photoelectric charges held in the sensing node to the floating diffusion; and a second transistor between the floating diffusion and a signal line, wherein the second transistor is configured to selectively cause a pixel signal having a voltage value corresponding to a charge amount of the photoelectric charge held in the floating diffusion to appear on the signal line.

2. The light detection device according to claim 1, wherein A first capacitance of the sensing node approximates a second capacitance of the floating diffusion.

3. The light detection device according to claim 1, wherein The capacitance of the first capacitive element is greater than or equal to 10 fF.

4. The light detection device according to claim 1, wherein The floating diffusion includes a second capacitive element.

5. The light detection device according to claim 4, wherein The capacitance of the first capacitive element is smaller than the capacitance of the second capacitive element. The light detection device according to claim 4 , wherein: An occupied area of ​​the first capacitive element is smaller than an occupied area of ​​the second capacitive element.

7. The light detection device according to claim 4, wherein The first capacitance element is arranged near the first transistor, and the second capacitance element is arranged at a position other than a position where the first transistor, the second transistor, and the first capacitance element are provided.

8. The light detection device according to claim 4, wherein A shielding member for shielding the first capacitive element and the second capacitive element is arranged between the first capacitive element and the second capacitive element.

9. The light detection device according to any one of claims 1 to 8, wherein: The first capacitance element includes any one of a metal oxide semiconductor (MOS) capacitor, a capacitor having a metal insulator metal (MIM) structure in which an insulator is sandwiched between metals, and a capacitor having a three-dimensional metal insulator metal (MIM) structure.

10. The light detection device according to claim 4, wherein The second capacitance element includes any one of a metal oxide semiconductor (MOS) capacitor, a capacitor having a metal insulator metal (MIM) structure in which an insulator is sandwiched between metals, and a capacitor having a three-dimensional metal insulator metal (MIM) structure.

11. The light detection device according to any one of claims 1 to 8, further comprising: a third transistor disposed on a wiring connecting the floating diffusion and a constant-voltage power supply to discharge the photoelectric charge held by the floating diffusion to the constant-voltage power supply; and A fourth transistor is arranged on a wiring connecting the second transistor and the signal line to switch the connection between the second transistor and the signal line. 12 . The light detection device according to claim 11 , further comprising a fifth transistor disposed on a wiring connecting the sensing node and the constant-voltage power supply to discharge the photoelectric charge held by the sensing node to the constant-voltage power supply.

13. The light detection device according to any one of claims 1 to 8, wherein The photoelectric conversion region includes any one of indium gallium arsenide (InGaAs), indium arsenide antimony (InAsSb), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots or organic compounds.

14. The light detection device according to any one of claims 1 to 8, wherein The electrode connected to the photoelectric conversion region and the electrode connected to the sensing node are directly joined and electrically conductive.

15. The light detection device according to any one of claims 1 to 8, wherein A terminal connected to the photoelectric conversion region and a terminal connected to the sensing node are connected through a bump electrode and are electrically conductive.

16. The light detection device according to claim 4, wherein At least a portion of the first capacitive element and at least a portion of the second capacitive element are formed by a first wiring layer.

17. The light detection device according to claim 16, wherein The first wiring layer is provided between the photoelectric conversion region and the sensing node.

18. The light detection device according to claim 16, wherein The first capacitive element and the second capacitive element are connected to a first voltage source.

19. The light detection device according to any one of claims 1 to 8, wherein The photoelectric conversion region has a p-type impurity region connected to the sensing node.

20. An electronic device comprising: A pixel array, wherein a plurality of pixels are arranged in row and column directions; a driving circuit configured to drive a pixel to be read out among the plurality of pixels; and a processing circuit configured to read out pixel signals from pixels to be read out that are driven by the driving circuit, Each of the plurality of pixels includes: a photoelectric conversion region configured to generate photoelectric charges; a sensing node including a first capacitive element and holding the photoelectric charge generated by the photoelectric conversion region; a floating diffusion that includes a second capacitance element and holds the photoelectric charge transferred from the first charge holding unit; a first transistor disposed between the sensing node and the floating diffusion, wherein the first transistor is configured to selectively transfer the photoelectric charge held in the sensing node to the floating diffusion; and a second transistor between the floating diffusion and the signal line, wherein the second transistor is configured to selectively cause a pixel signal having a voltage value corresponding to a charge amount of the photoelectric charges held in the second charge holding unit to appear on the signal line.

Images