Read operations using compressed memory

Abstract

The present application relates to a read operation using compressed memory. An apparatus may include a host system coupled to a non-volatile memory device and a volatile memory device. The host system may store a compressed copy of the data in the volatile memory device, for example, based on a score assigned to the data stored in the non-volatile memory device. The host system may recognize that the compressed copy of the data is stored in the volatile memory device and may transmit a read command including a logical address associated with a logical block address of the data stored in the non-volatile memory device to the volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 144,573 to Matturi et al., filed on January 8, 2021, entitled “READ OPERATION USING COMPRESSED MEMORY,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to a read operation using a compressed memory. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logic 1 or a logic 0. In some instances, a single memory cell can support more than two possible states, either of which can be stored. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] An apparatus is described. The apparatus may include: a host system coupled to a nonvolatile memory device and a volatile memory device; and a controller coupled to the host system and operable to cause the apparatus to: transmit a read command including a logical address associated with a logical block address (LBA) of data stored in the nonvolatile memory device to the volatile memory device; and receive, at the host system, from the volatile memory device a compressed copy of the data stored at the logical address of the volatile memory device.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit a read command from a host system to a volatile memory device coupled to the host system, the read command including a logical address associated with an LBA of data stored in the non-volatile memory device coupled to the host system; and receive, at the host system, from the volatile memory device a compressed copy of the data associated with the LBA stored in the volatile memory device.

[0008] A method performed by a host system is described. The method may include transmitting a read command to a volatile memory device coupled to the host system, the read command including a logical address associated with an LBA of data stored in a non-volatile memory device coupled to the host system; and receiving, from the volatile memory device, a compressed copy of the data associated with the LBA stored in the volatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 and 2 An example of a system supporting read operations using compressed memory according to examples as disclosed herein is described.

[0010] Figure 3 An example of a storage scheme supporting read operations using compressed memory according to examples as disclosed herein is described.

[0011] Figure 4 An example of a timing diagram is illustrated to support read operations using compressed memory according to examples as disclosed herein.

[0012] Figure 5 An example of a process flow is illustrated to support read operations using compressed memory according to examples as disclosed herein.

[0013] Figure 6 A block diagram is shown of a host system supporting read operations using compressed memory according to examples as disclosed herein.

[0014] Figure 7A flowchart illustrating one or more methods of supporting read operations using compressed memory according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0015] A memory system may include multiple types of memory devices for performing various functions. Each type of memory device may be associated with characteristics for performing the corresponding function. For example, a volatile memory device (e.g., a random access memory (RAM) device or another volatile memory device) may support fast access speeds and other characteristics, and a non-volatile memory device (e.g., a non-AND (NAND) memory device or another non-volatile memory device) may support large storage capacities that are maintained when power is removed and other characteristics. A host system may communicate with one or more volatile memory devices and one or more non-volatile memory devices, for example, to write data and read data. In some cases, the host system may store hot data (e.g., data that is likely to be accessed or frequently accessed) in a volatile memory device to achieve faster access speeds for the hot data. In some cases, retrieving information from a non-volatile memory device (e.g., a NAND device) may take longer than retrieving information from a volatile memory device (e.g., a DRAM device). However, in some cases, volatile memory devices may have reduced storage capacity compared to non-volatile memory devices, and the volatile memory devices may not have sufficient available memory to store hot data. Consequently, the host system may store hot data in the non-volatile memory devices, which may increase the latency associated with reading the hot data. Furthermore, increasing the storage capacity of the volatile memory devices may increase costs and use additional space. Therefore, it may be desirable to increase the amount of data that can be written to the volatile memory devices without increasing the storage capacity of the volatile memory devices.

[0016] Described herein are techniques, systems, and devices for accessing a volatile memory device to read a compressed copy of data also stored in a non-volatile memory device. For example, a volatile memory device may allocate a portion of the volatile memory device to store a compressed copy of data stored in the non-volatile memory device. In some cases, the allocated portion may be referred to as compressed RAM (cRAM). A host system coupled to the volatile memory device and the non-volatile memory device may determine that data stored in the non-volatile memory device is accessed relatively frequently (e.g., it is 'hot' data) and store a compressed copy of the data in the cRAM. For example, the host system may determine to store a compressed copy of the data, retrieve the data from the non-volatile memory device based on the determination, compress the data, and store the compressed copy in the cRAM. The host system may determine to read the data and may identify that the compressed copy of the data is stored in the cRAM. The host system may transmit a read command to the volatile memory device, the read command including a logical address associated with a logical block address (LBA) of the data stored in the non-volatile memory device. The host system can receive a compressed copy of the data from the volatile memory device and decompress the data. Thus, if the compressed copy of the data is stored in the volatile memory device, the host system can read the data from the volatile memory device instead of the non-volatile memory device. In this way, because the compressed data takes up less storage space than uncompressed data (e.g., 4 times less space, or some other smaller storage space), the host system can store additional data in the volatile memory device (e.g., because the data is also stored in the non-volatile memory device) without risking loss of information, which can result in increased access speeds associated with accessing the data and reduced power consumption at the host system.

[0017] First, in the reference Figure 1 and 2 The features of the present disclosure are described in the context of the described system. Figures 3 to 5 The features of the present disclosure are described in the background storage scheme, timing diagram and process flow. Figure 6 and 7 These and other features of the present disclosure are further illustrated and described with reference to the device diagrams and flow diagrams depicting read operations using compressed memory.

[0018] Figure 1 1 is an example of a system 100 that supports read operations using compressed memory according to examples as disclosed herein. The system 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0020] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0021] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and to read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0022] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more of these interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0023] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, where memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0024] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations, which can generally be referred to as access operations, at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. And in some cases, the memory system controller 115 can exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static RAM (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may serve as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when read from or written to the memory device 130 and may be available in the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0028] although Figure 1 The example of the memory system 110 in FIG. 1 has been described as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130, to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof in some cases. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive RAM (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, memory devices 130 may each include a local controller 135 (e.g., on the same die or within the same package) that may perform operations on one or more memory cells of memory devices 130. Local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) if configured to each store two bits of information, a triple-level cell (TLC) if configured to each store three bits of information, a quad-level cell (QLC) if configured to each store four bits of information, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., with respect to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity), but can be erased at a second level of granularity (e.g., at a block granularity). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0036] System 100 may include a memory device 131 that may be coupled (e.g., via a physical host interface, or some other interface) to a host system 105. In some examples, this coupling may include interfacing with a host system controller 106. In some examples, memory device 131 may include one or more memory arrays of volatile memory cells, such as RAM memory cells.

[0037] Host system 105 may use memory device 131 as a random access memory device, for example, to write data to and read data from memory device 131. Memory device 131 allocates a portion of memory device 131 as cRAM (e.g., to store a compressed copy of data stored in a non-volatile memory device). Host system 105 may store a compressed copy of data stored in memory device 130-a in the cRAM of memory device 131. For example, host system 105 may determine that a compressed copy of the data is stored and, based on this determination, may retrieve the data from memory device 130-a. Host system 105 may include a compression / decompression engine 107 (e.g., included in host system controller 106) that can compress data. Host system 105 may store the compressed copy in the cRAM. Additionally or alternatively, host system 105 may compress and write a copy of the data to the cRAM simultaneously with writing the data to memory device 130-a. Host system 105 may determine that the data is to be read and may recognize that the compressed copy of the data is stored in the cRAM. The host system 105 may transmit a read command to the memory device 131 that includes a logical address associated with the LBA of the data stored in the memory device 130-a. The host system 105 may receive a compressed copy of the data from the memory device 131 and decompress the data using the compression / decompression engine 107. This approach may result in increased access speeds associated with accessing the data, reduced power consumption, and may enable the host system 105 to store additional data in the memory device 131 (e.g., compared to storing uncompressed data in the memory device 131).

[0038] The system 100 may include any number of non-transitory computer-readable media that support read operations using compressed memory. For example, the host system 105, the memory system controller 115, or the memory device 130-a may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130-a. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130-a (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130-a to perform one or more associated functions as described herein.

[0039] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a MNAND system.

[0040] Figure 2 An example of a system 200 for supporting read operations using compressed memory according to an example disclosed herein is described. The system 200 may be as described in reference Figure 1 Examples of the described system 100 or aspects thereof. For example, the system 200 may include a controller 205, a memory device 210, and a memory device 215, which may be as described with reference to FIG. Figure 1 Examples of host system controller 106, memory device 131, and memory device 130 are depicted.

[0041] Controller 205 can be coupled to and communicate with memory device 210 and memory device 215 to perform operations, such as access operations. For example, controller 205 can be coupled to memory device 210 via conductive line 235-a and can be coupled to memory device 215 via conductive line 235-b. In some cases, controller 205 can be included in or coupled to a host device (not shown). Memory device 210 can be an example of a volatile memory device, and memory device 215 can be an example of a non-volatile memory device (e.g., a NAND device). In some examples, memory device 210 can be associated with faster access speeds relative to memory device 215, and memory device 215 can be associated with increased storage capacity relative to memory device 210.

[0042] In some cases, the controller 205 may store hot data (e.g., data that is likely to be accessed, data that is frequently accessed, or both) in the memory device 210 to achieve faster access speeds for the hot data. However, in some cases, the memory device 210 may not have enough available memory to store the hot data. For example, the memory device 210 may store multiple types of data that may be associated with various operations performed by the memory device 210, such as system data, application data, user data, cached data, and shared data, as well as other types of data. In some cases, because the memory device 210 stores such data to perform associated operations, the memory device 210 may not have available memory to store the hot data. The controller 205 may then store the hot data in the memory device 215, which may increase the latency associated with reading the hot data. For example, retrieving data from a non-volatile memory device may typically be slower than retrieving data from a volatile memory device. Therefore, retrieving hot data stored in the memory device 215 may increase latency relative to retrieving hot data stored in the memory device 210. Additionally, increasing the storage capacity of memory device 210 may increase costs and use additional space. Therefore, it may be desirable to increase the amount of data that can be written to memory device 210 without increasing the storage capacity of memory device 210.

[0043] To increase the amount of data that can be written to memory device 210 and to reduce the number of read operations on memory device 215, memory device 210 may allocate a portion of memory device 210 to store compressed data. For example, memory device 210 may allocate different portions of memory device 210 for different purposes. For example, memory device 210 may allocate portion 220 to store uncompressed data of any data type and may allocate portion 225 to store compressed copies of data stored in memory device 215. In some examples, memory device 210 may allocate portion 230 to store compressed data of a subset of data types (e.g., anonymous data, user data associated with a specific application, private user data); in some cases, portion 230 may be referred to as zRAM. In some examples, memory device 210 may allocate portions 220, 225, 230, or a combination thereof based on receiving an allocation command from controller 205.

[0044] To store a compressed copy of data stored in memory device 215 in portion 225, controller 205 may assign a score to the data stored in memory device 215. For example, the data stored in memory device 215 may be associated with an access frequency parameter. The access frequency parameter may indicate the likelihood that the data will be accessed, the frequency with which the data will be accessed, or both. Based on the access frequency parameter, controller 205 may assign a score to the data. The score may indicate whether the data is hot data. If the assigned score meets a threshold score (e.g., the data is hot data), controller 205 may determine to store a compressed copy of the data in memory device 210 (e.g., in portion 225). Controller 205 may retrieve the data from memory device 215 based on the score exceeding the threshold score, compress the data to generate a compressed copy of the data, and store the compressed copy of the data in portion 225. In some examples, controller 205 may generate a pointer to the compressed copy of the data based on storing the compressed copy of the data and store the pointer in controller 205. Controller 205 may then use the pointer to identify where memory device 210 stores the compressed copy of the data.

[0045] Additionally or alternatively, the controller 205 may store a compressed copy of the data in the portion 225 while simultaneously storing the data in the memory device 215. For example, the controller 205 may determine that data to be written to the memory device 215 is likely to be accessed by the controller 205 (e.g., video data, image data, or other data is likely to be accessed) and may compress and write a copy of the data (e.g., to the portion 225) while simultaneously writing the data to the memory device 215.

[0046] Controller 205 may read a compressed copy of data stored in memory device 210 instead of reading data in memory device 215. For example, controller 205 may determine to read data stored in memory device 215 and may identify (e.g., based on a pointer stored in controller 205) that memory device 210 stores a compressed copy of the data. Based on identifying that memory device 210 stores a compressed copy of the data, controller 205 may transmit a read command including a logical address associated with the data to memory device 210 instead of memory device 215. Controller 205 may receive a compressed copy of the data from a volatile memory device and may decompress the data to read the data. Thus, controller 205 may reduce the latency associated with reading the data.

[0047] In some examples, the controller 205 may determine to read the second data stored in the memory device 215, wherein the compressed copy of the second data is not stored in the memory device 210. Here, the controller 205 may recognize that the compressed copy of the second data is not stored in the memory device 210 and may transmit a read command to the memory device 215 to read the second data.

[0048] The controller 205 may update the score assigned to data stored in the memory device 215. In some examples, the controller 205 may update the score assigned to the data based on transmitting a read command to the memory device 210. For example, the controller 205 may increase the score assigned to the data in response to the controller 205 accessing a compressed copy of the data. In some other examples, the controller 205 may update the score assigned to the data based on not accessing the compressed copy of the data for a period of time. For example, if the controller 205 does not access the compressed copy of the data for a period of time, the controller 205 may periodically decrease the score assigned to the data. In some examples, the controller 205 may update an access frequency parameter associated with the data and may update the score assigned to the data based on the updated access frequency parameter.

[0049] Controller 205 may delete a compressed copy of data stored in memory device 210. For example, the score assigned to the data may be less than a threshold score (e.g., based on an update score). Controller 205 may determine that the data is no longer hot based on the score falling below the threshold score and may transmit a command to memory device 210 to delete the compressed copy of the data. In some examples, controller 205 may delete at least a portion of the compressed copy of the data by overwriting a portion of the compressed copy of the data. For example, controller 205 may identify second data stored in memory device 215 as hot data. Controller 205 may retrieve the second data from memory device 215, compress the second data to generate a compressed copy of the second data, and store the compressed copy of the second data in portion 225 by overwriting at least a portion of the compressed copy of the data with at least a portion of the compressed copy of the second data. Alternatively, controller 205 may transmit a write command including a second LBA to store the second data in memory device 215. Controller 205 may generate a compressed copy of the second data and may store the compressed copy of the second data in portion 225 while writing the second data to memory device 210 by overwriting at least a portion of the compressed copy of the data with at least a portion of the compressed copy of the second data.

[0050] In some examples, memory device 210 may reallocate portions 220, 225, and 230. For example, memory device 210 may determine a threshold amount of memory usage for portion 220. Memory device 210 may reallocate portion 225, at least a portion of portion 230, or a combination thereof to portion 220. Here, a fraction of the data may satisfy the threshold fraction for storing a compressed copy of the data in portion 225; however, memory device 210 may delete the compressed copy of the data and reallocate a portion of portion 225 to portion 220 based on determining the threshold amount of memory usage for portion 220. In some examples, memory device 210 may reallocate portion 220, at least a portion of portion 230, or a combination thereof to portion 225. For example, rather than deleting, reclaiming, or overwriting a compressed copy of the data stored in portion 225 to store the additional compressed copy of the data, memory device 210 may reallocate portion 220, at least a portion of portion 230, or a combination thereof to portion 225 to store the additional compressed copy of the data. In some cases, memory device 210 may reallocate portion 220, 225, or 230 based on receiving a reallocate command from controller 205. For example, controller 205 may determine a threshold amount of memory used for portion 220 and transmit a reallocate command to memory device 210. In some examples, memory device 210 may reallocate portions 220, 225, and 230 based on one or more operations performed by memory device 210. For example, memory device 210 may reallocate at least a portion of portions 220, 225, 230, or a combination thereof, to increase the respective allocation of portion 220 or 225 in order to perform one or more operations (e.g., an access operation, a cache operation, a flush operation, or some other operation).

[0051] In some examples, the controller 205 may store a compressed copy of the data in the memory device 215. For example, the controller 205 may determine to delete the compressed copy of the data stored in the memory device 210 (e.g., based on the score being less than a threshold score, based on reallocating a portion of the portion 225 storing the compressed copy of the data) and may reclaim the compressed copy of the data. The controller 205 may store the reclaimed compressed copy of the data in the memory device 215, for example, to occupy less memory in the memory device 215. In some cases, the controller 205 may delete the data stored in the memory device 215 after or concurrently with storing the compressed copy of the data in the memory device 215. The controller 205 may subsequently retrieve the compressed copy of the data from the memory device 215. For example, the controller 205 may transmit a read command including a logical address associated with the LBA of the data to the memory device 215 and may receive the compressed copy of the data from the memory device 215.

[0052] Figure 3An example of a storage scheme 300 that supports read operations using compressed memory according to examples disclosed herein is illustrated. The storage scheme 300 can implement aspects of the system 100. For example, the storage scheme 300 can be implemented by a memory device 305, which can be a memory device 305, respectively. Figure 1 and 2 3. Examples of memory device 131 or memory device 210 are described. Storage scheme 300 can be implemented to reduce latency and power consumption of a system including memory device 305 and a host device, among other benefits.

[0053] Memory device 305 may include multiple memory arrays of volatile memory cells (e.g., RAM memory cells). In some examples, memory device 305 may organize RAM memory cells into pages, which may be associated with a specific amount of memory (e.g., 4 kilobytes (KB) of memory, or some other amount of memory). Pages may be associated with a page type. For example, a page may be considered a used page 340, a cached page 345, a free page 350, or a compressed page 355 based on the type of data stored in the page. Used pages 340 may include data actively used by memory device 305. Cached pages 345 may serve as a cache for a host device coupled to memory device 305 or for memory device 305. Free pages 350 may be used to store data (e.g., data that may not currently be stored). Compressed pages 355 may store compressed copies of data stored in a non-volatile memory device. In some cases, compressed pages 355 may be reserved to store hot data 360 (e.g., data that is likely to be accessed by a host device, data that is frequently accessed by a host device).

[0054] Memory device 305 may organize or allocate groups of pages into blocks of memory. Memory device 305 may use different blocks of memory for different purposes. For example, memory device 305 may allocate blocks of system memory 310, application 1 (App1) memory 315, shared memory 320, application 2 (App2) memory 325, free memory 330, and compressed memory 335. In some examples, App1 memory block 315 may include used pages 340 or cached pages 345, or both, of data associated with a first application; App2 memory block 315 may include pages associated with used pages 340 or cached pages 345, or both, of data associated with a second application; and shared memory block 320 may include cached pages 345 of shared data between the first and second applications. Free memory block 330 may include one or more free pages 350, and compressed memory block 335 may include one or more compressed pages 355. Memory device 305 may allocate any number of pages to each block of memory.

[0055] Memory device 305 may compress the data stored in cached page 345 and store the compressed data in compressed page 355 of compressed memory block 335. For example, memory device 305 may determine that cached page 345 of App1 memory block 315 stores hot data. Memory device 305 may compress the hot data stored in cached page 345 and store the hot data in compressed page 355. In some examples, the data stored in cached page 345 may also be stored in a non-volatile memory device. Therefore, memory device 305 may store the compressed data in compressed page 355 without risk of losing information.

[0056] Figure 4 An example of a timing diagram 405 is shown for supporting read operations using compressed memory according to examples as disclosed herein. The timing diagram 405 shows the timing diagram 405 of FIG. Figure 1 and 2 Various memory usage scenarios associated with components of the described system 100 or system 200. For example, timing diagram 405-a depicts example memory usage over time for a non-volatile memory device (e.g., a UFS device) and a volatile memory device without cRAM allocation. Timing diagram 405-b depicts example memory usage over time for a non-volatile memory device and a volatile memory device with cRAM allocation.

[0057] Timing diagram 405-a may correspond to memory usage of a memory device when recording and subsequently accessing video without using cRAM. For example, timing diagram 405-a illustrates free DRAM 410-a (e.g., available DRAM) and DRAM 415-a used as cache when recording and subsequently accessing video without using cRAM. Additionally, timing diagram 405-a illustrates the amount of data fetched (e.g., read) from the UFS device (e.g., UFS fetches 420-a) and the amount of data written to the UFS device (e.g., UFS writes 425-a) when recording and subsequently accessing video without using cRAM.

[0058] At time t1, video recording may begin. Between times t1 and t3, the host device may write video data to the UFS device according to UFS write 425-a. Additionally, at time t1, the host device may begin caching video data in DRAM according to DRAM 415-a used as cache. Consequently, the free DRAM of the volatile memory device may decrease according to free DRAM 410-a. The host device may extract data from the UFS device according to UFS extract 420-a. In some cases, the host device extracting data from the UFS device before time t3 may be associated with an access operation not associated with video data.

[0059] At time t2, the volatile memory device may consume DRAM available for caching video data, and DRAM 415-a used as cache may begin to flatten (i.e., the host device may stop caching video data). In some cases, the volatile memory device may begin to flush (e.g., delete) cached video data at time t2. At time t3, video recording may end, and the host device may access the recorded video. Because DRAM is not available to cache all video data, the host device may extract the video data from the UFS device as shown in UFS extraction 420-a. In some cases, the volatile memory device may cache the extracted video data to create a video file (e.g., including video data, video title, thumbnail, or any other video file information). Therefore, cached DRAM may increase at time t3 based on DRAM 415-a used as cache, and free DRAM may decrease at time t3 based on free DRAM 410-a. In some cases, fetching video data from the UFS device and caching the video data at time t3 may increase latency and increase power consumption of a system including the host device, volatile memory device, and the UFS device (eg, due to fetching and caching the video data).

[0060] Timing diagram 405-b may correspond to memory usage of a memory device when recording and subsequently accessing video using cRAM. For example, timing diagram 405-b illustrates free DRAM 410-b (e.g., available DRAM), DRAM 415-b used as cache, and cRAM 430 used when recording and subsequently accessing video without using cRAM. In addition, timing diagram 405-b illustrates the amount of data fetched (e.g., read) from the UFS device (e.g., UFS fetches 420-b) and the amount of data written to the UFS device (e.g., UFS writes 425-b) when recording and subsequently accessing video without using cRAM.

[0061] At time t4, video recording may begin. Between times t4 and t5, the host device may write video data to the UFS device according to UFS write 425-a. Additionally, the host device may compress the video data and write the compressed video data to the cRAM of the volatile memory device according to used cRAM 430. Because the host device writes the compressed data to the cRAM, the host device may reduce the amount of DRAM used as a cache for the video data, as shown in DRAM used as a cache 415-b. Additionally, because compressed video data takes up less space than uncompressed video data, the amount of free DRAM may increase, as shown in free DRAM 410-b. Between times t4 and t5, the host device may extract data from the UFS device according to UFS extract 420-b.

[0062] At time t5, video recording may end, and the host device may access the recorded video. The host device may determine that the compressed video data is stored in cRAM and may retrieve the compressed video data from cRAM. In this way, the host device can avoid fetching video data from the UFS device and caching the fetched video data in DRAM. This approach can reduce system latency and power consumption.

[0063] Figure 5 An example of a process flow 500 for supporting read operations using compressed memory according to examples disclosed herein is illustrated. Aspects of the process flow 500 may be implemented by components of a system, such as those described with reference to Figure 1 and 2 For example, the process flow 500 may be implemented by a controller 505, a volatile memory device 510, and a non-volatile memory device 515, which may be as described with reference to FIG. Figure 1 and 2 5. The process flow 500 is described as an example of a host system controller 106 or controller 205, memory devices 131, 210, and memory devices 130, 215. Process flow 500 can be implemented to reduce latency and power consumption and improve system performance, among other benefits. Aspects of process flow 500 can be implemented by a controller as well as other components. Additionally or alternatively, aspects of process flow 500 can be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to volatile memory device 510 and non-volatile memory device 515). For example, the instructions, when executed by a controller (e.g., controller 205), can cause the controller to perform the operations of process flow 500.

[0064] In the following description of process flow 500, operations may be performed in a different order or at a different time. Some operations may also be omitted from process flow 500, and other operations may be added to process flow 500.

[0065] At 520, compressed memory can be allocated at the volatile memory device 510. For example, the volatile memory device 510 can allocate a portion of the volatile memory device 510 for cRAM (e.g., to store a compressed copy of data stored in the non-volatile memory device 515). In some cases, the volatile memory device 510 can allocate the portion based on a command from the controller 505 instructing the volatile memory device 510 to allocate the portion.

[0066] At 525, a score may be assigned to the data stored in the non-volatile memory device 515. For example, the controller 505 may assign a score to the data stored in the non-volatile memory device 515 based on an access frequency parameter associated with the data. The access frequency parameter may indicate the likelihood that the data will be accessed or the frequency with which the data will be accessed, or both. An access frequency parameter indicating frequently accessed data or data that is likely to be accessed may correspond to a higher score assigned to the data. For example, an access frequency parameter associated with video data of a recently recorded video may indicate that video data is likely to be accessed. Therefore, the controller 505 may assign a relatively higher score to the video data. Conversely, an access frequency parameter indicating infrequently accessed data or data that is relatively unlikely to be accessed may correspond to a lower score assigned to the data.

[0067] At 530, data can be received from the non-volatile memory device 515. For example, if the score satisfies (e.g., is greater than) a threshold score, the controller 505 can determine that the data is hot data. The controller 505 can retrieve the data from the non-volatile memory device 515 based on the data being hot data (e.g., by transmitting a read command to the non-volatile memory device 515 associated with the data).

[0068] At 535 , the data can be compressed. For example, the controller 505 can compress the retrieved data to produce a compressed copy of the data that is stored in the non-volatile memory device 515 .

[0069] At 540, the compressed copy of the data may be transferred to the volatile memory device 510. For example, the controller 505 may transfer the compressed copy of the data to the volatile memory device 510 to store the compressed copy of the data in the volatile memory device 510 (e.g., in cRAM). In some examples, the controller 505 may generate a pointer to the compressed copy of the data and may store the pointer at the controller 505.

[0070] At 545, the compressed copy of the data may be identified as being stored in the volatile memory device 510. For example, the controller 505 may determine to read data stored in the non-volatile memory device 515. Before transmitting a read command to read the data from the non-volatile memory device 515, the controller 505 may identify that the compressed copy of the data is stored in the volatile memory device 510, for example, based on a stored pointer to the compressed copy of the data.

[0071] At 550, a read command may be sent to the volatile memory device 510. For example, the controller 505 may determine to read a compressed copy of the data stored in the volatile memory device 510 rather than reading the data stored in the non-volatile memory device 515. Based on the determination to read the compressed copy of the data, the controller 505 may transmit a read command to the volatile memory device 510 that includes a logical address associated with the LBA of the data stored in the non-volatile memory device 515.

[0072] At 555, the compressed copy of the data may be transferred from the volatile memory device 510 to the controller 505. For example, the volatile memory device 510 may transfer the compressed copy of the data stored at the logical address to the controller 505 in response to receiving a read command.

[0073] The compressed copy of the data can be decompressed at 560. For example, the controller 505 can receive the compressed copy of the data and can decompress the compressed copy of the data.

[0074] At 565, the score assigned to the data may be updated. For example, based on accessing the compressed copy of the data, the controller 505 may update (e.g., increase) the score assigned to the data. In some cases, if the controller 505 does not access the compressed copy of the data for a period of time, the controller 505 may periodically decrease the score assigned to the data.

[0075] At 570, a delete command associated with the compressed copy of the data may be transmitted to the volatile memory device 510. For example, the controller 505 may determine that the data is no longer hot data and may transmit a delete command to delete the compressed copy of the data from the volatile memory device 510. In some examples, the controller 505 may delete the compressed copy of the data if the score assigned to the data drops below a threshold score.

[0076] At 575, the compressed copy of the data may optionally be transferred to the non-volatile memory device 515. For example, the controller 505 may retract the compressed copy of the data from the volatile memory device 510 based on the score assigned to the data falling below a threshold score. The controller 505 may store the compressed copy of the data in the non-volatile memory device 515, e.g., to occupy less memory of the non-volatile memory device 515. In some cases, the controller 505 may delete the data stored in the non-volatile memory device 515 after storing the compressed copy of the data.

[0077] At 580, the compressed copy of the data may be identified as not being stored in the volatile memory device 510. For example, the controller 505 may determine to read the data stored in the non-volatile memory device 515. Based on deleting the compressed copy of the data, the controller 505 may identify that the compressed copy of the data is not being stored in the volatile memory device 510.

[0078] At 585, a read command associated with the data may be transmitted to the non-volatile memory device 515. For example, based on identifying that a compressed copy of the data is not stored in the volatile memory device 510, the controller 505 may transmit a read command to the non-volatile memory device 515 that includes a logical address associated with an LBA of the data stored in the non-volatile memory device 515.

[0079] At 590, data may be received from the nonvolatile memory device 515. For example, the nonvolatile memory device 515 may transmit the data to the controller 505 based on receiving the read command. In some cases, if the stored data is a compressed copy of the data, the nonvolatile memory device 515 may transmit the compressed copy of the data.

[0080] At 595, at least a portion of the compressed memory of the volatile memory device 510 may be optionally reallocated. For example, the volatile memory device 510 may determine a threshold amount of memory usage of the second portion of the volatile memory device 510 for storing uncompressed data. Accordingly, the volatile memory device 510 may reallocate at least a portion of the portion of the volatile memory device to the second portion. Because the portion of the volatile memory device 510 stores a compressed copy of the data stored in the non-volatile memory device 515, the volatile memory device 510 may reallocate the portion without transferring any data stored in the portion to the non-volatile memory device 515.

[0081] Figure 6 A block diagram 600 is shown of a host system 620 that supports read operations using compressed memory according to examples as disclosed herein. The host system 620 may be a host system 620 such as that described in reference Figures 1 to 5 6. The host system 620 or its various components may be examples of means for performing various aspects of read operations using compressed memory as described herein. For example, the host system 620 may include a command component 630, a communication component 635, a compression engine 640, a score manager 645, a storage manager 650, a memory manager 655, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0082] The command component 630 can be configured to or otherwise support means for transmitting a read command to a volatile memory device coupled to a host system, the read command including a logical address associated with an LBA of data stored in a non-volatile memory device coupled to the host system. The communication component 635 can be configured to or otherwise support means for receiving, from the volatile memory device, a compressed copy of the data associated with the LBA stored in the volatile memory device.

[0083] In some examples, compression engine 640 may be configured to or otherwise support means for decompressing a compressed copy of data stored in a volatile memory device based at least in part on receiving the compressed copy of the data stored in the volatile memory device.

[0084] In some examples, command component 630 may be configured to or otherwise support means for identifying that a compressed copy of the data is stored in the volatile memory device, wherein transmitting the read command to the volatile memory device is based at least in part on identifying that the compressed copy of the data is stored in the volatile memory device.

[0085] In some examples, score manager 645 can be configured to or otherwise support means for assigning a score to data based at least in part on an access frequency parameter associated with the data. In some examples, storage manager 650 can be configured to or otherwise support means for storing a compressed copy of the data in a volatile memory device based at least in part on the score satisfying a threshold score, wherein identifying that the compressed copy of the data is to be stored in the volatile memory device is based at least in part on storing the compressed copy of the data.

[0086] In some examples, command component 630 can be configured to or otherwise support means for retrieving data from a non-volatile memory device based at least in part on the score exceeding a threshold score. In some examples, compression engine 640 can be configured to or otherwise support means for compressing the data to produce a compressed copy of the data based at least in part on the retrieved data, wherein storing the compressed copy of the data is based at least in part on the compressed data.

[0087] In some examples, the access frequency parameter includes an indication of the likelihood of accessing the data, the frequency of accessing the data, or a combination thereof.

[0088] In some examples, the score manager 645 can be configured to or otherwise support means for identifying a score associated with data stored in a non-volatile memory device based at least in part on an access frequency parameter associated with the data. In some examples, the storage manager 650 can be configured to or otherwise support means for deleting compressed copies of data stored in a volatile memory device based at least in part on the score being less than a threshold score.

[0089] In some examples, the command component 630 can be configured to or otherwise support means for transmitting, from the host system, a write command including the second LBA to store the second data in the non-volatile memory device. In some examples, the storage manager 650 can be configured to or otherwise support means for storing the compressed copy of the second data in the volatile memory device by overwriting at least a portion of the compressed copy of the data with at least a portion of the compressed copy of the second data based at least in part on transmitting the write command.

[0090] In some examples, score manager 645 may be configured to or otherwise support means for updating a score associated with data based at least in part on receiving a read command.

[0091] In some examples, the memory manager 655 may be configured to or otherwise support means for allocating a portion of a volatile memory device to store a compressed copy of data stored in a non-volatile memory device, the portion of the volatile memory device being configured to provide low-latency access to the compressed copy of the data, wherein receiving the compressed copy of the data stored in the volatile memory device is based at least in part on allocating the portion.

[0092] In some examples, the memory manager 655 may be configured to or otherwise support means for determining a threshold amount of memory usage of the second portion of the volatile memory device for storing uncompressed data. In some examples, the memory manager 655 may be configured to or otherwise support means for reallocating at least a portion of the portion of the volatile memory device to the second portion based at least in part on determining the threshold amount of memory usage.

[0093] In some examples, the command component 630 can be configured to or otherwise support means for identifying that the compressed copy of the second data stored in the non-volatile memory device is not stored in the volatile memory device. In some examples, the command component 630 can be configured to or otherwise support means for transmitting a second read command to the non-volatile memory device, the second read command including a second logical address associated with a second LBA of the second data. In some examples, the communication component 635 can be configured to or otherwise support means for receiving the second data from the non-volatile memory device based at least in part on transmitting the second read command to the non-volatile memory device.

[0094] In some examples, the storage manager 650 may be configured to or otherwise support means for retrieving a compressed copy of data from a volatile memory device based at least in part on a score associated with the data stored in the non-volatile memory device being less than a threshold score. In some examples, the storage manager 650 may be configured to or otherwise support means for storing a compressed copy of the data in a non-volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device.

[0095] In some examples, the command component 630 can be configured to or otherwise support means for identifying that a compressed copy of the data is not stored in the volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device. In some examples, the command component 630 can be configured to or otherwise support means for transmitting a second read command to the non-volatile memory device, the second read command including a logical address associated with an LBA of the data stored in the non-volatile memory device. In some examples, the communication component 635 can be configured to or otherwise support means for receiving a compressed copy of the data stored in the non-volatile memory device based at least in part on storing the compressed copy of the data in the non-volatile memory device.

[0096] In some examples, to support volatile memory devices, the memory manager 655 may be configured or otherwise support components of a first portion of RAM cells configured to store uncompressed data of any data type. In some examples, to support volatile memory devices, the memory manager 655 may be configured or otherwise support components of a second portion of RAM cells configured to store compressed data of a first type of data. In some examples, to support volatile memory devices, the memory manager 655 may be configured or otherwise support components of a third portion of RAM cells configured to store a compressed copy of host data stored by a non-volatile memory device, wherein the compressed copy of the data is stored in the third portion.

[0097] In some examples, the non-volatile memory devices include NAND memory cells and the volatile memory devices include RAM cells.

[0098] Figure 7 A flowchart illustrating a method 700 for supporting read operations using compressed memory according to examples as disclosed herein is shown. The operations of the method 700 may be performed by a host system or components thereof as described herein. For example, the operations of the method 700 may be performed by a host system or components thereof as described herein. Figures 1 to 6 The host system described herein performs the functions described herein. In some examples, the host system may execute an instruction set to control functional elements of the device to perform the functions described herein. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the functions described herein.

[0099] At 705, the method may include transmitting a read command to a volatile memory device coupled to a host system, the read command including a logical address associated with an LBA of data stored in a non-volatile memory device coupled to the host system. The operations of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 705 may be implemented as described in reference to Figure 6 The command component 630 is described as executing.

[0100] At 710, the method may include receiving a compressed copy of data associated with an LBA stored in the volatile memory device from the volatile memory device. The operations of 710 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 710 may be performed as described in reference to Figure 6 The communication component 635 is described as executing.

[0101] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting a read command to a volatile memory device coupled to a host system, the read command including a logical address associated with an LBA of data stored in a non-volatile memory device coupled to the host system; and receiving, from the volatile memory device, a compressed copy of the data associated with the LBA stored in the volatile memory device.

[0102] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for decompressing a compressed copy of data stored in a volatile memory device based at least in part on receiving the compressed copy of the data stored in the volatile memory device.

[0103] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for identifying that a compressed copy of the data may be stored in a volatile memory device, wherein transmitting the read command to the volatile memory device may be based at least in part on identifying that a compressed copy of the data may be stored in the volatile memory device.

[0104] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: assigning a score to data based at least in part on an access frequency parameter associated with the data; storing a compressed copy of the data in a volatile memory device based at least in part on the score satisfying a threshold score, wherein identifying that a compressed copy of the data may be stored in the volatile memory device may be based at least in part on storing the compressed copy of the data.

[0105] Some instances of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: retrieving data from a non-volatile memory device based at least in part on a score exceeding a threshold score; and compressing the data to produce a compressed copy of the data based at least in part on the retrieved data, wherein storing the compressed copy of the data may be based at least in part on the compressed data.

[0106] In some examples of the method 700 and apparatus described herein, the access frequency parameter includes an indication of a likelihood that the data may be accessed, a frequency with which the data may be accessed, or a combination thereof.

[0107] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying a score associated with data stored in a non-volatile memory device based at least in part on an access frequency parameter associated with the data; and deleting a compressed copy of the data stored in the volatile memory device based at least in part on the score being less than a threshold score.

[0108] Some instances of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: transmitting a write command including a second LBA from a host system to store second data in a non-volatile memory device; and storing a compressed copy of the second data in a volatile memory device by overwriting at least a portion of the compressed copy of the data with at least a portion of the compressed copy of the second data based at least in part on transmitting the write command.

[0109] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for updating a score associated with the data based at least in part on receiving a read command.

[0110] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for allocating a portion of a volatile memory device to store a compressed copy of data stored in a non-volatile memory device, the portion of the volatile memory device being configured to provide low-latency access to the compressed copy of the data, wherein receiving the compressed copy of the data stored in the volatile memory device may be based at least in part on allocating the portion.

[0111] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining a threshold amount of memory available for use in a second portion of the volatile memory device for storing uncompressed data; and reallocating at least a portion of the portion of the volatile memory device to the second portion based at least in part on determining the threshold amount of memory available.

[0112] Some instances of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying that a compressed copy of second data stored in a non-volatile memory device may not be stored in the volatile memory device; transmitting a second read command to the non-volatile memory device including a second logical address that may be associated with a second LBA of the second data; and receiving second data from the non-volatile memory device based at least in part on transmitting the second read command to the non-volatile memory device.

[0113] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: retrieving a compressed copy of data from a volatile memory device based at least in part on a score associated with the data stored in the non-volatile memory device being less than a threshold score; and storing a compressed copy of the data in a non-volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device.

[0114] Some instances of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying that a compressed copy of the data may not be stored in the volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device; transmitting a second read command to the non-volatile memory device that includes a logical address that may be associated with an LBA of the data stored in the non-volatile memory device; and receiving a compressed copy of the data stored in the non-volatile memory device based at least in part on storing the compressed copy of the data in the non-volatile memory device.

[0115] In some examples of the method 700 and apparatus described herein, a volatile memory device may include: a first portion of RAM cells configured to store uncompressed data of any data type; a second portion of RAM cells configured to store compressed data of the first type of data; and a third portion of RAM cells configured to store a compressed copy of host data stored by the non-volatile memory device, wherein the compressed copy of the data may be stored in the third portion.

[0116] In some examples of the method 700 and apparatus described herein, the non-volatile memory device includes NAND memory cells and the volatile memory device includes RAM cells.

[0117] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0118] An apparatus is described. The apparatus may include: a host system coupled to a non-volatile memory device and a volatile memory device; a controller coupled to the host system and operable to cause the apparatus to: transmit a read command including a logical address associated with an LBA of data stored in the non-volatile memory device to the volatile memory device; and receive, at the host system, from the volatile memory device a compressed copy of the data stored at the logical address of the volatile memory device.

[0119] In some examples of the apparatus, the controller may be further configured to cause the apparatus to decompress the compressed copy of the data stored in the volatile-memory device based at least in part on receiving the compressed copy of the data stored in the volatile-memory device.

[0120] In some examples of the apparatus, the controller may be further configured to cause a compressed copy of the apparatus identification data to be stored in the volatile memory device, wherein transmitting the read command to the volatile memory device may be based at least in part on the compressed copy of the identification data being stored in the volatile memory device.

[0121] In some instances of the device, the controller may be further configured to cause the device to assign a score to the data based at least in part on an access frequency parameter associated with the data; and store a compressed copy of the data in a volatile memory device based at least in part on the score satisfying a threshold score, wherein receiving the compressed copy of the data stored in the volatile memory device may be based at least in part on storing the compressed copy of the data.

[0122] In some instances of the device, the controller may be further configured to cause the device to retrieve data from the non-volatile memory device based at least in part on the score exceeding a threshold score; and compress the data to produce a compressed copy of the data based at least in part on the retrieved data, wherein storing the compressed copy of the data may be based at least in part on the compressed data.

[0123] In some examples of the apparatus, the access frequency parameter includes an indication of a likelihood that the data may be accessed, a frequency with which the data may be accessed, or a combination thereof.

[0124] In some instances of the apparatus, the controller may be further configured to cause the apparatus to identify a score associated with data stored in the non-volatile memory device based at least in part on an access frequency parameter associated with the data; and to delete the compressed copy of the data stored in the volatile memory device based at least in part on the score being less than a threshold score.

[0125] In some instances of the device, the controller may be further configured to cause the device to transmit a write command including a second LBA from a host system to store the second data in the non-volatile memory device; and store the compressed copy of the second data in the volatile memory device by overwriting at least a portion of the compressed copy of the data with at least a portion of the compressed copy of the second data based at least in part on transmitting the write command.

[0126] In some examples of the device, the controller may be further configured to cause the device to update a score associated with the data based at least in part on receiving the read command.

[0127] In some instances of the device, the controller may be further configured to cause the device to allocate a portion of the volatile memory device to store a compressed copy of data stored in the non-volatile memory device, the portion of the volatile memory device being configured to provide low-latency access to the compressed copy of the data, wherein receiving the compressed copy of the data stored in the volatile memory device may be based at least in part on allocating the portion.

[0128] In some examples of the device, the controller may be further configured to cause the device to determine a threshold amount of memory available for use of a second portion of the volatile memory device for storing uncompressed data; and reallocate at least a portion of the portion of the volatile memory device to the second portion based at least in part on determining the threshold amount of memory available.

[0129] In some instances of the apparatus, the controller may be further configured to cause the apparatus to recognize that a compressed copy of second data stored in the non-volatile memory device may not be stored in the volatile memory device; transmit a second read command including a second logical address that may be associated with a second LBA of the second data to the non-volatile memory device; and receive the second data from the non-volatile memory device based at least in part on transmitting the second read command to the non-volatile memory device.

[0130] In some instances of the device, the controller may be further configured to cause the device to retrieve a compressed copy of the data from the volatile memory device based at least in part on a score associated with the data stored in the non-volatile memory device being less than a threshold score; and to store the compressed copy of the data in the non-volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device.

[0131] In some instances of the device, the controller may be further configured to cause the device to identify that the compressed copy of the data may not be stored in the volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device; transmit a second read command including a logical address that may be associated with an LBA of the data stored in the non-volatile memory device to the non-volatile memory device; and receive the compressed copy of the data stored in the non-volatile memory device based at least in part on storing the compressed copy of the data in the non-volatile memory device.

[0132] In some examples of an apparatus, a volatile memory device includes a first portion of RAM cells configured to store uncompressed data of any data type; a second portion of RAM cells configured to store compressed data of the first type of data; and a third portion of RAM cells configured to store a compressed copy of host data stored by the non-volatile memory device, wherein the compressed copy of the data may be stored in the third portion.

[0133] In some examples of the apparatus, the non-volatile memory devices include NAND memory cells and the volatile memory devices include RAM cells.

[0134] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0135] The terms "electronic communication," "conductive contact," "connect," and "couple" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0136] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via the conductive paths, to a closed-circuit relationship between the components, in which signals are able to communicate between the components via the conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive paths that previously did not permit signal flow.

[0137] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0138] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0139] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated."

[0140] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "advantageous" to other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0141] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0142] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0143] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0144] As used herein, "or," as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), included in the claims, indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based, at least in part, on."

[0145] Computer-readable media include both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0146] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic device comprising: a host system coupled to the non-volatile memory device and the volatile memory device; as well as a controller coupled to the host system and operable to cause the electronic device to: receiving a command to access data stored in the non-volatile memory device; determining, based at least in part on receiving the command, whether a compressed copy of the data is additionally stored in the volatile memory device, the compressed copy of the data being associated with a logical block address (LBA) of the non-volatile memory device; transmitting, based at least in part on determining whether the compressed copy of the data is stored in the volatile memory device, a read command to the volatile memory device including a logical address of the volatile memory device associated with the LBA of data stored in the non-volatile memory device; as well as The compressed copy of the data otherwise stored in the non-volatile memory device stored at the logical address of the volatile memory device is received from the volatile memory device at the host system.

2. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: The compressed copy of the data stored in the volatile memory device is decompressed based at least in part on receiving the compressed copy of the data stored in the volatile memory device.

3. The electronic device according to claim 1 , wherein the controller is further configured to cause the electronic device to: Identifying that the compressed copy of the data is stored in the volatile memory device, wherein transmitting the read command to the volatile memory device is based at least in part on identifying that the compressed copy of the data is stored in the volatile memory device.

4. The electronic device according to claim 1 , wherein the controller is further configured to cause the electronic device to: assigning a score to the data based at least in part on an access frequency parameter associated with the data; compressing a copy of the data stored in the non-volatile memory device based at least in part on the score satisfying a threshold score; and The compressed copy of the data stored in the non-volatile memory device is stored in the volatile memory device based at least in part on the score satisfying the threshold score, wherein receiving the compressed copy of the data stored in the volatile memory device is based at least in part on storing the compressed copy of the data.

5. The electronic device according to claim 4, wherein the controller is further configured to cause the electronic device to: retrieving the data from the non-volatile memory device based at least in part on the score exceeding the threshold score; and The data is compressed based at least in part on retrieving the data to produce the compressed copy of the data, wherein storing the compressed copy of the data is based at least in part on compressing the data. 6 . The electronic device of claim 4 , wherein the access frequency parameter comprises an indication of a likelihood of accessing the data, a frequency of accessing the data, or a combination thereof.

7. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: identifying a score associated with the data stored in the non-volatile memory device based at least in part on an access frequency parameter associated with the data; and The compressed copy of the data stored in the volatile memory device is deleted based at least in part on the score being less than a threshold score.

8. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: transmitting, from the host system, a write command including a second LBA to store second data in the nonvolatile memory device; and The compressed copy of the second data is stored in the volatile memory device by overwriting at least a portion of the compressed copy of the second data with at least a portion of the compressed copy of the second data based at least in part on transmitting the write command.

9. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: A score associated with the data is updated based at least in part on receiving the read command.

10. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: Allocating a portion of the volatile memory device to store a compressed copy of data stored in the non-volatile memory device, the portion of the volatile memory device being configured to provide lower latency access to the compressed copy of the data relative to accessing information in the non-volatile memory device, wherein receiving the compressed copy of the data stored in the volatile memory device is based at least in part on allocating the portion.

11. The electronic device according to claim 10, wherein the controller is further configured to cause the electronic device to: determining a threshold amount of memory usage of a second portion of the volatile memory device for storing uncompressed data; and At least a portion of the portion of the volatile memory device is reallocated to the second portion based at least in part on determining that the threshold amount of memory is used.

12. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: identifying that a compressed copy of second data stored in the non-volatile memory device is not stored in the volatile memory device; transmitting a second read command including a second logical address associated with a second LBA of the second data to the nonvolatile memory device; as well as The second data is received from the nonvolatile memory device based at least in part on transmitting the second read command to the nonvolatile memory device.

13. The electronic device according to claim 1, wherein the controller is further configured to cause the electronic device to: evicting the compressed copy of the data from the volatile memory device based at least in part on a score associated with the data stored in the non-volatile memory device being less than a threshold score; and The compressed copy of the data is stored in the non-volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device.

14. The electronic device according to claim 13, wherein the controller is further configured to cause the electronic device to: identifying that the compressed copy of the data is not stored in the volatile memory device based at least in part on retrieving the compressed copy of the data from the volatile memory device; transmitting a second read command including the logical address associated with the LBA of the data stored in the nonvolatile memory device to the nonvolatile memory device; as well as The compressed copy of the data stored in the non-volatile memory device is received based at least in part on storing the compressed copy of the data in the non-volatile memory device.

15. The electronic device of claim 1 , wherein the volatile memory device comprises: a first portion of a random access memory unit configured to store uncompressed data of any data type; a second portion of the random access memory unit configured to store compressed data of the first type of data; as well as A third portion of the random access memory unit is configured to store a compressed copy of host data stored by the non-volatile memory device, wherein the compressed copy of the data is stored in the third portion.

16. The electronic device of claim 1, wherein the non-volatile memory device comprises NAND memory cells and the volatile memory device comprises random access memory cells.

17. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command to access data stored in a non-volatile memory device; determining, by a host system coupled to the non-volatile memory device and the volatile memory device, based at least in part on receiving the command, whether a compressed copy of the data is additionally stored in the volatile memory device, the compressed copy of the data being associated with a logical block address (LBA) of the non-volatile memory device; transmitting, based at least in part on determining whether the compressed copy of the data is stored in the volatile memory device, a read command from the host system to the volatile memory device coupled to the host system, the read command including a logical address of the volatile memory device associated with the LBA of data stored in the non-volatile memory device coupled to the host system; as well as The compressed copy associated with the LBA stored in the volatile memory device of the data stored in the non-volatile memory device is received from the volatile memory device at the host system.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Identifying that the compressed copy of the data is stored in the volatile memory device, wherein transmitting the read command to the volatile memory device is based at least in part on identifying that the compressed copy of the data is stored in the volatile memory device.

19. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: assigning a score to the data based at least in part on an access frequency parameter associated with the data; compressing a copy of the data stored in the non-volatile memory device based at least in part on the score satisfying a threshold score; as well as The compressed copy of the data stored in the non-volatile memory device is stored in the volatile memory device based at least in part on the score satisfying the threshold score, wherein identifying that the compressed copy of the data is stored in the volatile memory device is based at least in part on storing the compressed copy of the data.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: retrieving the data from the non-volatile memory device based at least in part on the score exceeding the threshold score; and The data is compressed based at least in part on retrieving the data to produce the compressed copy of the data, wherein storing the compressed copy of the data is based at least in part on compressing the data.

21. The non-transitory computer-readable medium of claim 19, wherein the access frequency parameter comprises an indication of a likelihood of accessing the data, a frequency of accessing the data, or a combination thereof.

22. A method performed by a host system coupled to a non-volatile memory device and a volatile memory device, comprising: receiving a command to access data stored in the non-volatile memory device; determining, based at least in part on receiving the command, whether a compressed copy of the data is additionally stored in the volatile memory device, the compressed copy of the data being associated with a logical block address (LBA) of the non-volatile memory device; transmitting, based at least in part on determining whether the compressed copy of the data is stored in the volatile memory device, a read command to the volatile memory device coupled to the host system, the read command including a logical address of the volatile memory device associated with the LBA of data stored in the non-volatile memory device coupled to the host system; as well as The compressed copy associated with the LBA stored in the volatile memory device and associated with the data stored in the non-volatile memory device is received from the volatile memory device.

23. The method of claim 22, further comprising: Identifying that the compressed copy of the data is stored in the volatile memory device, wherein transmitting the read command to the volatile memory device is based at least in part on identifying that the compressed copy of the data is stored in the volatile memory device.

24. The method of claim 22, further comprising: assigning a score to the data based at least in part on an access frequency parameter associated with the data; compressing a copy of the data stored in the non-volatile memory device based at least in part on the score satisfying a threshold score; as well as The compressed copy of the data stored in the non-volatile memory device is stored in the volatile memory device based at least in part on the score satisfying the threshold score, wherein identifying that the compressed copy of the data is stored in the volatile memory device is based at least in part on storing the compressed copy of the data.

25. The method of claim 24, further comprising: retrieving the data from the non-volatile memory device based at least in part on the score exceeding the threshold score; as well as The data is compressed based at least in part on retrieving the data to produce the compressed copy of the data, wherein storing the compressed copy of the data is based at least in part on compressing the data.

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