Display panel driver architecture

Abstract

The present invention provides a driving structure of a display panel, which includes at least one driving group and at least one control circuit. The driving group is arranged on a display panel, each driving group includes a plurality of drivers, the drivers are connected in series, and each driver is coupled to at least one display element of the display panel. The control circuit is arranged on the display panel and coupled to the driving group, and controls the driving group. By applying the driving structure of the present invention to the display panel, it is not necessary to arrange a scan line on the display panel, and the structure of the display panel can be simplified.

Description

Technical Field

[0001] The present invention relates to a driving structure, and more particularly to a driving structure of a display panel. Background Art

[0002] Display devices have become essential equipment for electronic products to display information. Display devices have evolved from liquid crystal display devices to sub-millimeter light-emitting diode (Mini LED) display devices and micro light-emitting diode (Micro LED) display devices. Due to the evolution of display devices, conventional driving architectures are no longer suitable for evolved display panels, such as sub-millimeter light-emitting diode display panels or micro light-emitting diode display panels. When using conventional driving architectures to drive display panels, the display panels must be provided with scan lines, which increases the complexity of the structure of the display panels.

[0003] Based on the above, the present invention provides a driving structure of a display panel. By using the driving structure to drive the display panel, it is unnecessary to set a scan line on the display panel, thereby simplifying the structure of the display panel. Summary of the invention

[0004] An object of the present invention is to provide a driving structure of a display panel, which includes at least one driving group, and the driving group includes a plurality of drivers connected in series. These drivers receive input data at different times, that is, the pixel data of the input data received by these drivers are different, so as to drive the plurality of display elements of the display panel, so that there is no need to set scan lines on the display panel.

[0005] An object of the present invention is to provide a driving structure of a display panel, wherein the driver includes a storage circuit that can store data. When the data is not updated, the driver can drive the display element to display an image according to the stored data.

[0006] The present invention provides a driving structure of a display panel, which includes at least one driving group and at least one control circuit. The driving group and the control circuit are arranged on a display panel, each driving group includes a plurality of drivers, the drivers are connected in series, and each driver is coupled to at least one display element of the display panel. The control circuit is coupled to the driving group and controls the driving group. By using the driving structure of the present invention to drive the display panel, it is not necessary to set a scan line on the display panel, and the structure of the display panel can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 : It is a schematic diagram of an embodiment of the driving architecture of the present invention;

[0008] Figure 2 :It is a block diagram of an embodiment of the control circuit and the driving group of the present invention; and

[0009] Figure 3 : It is a circuit diagram of an embodiment of the driver of the present invention.

[0010]

Figure number comparison

[0011] 10 Display Panel

[0012] 14 Display components

[0013] 20 Drive Group

[0014] 22 Driver

[0015] 24 Enable circuit

[0016] 26 Storage Circuit

[0017] 261 Buffer

[0018] 263 Controller

[0019] 265 Memory

[0020] 28. Driving Circuit

[0021] 281 Comparator

[0022] 283 Counter

[0023] 285 Level conversion circuit

[0024] 286 The First Transistor

[0025] 288 Second transistor

[0026] 30 Control circuit

[0027] 32 Input Interface

[0028] 33 Enabling Circuit

[0029] 34 Buffer

[0030] 36 Timing Controller

[0031] 38 Buffer

[0032] 39 Adjustment circuit

[0033] DCLK clock signal

[0034] Din Input Data

[0035] PWMCLK clock signal

[0036] VDD Supply Voltage

[0037] VR Adjustment Signal DETAILED DESCRIPTION

[0038] In order to further understand and appreciate the structural features and effects of the present invention, a preferred embodiment and detailed description are provided as follows:

[0039] Certain words are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same component. Moreover, the specification and claims do not use the difference in name as a way to distinguish components, but use the overall technical difference of the components as the criterion for distinction. The word "including" mentioned throughout the specification and claims is an open term and should be interpreted as "including but not limited to". Furthermore, the word "coupled" here includes any direct and indirect connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.

[0040] See also Figure 1 , which is a schematic diagram of a first embodiment of the driving architecture of the present invention. As shown in the figure, the driving architecture of the present invention is used to drive a display panel 10 to display an image. The driving architecture includes at least one driving group 20 and at least one control circuit 30. In this embodiment, a plurality of driving groups 20 and a plurality of control circuits 30 are used as examples to illustrate the driving architecture of the present invention. The driving groups 20 and the control circuits 30 are disposed on the display panel 10, and the control circuits 30 are coupled to the driving groups 20 and control the driving groups 20. In one embodiment of the present invention, each control circuit 30 may be an independent chip, but is not limited thereto, and the control circuits 30 may be integrated into one chip.

[0041] In addition, each driving group 20 includes a plurality of drivers 22, and the drivers 22 are connected in series. The drivers 22 of each driving group 20 are arranged on the display panel 10 along a direction. In this embodiment, the drivers 22 of each driving group 20 are arranged on the display panel 10 along the longitudinal direction, which means that the driving groups 20 are respectively arranged on the display panel 10 longitudinally and are adjacent to each other, but it is not limited to this. In one embodiment of the present invention, each driver 22 can be an independent chip, but it is not limited to this. Each driver 22 is coupled to at least one display element 14 (such as Figure 2) to drive the display element 14 to display an image. The display element 14 may be a sub-millimeter light emitting diode (Mini LED) or a micro light emitting diode (MicroLED), and the display panel 10 is a sub-millimeter light emitting diode display panel or a micro light emitting diode display panel. However, the driving architecture of the present invention is not limited to the above two display panels. The control circuits 30 are coupled to the drive groups 20 to control the drive groups 20.

[0042] See also Figure 1 , the control circuit 30 transmits an input data to the driving group 20. In one embodiment of the present invention, the input data may be a serial data and includes a plurality of pixel data. The drivers 22 of the driving group 20 are all coupled to a bus (not shown), and the control circuit 30 transmits the input data to the bus, and the drivers 22 receive the input data via the bus. The drivers 22 receive the input data at different times, so that the pixel data received by each of the drivers 22 is different. For example, when a driver 22 of the driving group 20 receives the input data, the other drivers 22 do not receive the input data, and after the driver 22 receives one pixel data of the input data, it drives another driver 22 to receive the input data to receive another pixel data of the input data. Since the above two drivers 22 receive the input data at different times, the pixel data of the input data received by the two drivers 22 are different, so as to drive the plurality of display elements 14 of the display panel 10 to display different images. The operation of the other drivers 22 is the same as described above. According to the above description, after receiving the pixel data of the input data, the driver 22 further drives another driver 22 to receive another pixel data of the input data. In this way, there is no need to set additional scan lines on the display panel 10, thereby simplifying the structure of the display panel 10.

[0043] In addition, in another embodiment of the present invention, a driver 22 of a driver group 20 of the driver groups 20 can be coupled to a driver 22 of another driver group 20. For example, the last driver 22 of each driver group 20 can be coupled to each other to transmit data or signals, but the present invention is not limited thereto. In addition, the driver groups 20 and the control circuits 30 are disposed in a display area of ​​the display panel 10, but the present invention is not limited thereto. The control circuits 30 can be disposed in a non-display area of ​​the display panel 10.

[0044] See also Figure 2, which is a block diagram of an embodiment of the control circuit and the driving group of the present invention. For the convenience of explanation, the driving group 20 of this embodiment includes two drivers 22. As shown in the figure, the control circuit 30 includes an input interface 32, an enabling circuit 33, a buffer 34, a timing controller 36, a register 38 and an adjustment circuit 39. The control circuit 30 is coupled to a host, such as a microprocessor of an electronic product, to receive input data, control commands or related control parameters. The input interface 32 receives input data, control commands or control parameters. The enabling circuit 33 is coupled to the input interface 32, and enables the input interface 32 according to the received enabling signal, driving the input interface 32 to receive input data, control commands or control parameters.

[0045] See also Figure 2 , the buffer 34 is coupled to the input interface 32 and the timing controller 36. The input interface 32 transmits input data to the buffer 34. The buffer 34 buffers the input data and transmits the buffered input data to the timing controller 36. The timing controller 36 transmits the input data to the driving group 20 via the bus and outputs a timing signal to the driver 22 of the driving group 20 to control the operation of the driver 22. The register 38 is coupled to the input interface 32, the timing controller 36 and the adjustment circuit 39. The input interface 32 transmits control parameters to the register 38. The register 38 stores the control parameters and provides the control parameters to the timing controller 36 and the adjustment circuit 39. The timing controller 36 generates a timing signal according to the control parameters. The adjustment circuit 39 generates an adjustment signal to the driver 22 according to the control parameters to adjust the strength of a driving signal generated by the driver 22. The driving signal is used to drive the display element 14 of the display panel 10. The strength of the driving signal determines the brightness of the display element 14.

[0046] See also Figure 2 Each driver 22 includes an enabling circuit 24, a storage circuit 26, and a driving circuit 28. The storage circuit 26 is coupled to the timing controller 36 of the control circuit 30 via a bus to receive input data transmitted by the timing controller 36. Figure 3 ), and enables the storage circuit 26 to drive the storage circuit 26 to receive input data and store the input data. In one embodiment of the present invention, the enabling circuit 24 enables the storage circuit 26 for a predetermined time, and the storage circuit 26 receives input data at the predetermined time and stores the received input data. After the enabling circuit 24 enables the storage circuit 26 for the predetermined time, the storage circuit 26 is disabled, that is, the storage circuit 26 does not receive input data.

[0047] For example, the enabling circuit 24 of the first driver 22 is coupled to the timing controller 36 of the control circuit 30, and the timing controller 36 sends an enabling signal to the enabling circuit 24 of the first driver 22, driving the enabling circuit 24 of the first driver 22 to enable the storage circuit 26 to receive input data. This means that the timing controller 36 drives the first driver 22 to receive input data. The above-mentioned enabling signal can be a clock signal. When the enabling circuit 24 of the first driver 22 enables the storage circuit 26 of the first driver 22, the enabling circuits 24 of the remaining drivers 22 disable the storage circuits 26 of the remaining drivers 22, that is, do not receive input data. After the enabling circuit 24 of the first driver 22 disables the storage circuit 26 of the first driver 22, it sends an enabling signal to the enabling circuit 24 of another driver 22. In one embodiment of the present invention, the enabling circuit 24 of the first driver 22 sends an enabling signal to the enabling circuit 24 of the second driver 22, driving the enabling circuit 24 of the second driver 22 to enable the storage circuit 26 of the second driver 22 to receive input data. Similarly, after a predetermined time, the enabling circuit 24 of the second driver 22 disables the storage circuit 26 of the second driver 22, and sends an enabling signal to the enabling circuit 24 of another driver 22, such as the third driver 22, to enable the storage circuit 26 of another driver 22. As can be seen from the above description, the storage circuits 26 of the drivers 22 receive input data at different times, which is equivalent to receiving input data in time sharing. In this way, the pixel data of the input data received by the storage circuits 26 of the drivers 22 are different. For example, the pixel data received and stored by the storage circuit 26 of the first driver 22 is different from the pixel data received and stored by the storage circuit 26 of the second driver 22.

[0048] Initially, the timing controller 36 is not limited to sending the enable signal to the enable circuit 24 of the first driver 22. The timing controller 36 can be set to send the enable signal to the enable circuit 24 of other drivers 22, such as the enable circuit 24 of the second driver 22, according to the use requirements. In addition, the enable circuit 24 of the first driver 22 disables the storage circuit 26 of the first driver 22 and then sends the enable signal to the enable circuit 24 of the second driver 22. This is only an embodiment of the present invention and is not limited thereto. The order of enabling the drivers 22 to receive input data can be set according to the requirements.

[0049] See also Figure 2 The driving circuit 28 of each driver 22 is coupled to the storage circuit 26 and at least one display element 14 (eg, Figure 3). The driving circuit 28 receives the pixel data of the input data stored in the storage circuit 26, and generates a driving signal according to the received pixel data to drive the display element 14 to display an image. In addition, the adjustment circuit 39 of the control circuit 30 is coupled to the driving circuits 28 of the drivers 22, and the adjustment circuit 39 outputs an adjustment signal to the driving circuits 28 to adjust the intensity of the driving signals output by the driving circuits 28, so as to adjust the brightness of the display elements 14. In one embodiment of the present invention, the adjustment signal is a voltage, and the intensity of the driving signal is adjusted by changing the intensity of the voltage.

[0050] See also Figure 1 and Figure 2 , the control circuits 30 are connected in series and arranged along a direction. In this embodiment, the control circuits 30 are arranged in the horizontal direction on the display panel 10, but the present invention is not limited thereto. In one embodiment of the present invention, the enabling circuit 33 of one of the control circuits 30 enables the input interface 32 for a predetermined time to drive the input interface 32 to receive input data at the predetermined time. The enabling circuit 33 enables the input interface 32 for the predetermined time and then disables the input interface 32, that is, the input interface 32 does not receive input data. During the predetermined time, the enabling circuits 33 of the other control circuits 30 disable the input interfaces 32 of the other control circuits 30 and do not receive input data. In addition, the enabling circuit 33 enables the input interface 32 for the predetermined time and then disables the input interface 32, and sends an enabling signal to the enabling circuit 33 of another control circuit 30 to enable the input interface 32 of the other control circuit 30 to receive input data. In this way, the control circuit 30 receives input data in a time-sharing manner like the drivers 22, and the input data received by the control circuits 30 are different. In another embodiment of the present invention, the control circuits 30 may not be connected in series, and the control circuits 30 may receive input data from the host, and the host may control the control circuits 30 respectively to drive the control circuits 30 to receive input data. In this way, the control circuit 30 may not need to be provided with an enabling circuit 33.

[0051] See also Figure 3, which is a circuit diagram of an embodiment of the driver of the present invention. As shown in the figure, each storage circuit 26 includes a buffer 261, a controller 263 and a plurality of memories 265. The buffer 261 is coupled to the enabling circuit 24 and receives input data Din and a clock signal DCLK. The enabling circuit 24 enables the buffer 261 according to the received enabling signal and the clock signal DCLK, drives the buffer 261 to receive the input data Din according to the clock signal DCLK, and the buffer 261 buffers the input data Din. The buffer 261 and the memories 265 are coupled to a bus, and the buffer 261 outputs the input data Din to the bus. The memories 265 can receive the input data Din from the bus and store the input data Din. The controller 263 is coupled to the memories 265 and receives the clock signal DCLK, and controls the memories 265 to receive input data from the bus at different times according to the clock signal DCLK, that is, the memories 265 receive input data from the bus in a time-sharing manner, so that the pixel data of the input data received by the memories 265 are different. In one embodiment of the present invention, the controller 263 can be a counter, and controls the memories 265 to receive the input data Din output by the buffer 261 at different times.

[0052] See also Figure 3 The driving circuit 28 includes a plurality of comparators 281, a counter 283, a plurality of level conversion circuits 285, and a plurality of signal generating circuits. The comparators 281 are coupled to the memories 265 and the counter 283. The counter 283 receives a clock signal PWMCLK, and outputs a counting signal according to the counting of the clock signal PWMCLK. The counting signal changes with the counting of the counter 283. Each comparator 281 receives the counting signal and the pixel data of the input data Din stored in the memory 265, and compares the counting signal with the pixel data. When the pixel data is greater than the counting signal, the comparator 281 outputs a driving level, such as a high level. In another embodiment of the present invention, when the pixel data is less than the counting signal, the comparator 281 outputs the driving level.

[0053] The level conversion circuits 285 are coupled to the comparators 281 to convert the driving level output by the comparator 281 to generate an enabling level. Each signal generating circuit includes a first transistor 286 and a second transistor 288. The first transistor 286 and the second transistor 288 are connected in series with each other, one end of the first transistor 286 is coupled to one end of the display element 14, and one end of the second transistor 288 is coupled to a ground terminal. The level conversion circuits 285 are coupled to the gate of the second transistor 288 of the signal generating circuits, and output the enabling level to the gate of the second transistor 288 to turn on the second transistor 288, thereby generating a driving signal to drive the display element 14 to emit light to display an image. The driving signal is a current flowing from a supply voltage VDD to the ground terminal. The supply voltage VDD is coupled to the other end of the display element 14. In addition, the gate of the first transistor 286 is coupled to the adjustment signal VR transmitted by the adjustment circuit 39 of the control circuit 30. The adjustment signal VR can control the conduction degree of the first transistor 286, and can control the intensity of the current flowing through the display element 14 to control the brightness of the display element 14. From the above description, it can be seen that the time for the comparator 281 to continuously generate the driving level is the driving time, that is, the time for driving the display element 14, which determines the brightness of the display element 14.

[0054] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications to the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A display panel driving architecture, characterized in that: It contains: At least one driving group is disposed on a display panel, each of the driving groups includes a plurality of drivers, the drivers are connected in series, and each of the drivers is coupled to at least one display element of the display panel; as well as At least one control circuit is disposed on the display panel, coupled to the driving group, and controls the driving group; Each of the drivers includes an enabling circuit, which enables the driver to receive input data transmitted by the at least one control circuit. After the enabling circuit enables the driver, the enabling circuit disables the driver from receiving the input data and drives the enabling circuit of another driver to enable the other driver to receive the input data transmitted by the at least one control circuit.

2. The display panel driving architecture according to claim 1, wherein: The drivers of each driving group are arranged on the display panel along a direction; the two drivers of each driving group receive the input data at different times, and the two drivers of each driving group drive the at least one display element coupled to the two drivers of each driving group when the display panel is not provided with a scan line.

3. The display panel driving architecture according to claim 1, wherein: The at least one driving group includes a plurality of driving groups, and a driver of one driving group of the driving groups is coupled to a driver of another driving group.

4. The display panel driving architecture according to claim 1, wherein: Each of the drives contains: a storage circuit coupled to a bus and to the control circuit, the control circuit transmits the input data to the bus, and the storage circuit stores the input data transmitted by the control circuit; as well as The enabling circuit is coupled to the storage circuit and enables the storage circuit to receive the input data; After the enabling circuit enables the storage circuit, the enabling circuit disables the storage circuit from receiving the input data, and drives the enabling circuit of another driver to enable the storage circuit of the other driver to receive the input data transmitted by the control circuit.

5. The display panel driving architecture as claimed in claim 4, characterized in that: The control circuit includes a timing controller, which is coupled to the storage circuit to transmit the input data to the storage circuit. The timing controller is further coupled to the enabling circuit to drive the enabling circuit to enable the storage circuit.

6. The display panel driving architecture as claimed in claim 1, wherein: The at least one control circuit is coupled to a bus and transmits the input data to the bus. Each driver is coupled to the bus and includes a driving circuit. The driving circuit drives the at least one display element according to the input data.

7. The display panel driving architecture as claimed in claim 6, wherein: The control circuit includes an adjustment circuit, which is coupled to the driving circuit and adjusts the intensity of a driving signal output by the driving circuit, and the driving signal drives the display element of the display panel.

8. The display panel driving architecture as claimed in claim 1, wherein: The control circuit is located in a display area of ​​the display panel.

9. The display panel driving architecture as claimed in claim 1, wherein: The control circuit comprises: An input interface for receiving the input data; a buffer, coupled to the input interface, for buffering the input data; and A timing controller is coupled to the buffer, receives the input data, outputs the input data to the driving group, and drives a driver of the driving group to receive the input data.

10. A display panel driving architecture, characterized in that: It contains: A plurality of driving groups are disposed on a display panel, each of the driving groups includes a plurality of drivers, the drivers are connected in series, and each of the drivers is coupled to at least one display element of the display panel; as well as A plurality of control circuits are disposed on the display panel, coupled to the driving groups, and control the driving groups; Each of the control circuits comprises: An enabling circuit enables the control circuit to receive an input data. After the enabling circuit enables the control circuit, the enabling circuit disables the control circuit from receiving the input data and drives the enabling circuit of another control circuit to enable the other control circuit to receive the input data.

11. The display panel driving architecture according to claim 10, wherein: The control circuits are connected in series.

12. The display panel driving architecture according to claim 10, wherein: Each of the control circuits comprises: an input interface for receiving the input data; and The enabling circuit is coupled to the input interface and enables the input interface to receive the input data; After the enabling circuit enables the input interface, the enabling circuit disables the input interface to not receive the input data, and drives the enabling circuit of another control circuit to enable the input interface of the other control circuit to receive the input data.

13. The display panel driving architecture according to claim 10, wherein: Each of the control circuits comprises: An input interface for receiving the input data; a buffer, coupled to the input interface, for buffering the input data; and A timing controller is coupled to the buffer, receives the input data, outputs the input data to the driving group, and drives a driver of the driving group to receive the input data.

Images