A Hybrid Modulation Method of CBPWM and VSVPWM with Multi-objective Coordination

Abstract

The present invention relates to a multi-objective coordinated CBPWM and VSVPWM hybrid modulation method, which includes: first, under CBPWM modulation, the modulation strategy realizes active control of the midpoint potential by injecting zero-sequence voltage to eliminate midpoint voltage oscillation; second, by rationally arranging the carrier sequence to suppress the common-mode voltage, and adopts VSVPWM modulation when the midpoint potential cannot be balanced or the common-mode voltage cannot be suppressed using CBPWM modulation. The modulation method of the present invention can effectively control the midpoint voltage like VSVPWM, but with less switching loss; within the full power factor and full modulation range, it can limit the common-mode voltage to ±u DC / within 6.

Description

Technical Field

[0001] The present invention belongs to the technical field of inverter modulation, and in particular relates to a multi-objective coordinated CBPWM and VSVPWM hybrid modulation method. Background Art

[0002] With the continued development of power electronics technology, power electronics devices have made rapid progress. Converters, as a core component, have also received in-depth research. Advances in the energy industry have led to an increasing demand for high-voltage, high-power converters in the current industrial sector. Three-level converters, due to their superior performance, are widely used. This has also presented new challenges. The increased number of power transistors complicates control algorithms, and is accompanied by issues such as midpoint voltage offset and switching losses. Maintaining midpoint voltage balance is a prerequisite for safe and reliable converter operation. Unbalanced and fluctuating midpoint voltages not only degrade the converter's output voltage and current, impacting converter efficiency, but in severe cases, can even cause excessive DC-side capacitor withstand voltage, leading to losses and shortening the converter system's service life. Converter switching losses are also a key indicator of converter efficiency. Low switching losses ensure optimal converter operation, while high switching losses significantly reduce converter efficiency and shorten its lifespan.

[0003] In order to ensure that the three-level inverter has good output characteristics, an excellent pulse width modulation strategy should meet the following two requirements:

[0004] (1) It has a certain ability to balance the midpoint voltage. The fluctuation of the midpoint voltage is one of the key issues of the three-level inverter.

[0005] (2) Smaller switching losses to improve system efficiency. Switching loss is also one of the important indicators for measuring the efficient operation of the inverter. The increase in switching loss will inevitably reduce the use of power devices.

[0006] Currently, there are two main algorithms commonly used to achieve neutral-point potential balancing: carrier pulse width modulation (CBPWM) based on zero-sequence component injection and space vector modulation (SVPWM) based on redundant vector adjustment. The computational complexity of the control algorithm is significantly increased due to the zero-sequence voltage calculation in the CBPWM method and the complexity of the vector synthesis rules in the space vector modulation method. While the VSVPWM method can achieve neutral-point voltage balancing, one phase power device switches twice during any switching cycle, increasing system switching losses. Therefore, a modulation method for three-level inverters is needed that can simultaneously reduce system switching losses and achieve neutral-point voltage balancing.

[0007] Therefore, it is necessary to provide a new multi-objective coordinated CBPWM and VSVPWM hybrid modulation method to solve the above technical problems. Summary of the Invention

[0008] The purpose of the present invention is to provide a multi-objective coordinated CBPWM and VSVPWM hybrid modulation method in order to solve the above problems.

[0009] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0010] A multi-objective coordinated CBPWM and VSVPWM hybrid modulation method includes the following steps:

[0011] S1: Collect the DC side voltage u of the three-level inverter DC , three-phase output phase current i A 、i B 、i C And the three-phase output phase voltage u A 、u B 、u C and obtaining first calculation data after performing calculation;

[0012] S2: Making a judgment based on the first calculated data, the midpoint voltage balance condition, and the common-mode voltage suppression condition; if both the midpoint voltage balance condition and the common-mode voltage suppression condition are satisfied, adopting the CBPWM modulation method; otherwise, adopting the VSVPWM modulation method;

[0013] The common mode voltage suppression condition is that the common mode voltage is limited to ±u DC / Within 6.

[0014] As a further optimization solution of the present invention, the first data calculation data in step S1 is specifically: the maximum current i max =max(i A ,i B ,i C ), minimum current i min =min(i A ,i B ,i C ), intermediate current i mid =mid(i A ,i B ,i C ), maximum voltage u max =max(u A ,u B ,u C ), minimum voltage u min =min(u A ,u B ,u C) and the intermediate voltage u mid =mid(u A ,u B ,u C ).

[0015] As a further optimization solution of the present invention, the process of determining the midpoint voltage balance condition in step S2 is specifically as follows:

[0016] S201: Inject zero-sequence voltage u Z , determine whether the injected zero-sequence voltage meets the limiting condition, if so, proceed to step S202, otherwise the midpoint voltage balance is not met;

[0017] S202: Determine when u mid >0, zero sequence voltage u Z Whether it meets:

[0018]

[0019] When u mid <0, zero sequence voltage u Z Whether it meets:

[0020]

[0021] If both conditions are met at the same time, the midpoint voltage balance is satisfied, otherwise the midpoint voltage balance is not satisfied;

[0022] The limiting condition is that the three-phase voltage does not overshoot and the polarity of the three-phase voltage does not change.

[0023] As a further optimization solution of the present invention, the process of determining the common mode voltage suppression condition in step S2 is specifically as follows:

[0024] The phase with positive voltage adopts concave carrier, and the phase with negative voltage adopts convex carrier; the phase with maximum voltage adopts concave carrier, and the phase with minimum voltage adopts convex carrier. mid and the injected zero-sequence voltage to determine the common-mode voltage rejection condition:

[0025] When u mid >0,u Z >0:

[0026] Limit the 1-level output corresponding to the voltage mid-phase to L max +L min = 0 to avoid high common mode voltage, where L max , L mid and L min Respectively represent u max ,u mid ,u min The corresponding instantaneous output level;

[0027] When using concave carrier, only when d mid,1 <d min,-1 When the common mode voltage does not exceed u DC / 6, then we get:

[0028]

[0029] When using convex carrier, we solve:

[0030]

[0031] Right now It shows that in order to suppress the common mode voltage, a concave carrier should be used in the middle of the voltage when the modulation index is high; a convex carrier should be used in the middle of the voltage when the modulation index is low.

[0032] When u mid <0,u Z <0

[0033] Limit the -1 level output of the voltage intermediate phase to L max +L min =0, the zero sequence voltage u Z Should meet the following requirements:

[0034] When the voltage intermediate phase adopts a convex carrier, the solution is:

[0035]

[0036] When the voltage intermediate phase adopts a concave carrier, the solution is:

[0037]

[0038] As a further optimization solution of the present invention, after step S2, the method further includes: when VSVPWM modulation is adopted, the voltage maximum phase and minimum phase carriers use different carriers, thereby reducing the common mode voltage.

[0039] As a further optimization solution of the present invention, when the determined modulation method is the VSVPWM modulation method, under the VSVPWM modulation method, the voltage maximum phase and minimum phase carriers are made to use different carriers, thereby reducing the common mode voltage, including the following steps:

[0040] Step 301: Set the total average midpoint current i introduced by the three phases NP is zero, that is:

[0041] d max,0 =d mid,0 =d min,0 ;

[0042] Satisfy i NPThe duty ratios of the three-phase levels for zero conditions are as follows:

[0043]

[0044] Step 302: according to the duty cycle of each level of the three phases, different carriers are set for the maximum voltage phase and the minimum voltage phase, and the sum of the output levels of the maximum voltage phase and the minimum voltage phase is 0, thereby reducing the common mode voltage.

[0045] The beneficial effects of the present invention are:

[0046] The modulation method of the present invention can effectively control the midpoint voltage like VSVPWM, but with less switching loss; within the full power factor and full modulation range, it can limit the common mode voltage to ±u DC / Within 6. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a flowchart of the present invention;

[0048] Figure 2 This is the main circuit diagram of the three-level inverter;

[0049] Figure 3 The common mode voltage diagram of carrier in-phase CBPWM and carrier inverse CBPWM;

[0050] Figure 4 The common mode voltage diagram under different conditions after zero-sequence voltage is injected;

[0051] Figure 5 It is the common mode voltage diagram of carrier in-phase VSVPWM and carrier inverse-phase VSVPWM;

[0052] Figure 6a for When CBPWM is used, the midpoint voltage can be balanced and the common mode voltage can be limited to ±u DC Schematic diagram of the area of ​​ / 6;

[0053] Figure 6b for When CBPWM is used, the midpoint voltage can be balanced and the common mode voltage can be limited to ±u DC Schematic diagram of the area of ​​ / 6;

[0054] Figure 6c for When CBPWM is used, the midpoint voltage can be balanced and the common mode voltage can be limited to ±u DC Schematic diagram of the area of ​​ / 6;

[0055] Figure 6d for When CBPWM is used, the midpoint voltage can be balanced and the common mode voltage can be limited to ±u DC Schematic diagram of the area of ​​ / 6;

[0056] Figure 7a For CBPWM and VSVPWM Schematic diagram of switching loss comparison under m∈[0,1.1547];

[0057] Figure 7b The multi-objective coordinated CBPWM and VSVPWM hybrid modulation and CBPWM modulation are given. Schematic diagram of switching loss comparison under m∈[0,1.1547];

[0058] Figure 7c The multi-objective coordinated CBPWM and VSVPWM hybrid modulation and VSVPWM modulation are given. Schematic diagram of switching loss comparison under m∈[0,1.1547];

[0059] Figure 8 This is a flow chart of the algorithm for the multi-objective coordinated CBPWM and VSVPWM hybrid modulation of the present invention. DETAILED DESCRIPTION

[0060] The present application is further described in detail below in conjunction with the accompanying drawings. It is necessary to point out here that the following specific implementation methods are only used to further illustrate the present application and cannot be understood as limiting the scope of protection of the present application. Technical personnel in this field can make some non-essential improvements and adjustments to the present application based on the above application content.

[0061] Example 1

[0062] like Figure 1-8 As shown, a multi-objective coordinated CBPWM and VSVPWM hybrid modulation method includes the following steps:

[0063] Step S1: Use voltage sensor to collect Figure 2 The capacitances of C1 and C2 on the DC side of the three-level inverter are u C1 、u C2 , three-phase output phase current i A 、i B 、i C , three-phase output phase voltage u A 、u B 、u C , judge the three-phase output phase current and three-phase output phase voltage, and get the maximum current i max =max (i A ,i B ,i C), minimum current i min =min(i A ,i B ,i C ), intermediate current i mid =mid(i A ,i B , i C ), maximum voltage u max =max(u A ,u B ,u C ), minimum voltage u min =min(u A ,u B ,u C ) and the intermediate voltage u mid =mid(u A ,u B ,u C );

[0064] Step S2: Calculate the range in which CBPWM can balance the midpoint voltage and suppress the common mode voltage. The specific implementation is:

[0065] In one switching cycle, calculate the total average midpoint current i introduced by the three phases NP for:

[0066] i NP =i max d max,0 +i mid d mid,0 +i min d min,0 (1)

[0067] The condition for the midpoint voltage to be balanced is: if the midpoint voltage is balanced at the start of a switch, and the voltage remains balanced at the end of this cycle. In CBPWM, by injecting zero-sequence voltage u Z The midpoint voltage is balanced in this way. After injecting zero-sequence voltage, the modulation wave is:

[0068] u′ x =u x +u Z (2)

[0069] After injecting zero-sequence voltage, the duty cycle of the three-phase voltage output level is:

[0070]

[0071] where d x,1 , d x,0 and d x,-1 Represents the duty cycle of 1 level, 0 level and -1 level respectively.

[0072] When u mid When >0, the total average current introduced by the three phases after the zero-sequence voltage is injected is obtained from equations (1) and (3):

[0073]

[0074] Considering the ideal capacitor voltage balance condition i' NP =0, the zero-sequence voltage u that needs to be injected to balance the midpoint voltage Z for:

[0075]

[0076] When u mid <0, the total average current introduced by the three phases after the zero-sequence voltage is injected is:

[0077]

[0078] In order to balance the zero-sequence voltage u injected at the midpoint voltage Z for:

[0079]

[0080] The injected zero-sequence voltage has two limiting conditions: 1) the three-phase voltage does not overshoot; 2) the polarity of the three-phase voltage does not change.

[0081] Therefore, u mid >0, the zero-sequence voltage should meet the following requirements:

[0082]

[0083] Zero sequence voltage at u mid <0 should satisfy:

[0084]

[0085] When the conditions of equations (8) and (9) above are met, the conditions for CBPWM midpoint voltage balance are met.

[0086] After the zero-sequence voltage is injected, the phase voltage changes, and the common-mode voltage will also change accordingly. It is recommended to use a concave carrier for the maximum voltage phase and a convex carrier for the minimum voltage phase. The magnitude of the common-mode voltage is closely related to the carrier form of the intermediate voltage phase, so the carrier mode must be flexibly selected for the intermediate voltage phase. According to the polarity of the intermediate voltage phase and the zero-sequence voltage, there are four cases. Among them, u mid >0,0>u Z >-u mid and u mid <0,0 Z <-u mid ​These two cases are similar to the case without zero-sequence voltage injection. mid >0,u Z >0 and u mid <0,u Z <0 two situations.

[0087] Case 1: u mid >0,u Z >0

[0088] When u mid >0,u Z >0, the phase corresponding to the middle voltage will output 1 level for a period of time. In order to avoid high common mode voltage, the 1 level output corresponding to the middle phase of the voltage must be limited to L max +L min = 0. Because the voltage maximum phase uses a concave carrier and the voltage minimum phase uses a convex carrier, so L max +L min = 0 is located at the beginning and end of the switching cycle and in the middle. Therefore, the voltage mid-phase needs to be discussed separately for concave and convex carriers.

[0089] Among them, L max , L mid and L min Respectively represent u max ,u mid ,u min The corresponding instantaneous output level. When the voltage intermediate phase adopts concave carrier, such as Figure 4 (a) shows that only when d mid,1 <d min,-1 When the common mode voltage does not exceed u DC / 6, at this time:

[0090]

[0091] When the voltage intermediate phase adopts convex carrier, such as Figure 4 (b) can be solved similarly:

[0092]

[0093] Comparing (11) and (12), when Right now It shows that in order to suppress the common mode voltage, a concave carrier should be used in the middle of the voltage when the modulation index is high, and a convex carrier should be used in the middle of the voltage when the modulation index is low.

[0094] Case 2: u mid <0,u Z <0

[0095] When u mid <0,uZ <0, the voltage mid-phase will output -1 level for a period of time. Similarly, the -1 level output of the voltage mid-phase must be limited to L max +L min = 0. Similarly, the intermediate phase needs to be discussed separately for concave carrier and convex carrier.

[0096] When the voltage intermediate phase adopts a convex carrier, such as Figure 4 (c) is shown in the figure, and the solution is similar:

[0097]

[0098] When the voltage intermediate phase adopts concave carrier, such as Figure 4 (d) can be solved similarly:

[0099]

[0100] By comparing (13) and (14), we can conclude that, in order to suppress the common-mode voltage, a convex carrier should be used in the middle of the voltage when the modulation index is high, and a concave carrier should be used in the middle of the voltage when the modulation index is low.

[0101] When the above conditions are met, the common mode voltage conditions are met.

[0102] Step S3: Compare and determine whether CBPWM can meet the target requirements. If CBPWM can balance the midpoint voltage and limit the common mode voltage to ±u DC When the value is within / 6, CBPWM is used; otherwise, VSVPWM is used.

[0103] Step S4: After determining the modulation method, in order to reduce the common mode voltage, the common mode voltage is limited to ±u DC / 6, it is necessary to make some changes to the carrier mode. In order to obtain the PWM wave. Assuming that the modulation method is determined to be VSVPWM, the specific implementation is as follows:

[0104] The load current satisfies i A +i B +i C = 0. Therefore, for i NP =0, the simplest solution is:

[0105] d max,0 =d mid,0 =d min,0 (15)

[0106] The duty cycle of each level of the three phases that satisfies (15) is:

[0107]

[0108] In a three-phase three-wire system, the sum of the three-phase voltage and current is zero, that is:

[0109]

[0110] From formula (16) and (17), we can get that i in formula (1) NP = 0 is independent of power factor and modulation depth, meaning that VSVPWM can achieve unconditional midpoint voltage balance within a switching cycle over the full power factor and modulation depth range. Within a switching cycle, the maximum phase of VSVPWM undergoes one switching operation at two levels (0 and 1), two switching operations at three levels (-1, 0, and 1) in the middle phase, and one switching operation at two levels (-1 and 0) in the minimum phase, for a total of four switching operations. This results in significant switching losses.

[0111] In traditional VSVPWM, the voltage intermediate phase modulation wave is decomposed into u' mid and u" mid The switching sequence of the voltage intermediate phase is obtained by adding the sequences obtained by comparing the dual modulation wave with the dual carrier wave. The three-phase carrier wave adopts convex carrier wave or concave carrier wave. Taking the three-phase carrier wave adopting concave carrier wave as an example, the common mode voltage will reach ±u DC / 3, such as Figure 5 (a) shows that the common-mode voltage is not reduced by this carrier method.

[0112] According to formula (16), in VSVPWM, the action time of the three-phase 0 level is the same, and the action time of the 1 level of the maximum voltage phase is exactly equal to the action time of the -1 level of the minimum voltage phase. Therefore, the carriers of the maximum voltage phase and the minimum voltage phase use different carriers, and the sum of the output levels of the maximum voltage phase and the minimum voltage phase is 0. At this time, regardless of whether the level of the voltage intermediate phase is -1, 0 or 1, the common-mode voltage can be reduced. Now, taking the case where the carriers of the maximum voltage phase, the intermediate phase, and the minimum phase use concave carriers, concave carriers, and convex carriers respectively, the waveform shape of the common-mode voltage within one switching cycle is exactly the same as the switching sequence of the voltage intermediate phase, and the common-mode voltage is reduced, as shown in the figure below: Figure 5 (b) shown.

[0113] Figure 6 shows that the use of CBPWM can ensure that the midpoint voltage is balanced and the common mode voltage is limited to ±u DC / 6 area. Among them, the gray area and the brown area are the midpoint voltage balance and the common mode voltage is limited to ±u DC / 6 area. The white area indicates that the midpoint voltage can be balanced but the common mode voltage cannot be limited to ±u DC / 6 area. Black indicates that the midpoint voltage cannot be balanced and the common mode voltage cannot be limited to ±u DC / 6 area.

[0114] Figure 7 shows the P SL_VSV With P SL_CBThe ratio of P SL_Hyb With P SL_CB The ratio, P SL_Hyb With P SL_VSV The ratio of P SL_Hyb 、P SL_CB 、P SL_VSV They are multi-objective coordinated CBPWM and VSVPWM hybrid modulation, and switching losses of CBPWM and VSVPWM.

[0115] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A multi-objective coordinated CBPWM and VSVPWM hybrid modulation method, characterized in that: The following steps are involved: S1: Collect the DC side voltage u of the three-level inverter DC , three-phase output phase current i A 、i B 、i C And the three-phase output phase voltage u A 、u B 、u C and obtaining first calculation data after performing calculation; The first data calculation data is specifically: the maximum current i max =max(i A ,i B ,i C ), minimum current i min =min(i A ,i B ,i C ), intermediate current i mid =mid(i A ,i B ,i C ), maximum voltage u max =max(u A ,u B ,u C ), minimum voltage u min =min(u A ,u B ,u C ) and the intermediate voltage u mid =mid(u A ,u B ,u C ); S2: Making a judgment based on the first calculated data, the midpoint voltage balance condition, and the common-mode voltage suppression condition; if both the midpoint voltage balance condition and the common-mode voltage suppression condition are satisfied, adopting the CBPWM modulation method; otherwise, adopting the VSVPWM modulation method; The process of determining the midpoint voltage balance condition is as follows: S201: Inject zero-sequence voltage u Z , determine whether the injected zero-sequence voltage meets the limiting condition, if so, proceed to step S202, otherwise the midpoint voltage balance is not met; S202: Determine when u mid >0, zero sequence voltage u Z Whether it meets: When u mid <0, zero sequence voltage u Z Whether it meets: If both conditions are met at the same time, the midpoint voltage balance is satisfied, otherwise the midpoint voltage balance is not satisfied; The limiting condition is that the three-phase voltage does not overshoot and the three-phase voltage polarity does not change; The specific process of determining the common-mode voltage suppression condition is as follows: The phase with positive voltage adopts concave carrier, and the phase with negative voltage adopts convex carrier; the phase with maximum voltage adopts concave carrier, and the phase with minimum voltage adopts convex carrier. mid and the injected zero-sequence voltage to determine the common-mode voltage rejection condition: This u mid >0, u Z >0; Limit the 1-level output corresponding to the voltage mid-phase to L max +L min = 0 to avoid high common mode voltage, where L max , L mid and L min Respectively represent u max ,u mid ,u min The corresponding instantaneous output level; When using concave carrier, only when d mid,1 <d min,-1 When the common mode voltage does not exceed u DC / 6, then we get: When using convex carrier, we solve: Right now It shows that in order to suppress the common mode voltage, a concave carrier should be used in the middle of the voltage when the modulation index is high; a convex carrier should be used in the middle of the voltage when the modulation index is low. This u mid <0, u Z <0 Limit the -1 level output of the voltage intermediate phase to L max +L min =0, the zero sequence voltage u Z Should meet the following requirements: When the voltage intermediate phase adopts a convex carrier, the solution is: When the voltage intermediate phase adopts a concave carrier, the solution is: The common mode voltage suppression condition is that the common mode voltage is limited to ±u DC / Within 6.

2. The multi-objective coordinated CBPWM and VSVPWM hybrid modulation method according to claim 1, characterized in that: After step S2, the method further includes: when VSVPWM modulation is adopted, different carriers are used for the voltage maximum phase and minimum phase carriers, thereby reducing the common mode voltage.

3. The multi-objective coordinated CBPWM and VSVPWM hybrid modulation method according to claim 2, characterized in that: When the determined modulation method is the VSVPWM modulation method, the maximum voltage phase and the minimum voltage phase carriers are configured to use different carriers under the VSVPWM modulation method, thereby reducing the common mode voltage, including the following steps: Step 301: Set the total average midpoint current i introduced by the three phases NP is zero, that is: d max,0 =d mid,0 =d min,0 ; Satisfy i NP The duty ratios of the three-phase levels for zero conditions are as follows: Step 302: according to the duty cycle of each level of the three phases, different carriers are set for the maximum voltage phase and the minimum voltage phase, and the sum of the output levels of the maximum voltage phase and the minimum voltage phase is 0, thereby reducing the common mode voltage.

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