Encapsulated Core Components and Manufacturing Method

Abstract

The present disclosure relates to semiconductor core components and methods of forming the same. The semiconductor core components described herein can be used to form semiconductor package components, PCB components, PCB spacer components, chip carrier components, intermediate carrier components (e.g., for graphics cards), etc. In one embodiment, a silicon substrate core is constructed by direct laser patterning. One or more conductive interconnections are formed in the substrate core, and one or more redistribution layers are formed on its surface. Subsequently, the silicon substrate core can be used as a core structure for semiconductor packages, PCBs, PCB spacers, chip carriers, intermediate carriers, etc.

Description

[0001] Background

[0002] Field

[0003] Embodiments of the present disclosure generally relate to electronic mounting structures and methods of forming the same. More specifically, the embodiments described herein relate to semiconductor packages and PCB assemblies and methods of forming the same. Background Art

[0004] Due to the increasing demand for miniaturized electronic devices and components, the demand for faster processing power using greater circuit density poses corresponding demands on the materials, structures, and processes used in the manufacture of such integrated circuit chips. However, in addition to these trends towards greater integration and performance, there is an ongoing pursuit of reducing manufacturing costs.

[0005] Generally, due to the ease of forming features and connections in organic packaging substrates and the relatively low packaging manufacturing costs associated with organic composite materials, integrated circuit chips have been fabricated on organic packaging substrates coupled to a circuit board (e.g., a printed circuit board (PCB)). However, with increasing circuit density and further miniaturization of electronic devices, the use of organic packaging substrates and conventional interconnect PCBs becomes impractical due to limitations in the material structure resolution for maintaining device scale and associated performance requirements. Recently, passive silicon interposers have been utilized as redistribution layers to fabricate 2.5D and 3D integrated circuits to compensate for some of the limitations associated with organic packaging substrates. The use of silicon interposers is driven by potential for low power chip-to-chip communication with high bandwidth density, and for heterogeneous integration in advanced electronic mounting and packaging applications. However, the formation of features (such as through-silicon vias (TSVs)) in silicon interposers remains difficult and costly. In particular, high aspect ratio through-silicon via etching, chemical mechanical planarization, and semiconductor back-end-of-line (BEOL) interconnects result in higher costs.

[0006] Accordingly, there is a need in the art for improved semiconductor packages and PCB core components with increased density and methods of forming the same. Summary of the Invention

[0007] The present disclosure generally relates to electronic mounting structures and methods of forming the same.

[0008] In one embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes a silicon core structure having a first surface opposite a second surface and a thickness of less than about 1000 μm. One or more conductive interconnects are formed through the silicon core structure and protrude from the first and second surfaces. The semiconductor device assembly further includes a first redistribution layer formed on the first surface and a second redistribution layer formed on the second surface. Each of the first redistribution layer and the second redistribution layer has one or more conductive contacts formed thereon.

[0009] In one embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes a silicon core structure, a passivation layer, and a dielectric layer. The silicon core structure has a thickness of less than about 1000 μm. The passivation layer surrounds the silicon core structure and includes a thermal oxide. The dielectric layer is formed on the passivation layer and includes an epoxy resin having silica particles disposed therein.

[0010] In one embodiment, a semiconductor device assembly is provided. The semiconductor device includes: a silicon core structure; a passivation layer surrounding the silicon structure and including a thermal oxide; a dielectric layer surrounding the passivation layer and formed of an epoxy resin; and a redistribution layer formed on the dielectric layer. The redistribution layer further includes: an adhesion layer formed on the dielectric layer and formed of molybdenum; a copper seed layer formed on the adhesion layer; and a copper layer formed on the copper seed layer.

[0011] Embodiments of the present disclosure may further provide a semiconductor device assembly, comprising: a silicon core structure having a first side opposite a second side; a first redistribution layer formed on the first side; and a second redistribution layer formed on the second side. A dielectric layer including a flowable epoxy resin material may also be formed on the first and second sides and have a thickness between about 5 μm and about 50 μm. The silicon core structure may have a thickness of less than 1500 μm; metal cladding layers formed on the first and second sides; and one or more conductive interconnects formed in one or more through-component vias and having surfaces exposed at the first and second sides. Each of the one or more through-component vias is circumferentially defined by the dielectric layer. Each of the first redistribution layer and the second redistribution layer has one or more conductive contacts formed thereon. The metal cladding layer circumferentially surrounds each of the one or more conductive interconnects. The metal cladding layer may have a thickness between about 100 nm and about 5 μm on substantially all exposed surfaces of the silicon core. The metal cladding layer may be further conductively coupled to ground through one or more conductive cladding connections disposed in the first redistribution layer and the second redistribution layer.

[0012] Embodiments of the present disclosure may further provide a semiconductor device assembly, comprising: a silicon core structure having a thickness less than 1500 μm; a metal or oxide layer formed on at least two surfaces of the silicon core structure; and a dielectric layer formed on the metal or oxide layer, the dielectric layer comprising an epoxy resin having silica particles. One or more through-holes circumferentially defined by the dielectric layer and having a diameter less than about 1500 μm are provided through the semiconductor device assembly and filled with copper. The dielectric layer circumferentially defining the one or more through-holes may be further circumferentially surrounded by a metal or oxide layer. A redistribution layer having one or more redistribution connections may be formed on the dielectric layer. The redistribution connections and the copper-filled through-holes may together form an inductive coil. The silicon core structure may further comprise one or more pockets containing silicon capacitors therein. A heat exchanger may be further provided above the dielectric layer or coupled to the metal or oxide layer.

[0013] Embodiments of the present disclosure may further provide a semiconductor device assembly, comprising: a silicon core structure having a first side opposite to a second side and a thickness less than 1500 μm; a nickel cladding layer formed on the first side and the second side; and a dielectric layer comprising an epoxy resin and surrounding the nickel cladding layer. An array of through-holes is provided through the silicon core structure and filled with a conductive material, each through-hole in the array of through-holes being defined by the dielectric layer. A redistribution layer is formed on the dielectric layer and comprises: a molybdenum-containing adhesive layer formed on the dielectric layer; a copper seed layer formed on the adhesive layer; and a copper layer formed on the copper seed layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To enable a detailed understanding of the above-described features of the present disclosure, a more specific description of the present disclosure as briefly summarized above may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and should not be considered as limiting its scope, and other equivalent embodiments may be permitted.

[0015] Figure 1A A cross-sectional view schematically illustrating a semiconductor core assembly according to an embodiment described herein.

[0016] Figure 1B A cross-sectional view schematically illustrating a semiconductor core assembly according to an embodiment described herein.

[0017] Figure 1C A cross-sectional view schematically illustrating a semiconductor core assembly according to an embodiment described herein.

[0018] Figure 2 is a flowchart of a process for forming a semiconductor core assembly according to an embodiment described herein Figure 1A and Figure 1B of.

[0019] Figure 3 is a flowchart illustrating a process for constructing a substrate for a semiconductor core component according to an embodiment described herein.

[0020] Figures 4A to 4D Schematically illustrates according to an embodiment described herein Figure 3 a cross-sectional view of a substrate at different stages of the depicted process.

[0021] Figure 5 is a flowchart illustrating a process for forming an insulating layer on a core structure of a semiconductor core component according to an embodiment described herein.

[0022] Figures 6A to 6I Schematically illustrates according to an embodiment described herein Figure 5 a cross-sectional view of a core structure at different stages of the depicted process.

[0023] Figure 7 is a flowchart illustrating a process for forming an insulating layer on a core structure of a semiconductor core component according to an embodiment described herein.

[0024] Figures 8A to 8E Schematically illustrates according to an embodiment described herein Figure 7 a cross-sectional view of a core structure at different stages of the depicted process.

[0025] Figure 9 is a flowchart illustrating a process for forming interconnects in a semiconductor core component according to an embodiment described herein.

[0026] Figures 10A to 10H Schematically illustrates according to an embodiment described herein Figure 9 a cross-sectional view of a semiconductor core component at different stages of the depicted process.

[0027] Figure 11 is a flowchart illustrating a process for forming a redistribution layer on a semiconductor core component according to an embodiment described herein.

[0028] Figures 12A to 12L Schematically illustrates according to an embodiment described herein Figure 11 a cross-sectional view of a semiconductor core component at different stages of the depicted process.

[0029] Figure 13A Schematically illustrates a cross-sectional view of a chip carrier structure including a semiconductor core component according to an embodiment described herein.

[0030] Figure 13BSchematic cross-sectional view of a PCB structure including a semiconductor core component according to an embodiment described herein.

[0031] Figure 13C Schematic cross-sectional view of a PCB structure including a semiconductor core component according to an embodiment described herein.

[0032] Figure 14A Schematic cross-sectional view of a semiconductor core component having one or more passive devices integrated therein according to an embodiment described herein.

[0033] Figure 14B Schematic cross-sectional view of a semiconductor core component having one or more passive devices integrated therein according to an embodiment described herein.

[0034] Figure 14C Schematic cross-sectional view of a semiconductor core component having one or more passive devices integrated therein according to an embodiment described herein.

[0035] Figure 15A Schematic cross-sectional view of a semiconductor core component having one or more passive devices integrated therein according to an embodiment described herein.

[0036] Figure 15B Schematic cross-sectional view of a semiconductor core component having one or more passive devices integrated therein according to an embodiment described herein.

[0037] Figure 15C Schematic cross-sectional view of an exemplary passive device to be integrated into a semiconductor core component according to an embodiment described herein.

[0038] Figure 15D Schematic cross-sectional view of a semiconductor core component having Figure 15C a passive device integrated therein according to an embodiment described herein.

[0039] Figure 16 Schematic cross-sectional view of a semiconductor core component having a bridging device integrated therein according to an embodiment described herein.

[0040] For ease of understanding, the same reference numerals are used throughout the figures to denote the same elements common to the figures whenever possible. It is contemplated that the elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. Detailed Description

[0041] The present disclosure relates to semiconductor core components and methods of forming the same. The semiconductor core components described herein can be used to form semiconductor package components, PCB components, PCB spacer components, chip carrier components, intermediate carrier components (e.g., for graphics cards), etc. In one embodiment, a silicon substrate core is constructed by direct laser patterning. One or more conductive interconnects are formed in the substrate core, and one or more redistribution layers are formed on its surface. Subsequently, the silicon substrate core can serve as a core structure for semiconductor packages, PCBs, PCB spacers, chip carriers, intermediate carriers, etc.

[0042] The methods and apparatuses disclosed herein, including novel thin form factor semiconductor core structures, are designed to replace more conventional semiconductor package, PCB, and chip carrier structures that utilize glass fiber-filled epoxy resin frames. Generally, the scalability of current semiconductor packages, PCBs, spacers, and chip carriers is limited by the lack of rigidity and planarity of the materials commonly used to form these various structures (e.g., epoxy molding compounds, FR-4 and FR-5 grades of glass fiber woven cloth with epoxy adhesives, etc.). The inherent properties of these materials create difficulties in patterning and utilizing fine (e.g., micron-scale) features formed therein. Additionally, as a result of the properties (e.g., insulation) of the materials currently in use, there may be a mismatch in the coefficient of thermal expansion (CTE) between the glass fiber frames, boards, molding compounds, and any chips disposed adjacent thereto. Accordingly, current package, PCB, spacer, and carrier structures require larger solder bumps with greater spacing to mitigate the effects of any warping caused by the CTE mismatch. As a result, conventional semiconductor package, PCB, spacer, and carrier frames are characterized by a low electrical bandwidth through the structure, resulting in a reduced overall power efficiency. The methods and apparatuses described herein provide semiconductor core structures for overcoming many of the drawbacks associated with the conventional semiconductor package, PCB, spacer, and carrier structures described above.

[0043] Figures 1A to 1C FIG. is a cross-sectional view of a thin form factor semiconductor core component 100 in accordance with some embodiments. The semiconductor core component 100 can be used for structural support and electrical interconnect of a semiconductor package mounted thereon. In a further example, the semiconductor core component 100 can serve as a carrier structure for surface mount devices such as chips or graphics cards. The semiconductor core component 100 generally includes a core structure 102, an optional passivation layer 104 ( Figure 1A and Figure 1B shown) or a metal clad layer 114 ( Figure 1C shown) and an insulating layer 118.

[0044] In one embodiment, the core structure 102 includes a patterned (e.g., structured) substrate formed of any suitable substrate material. For example, the core structure 102 includes a substrate formed of a group III-V compound semiconductor material, silicon (e.g., having a resistivity between about 1 and about 10 Ohm-cm or a conductivity of about 100 W / mK), crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, undoped high-resistivity silicon (e.g., float-zone silicon having a low dissolved oxygen content and a resistivity between about 5000 and about 10000 ohm-cm), doped or undoped polysilicon, silicon nitride, silicon carbide (e.g., having a conductivity of about 500 W / mK), quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In one embodiment, the core structure 102 includes a single-crystal p-type or n-type silicon substrate. In one embodiment, the core structure 102 includes a polycrystalline p-type or n-type silicon substrate. In another embodiment, the core structure 102 includes a p-type or n-type silicon solar substrate. Generally, the substrate used to form the core structure 102 can have a polygonal or circular shape. For example, the core structure 102 can include a substantially square silicon substrate with or without chamfered edges, the lateral dimension of the silicon substrate being between about 120 mm and about 180 mm, such as about 150 mm, or between about 156 mm and about 166 mm. In another example, the core structure 102 can include a circular silicon-containing wafer, the diameter of the wafer being between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 200 mm or about 300 mm.

[0045] The thickness T1 of the core structure 102 is between about 50 μm and about 1500 μm, such as the thickness T1 being between about 90 μm and about 780 μm. For example, the thickness T1 of the core structure 102 is between about 100 μm and about 300 μm, such as the thickness T1 being between about 110 μm and about 200 μm. In another example, the thickness T1 of the core structure 102 is between about 70 μm and about 150 μm, such as the thickness T1 being between about 100 μm and about 130 μm. In another example, the thickness T1 of the core structure 102 is between about 700 μm and about 800 μm, such as the thickness T1 being between about 725 μm and about 775 μm.

[0046] The core structure 102 further includes one or more holes or core vias 103 (hereinafter referred to as "core vias") formed therein to enable conductive interconnects to be routed through the core structure 102. Generally, the shape of the one or more core vias 103 is substantially cylindrical. However, other suitable configurations of the core vias 103 are also contemplated. The core vias 103 may be formed as individual and separate core vias 103 passing through the core structure 102, or formed in one or more groups or arrays. In one embodiment, the minimum pitch P1 between each of the core vias 103 is less than about 1000 μm, such as between about 25 μm and about 200 μm. For example, the pitch P1 is between about 40 μm and about 150 μm, such as between about 100 μm and about 140 μm, for example about 120 μm. In one embodiment, the diameter V1 of the one or more core vias 103 is less than about 500 μm, such as the diameter V1 is less than about 250 μm. For example, the diameter V1 of the core vias 103 is between about 25 μm and about 100 μm, such as the diameter V1 is between about 30 μm and about 60 μm. In one embodiment, the diameter V1 of the core vias 103 is about 40 μm.

[0047] Figure 1A and Figure 1B An optional passivation layer 104 may be formed on one or more surfaces of the core structure 102, including the first surface 106, the second surface 108, and one or more sidewalls of the core vias 103. In one embodiment, the passivation layer 104 is formed on substantially all of the outer surfaces of the core structure 102 such that the passivation layer 104 substantially surrounds the core structure 102. Thus, the passivation layer 104 provides a protective outer barrier for the core structure 102 against corrosion and other forms of damage. In one embodiment, the passivation layer 104 is formed of an oxide film or oxide layer (such as a thermal oxide layer). In some examples, the thickness of the passivation layer 104 is between about 100 nm and about 3 μm, such as the thickness is between about 200 nm and about 2.5 μm. In one example, the thickness of the passivation layer 104 is between about 300 nm and about 2 μm, such as the thickness is about 1.5 μm.

[0048] In Figure 1CIn the illustrated embodiment, the core structure 102 includes a metal cladding layer 114 that is used to replace the passivation layer 104 and is formed on one or more surfaces of the core structure 102 (including the first surface 106, the second surface 108, and one or more sidewalls of the core via 103). In one embodiment, the metal cladding layer 114 is formed on substantially all of the outer surfaces of the core structure 102 such that the metal cladding layer 114 substantially surrounds the core structure 102. The metal cladding layer 114 acts as a reference layer (e.g., a ground layer or a voltage supply layer) and is disposed on the substrate 302 to protect the subsequently formed connections from electromagnetic interference and to shield semiconductor signals for the semiconductor material (Si) used to form the core structure 102. In one embodiment, the metal cladding layer 114 includes a conductive metal layer (including nickel, aluminum, gold, cobalt, silver, palladium, tin, etc.). In one embodiment, the metal cladding layer 114 includes a metal layer (including an alloy or a pure metal (including nickel, aluminum, gold, cobalt, silver, palladium, tin, etc.)). The thickness of the metal cladding layer 114 is generally between about 50 nm and about 10 μm, such as between about 100 nm and about 5 μm.

[0049] An insulating layer 118 is formed on one or more surfaces of the core structure 102, the passivation layer 104, or the metal cladding layer 114 and may substantially cover the passivation layer 104, the metal cladding layer 114, and / or the core structure 102. Thus, as Figure 1A depicted, the insulating layer 118 may extend into the core via 103 and coat the passivation layer 104 or the metal cladding layer 114 formed on the sidewalls of the core via 103, or directly coat the core structure 102, thereby defining a diameter V2. In one embodiment, the thickness T2 of the insulating layer 118 from the outer surface of the core structure 102, the passivation layer 114, or the metal cladding layer 114 to the adjacent outer surface of the insulating layer 118 (e.g., the main surfaces 105, 107) is less than about 50 μm, such as the thickness T2 is less than about 20 μm. For example, the thickness T2 of the insulating layer 118 is between about 5 μm and about 10 μm.

[0050] In one embodiment, the insulating layer 118 is formed of a polymer-based dielectric material. For example, the insulating layer 118 is formed of a flowable build-up material. Thus, although referred to hereinafter as an "insulating layer", the insulating layer 118 may also be described as a dielectric layer. In a further embodiment, the insulating layer 118 is formed of an epoxy resin material having ceramic fillers (such as silicon dioxide (SiO2) particles). Other examples of ceramic fillers that may be used to form the insulating layer 118 include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanate (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. In some examples, the size of the particles of the ceramic filler used to form the insulating layer 118 is in the range between about 40 nm and about 1.5 μm (such as between about 80 nm and about 1 μm). For example, the size of the particles of the ceramic filler is in the range between about 200 nm and about 800 nm (such as between about 300 nm and about 600 nm). In some embodiments, the size of the particles included in the ceramic filler is less than about 10% of the width or diameter of the adjacent core vias 103 in the core structure 102, such as less than about 5% of the width or diameter of the core via 103.

[0051] One or more through-component holes or vias 113 (hereinafter referred to as "through-component vias") are formed to pass through the insulating layer 118, where the insulating layer 118 extends into the core via 103. For example, the through-component via 113 can be formed centrally within the core via 103, and the core via 103 has the insulating layer 118 disposed therein. Thus, the insulating layer 118 forms one or more sidewalls of the through-component via 113, where the diameter V2 of the through-component via 113 is less than the diameter V1 of the core via 103. In one embodiment, the diameter V2 of the through-component via 113 is less than about 100 μm, such as less than about 75 μm. For example, the diameter V2 of the through-component via 113 is less than about 50 μm, such as less than about 35 μm. In one embodiment, the diameter of the through-component via 113 is between about 25 μm and about 50 μm, such as the diameter is between about 35 μm and about 40 μm.

[0052] The through-component via 113 provides a channel through which one or more electrical interconnections 144 are formed in the semiconductor core component 100. In one embodiment, the electrical interconnection 144 is formed to pass through the entire thickness of the semiconductor core component 100 (i.e., from the first major surface 105 to the second major surface 107 of the semiconductor core component 100). For example, the longitudinal length of the electrical interconnection 144 corresponding to the total thickness of the semiconductor core component 100 is between about 50 μm and about 1000 μm, such as the longitudinal length is between about 200 μm and about 800 μm. In one example, the longitudinal length of the electrical interconnection 144 is between about 400 μm and about 600 μm, such as the longitudinal length is about 500 μm. In another embodiment, the electrical interconnection 144 is only formed to pass through a part of the thickness of the semiconductor core component 100. In a further embodiment, the electrical interconnection 144 can be from the major surface of the semiconductor core component 100 (such as Figure 1AThe depicted main surfaces 105, 107) protrude. The electrical interconnect 144 can be formed of any conductive material used in the fields of integrated circuits, circuit boards, chip carriers, etc. For example, the electrical interconnect 144 is formed of a metallic material (such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.).

[0053] In Figure 1A the depicted embodiment, the lateral thickness of the electrical interconnect 144 is equal to the diameter V2 of the through-component via 113 in which the electrical interconnect 144 is formed. In another embodiment (such as as Figure 1B depicted), the semiconductor core component 100 further includes an adhesion layer 140 and / or a seed layer 142 formed thereon for electrical isolation of the electrical interconnect 144. In one embodiment, the adhesion layer 140 is formed on the surface of the insulating layer 118 adjacent to the electrical interconnect 144 (including the sidewalls of the through-component via 113). Thus, as Figure 1B depicted, the lateral thickness of the electrical interconnect 144 is less than the diameter V2 of the through-component via 113 in which the electrical interconnect 144 is formed. In yet another embodiment, the electrical interconnect 144 only covers the surface of the sidewalls of the through-component via 113 and can thus have a hollow core passing therethrough.

[0054] The adhesion layer 140 can be formed of any suitable material (including but not limited to titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, etc.). In one embodiment, the thickness B1 of the adhesion layer 140 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness B1 of the adhesion layer 140 is between about 75 nm and about 125 nm, such as about 100 nm.

[0055] The optional seed layer 142 contains a conductive material, including but not limited to copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. The seed layer 142 can be formed on the adhesion layer 140 or directly on the sidewalls of the through-component via 113 (e.g., on the insulating layer 118 without an adhesion layer therebetween). In one embodiment, the thickness of the seed layer 142 is between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the thickness of the seed layer 142 is between about 150 nm and about 250 nm, such as about 200 nm.

[0056] In some embodiments (such as as Figure 1B depicted), the semiconductor core component 100 further includes one or more redistribution layers 150 formed on the first side 175 and / or the second side 177 of the semiconductor core component 100 (the redistribution layer 150 is in Figure 1B(depicted as being formed on the second side 177). In one embodiment, the redistribution layer 150 is formed of substantially the same material as the insulating layer 118 (e.g., a polymer-based dielectric material), and thus forms an extension thereof. In other embodiments, the redistribution layer 150 is formed of a material different from the insulating layer 118. For example, the redistribution layer 150 may be formed of a photo-definable polyimide material, a non-photosensitive polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicon dioxide, and / or silicon nitride. In another example, the redistribution layer 150 is formed of an inorganic dielectric material different from the insulating layer 118. In one embodiment, the thickness of the redistribution layer 150 is between about 5 μm and about 50 μm, such as between about 10 μm and about 40 μm. For example, the thickness of the redistribution layer 150 is between about 20 μm and about 30 μm, such as about 25 μm.

[0057] The redistribution layer 150 may include one or more redistribution connections 154 formed to pass through the redistribution vias 153 to relocate the contact points of the electrical interconnections 144 to desired positions on the surface of the semiconductor core component 100 (such as the main surfaces 105, 107). In some embodiments, the redistribution layer 150 may further include one or more external electrical connections (not shown) formed on the main surfaces 105, 107 (such as a ball grid array or solder balls). Generally, the redistribution vias 153 and the redistribution connections 154 have substantially similar or smaller lateral dimensions relative to the through-component vias 113 and the electrical interconnections 144. For example, the diameter V3 of the redistribution via 153 is between about 2 μm and about 50 μm, such as between about 10 μm and about 40 μm, such as between about 20 μm and about 30 μm. In addition, the redistribution layer 150 may include an adhesion layer 140 and a seed layer 142 formed on the surface adjacent to the redistribution connections 154 (including the sidewalls of the redistribution vias 153).

[0058] In embodiments where the core structure 102 includes a metal cladding layer 114 (such as Figure 1C), the metal cladding layer 114 is further coupled to at least one cladding connection 116 to form connection points on at least one side of the semiconductor core component 100. In some embodiments, the metal cladding layer 114 is coupled to two cladding connections 116 formed on opposite sides of the semiconductor core component 100. The cladding connections 116 may be connected to a common ground (such as the exemplary ground 119) used by one or more semiconductor devices stacked (e.g., above or below) the semiconductor core component 100. Alternatively, the cladding connections 116 are connected to a reference voltage (such as a power voltage). As shown, the cladding connections 116 are formed in the insulating layer 118 and connect the metal cladding layer 114 to the connection ends of the cladding connections 116 disposed on or at the surface of the semiconductor core component 100 (such as the main surfaces 107 and 105), so that the metal cladding layer 114 can be connected to an external common ground or reference voltage (illustrated as an exemplary connection to the ground 119 in Figure 1C ).

[0059] The metal cladding layer 114 can be electrically coupled to the external ground 119 via the cladding connection 116 and any other suitable coupling member. For example, the cladding connection 116 can be indirectly coupled to the external ground 119 through solder bumps on opposite sides of the semiconductor core component 100. In some embodiments, before being coupled to the external ground 119, the cladding connection 116 can first pass through a separate electronic system or device wiring. The utilization of the ground path between the metal cladding layer 114 and the external ground 119 reduces or eliminates interference between the interconnect 144 and / or the redistribution connection 154 and prevents short circuits of the integrated circuits coupled thereto (which may damage the semiconductor core component 100 and any system or device integrated or stacked therewith).

[0060] Similar to the electrical interconnect 144 and the redistribution connection 154, the cladding connection 116 is formed of any suitable conductive material (including but not limited to nickel, copper, aluminum, gold, cobalt, silver, palladium, tin, etc.). The cladding connection 116 is deposited or plated through a cladding via 123, which is substantially similar to the through-component via 113 or the redistribution via 153, but only crosses a portion of the semiconductor core component 100 (e.g., from its surface to the core structure 102). Thus, the cladding via 123 can be formed to pass through the insulating layer 118, directly above or below the core structure 102 having the metal cladding layer 114 formed thereon. Additionally, similar to the electrical interconnect 144 and the redistribution connection 154, the cladding connection 116 can completely fill the cladding via 123 or line its inner peripheral wall, thereby having a hollow core.

[0061] In some embodiments, the lateral dimensions (e.g., diameter and lateral thickness, respectively) of the encapsulated vias 123 and the encapsulated connection 116 are substantially similar to diameter V2. In some embodiments, the adhesive layer 140 and the seed layer 142 are formed in the encapsulated vias 123, so the diameter of the encapsulated vias 123 can be substantially similar to diameter V2, and the lateral thickness of the encapsulated connection 116 can be less than diameter V2, such as the lateral thickness being substantially similar to diameter V3. In some embodiments, the diameter of the encapsulated vias 123 is about 5 μm.

[0062] Figure 2 Flowchart of a representative method 200 for forming a semiconductor core component is illustrated. Method 200 has a plurality of operations 210, 220, 230, and 240. Each operation is described in more detail with reference to Figures 3 to 12L which is described in more detail. The method may include one or more additional operations that are performed before any defined operation, between two defined operations, or after all defined operations (unless the context precludes the possibility).

[0063] Generally speaking, method 200 includes: at operation 210, constructing a substrate that serves as a core structure (e.g., a frame), with reference to Figure 3 and Figures 4A to 4D which is described in further detail. At operation 220, an insulating layer is formed on the core structure 102, and with reference to Figure 5 and Figures 6A to 6I and Figure 7 and Figures 8A to 8E which is described in more detail. At operation 230, one or more interconnects are formed to pass through the core structure 102 and the insulating layer, and with reference to Figure 9 and Figures 10A to 10H which is described in more detail. At operation 240, a redistribution layer is formed on the insulating layer to relocate the contact points of the interconnects to desired positions on the surface of the assembled core component, and then the core component is diced into individual chips. In some embodiments, one or more additional redistribution layers may be formed in addition to the first redistribution layer, with reference to Figure 11 and Figures 12A to 12L which is described in more detail.

[0064] Figure 3 Flowchart of a representative method 300 for constructing a substrate 400 to serve as a core structure is illustrated. Figures 4A to 4D Schematically illustrates Figure 3 Cross-sectional views of the substrate 400 at various stages of the substrate structuring process 300 represented. Thus, for clarity, Figure 3 and Figures 4A to 4D are described together herein.

[0065] Method 300 begins at operation 310 and corresponds to Figure 4A . As described with reference to the core structure 102 above, the substrate 400 is formed of any suitable substrate material, including but not limited to group III-V compound semiconductor materials, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, undoped high resistivity silicon, doped or undoped polysilicon, silicon nitride, silicon carbide, quartz, glass materials (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In one embodiment, the substrate 400 is a single crystal p-type or n-type silicon substrate. In one embodiment, the substrate 400 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, the substrate 400 is a p-type or n-type silicon solar substrate. The substrate 400 may further have a polygonal or circular shape. For example, the substrate 400 may include a substantially square silicon substrate with or without chamfered edges, the lateral dimension of which is between about 120 mm and about 180 mm. In another example, the substrate 400 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 200 mm or about 300 mm. Unless otherwise stated, the embodiments and examples described herein are carried out on substrates having a thickness between about 50 μm and about 1500 μm, such as a thickness between about 90 μm and about 780 μm. For example, the thickness of the substrate 400 is between about 100 μm and about 300 μm, such as a thickness between about 110 μm and about 200 μm.

[0066] Prior to operation 310, the substrate 400 may be sliced and separated from the bulk material by wire sawing, scribing and breaking, mechanical abrasive sawing, or laser cutting. Slicing typically causes mechanical defects or deformities (such as scratches, microcracks, chipping, and other mechanical defects) in the surface of the substrate formed from the slice. Thus, at operation 310, the substrate 400 is exposed to a first damage removal process to smooth and planarize its surface and remove mechanical defects in preparation for subsequent structuring operations. In some embodiments, the substrate 400 may be further thinned by adjusting the process parameters of the first damage process. For example, as the exposure to the first damage removal process increases, the thickness of the substrate 400 may be reduced.

[0067] At operation 310, the first damage removal process includes exposing the substrate 400 to a substrate polishing process and / or an etching process, and then exposing it to a rinse and dry process. In some embodiments, operation 310 includes a chemical mechanical polishing (CMP) process. In one embodiment, the etching process is a wet etching process including a buffered etching process that selectively removes desired materials (e.g., contaminants and other undesired compounds). In other embodiments, the etching process is a wet etching process utilizing an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the wet etching process. In one embodiment, the substrate 400 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 400 is immersed in an aqueous KOH etching solution for etching.

[0068] In some embodiments, during the etching process, the etching solution is heated to a temperature between about 30 °C and about 100 °C (such as between about 40 °C and 90 °C). For example, the etching solution is heated to a temperature of about 70 °C. In other embodiments, at operation 310, the etching process is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes. The thickness of the substrate 400 is adjusted by controlling the time the substrate 400 is exposed to the etchant (e.g., the etching solution) used during the etching process. For example, as the exposure to the etchant increases, the final thickness of the substrate 400 decreases. Alternatively, as the exposure to the etchant decreases, the substrate 400 can have a greater final thickness.

[0069] At operation 320, the now planarized and substantially defect-free substrate 400 is patterned to form one or more core vias 403 (four core vias 403 are depicted in the cross-section of the Figure 4B substrate 400). The core vias 403 are used to form direct contact electrical interconnections through the substrate 400.

[0070] Generally, one or more core vias 403 can be formed by laser ablation (e.g., direct laser patterning). Any suitable laser ablation system can be utilized to form one or more core vias 403. In some examples, the laser ablation system utilizes an infrared (IR) laser source. In some examples, the laser source is a picosecond ultraviolet (UV) laser. In other examples, the laser is a femtosecond UV laser. In still other examples, the laser source is a femtosecond green laser. The laser source of the laser ablation system generates a continuous laser beam or a pulsed laser beam for patterning the substrate 400. For example, the laser source can generate a pulsed laser beam having a frequency between 5 kHz and 500 kHz (such as between 10 kHz and about 200 kHz). In one example, the laser source is configured to deliver a pulsed laser beam with an output power between about 10 watts and about 100 watts, a wavelength between about 200 nm and about 1200 nm, and a pulse duration between about 10 ns and about 5000 ns. The laser source is configured to form any desired pattern of features (including core vias 403) in the substrate 400.

[0071] In some embodiments, prior to patterning, the substrate 400 is optionally coupled to a carrier plate (not shown). The optional carrier plate can provide mechanical support for the substrate 400 during patterning of the substrate 400 and can prevent the substrate 400 from breaking. The carrier plate can be formed of any suitable chemically stable and thermally stable rigid material (including but not limited to glass, ceramic, metal, etc.). In some examples, the thickness of the carrier plate is between about 1 mm and about 10 mm, such as between about 2 mm and about 5 mm. In one embodiment, the carrier plate has a textured surface. In other embodiments, the carrier plate has a polished or smoothed surface. The substrate 400 can be coupled to the carrier plate using any suitable temporary bonding material (including but not limited to wax, glue, or similar bonding materials).

[0072] In some embodiments, patterning the substrate 400 may cause undesirable mechanical defects on the surface of the substrate 400, including chipping, cracking, and / or warping. Thus, after performing operation 320 to form the core vias 403 in the substrate 400, at operation 330, the substrate 400 is exposed to a second damage removal and cleaning process (substantially similar to the first damage removal process at operation 310) to smooth the surface of the substrate 400 and remove undesirable debris. As described above, the second damage removal process includes exposing the substrate 400 to a wet or dry etching process, followed by rinsing and drying. The etching process is carried out for a predetermined duration to smooth the surface of the substrate 400, and in particular the surface exposed to the laser patterning operation. On the other hand, the etching process is used to remove any undesirable debris remaining on the substrate 400 from the patterning process.

[0073] After removing mechanical defects in substrate 400 at operation 330, at operation 340 and Figure 4D the substrate 400 is exposed to a passivation or metallization process to grow or deposit a passivation layer (such as oxide layer 404) or a metal layer (such as metal cladding layer 414) on a desired surface of the substrate 400 (e.g., the entire surface of the substrate 400). In one embodiment, the passivation process is a thermal oxidation process. The thermal oxidation process is carried out at a temperature between about 800 °C and about 1200 °C (e.g., between about 850 °C and about 1150 °C). For example, the thermal oxidation process is carried out at a temperature between about 900 °C and about 1100 °C (e.g., between about 950 °C and about 1050 °C). In one embodiment, the thermal oxidation process is a wet oxidation process using water vapor as an oxidant. In one embodiment, the thermal oxidation process is a dry oxidation process using molecular oxygen as an oxidant. It is contemplated that at operation 340, the substrate 400 can be exposed to any suitable passivation process to form an oxide layer 404 or any other suitable passivation layer thereon. The resulting oxide layer 404 typically has a thickness between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. For example, the thickness of the oxide layer 404 is between about 300 nm and about 2 μm, such as about 1.5 μm. Alternatively, the metallization process can be any suitable metal deposition process (including chemical deposition process, electroplating process, chemical vapor deposition process, evaporation deposition process, and / or atomic layer deposition process). In certain embodiments, at least a portion of the metal cladding layer 414 includes a deposited nickel (Ni) layer formed by direct displacement or displacement plating on the surface of the substrate 400 (e.g., an n-Si substrate or a p-Si substrate). For example, the substrate 400 is exposed to a nickel displacement plating bath having a composition including 0.5 M of NiSO4 and NH4OH at a temperature between about 60 °C and about 95 °C and a pH of about 11 for a period of time between about 2 minutes and about 4 minutes. In the absence of a reducing agent, exposing the silicon substrate 400 to an aqueous electrolyte having nickel ions causes a local oxidation / reduction reaction at the surface of the substrate 400, thereby resulting in the plating of metallic nickel thereon. Thus, nickel displacement plating enables the selective formation of a thin and pure nickel layer on the silicon material of the substrate 400 using a stable solution. Additionally, the process is self-limiting, so once all surfaces of the substrate 400 are plated (e.g., there is no remaining silicon on which nickel can form), the reaction stops. In certain embodiments, the nickel metal cladding layer 414 can be used as a seed layer for plating additional metal layers (such as plating nickel or copper by electroless and / or electroplating methods). In a further embodiment, the substrate 400 is exposed to an SC-1 pre-cleaning solution and an HF oxide etching solution prior to the nickel displacement plating bath to promote the adhesion of the nickel metal cladding layer 414 to the substrate 400.

[0074] After passivation or metallization, the substrate 400 is ready to be used as the core structure 402 for the formation of core components such as the semiconductor core component 100. Figure 5 And Figure 7 Flowcharts of representative methods 500 and 700 for forming the insulating layer 618 on the core structure 402 are respectively illustrated. Figures 6A to 6I Schematically illustrate Figure 5 Cross-sectional views of the core structure 402 at different stages of the depicted method 500, while Figures 8A to 8E Schematically illustrate Figure 7 Cross-sectional views of the core structure 402 at different stages of the depicted method 700. For clarity, they are described together herein Figure 5 And Figures 6A to 6I , and they are described together herein Figure 7 And Figures 8A to 8E .

[0075] Generally, method 500 begins at operations 502 and Figure 6A where the first surface 406 of the core structure 402 at the first side 475 (now having core vias 403 formed therein and an oxide layer 404 formed thereon) is placed and fixed on the first insulating film 616a. In one embodiment, the first insulating film 616a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 616a includes one or more layers formed of a flowable build-up material. In one embodiment, the first insulating film 616a includes a flowable epoxy resin layer 618a. Generally, the thickness of the epoxy resin layer 618a is less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the thickness of the epoxy resin layer 618a is between about 10 μm and about 25 μm.

[0076] The epoxy resin layer 618a can be formed of an epoxy resin containing ceramic fillers, such as an epoxy resin filled with silica (SiO2) particles (e.g., containing silica (SiO2) particles). Other examples of ceramic fillers that can be used to form the epoxy resin layer 618a and other layers of the insulating film 616a include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12) Magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. In some examples, the size of the particles of the ceramic filler used to form the epoxy resin layer 618a is in the range between about 40 nm and about 1.5 μm (such as between about 80 nm and about 1 μm). For example, the size of the particles of the ceramic filler used to form the epoxy resin layer 618a is in the range between about 200 nm and about 800 nm (such as between about 300 nm and about 600 nm).

[0077] In some embodiments, the first insulating film 616a further includes one or more protective layers. For example, the first insulating film 616a includes a polyethylene terephthalate (PET) protective layer 622a (such as a biaxial PET protective layer 622a). However, any suitable number and combination of layers and materials are contemplated for the first insulating film 616a. In some embodiments, the thickness of the entire insulating film 616a is less than about 120 μm, such as less than about 90 μm.

[0078] In some embodiments, after the core structure 402 is fixed to the first insulating film 616a, the core structure 402 can then be placed on a carrier 624 adjacent to its first side 475 for additional mechanical stability during later processing operations. Generally, the carrier 624 is formed of any suitable mechanically stable and thermally stable material capable of withstanding temperatures above 100°C. For example, in one embodiment, the carrier 624 comprises polytetrafluoroethylene (PTFE). In another example, the carrier 624 is formed of polyethylene terephthalate (PET).

[0079] At operation 504 and Figure 6B a first protective film 660 is fixed to a second surface 408 on the second side 477 of the core structure 402. The protective film 660 is coupled to the core structure 402 on the second side 477 and is opposite the first insulating film 616a such that the protective film 660 covers the core through-hole 403. In one embodiment, the protective film 660 is formed of a material similar to the protective layer 622a. For example, the protective film 660 is formed of PET (such as biaxial PET). However, the protective film 660 can be formed of any suitable protective material. In some embodiments, the thickness of the protective film 660 is between about 50 μm and about 150 μm.

[0080] At operation 506, the core structure 402 (now fixed to the insulating film 616a at the first side 475 and to the protective film 660 at the second side 477) is exposed to a first lamination process. During the lamination process, the core structure 402 is exposed to an elevated temperature, causing the epoxy resin layer 618a of the insulating film 616a to soften and flow into the open void or volume between the insulating film 616a and the protective film 660 (such as into the core via 403). Thus, as Figure 6C depicted, the core via 403 is at least partially filled (e.g., occupied) with the insulating material of the epoxy resin layer 618a. Additionally, the core structure 402 is partially surrounded by the insulating material of the epoxy resin layer 618a.

[0081] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In one embodiment, the lamination process is performed by using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 pound per square inch and about 150 pounds per square inch while applying a temperature between about 80°C and about 140°C to the core structure 402 and the insulating film 616a for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 pounds per square inch and about 100 pounds per square inch and a temperature between about 100°C and about 120°C for a period of time between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of about 5 minutes.

[0082] At operation 508, the protective film 660 is removed, and the core structure 402 (now having the laminated insulating material of the epoxy resin layer 618a that at least partially surrounds the core structure 402 and partially fills the core via 403) is placed on a second protective film 662. As Figure 6DAs depicted, a second protective film 662 is coupled to the core structure 402 adjacent to the first side 475 such that the second protective film 662 is disposed against (e.g., adjacent to) the protective layer 622a of the insulating film 616a. In some embodiments, the core structure 402 (now coupled to the protective film 662) may optionally be placed on a carrier 624 for additional mechanical support on the first side 475. In some embodiments, the protective film 662 is placed on the carrier 624 before coupling the protective film 662 to the core structure 402. Generally, the protective film 662 is substantially similar in composition to the protective film 660. For example, the protective film 662 may be formed of PET (such as biaxial PET). However, the protective film 662 may be formed of any suitable protective material. In some embodiments, the thickness of the protective film 662 is between about 50 μm and about 150 μm.

[0083] After coupling the core structure 402 to the second protective film 662, at operation 510 and Figure 6E at, a second insulating film 616b (substantially similar to the first insulating film 616a) is placed over the second side 477, thereby replacing the protective film 660. In one embodiment, the second insulating film 616b is positioned on the second side 477 of the core structure 402 such that the epoxy resin layer 618b of the second insulating film 616b covers the core via 403. In one embodiment, the placement of the second insulating film 616b on the core structure 402 may form one or more voids between the insulating film 616b and the laminated insulating material of the epoxy resin layer 618a (partially surrounding the core structure 402 and partially filling the core via 403). Similar to the insulating film 616a, the second insulating film 616b may include one or more layers formed of a polymer-based dielectric material. As Figure 6E depicted, the second insulating film 616b includes an epoxy resin layer 618b that is substantially similar to the epoxy resin layer 618a described above. The second insulating film 616b may further include a protective layer 622b formed of a material similar to the protective layer 622a (such as PET).

[0084] At operation 512, as Figure 6F depicted, a third protective film 664 is placed over the second insulating film 616b. Generally, the protective film 664 is substantially similar in composition to the protective films 660, 662. For example, the protective film 664 is formed of PET (such as biaxial PET). However, the protective film 664 may be formed of any suitable protective material. In some embodiments, the thickness of the protective film 664 is between about 50 μm and about 150 μm.

[0085] At operation 514 and Figure 6GAt this point, the core structure 402 (now fixed to the insulating film 616b and the protective film 664 on the second side 477 and fixed to the protective film 662 and the optional carrier 624 on the first side 475) is exposed to a second lamination process. Similar to the lamination process at operation 504, the core structure 402 is exposed to an elevated temperature, causing the epoxy resin layer 618b of the insulating film 616b to soften and flow into any open voids or volumes between the laminated insulating materials of the insulating film 616b and the epoxy resin layer 618a, thereby integrating itself with the insulating material of the epoxy resin layer 618a. As a result, the core vias 403 become completely filled (e.g., encapsulated, sealed) with the insulating materials of the two epoxy resin layers 618a, 618b.

[0086] In one embodiment, the second lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In one embodiment, the lamination process is performed by using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 psi and about 150 psi while applying a temperature between about 80°C and about 140°C to the core structure 402 and the insulating film 616a for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 psi and about 100 psi and a temperature between about 100°C and about 120°C for a period of time between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of about 5 minutes.

[0087] After lamination, at operation 516, the core structure 402 is detached from the carrier 624, and the protective films 662, 664 are removed, resulting in the laminated intermediate core assembly 602. As Figure 6H depicted, the intermediate core assembly 602 includes the core structure 402 having one or more core vias 403 that are formed through the core structure 402 and filled with the insulating dielectric materials of the insulating films 616a, 616b. The insulating dielectric materials of the epoxy resin layers 618a, 618b further coat the core structure 402 having an oxide layer 404 formed thereon such that the insulating material covers at least two surfaces or sides (e.g., surfaces 406, 408) of the core structure 402. In some examples, at operation 516, the protective layers 622a, 622b are also removed from the intermediate core assembly 602. Generally, the protective layers 622a and 622b, the carrier 624, and the protective films 662 and 664 are removed from the intermediate core assembly 602 by any suitable mechanical process (e.g., peeling from the intermediate core assembly 602).

[0088] After removing the protective layers 622a, 622b and the protective films 662, 664, the intermediate core assembly 602 is exposed to a curing process to fully cure (i.e., harden through chemical reaction and crosslinking) the insulating dielectric materials of the epoxy resin layers 618a, 618b, thereby forming the insulating layer 618. The insulating layer 618 substantially surrounds the core structure 402 and fills the core vias 403. For example, the insulating layer 618 at least contacts or encapsulates 107, 477 (including the surfaces 406, 408) of the core structure 402.

[0089] In one embodiment, the curing process is performed at a high temperature to fully cure the intermediate core assembly 602. For example, the curing process is performed at a temperature between about 140°C and about 220°C and for a period between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C and for a period between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C and for a period of about 30 minutes. In a further embodiment, the curing process at operation 516 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0090] After curing, at operation 518, one or more through-component vias 613 are drilled through the intermediate core assembly 602, thereby forming channels through the entire thickness of the intermediate core assembly 602 for subsequent interconnect formation. In some embodiments, the intermediate core assembly 602 may be placed on a carrier (such as carrier 624) for mechanical support during the formation of the through-component vias 613. The through-component vias 613 are drilled through the core vias 403 formed in the core structure 402 and subsequently filled with the insulating layer 618. Thus, the insulating layer 618 filled in the core vias 403 may circumferentially surround the through-component vias 613. By lining the walls of the core vias 403 with the epoxy resin material of the insulating layer 618 containing ceramic fillers, compared to other conventional interconnect structures using conventional via insulation liners or films, the capacitive coupling (refer to Figure 10G , Figure 11 and Figure 12K and Figure 12L description) between the conductive silicon-based core structure 402 and the interconnect 1044 in the completed (e.g., final) semiconductor core assembly 1270 (refer to Figure 9 and Figures 10A to 10H description) is significantly reduced. In addition, the flowable nature of the epoxy resin material of the insulating layer 618 enables more consistent and reliable encapsulation and insulation, thereby enhancing the electrical performance by minimizing the leakage current of the completed semiconductor core assembly 1270.

[0091] In one embodiment, the diameter of the through-component via 613 is less than about 100 μm, such as less than about 75 μm. For example, the diameter of the through-component via 613 is less than about 50 μm, such as less than about 35 μm. In some embodiments, the diameter of the through-component via 613 is between about 25 μm and about 50 μm, such as between about 35 μm and about 40 μm. In one embodiment, any suitable mechanical process is used to form the through-component via 613. For example, a mechanical drilling process is used to form the through-component via 613. In one embodiment, the through-component via 613 through the intermediate core component 602 is formed by laser ablation. For example, an ultraviolet laser is used to form the through-component via 613. In one embodiment, the frequency of the laser source for laser ablation is between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse energy between about 50 microjoules (μJ) and about 500 μJ and a pulse duration between about 10 ns and about 100 ns. The use of an epoxy resin material containing small ceramic filler particles further facilitates more precise and accurate laser patterning of small-diameter vias, such as the through-component via 613, because the small ceramic filler particles in the epoxy resin material exhibit reduced laser reflection, scattering, diffraction, and transmission of the laser leaving the area where the via is to be formed.

[0092] In some embodiments, the through-component via 613 is formed within (e.g., through) the core via 403 such that the average thickness of the remaining epoxy resin material containing ceramic filler (e.g., dielectric insulating material) on the sidewalls of the core via 403 is between about 1 μm and about 50 μm. For example, the average thickness of the remaining epoxy resin material containing ceramic filler on the sidewalls of the core via 403 is between about 5 μm and about 40 μm, such as between about 10 μm and about 30 μm. Thus, the resulting structure after forming the through-component via 613 can be described as a "via-in-via" (e.g., a via formed centrally within the dielectric material in the via of the core structure). In certain embodiments, the via-in-via structure includes dielectric sidewall passivation, which consists of an epoxy resin material filled with ceramic particles and is disposed on a thin layer of thermally grown oxide formed on the sidewalls of the core via 403.

[0093] In embodiments where the metal cladding layers 114, 414 are formed over the core structure 102, one or more cladding vias 123 can also be formed at operation 518 to provide channels for cladding connections 116 (as Figure 1CAs described above, the encapsulated vias 123 are formed in the insulating layer 118 above and / or below the core structure 102 such that the metal encapsulation layers 114, 414 can be coupled to the encapsulated connection 116, enabling the metal encapsulation layers 114, 414 to be connected to an external common ground or reference voltage. In one embodiment, the diameter of the encapsulated via 123 is less than about 100 μm, such as less than about 75 μm. For example, the diameter of the encapsulated via 123 is less than about 50 μm, such as less than about 35 μm. In some embodiments, the diameter of the encapsulated via 123 is between about 5 μm and about 25 μm, such as between about 10 μm and about 20 μm.

[0094] After forming the through-component vias 613 and / or the encapsulated vias 123 (as Figure 1C shown), the intermediate core component 602 is exposed to a cleaning process. During the cleaning process, any unwanted residues and / or debris resulting from the laser ablation during the formation of the through-component vias 613 and / or the encapsulated vias 123 are removed from the intermediate core component 602. Thus, the cleaning process cleans the vias for subsequent metallization. In one embodiment, the cleaning process is a wet cleaning process. Any suitable solvent, etchant, and / or combination thereof can be used for the wet cleaning process. In one example, methanol can be used as the solvent, and copper(II) chloride dihydrate (CuCl2·H2O) can be used as the etchant. Depending on the residue thickness, the exposure duration of the intermediate core component 602 to the wet cleaning process can vary. In another embodiment, the cleaning process is a dry cleaning process. For example, the cleaning process can be a plasma cleaning process using an O2 / CF4 gas mixture. The plasma cleaning process can include generating a plasma by applying a power of about 700 W and flowing O2:CF4 at a ratio of about 10:1 (e.g., 100:10 sccm) for a period between about 60 seconds and about 120 seconds. In a further embodiment, the cleaning process is a combination of wet and dry processes.

[0095] After the cleaning process at operation 518, the intermediate core component 602 is ready to have interconnect paths formed therein, which will be described below with reference to Figure 9 and Figures 10A to 10H which will be described below with reference to

[0096] As described above, Figure 5 and Figures 6A to 6I FIGS. illustrate a representative method 500 for forming the intermediate core component 602. Figure 7 and Figures 8A to 8EAn alternative method 700 whose illustration is basically similar to method 500 but has fewer operations. Generally speaking, method 700 includes five operations 710 to 750. However, operations 710, 740, and 750 of method 700 are basically similar to operations 502, 516, and 518 of method 500 respectively. Therefore, for the sake of clarity, only operations 720, 730, and 740 depicted respectively are described herein. Figure 8B , Figure 8C and Figure 8D respectively.

[0097] At operation 720 and Figure 8B , after fixing the first insulating film 616a to the first surface 406 on the first side 475 of the core structure 402, the second insulating film 616b is coupled to the second surface 408 on the opposite side 477. In some embodiments, the second insulating film 616b is positioned on the surface 408 of the core structure 402 such that the epoxy resin layer 618b of the second insulating film 616b covers all the core vias 403. As Figure 8B depicted, the core vias 403 form one or more voids or gaps between the insulating films 616a and 616b. In some embodiments, the second carrier 625 is fixed to the protective layer 622b of the second insulating film 616b for additional mechanical support during later processing operations.

[0098] At operation 730 and Figure 8C , the core structure 402 (now fixed to the insulating films 616a and 616b on opposite sides of the core structure 402) is exposed to a single lamination process. During the single lamination process, the core structure 402 is exposed to an elevated temperature, causing the epoxy resin layers 618a and 618b of the two insulating films 616a and 616b to soften and flow into the open voids or volumes established by the core vias 403 between the insulating films 616a and 616b. Therefore, the core vias 403 are filled with the insulating material of the epoxy resin layers 618a and 618b.

[0099] Similar to that referred to Figure 5 and Figures 6A to 6IThe described lamination process, the lamination process at operation 730 can be a vacuum lamination process that can be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed by using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 psi and about 150 psi while applying a temperature between about 80°C and about 140°C to the core structure 402 and the insulating films 616a, 616b for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psi and about 100 psi and a temperature between about 100°C and about 120°C, and for a period of time between about 2 minutes and 10 minutes. For example, the lamination process at operation 730 is performed at a temperature of about 110°C for a period of about 5 minutes.

[0100] At operation 740, one or more protective layers of the insulating films 616a, 616b are removed from the core structure 402, thereby producing a laminated intermediate core assembly 602. In one example, the protective layers 622a, 622b are removed from the core structure 402, and thus the intermediate core assembly 602 is also separated from the first carrier 624 and the second carrier 625. Generally, the protective layers 622a, 622b and the carriers 624, 625 are removed by any suitable mechanical process (such as peeling them off). As Figure 8D depicted, the intermediate core assembly 602 includes a core structure 402 having one or more core through-holes 403 formed in the core structure 402 and filled with the insulating dielectric material of the epoxy resin layers 618a and 618b. The insulating material further coats the core structure 402 such that the insulating material covers at least two surfaces or sides of the core structure 402 (e.g., surfaces 406, 408).

[0101] After the protective layers 622a, 622b are removed, the intermediate core assembly 602 is exposed to a curing process to fully cure the insulating dielectric material of the epoxy resin layers 618a, 618b. The curing of the insulating material results in the formation of the insulating layer 618. As Figure 8D depicted and similar to operation 516 corresponding to Figure 6H the insulating layer 618 substantially surrounds the core structure 402 and fills the core through-holes 403.

[0102] In one embodiment, the curing process is performed at an elevated temperature to fully cure the intermediate core component 602. For example, the curing process is performed at a temperature between about 140°C and about 220°C and for a period of time between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C and for a period of time between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C and for a period of time of about 30 minutes. In a further embodiment, the curing process at operation 740 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0103] After curing at operation 740, method 700 is substantially similar to operation 518 of method 500. Accordingly, one or more through-component vias 613 and / or wrap vias 123 (as Figure 1C shown) are drilled through the intermediate core component 602, and then the intermediate core component 602 is exposed to a decontamination process. After completion of the decontamination process, the intermediate core component 602 is ready to have interconnect paths formed therein, as described below.

[0104] Figure 9 FIG. is a flow chart of a representative method 900 for forming electrical interconnects through an intermediate core component 602. Figures 10A to 10H Schematically illustrates Figure 9 cross-sectional views of the intermediate core component 602 at different stages of the process of the depicted method 900. Accordingly, for clarity, the present description is presented together Figure 9 and Figures 10A to 10H .

[0105] In one embodiment, the electrical interconnects formed through the intermediate core component 602 are formed of copper. Accordingly, method 900 generally begins at operations 910 and Figure 10A wherein the intermediate core component 602 having through-component vias 613 formed therein has a barrier or adhesion layer 1040 and / or a seed layer 1042 formed thereon. A partial enlarged view of the adhesion layer 1040 and the seed layer 1042 formed on the intermediate core component 602 is depicted in Figure 10H for reference. The adhesion layer 1040 may be formed on a desired surface of the insulating layer 618 (such as surfaces corresponding to the main surfaces 1005, 1007 of the intermediate core component 602 and the sidewalls of the through-component vias 613 and / or wrap vias 123) to assist in promoting the adhesion of the subsequently formed seed layer 1042, electrical interconnect 1044, and / or wrap connection 116 (as Figure 1C shown) and to prevent diffusion. Accordingly, in one embodiment, the adhesion layer 1040 acts as an adhesion layer; in another embodiment, the adhesion layer 1040 acts as a barrier layer. However, in both embodiments, the adhesion layer 1040 is described hereinafter as an "adhesion layer".

[0106] In one embodiment, the adhesion layer 1040 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, the thickness of the adhesion layer 1040 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness of the adhesion layer 1040 is between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer 1040 is formed by any suitable deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc.).

[0107] The seed layer 1042 may be formed on the adhesion layer 1040 or directly on the insulating layer 618 (e.g., without forming the adhesion layer 1040). In some embodiments, the seed layer 1042 is formed on all surfaces of the insulating layer 618, while the adhesion layer 1040 is formed only on the desired surfaces or the desired portions of the surfaces of the insulating layer 618. For example, the adhesion layer 1040 may be formed on the main surfaces 1005, 1007 and not on the sidewalls of the through-component vias 613 and / or the encapsulation vias 123 (as Figure 1C shown), while the seed layer 1042 is formed on the main surfaces 1005, 1007 and the sidewalls of the vias. The seed layer 1042 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, the thickness of the seed layer 1042 is between about 0.05 μm and about 0.5 μm, such as between about 0.1 μm and about 0.3 μm. For example, the thickness of the seed layer 1042 is between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. In one embodiment, the thickness of the seed layer 1042 is between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1040, the seed layer 1042 is formed by any suitable deposition process such as CVD, PVD, PECVD, ALD dry process, wet chemical plating process, etc. In one embodiment, a copper seed layer 1042 may be formed on a molybdenum adhesion layer 1040 on the intermediate core component 602. The combination of the molybdenum adhesion and the copper seed layer enables improved adhesion to the surface of the insulating layer 618 and reduces undercutting of the conductive interconnect lines during the subsequent seed layer etching process at operation 970.

[0108] At operations 920 and 930 (respectively associated with Figure 10B with Figure 10CCorrespondingly, a spin-coated / sprayed or dry resist film 1050 (such as a photoresist) is applied to the two main surfaces 1005, 1007 of the intermediate core assembly 602 and then patterned. In one embodiment, the resist film 1050 is patterned via selective exposure to UV radiation. In one embodiment, a adhesion promoter (not shown) is applied to the intermediate core assembly 602 before forming the resist film 1050. The adhesion promoter improves the adhesion of the resist film 1050 to the intermediate core assembly 602 by creating an interfacial adhesion layer for the resist film 1050 and by removing any moisture from the surface of the intermediate core assembly 602. In some embodiments, the adhesion promoter is formed of bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0109] At operation 940, the intermediate core assembly 602 is exposed to a resist film development process. As Figure 10D depicted, the development of the resist film 1050 results in the exposure of the through-component vias 613 and / or the clad vias 123 (as Figure 1C shown) (which may now have an adhesion layer 1040 and / or a seed layer 1042 formed thereon). In one embodiment, the film development process is a wet process (such as a wet process that includes exposing the resist film 1050 to a solvent). In one embodiment, the film development process is a wet etching process that utilizes an aqueous etching process. For example, the film development process is a wet etching process that utilizes a buffered etching process selectively targeted at the desired material. Any suitable combination of wet solvents or wet etchants can be used for the resist film development process.

[0110] At operations 950 and 960 (corresponding to Figure 10E and Figure 10F respectively), electrical interconnects 1044 are formed to pass through the exposed through-component vias 613, and after that, the resist film 1050 is removed. In embodiments where the core structure 102 has a metal clad layer 114, 414 formed thereon, at operation 950, clad connections 116 (as Figure 1C shown) can also be formed to pass through the exposed clad vias 123 (as Figure 1C shown). The interconnects 1044 and / or the clad connections 116 are formed by any suitable method (including electroplating and electroless plating). In one embodiment, the resist film 1050 is removed via a wet process. As Figure 10E and Figure 10FAs depicted, after removing the resist film 1050, the electrical interconnect 1044 can completely fill through-component vias 613 (the encapsulation connection 116 can also completely fill encapsulation vias 123), and protrude from the surfaces 1005, 1007 of the intermediate core component 602. In some embodiments, the electrical interconnect 1044 and / or the encapsulation connection 116 may line only the sidewalls of the vias without completely filling the vias. In one embodiment, the electrical interconnect 1044 and / or the encapsulation connection 116 is formed of copper. In other embodiments, the electrical interconnect 1044 and / or the encapsulation connection 116 may be formed of any suitable conductive material (including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.).

[0111] At operation 970 and Figure 10G the intermediate core component 602 having electrical interconnects 1044 and / or encapsulation connections 116 formed therein is exposed to a seed layer etch process to remove the exposed adhesion layer 1040 and seed layer 1042 (e.g., surfaces 1005, 1007) on its outer surface. In some embodiments, the adhesion layer 1040 and / or the seed layer 1042 formed between the interconnect and the sidewalls of the vias may be retained after the seed layer etch process. In one embodiment, the seed layer etch is a wet etch process that includes rinsing and drying the intermediate core component 602. In one embodiment, the seed layer etch process is a buffered etch process selectively for a desired material (such as copper, tungsten, aluminum, silver, or gold). In other embodiments, the etch process is an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process.

[0112] After the seed layer etch process at operation 970, one or more semiconductor core components can be diced from the intermediate core component 602 into individual dies and used as fully functional semiconductor core components 1270 (e.g., electronic mounting or packaging structures). For example, one or more semiconductor core components can be diced into individual dies and used as circuit board structures, chip carrier structures, integrated circuit packages, etc. Alternatively, the intermediate core component 602 can have one or more redistribution layers 1260 formed thereon ( Figure 12J and Figure 12K as shown) to re-route the external contact points of the electrical interconnect 1044 to desired locations on the surface of the final semiconductor core component.

[0113] Figure 11 The flowchart of a representative method 1100 for forming a redistribution layer 1260 on an intermediate core component 602 (which has not been diced into semiconductor core components 1270) is illustrated. Figures 12A to 12K Schematically illustrated Figure 11Cross-sectional views of the intermediate core component 602 at different stages of the depicted method 1100. For clarity, the description herein is presented together Figure 11 and Figures 12A to 12K .

[0114] Method 1100 is substantially similar to methods 500, 700, and 900 described above. Generally, method 1100 begins at operations 1102 and Figure 12A where the insulating film 1216 is fixed to the intermediate core component 602, and lamination is performed thereafter. The insulating film 1216 is substantially similar to the insulating films 616a, 616b. In one embodiment, as Figure 12A depicted, the insulating film 1216 includes an epoxy resin layer 1218 and one or more protective layers. For example, the insulating film 1216 may include a protective layer 1222. Any suitable combination of layers and insulating materials is contemplated for the insulating film 1216. In some embodiments, an optional carrier 1224 is coupled to the insulating film 1216 to increase support. In some embodiments, a protective film (not shown) may be coupled to the insulating film 1216.

[0115] Generally, the thickness of the epoxy resin layer 1218 is less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the thickness of the epoxy resin layer 1218 is between about 10 μm and about 25 μm. In one embodiment, the combined thickness of the epoxy resin layer 1218 and the PET protective layer 1222 is less than about 120 μm, such as less than about 90 μm. The insulating film 1216, and in particular the epoxy resin layer 1218, is fixed to the surface (such as the main surface 1005) of the intermediate core component 602 having exposed electrical interconnections 1044.

[0116] After placement of the insulating film 1216, the intermediate core component 602 is exposed to a lamination process (substantially similar to the lamination processes described with respect to operations 506, 514, and 730). The intermediate core component 602 is exposed to an elevated temperature to soften the epoxy resin layer 1218 of the insulating film 1216, and the epoxy resin layer 1218 subsequently bonds to the insulating layer 618. Thus, the epoxy resin layer 1218 integrates with the insulating layer 618 and forms an extension of the insulating layer 618 and is thus described hereinafter as a single insulating layer 618. The integration of the epoxy resin layer 1218 with the insulating layer 618 further results in an enlarged insulating layer 618 surrounding the previously exposed electrical interconnections 1044.

[0117] At operation 1104 and Figure 12BThere, the protective layer 1222 and the carrier 1224 are removed from the intermediate core component 602 by mechanical means, and the intermediate core component 602 is exposed to a curing process to fully harden the newly extended insulating layer 618. In one embodiment, the curing process is substantially similar to the curing processes described with reference to operations 516 and 740. For example, the curing process is performed at a temperature between about 140°C and about 220°C and for a period of time between about 15 minutes and about 45 minutes.

[0118] Then, at operations 1106 and Figure 12C There, the intermediate core component 602 is selectively patterned by laser ablation. The laser ablation process at operation 1106 forms one or more redistribution vias 1253 in the newly extended insulating layer 618 and exposes the desired electrical interconnections 1044 for their contact points. In one embodiment, the diameter of the redistribution vias 1253 is substantially similar to or less than the diameter of the through-component vias 613. For example, the diameter of the redistribution vias 1253 is between about 5 μm and about 600 μm, such as between about 10 μm and about 50 μm, such as between about 20 μm and about 30 μm. In one embodiment, the laser ablation process at operation 1106 is performed using a CO2 laser. In one embodiment, the laser ablation process at operation 1106 is performed using a UV laser. In another embodiment, the laser ablation process at operation 1106 is performed using a green laser. In one example, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver the pulsed laser beam at a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and with a pulse energy between about 10 μJ and about 300 μJ.

[0119] In embodiments where the metal cladding layers 114, 414 are formed on the core structure 102 (as Figure 1C shown), the intermediate core component 602 can also be patterned at operation 1106 to form one or more cladding vias 123 through the extended insulating layer 618. Thus, for a semiconductor core component having one or more redistribution layers, at operation 518 or 750, the cladding vias 123 and the redistribution vias 1253 can be formed simultaneously, rather than forming the cladding vias 123 and the through-component vias 613. However, in some other embodiments, at operation 518 or 750, the cladding vias 123 can be patterned first, then metallized using the cladding connection 116, and then extended or elongated through the extended insulating layer 618 at operation 1106.

[0120] At operations 1108 and Figure 12DThere, the adhesive layer 1240 and / or the seed layer 1242 are optionally formed on one or more surfaces of the insulating layer 618. In one embodiment, the adhesive layer 1240 and the seed layer 1242 are respectively substantially similar to the adhesive layer 1040 and the seed layer 1042. For example, the adhesive layer 1240 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or a combination thereof. In one embodiment, the thickness of the adhesive layer 1240 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness of the adhesive layer 1240 is between about 75 nm and about 125 nm, such as about 100 nm. The adhesive layer 1240 can be formed by any suitable deposition process (including but not limited to CVD, PVD, PECVD, ALD, etc.).

[0121] The seed layer 1242 is formed of a conductive material (such as copper, tungsten, aluminum, silver, gold) or any other suitable material or a combination thereof. In one embodiment, the thickness of the seed layer 1242 is between about 0.05 μm and about 0.5 μm, such as between about 0.1 μm and about 0.3 μm. For example, the thickness of the seed layer 1242 is between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. Similar to the adhesive layer 1240, the seed layer 1242 can be formed by any suitable deposition process (such as CVD, PVD, PECVD, ALD dry process, wet chemical plating process, etc.). In one embodiment, the molybdenum adhesive layer 1240 and the copper seed layer 1242 are formed on the intermediate core component 602 to reduce the formation of undercut during the subsequent seed layer etching process at operation 1122.

[0122] At operations 1110, 1112, and 1114 (respectively associated with Figure 12E , Figure 12F and Figure 12GCorrespondingly, a spin-coated / sprayed or dry resist film 1250 (such as a photoresist) is applied over the seed surface of the intermediate core assembly 602 and then patterned and developed. In one embodiment, a adhesion promoter (not shown) is applied to the intermediate core assembly 602 before placing the resist film 1250. The exposure and development of the resist film 1250 result in the opening of redistribution vias 1253 and, in some embodiments, the opening of encapsulation vias 123. Thus, patterning of the resist film 1250 can be performed by selectively exposing portions of the resist film 1250 to UV radiation and subsequent development of the resist film 1250 by a wet process (such as a wet etching process). In one embodiment, the resist film development process is a wet etching process that utilizes a buffered etching process selectively targeted at the desired material. In other embodiments, the resist film development process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the resist film development process.

[0123] At operations 1116 and 1118 (corresponding to Figure 12H and Figure 12I respectively), redistribution connections 1244 are formed to pass through the exposed redistribution vias 1253, and after that, the resist film 1250 is removed. In some embodiments, at operation 1116, encapsulation connections 116 are also formed to pass through the exposed encapsulation vias 123. In one embodiment, the resist film 1250 is removed via a wet process. As Figure 12H and Figure 12I depicted, after removing the resist film 1250, the redistribution connections 1244 fill the redistribution vias 1253 and protrude from the surface of the intermediate core assembly 602. In one embodiment, the redistribution connections 1244 are formed of copper. In other embodiments, the redistribution connections 1244 are formed of any suitable conductive material (including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.). Any suitable method can be used to form the redistribution connections 1244 (including electroplating and electroless deposition).

[0124] At operations 1120 and Figure 12J , the intermediate core assembly 602 having the redistribution connections 1244 formed thereon is exposed to a seed layer etching process substantially similar to operation 970. In one embodiment, the seed layer etching is a wet etching process that includes rinsing and drying the intermediate core assembly 602. In one embodiment, the seed layer etching process is a wet etching process that utilizes a buffered etching process selectively targeted at the desired material of the seed layer 1242. In other embodiments, the etching process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etching process.

[0125] After completing the seed layer etching process at operation 1120, the above sequence and processes can be utilized to form one or more additional redistribution layers 1260 on the intermediate core component 602. For example, one or more additional redistribution layers 1260 can be formed on the first redistribution layer 1260 and / or on the opposing surfaces (such as the main surface 1007) of the intermediate core component 602. In one embodiment, one or more additional redistribution layers 1260 can be formed of a polymer-based dielectric material (such as a flowable build-up material) different from the material of the first redistribution layer 1260 and / or the insulating layer 618. For example, in some embodiments, the insulating layer 618 can be formed of an epoxy filled with ceramic fibers, while the first and / or any additional redistribution layers 1260 are formed of polyimide, BCB, and / or PBO. Alternatively, at operations 1122 and Figure 12K after forming the desired number of redistribution layers 1260, one or more completed semiconductor core components 1270 can be diced from the intermediate core component 602.

[0126] The completed semiconductor core component 1270 formed at operation 1120 can be used in any suitable stacked package component, PCB component, PCB spacer component, chip carrier component, intermediate carrier component, etc. In Figure 13A one exemplary embodiment depicted, a single semiconductor core component 1270 serves as the carrier for a chip 1360 in a chip carrier component 1300. The chip 1360 can be any suitable type of chip (including memory chips, microprocessors, complex system-on-chip (SoC), or standard chips). Suitable types of memory chips include DRAM chips or NAND flash chips. In some further examples, the chip 1360 is a digital chip, an analog chip, or a hybrid chip. The chip 1360 is disposed adjacent to one of the main surfaces 1005, 1007 of the semiconductor core component 1270. In some embodiments, two or more chips 1360 can be disposed adjacent to a single main surface 1005, 1007. In another embodiment, one or additional devices and / or structures (such as one or more components of a PCB or a package substrate) can be disposed adjacent to the chip 1360. For example, one or more passive components (such as capacitors, resistors, inductors, etc.) can be disposed adjacent to the chip 1360. In another example, one or more connectors can be disposed adjacent to the chip 1360.

[0127] The chip 1360 includes one or more contacts 1348 formed on its active surface 1352. As shown, the contacts 1348 are conductively coupled to one or more redistribution connections 1244 of the semiconductor core component 1270 through one or more solder bumps 1346 disposed between the active surface 1352 and the main surface 1005. In some embodiments, the contacts 1348 may be conductively coupled to one or more interconnects 1044 through one or more solder bumps 1346. In one embodiment, the contacts 1348 and / or the solder bumps 1346 are formed of a material substantially similar to that of the interconnects 1044 and the redistribution connections 1244. For example, the contacts 1348 and the solder bumps 1346 may be formed of a conductive material (such as copper, tungsten, aluminum, silver, gold) or any other suitable material or a combination thereof.

[0128] In one embodiment, the solder bumps 1346 include C4 solder bumps. In one embodiment, the solder bumps 1346 include C2 (copper pillar with solder cap) solder bumps. The use of C2 solder bumps can achieve a smaller pitch length and improved thermal and / or electrical properties of the chip carrier assembly 1300. The solder bumps 1346 can be formed by any suitable wafer bumping process, including but not limited to electrochemical deposition (ECD) and electroplating.

[0129] In Figure 13B In another exemplary embodiment depicted, the semiconductor core component 1270 is used in the PCB assembly 1302. Thus, the semiconductor core component 1270 is configured to function as a PCB structure for supporting (e.g., carrying) the package assembly 1310. The structure and material of the package assembly 1310 may be substantially similar to that of the semiconductor core component 1270, but the package assembly 1310 includes an embedded die 1326 (substantially surrounded by an insulating layer 618) disposed within a cavity 1320 formed within the core structure 402. The embedded die 1326 may further include an active surface 1328 having one or more contacts 1330 formed thereon and coupled to the interconnects 1342 and / or the redistribution connections 1344 of the package assembly 1310. Similar to Figure 13A the chip carrier assembly 1300, the contacts 1330 and / or the interconnects 1342 and / or the redistribution connections 1344 of the package assembly 1310 are conductively coupled to one or more redistribution connections 1244 of the semiconductor core component 1270 through one or more solder bumps 1346 disposed between the active surface 1328 and the main surface 1005. In some embodiments, the contacts 1330 may be conductively coupled to one or more interconnects 1044 through one or more solder bumps 1346.

[0130] Figure 13CFIG. illustrates yet another exemplary embodiment of utilizing the semiconductor core component 1270 as a PCB spacer structure in the PCB component 1304. As shown, the semiconductor core component 1270 is disposed between two PCBs 1362a, 1362b and is configured to position the first PCB 1362a relative to the second PCB 1362b such that a physical space is retained between them when the first PCB 1362a and the second PCB 1362b are conductively connected. Thus, the PCBs 1362a, 1362b include one or more conductive pads 1368 formed on their main surfaces 1364a, 1364b, respectively. The one or more conductive pads 1368 are conductively coupled to the redistribution connections 1244 and / or the interconnects 1044 of the semiconductor core component 1270 via one or more solder bumps 1346. Similar to the contacts 1330, 1348, the conductive pads 1368 are formed of a material substantially similar to the solder bumps 1346, the interconnects 1044, and the redistribution connections 1244 to achieve conductivity therethrough. For example, the conductive pads 1368 may be formed of a conductive material (such as copper, tungsten, aluminum, silver, gold) or any other suitable material or a combination thereof.

[0131] Figures 14A to 14C FIG. illustrates a configuration of the semiconductor core component 1270 in which one or more passive components or devices are integrated. As Figure 14A shown, in certain embodiments, the semiconductor core component 1270 may include one or more capacitors 1410a and / or 1410b integrated within a pocket 1420 in the core structure 402 to achieve more stable power delivery across the semiconductor core component 1270. Thus, in certain embodiments, the capacitors 1410a, 1410b may serve as decoupling capacitors. In certain embodiments, the capacitors 1410a, 1410b are trench capacitors or planar capacitors. The capacitors 1410a, 1410b are formed of any suitable dielectric material (including but not limited to ceramics or silicon). In certain embodiments, the capacitors 1410a, 1410b are formed from a silicon wafer cut into monolithic pieces, which may be cut into individual capacitors after the silicon wafer is ground to a desired thickness. In such embodiments, the silicon wafer may be ground to a thickness substantially similar to that of the core structure 402 before being cut into monolithic pieces.

[0132] Generally, the lateral dimensions of capacitors 1410a, 1410b are between about 750 μm and about 175 mm, such as between about 1 mm and about 1.5 mm. Additionally, the thickness of capacitors 1410a, 1410b is substantially equal to or less than the thickness of the core structure 402, such as less than about 1500 μm, such as less than about 780 μm, such as less than about 300 μm or about 200 μm. For example, the thickness of capacitors 1410a, 1410b can be less than about 150 μm or about 120 μm. In some embodiments, the capacitors integrated within the semiconductor core assembly 1270 are discrete devices (such as capacitor 1410a) having a thickness substantially similar to the thickness of the core structure 402. In some embodiments, the capacitors are support devices (such as capacitor 1410b) coupled to the thin substrate 1402 and thus have a thickness less than the thickness of the core structure 402. Before being integrated into the semiconductor core assembly 1270, capacitor 1410b can be bonded to the substrate 1402 with an adhesive 1404. For example, multiple capacitors 1410 can be bonded to the bulk substrate 1402 and then cut into support devices having the desired dimensions for integration with the semiconductor core assembly 1270.

[0133] The capacitor 1410a, 1410b can be integrated into the semiconductor core component 1270 using the above method. Generally, at operation 320 of method 300, the pocket 1420 is patterned into the core structure 402 together with the core via 403. In some embodiments, the lateral dimension of the pocket 1420 is between about 10 μm and about 250 μm, greater than (e.g., longer than) the lateral dimension of the capacitor 1410a or 1410b to be embedded therein, such as between about 20 μm and about 150 μm, or between about 30 μm and about 100 μm. For example, the lateral dimension of the pocket 1420 can be sized to achieve a 50 μm gap between the surface of the capacitor 1410a and / or 1410b and the sidewall of the pocket 1420. Then, in one embodiment using method 500, after performing operation 504 (where the patterned core structure 402 is fixed to the first insulating film 616a) but before operation 506 (where the first protective film 660 is placed over the core structure 402), the capacitor 1410a and / or 1410b is placed within the pocket 1420. Alternatively, in another embodiment using method 700, after fixing the patterned core structure 402 to the first insulating film 616a at operation 710 but before fixing the second insulating film 616b to the core substrate 402 at operation 720, the capacitor 1410a and / or 1410b is placed within the pocket 1420. In any embodiment, the capacitors 1410a, 1410b are embedded within the pocket 1420 by an insulating layer 618, which is formed after laminating the two insulating films 616a and 616b.

[0134] Thereafter, as described with reference to operations 518 and 750, through-component vias 613 and / or redistribution vias 1253 are drilled through the insulating layer 618 directly above or below the contacts of the capacitors 1410a, 1410b to expose the contacts. Then, the through-component vias 613 and / or redistribution vias 1253 can be metallized so that the capacitors 1410a, 1410b can be electrically coupled to other devices (e.g., power and ground) stacked with the semiconductor core component 1270. For example, one or more interconnects 1044 and / or redistribution connections 1244 can be formed according to method 900 and / or 1100.

[0135] Figure 14B and Figure 14C An exemplary configuration of a semiconductor core component 1270 having one or more inductors 1450a and / or 1450b integrated therein is illustrated. Figure 14B is a cross-sectional view of the semiconductor core component 1270, and Figure 14Cis a top view thereof. As shown, the interconnect 1044 and the redistribution connection 1244 are electrically coupled in a coil-like arrangement, where the redistribution connection 1244 is metallized in a non-linear pattern or connects non-adjacent interconnects 1044. Thus, this coil-like arrangement forms inductors 1450a, 1450b embedded within the semiconductor core component 1270 (rather than disposed on its surface), thereby saving surface area for stacking other components or devices on the semiconductor core component 1270. In addition, the electrical connections of the semiconductor core component 1270 forming the coil-like shape achieve its overall reduced profile without the need to utilize additional resources or operations to incorporate inductive devices.

[0136] In some embodiments, the inductor integrated into the semiconductor core component 1270 includes a coil-like arrangement of interconnects 1044 and redistribution connections 1244 formed around the core structure 402 and the insulating layer 618 without the need to utilize a magnetic core (e.g., inductor 1450a). In some other embodiments, the inductor further includes a magnetic core 1460 (e.g., inductor 1450b) embedded within a pocket 1420 of the core structure 402 and surrounded by the coil-like arrangement of interconnects 1044 and redistribution connections 1244. The magnetic core 1460 can be formed of a ferrite-based material or a metal-polymer composition (generally including a polymer matrix having metal particles dispersed therein).

[0137] Similar to Figure 14A the capacitors, the inductors 1450a, 1450b can be integrated within the semiconductor core component 1270 using the methods described above. For example, as described with reference to methods 500 and 700, the magnetic core 1460 can be placed within the patterned pocket 1420 of the core structure 402 and then embedded after laminating one or more insulating films (e.g., insulating films 616a, 616b). In addition, the drilling of vias 403, through-component vias 613, and redistribution vias 1253 and the metallization of the interconnects 1044 and redistribution connections 1244 (e.g., including patterning of the resist 1250) can be performed in a manner that establishes the coil-like arrangement of the interconnects 1044 and redistribution connections 1244 within the semiconductor core component 1270.

[0138] Figures 15A to 15D illustrates other configurations of the semiconductor core component 1270 integrating other types of passive devices. As Figures 15A to 15BAs shown, semiconductor core component 1270 includes heat exchangers 1510a-c integrated at various locations. The integration of heat exchangers 1510a-c (such as heat sinks) improves the heat dissipation and thermal characteristics of semiconductor core component 1270 by transferring the heat conducted by silicon core structure 402. This arrangement is particularly advantageous compared to conventional PCBs formed of glass-reinforced epoxy laminate with low thermal conductivity, for which adding heat exchangers has little value. Suitable types of heat exchangers 1510a-c include pin heat sinks, straight heat sinks, torch heat sinks, etc. that can be formed of any suitable material (such as aluminum or copper). In some embodiments, heat exchangers 1510a-c are formed of extruded aluminum.

[0139] Generally, heat exchangers 1510a-c can be added to one or both sides of semiconductor core component 1270. In some embodiments, each of heat exchangers 1510a-c is placed directly on or under core structure 402 without the need for an insulating layer 618 therebetween (as shown for heat exchanger 1510a). To achieve this configuration, laser ablation can be performed on the desired regions of insulating layer 618 of the completed semiconductor core component 1270 to form pockets, and then heat exchanger 1510a can be mounted on core structure 402. For example, regions of insulating layer 618 having a lateral dimension corresponding to the lateral dimension of heat exchanger 1510a can be removed by a CO2, UV, or IR laser configured to ablate only the dielectric material of insulating layer 618 and keep core structure 402 intact. Then, heat exchanger 1510a can be placed within the opening and mounted on core structure 402 (which can include an oxide layer or a metal cladding layer) via any suitable mounting method. In some embodiments, an interface layer 1520 is formed between heat exchanger 1510a and core structure 402. For example, interface layer 1520 can be formed of a thermal interface material (TIM) (such as a thermal adhesive or a potting mixture). In some embodiments, interface layer 1520 is a thin layer of a flowable dielectric material substantially similar to insulating layer 618.

[0140] In some embodiments, heat exchangers 1510a-c are placed directly on top of the insulating layer 618 of the semiconductor core component 1270 (as shown by heat exchanger 1510b). In such an example, laser ablation of the insulating layer 618 is not required. To optimize heat transfer between the core substrate 402 and the heat exchanger 1510b, the semiconductor core component 1270 may include one or more thermal connections 1544 for thermally coupling the core structure 402 to the heat exchanger 1510b. Different from the interconnects 1044 and the redistribution connections 1244, the thermal connections 1544 do not have any electrical function and only provide a path for conducting heat to the heat exchanger 1510b. In some embodiments, the thermal connections 1544 are formed in vias that are substantially similar to the through-component vias 613 and the redistribution vias 1253 described above. Generally, the thermal connections 1544 are formed of a metallic material (such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.).

[0141] In some embodiments, the heat exchangers 1510a-c are placed adjacent to the active devices and components stacked with the semiconductor core component 1270. Generally, the heat exchangers 1510a-c can be arranged relative to any configuration of the active devices or components attached to the semiconductor core component 1270. In Figures 15A to 15B the example, the heat exchanger 1510c is placed on the active devices 1550 and 1560, and the heat exchanger 1510b is disposed on the side of the active devices 1550, 1560 (e.g., laterally disposed). The placement of the heat exchangers above and on the side of the active devices 1550, 1560 increases heat conduction away from the active devices. In some embodiments, additional heat exchangers may be provided on the side of the semiconductor core component 1270 opposite to any active device or component (such as depicted by the heat exchanger 1510a). In some embodiments, the thermal connections 1544 may also be formed between the core structure 402 and the active devices 1550, 1560 to thermally connect the active devices 1550, 1560 to the core structure 402 and assist in heat conduction from the active devices to the core.

[0142] As Figure 15B shown, the heat exchangers 1510a-c may be further coupled to one or more fans 1570 that assist in heat dissipation by providing additional fluid flow for convection. Although depicted as being directly mounted to the heat exchangers 1510a-c, the fans 1570 may be attached along the semiconductor core component 1270 and oriented in any suitable position for optimized fluid flow and thermal regulation. In an example where the semiconductor core component 1270 is stacked with other packaging structures (such as PCBs 1362a, 1362b), cavities 1580 may be formed in additional structures directly above or below the heat exchangers 1510a-c to enable the placement of one or more fans 1570 and / or facilitate heat dissipation therefrom.

[0143] Alternatively or in addition to the above heat exchanger, the semiconductor core component 1270 may also have one or more heat pipes or heat spreaders 1590 integrated at various positions thereon to improve heat dissipation and thermal modulation. Figure 15C and Figure 15D Illustrated is an exemplary heat spreader 1590 and an exemplary arrangement of the heat spreader 1590 on the semiconductor core component 1270. Similar to the above heat exchange, the heat spreader 1590 transfers the heat conducted by the silicon core structure 402. However, the heat spreader 1590 utilizes the phase conversion of the liquid contained within its plenum 1593. For example, as Figure 15C shown, the heat spreader 1590 includes a heat interface or evaporator 1591 at which the contained liquid turns into vapor 1594 by absorbing heat therefrom. In certain embodiments, the liquid contacts the evaporator 1591 via a wick 1592 disposed within the plenum 1593. After vaporization, the vapor 1594 travels within the heat spreader 1590 to a cold surface or condenser 1596 at which the vapor 1584 condenses into a liquid condensate 1595 and releases latent heat, thereby dissipating heat. Then, the liquid condensate 1595 returns to the evaporator 1591 through the wick 1592 by capillary action (as indicated by reference numeral 1597), and this cycle can be repeated for further heat transfer. This principle enables efficient lateral transfer of heat away from the core structure 402 of the semiconductor core component 1270 and, for example, towards other heat dissipation devices.

[0144] Similar to the above heat exchanger, the heat spreader 1590 can be placed directly above or below the core structure 402 without the need for an insulating layer 618 therebetween. As Figure 15D shown, in certain embodiments, the heat spreader 1590 is disposed directly between the core structure 402 and a heat exchanger (such as heat exchanger 1510c) to transfer heat therebetween. In certain embodiments, one or more thermal connections 1544 that thermally couple the heat spreader 1590 to the core structure 402 are used to place the heat spreader 1590 directly on top of the insulating layer 618. Generally, the heat spreader 1590 is oriented such that the "hot side" or the side containing the evaporator of the heat spreader 1590 is set closest to the core structure 402, while the "cold side" or the side containing the condenser is set away from the core structure 402 (such as adjacent to Figure 15D the heat exchanger 1510c in [[ ]]). In some examples, the heat spreader 1590 may also be used in combination with one or more fans 1570 disposed near the heat spreader 1590 and / or other heat dissipation devices for additional heat dissipation by air convection.

[0145] Figure 16Illustrated is an exemplary arrangement 1600 of the semiconductor core component 1270, where the semiconductor core component 1270 contributes to variable density of the interconnect 1044 and the redistribution connection 1244 for bridging two active devices 1650 and 1660 having active layers 1652 and 1662, respectively. As shown, the semiconductor core component 1270 includes a bridge 1610 embedded within a pocket 1420 of the core structure 402, and through the bridge 1610, the active devices 1650 and 1660 are partially interconnected via its bridge redistribution layer 1620. The bridge 1610 is disposed beneath adjacent ends of the active layers 1652, 1662 and provides high-density and short-distance interconnection of the active device connections disposed at or near these ends, thereby achieving local high-density interconnection. However, the active device connections disposed at the distal ends of the active layers 1652, 1662 can be interconnected via a lower-density but higher-range signal path formed by the interconnect 1044 and the redistribution connection 1244 through the insulating layer 618 of the semiconductor core component 1270, which can have reduced crosstalk compared to the high-density and short-distance interconnection.

[0146] Generally, the bridge 1610 includes a silicon-containing base 1630, and the thickness of the silicon-containing base 1630 is substantially equal to or less than the thickness of the core structure 402. For example, the thickness of the base 1630 is between about 80 μm and about 775 μm, such as between about 100 μm and about 400 μm, or between about 110 μm and about 300 μm. In certain embodiments, the base 1630 is a high-density substrate (such as a high-density fan-out substrate containing silicon dioxide), and the redistribution layer 1620 is a back-end-of-line (BEOL) redistribution layer.

[0147] In certain embodiments, the base 1630 is a high-density silicon interposer, and the redistribution layer 1620 is a dual-damascene BEOL redistribution layer. The base 1630 supports the redistribution layer 1620 having a thickness of up to about 1 μm. In certain embodiments, the base 1630 supports a connection pitch in the range between about 0.3 μm and about 2 μm (such as between about 0.5 μm and about 1.5 μm). To make full use of the relatively small pitch of the bridge 1610, the active devices 1650, 1660 can be soldered to the semiconductor core component 1270 via micro-bumps 1646 having a width or diameter between about 20 μm and about 150 μm or between about 30 μm and about 80 μm, thereby achieving higher-density interconnection therebetween. The micro-bumps 1646 are formed of a material substantially similar to the material of the interconnect 1044, the redistribution connection 1244, or the solder bump 1346 (such as copper, tungsten, aluminum, silver, gold, or any other suitable material or a combination thereof). Similar to Figures 14A to 14CFor a passive device, the bridge 1610 can be integrated into the semiconductor core component 1270 using any of the above methods. For example, according to methods 500 and 700, the bridge 1610 on which the redistribution layer 1620 has been formed can be placed within the patterned pocket 1420 of the core structure 402 and then embedded after lamination for one or more insulating films (e.g., insulating films 616a, 616b). Additionally, through-component vias 613 can be drilled through the insulating layer 618 directly above the contacts of the redistribution layer 1620 and then metallized to form the interconnections 1044 and 1244, thereby enabling subsequent connection of the bridge 1610 to the active devices 1650 and 1660.

[0148] In the embodiment shown above, the utilization of the semiconductor core component 1270 provides several advantages over conventional packages, PCBs, PCB spacers, and chip carrier structures. Such benefits include a thin form factor and a high chip or die-to-package volume ratio, which enables a larger I / O scaling ratio to meet the increasing bandwidth and power efficiency requirements of artificial intelligence (AI) and high-performance computing (HPC). The utilization of the structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability in 3D integrated circuit (3D IC) architectures. Additionally, compared to conventional TSV technologies, the manufacturing method of the through-assembly vias and vias-in-via structures described herein provides high performance and flexibility for 3D integration at a relatively low manufacturing cost.

[0149] By utilizing the above methods, high aspect ratio features can be formed on glass and / or silicon core structures, thereby enabling thinner and narrower circuit boards, chip carriers, integrated circuit packages, etc. to be formed economically. The semiconductor core components manufactured using the above methods not only provide the benefits of high I / O density and improved bandwidth and power, but also provide the benefit of higher reliability due to low stress attributed to reduced weight / inertia and a component architecture that allows for flexible solder ball distribution. Further advantages of the above methods include economic manufacturing with dual-sided metallization capabilities and high productivity. Additionally, the utilization of the silicon core reduces or eliminates the mismatch in the coefficient of thermal expansion (CTE) between the core component and any chips connected thereto, thereby enabling a smaller solder pitch and increased device density.

[0150] Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure may be designed without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A semiconductor device assembly, comprising: a silicon or glass core structure, the silicon or glass core structure comprising: a first side opposite a second side; a metal cladding layer formed on the first side and the second side and directly contacting the first side and the second side; a dielectric layer formed over the metal cladding layer; one or more conductive interconnects formed through the silicon or glass core structure and having surfaces exposed at the first side and the second side; a first redistribution layer formed over the first side; and a second redistribution layer formed over the second side, wherein each of the first redistribution layer and the second redistribution layer has one or more conductive contacts formed thereon, and wherein the metal cladding layer is conductively coupled to ground or a reference voltage through at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

2. The semiconductor device assembly of claim 1, wherein the metal cladding layer comprises nickel.

3. The semiconductor device assembly of claim 1, wherein the metal cladding layer has a thickness between 100 nm and 5 μm on all exposed surfaces of the silicon or glass core structure.

4. The semiconductor device assembly of claim 1, wherein the metal cladding layer circumferentially surrounds the one or more conductive interconnects formed through the silicon or glass core structure.

5. The semiconductor device assembly of claim 4, wherein the metal cladding layer is conductively coupled to ground through at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

6. The semiconductor device assembly of claim 4, wherein the metal cladding layer is conductively coupled to a reference voltage through at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

7. The semiconductor device assembly of claim 1, wherein the dielectric layer comprises a flowable epoxy resin material.

8. The semiconductor device assembly of claim 7, wherein the epoxy resin material comprises silica particles having a size in the range of 80 nm to 1 μm.

9. The semiconductor device assembly of claim 8, wherein the dielectric layer has a thickness between 5 μm and 50 μm.

10. The semiconductor device assembly of claim 7, further comprising: one or more through-component vias configured to pass through the semiconductor device assembly, each of the one or more through-component vias having one of the one or more conductive interconnects formed therein.

11. The semiconductor device assembly of claim 10, wherein each of the one or more through-component vias is circumferentially defined by the dielectric layer.

12. A semiconductor device assembly, comprising: a silicon or glass core structure; A metal layer, the metal layer being formed on at least two surfaces of the silicon or glass core structure and directly contacting at least two surfaces of the silicon or glass core structure; and A dielectric layer, the dielectric layer being formed on the metal layer, the dielectric layer comprising an epoxy resin having silica particles disposed therein, wherein the metal layer is conductively coupled to ground or a reference voltage through one or more conductive vias formed through the dielectric layer.

13. The semiconductor device assembly of claim 12, further comprising: One or more arrays of through-holes configured to pass through the semiconductor device assembly and filled with copper, each of the through-holes in the one or more arrays having a diameter of less than 500 μm.

14. The semiconductor device assembly of claim 13, wherein each through-hole in the one or more arrays is circumferentially defined by the dielectric layer.

15. The semiconductor device assembly of claim 14, wherein the dielectric layer circumferentially defining the one or more through-holes is circumferentially surrounded by the metal layer.

16. The semiconductor device assembly of claim 13, further comprising a redistribution layer formed on the dielectric layer and having one or more redistribution connections, wherein the redistribution connections and the copper-filled through-holes form an inductive coil.

17. The semiconductor device assembly of claim 12, wherein the silicon or glass core structure further comprises one or more pockets formed therein, at least one of the one or more pockets containing a silicon capacitor therein.

18. The semiconductor device assembly of claim 12, further comprising: A heat exchanger, the heat exchanger being coupled to the metal layer.

19. The semiconductor device assembly of claim 12, further comprising: A heat exchanger, the heat exchanger being disposed above the dielectric layer.

20. A semiconductor device assembly, comprising: A silicon or glass core structure, the silicon or glass core structure having a first side opposite to a second side; A nickel coating layer, the nickel coating layer being formed on the first side and the second side and directly contacting the first side and the second side; A dielectric layer, the dielectric layer surrounding the nickel coating layer, the dielectric layer comprising an epoxy resin; An array of through-holes configured to pass through the silicon or glass core structure and filled with a conductive material, each through-hole in the array of through-holes being defined by the dielectric layer; and A redistribution layer, the redistribution layer being formed on the dielectric layer, the redistribution layer comprising: An adhesion layer, the adhesion layer being formed on the dielectric layer, the adhesion layer comprising molybdenum; A copper seed layer, the copper seed layer being formed on the adhesion layer; and A copper layer, the copper layer being formed on the copper seed layer, wherein the nickel coating layer is conductively coupled to ground or a reference voltage through a conductive via that passes through at least the dielectric layer.

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