Nonlinear correction

Abstract

The present invention relates to a method (600) for nonlinear correction, comprising receiving (608, 622) a first output signal from a data signal path including a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method further comprises generating (624, 626, 628) a first nonlinear coefficient using the first output signal and generating (610, 612, 614, 616) a second nonlinear coefficient using the first and second output signals. The method further comprises applying (634) the first and second nonlinear coefficients by a nonlinear corrector in the data signal path to compensate for nonlinear components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

Description

Technical Field

[0001] The present invention relates generally to nonlinear correction, and more particularly to generating nonlinear correction coefficients and performing nonlinear correction within a system. Background Art

[0002] Electronic systems such as mobile phones, audio and video equipment, wired communication systems, measurement equipment, radar systems, etc. may include one or more nonlinear circuits or components that may adversely affect the performance of the system. One such nonlinear circuit is an analog-to-digital converter ("ADC"), which converts a continuous-time analog signal (e.g., voltage or current) into a discrete-time representation (a digital or digitized signal) that is proportional to the magnitude of the continuous-time signal. However, other sources of nonlinearity may exist within the system, such as from circuits on a printed circuit board ("PCB" or "board"), for example, at the user end where the ADC is mounted. There may also be "source nonlinearity" caused by components of the transmitter of the continuous-time signal. Nonlinear correctors may be used to compensate for nonlinearities within the system. Summary of the Invention

[0003] As technology advances, some nonlinearity correction methods may not meet target performance specifications. For example, the wireless infrastructure (“WI”) market is moving towards sampling architectures based on radio frequency ADCs (“RF-ADCs”) due to their ease of supporting multiple frequency bands and wider bandwidths while reducing board space. Therefore, key concerns include RF-ADC nonlinearity performance metrics such as second- and third-order harmonic distortion and second- and third-order intermodulation distortion. An example target spurious-free dynamic range (“SFDR”) specification is -80dBFS under various receiver operating scenarios, such as various input levels, Nyquist zones (frequencies), and temperature ranges (e.g., -40°C to 125°C). However, achieving the target SFDR of -80dBFS is challenging when the uncorrected ADC output signal level is -55dBFS, which occurs in some applications.

[0004] In addition, there may be nonlinearities caused by the board circuitry at the user end (e.g., second-order nonlinearities) and nonlinearities due to temperature, voltage variations, and / or aging effects, which, if not corrected, make it difficult to meet target performance specifications. Furthermore, it is desirable to correct for nonlinearities caused by the ADC (and other circuitry, such as residing on a chip with the ADC) and nonlinearities caused by board circuitry and other effects within the system without correcting for source nonlinearities. For example, source nonlinearities may be caused by the transmitter's RF power amplifier and digital predistortion circuitry.

[0005] One solution to correcting or compensating for nonlinearities in a system is to apply factory-calibrated nonlinearity correction to the digital signal output from the ADC. That is, at production time, nonlinearity correction coefficients are determined for a range of sampling rates, Nyquist zones, and digital step attenuator (DSA) indices and stored in memory. During operation, the appropriate nonlinearity correction coefficients are programmed from memory into the nonlinearity corrector based on the receiver configuration. However, this approach has several limitations. For example, the time required to perform factory calibration and the memory required to store the coefficients increase the cost of the device. Furthermore, factory calibration does not account for other sources of nonlinearity, such as second-order nonlinearities caused by the board on which the ADC is mounted, as well as variations due to temperature, voltage, and / or aging.

[0006] The disclosed examples of nonlinear correction address these limitations. According to one or more examples of the present disclosure, digital signals output from a data signal path containing a board circuit, a main (e.g., first) ADC, and a nonlinear corrector are used to determine or generate (e.g., by estimation) some nonlinear correction coefficients used by the nonlinear corrector to correct the digital signal output from the main ADC. For example, the digital signals output from the data signal path are used to determine nonlinear correction coefficients used to correct, for example, second-order nonlinearities caused by the main ADC (and circuitry co-located with the main ADC) and by the board circuit. In addition, digital signals output from both the data signal path and a reference path containing a reference (e.g., second) ADC are used to estimate the remainder of the nonlinear correction coefficients used by the nonlinear corrector. For example, the reference path is used to subtract a signal containing source nonlinearities and second-order nonlinearities caused by the board circuit in order to determine nonlinear correction coefficients used to correct, for example, third-order nonlinearities caused by the main ADC (and circuitry co-located with the main ADC).

[0007] In this manner, the disclosed embodiments can be implemented at runtime to compensate for or correct nonlinearities introduced by circuits in the data signal path without correcting or compensating for the source nonlinearities. Furthermore, the disclosed embodiments can be implemented at periodic intervals to correct for or compensate for variations in nonlinear performance due to temperature, voltage, and / or aging. Furthermore, because the nonlinearity correction coefficients are determined at runtime, the cost of a system implementing one or more of the embodiments described herein can be reduced by eliminating factory calibration and nonvolatile storage of the correction coefficients.

[0008] In one example, a method for nonlinear correction includes receiving a first output signal from a data signal path including a first analog-to-digital converter and a second output signal from a second analog-to-digital converter. The method also includes generating a first nonlinear coefficient using the first output signal and generating a second nonlinear coefficient using the first and second output signals. The method further includes applying the first and second nonlinear coefficients to compensate for nonlinear components in a digitized signal output from the first analog-to-digital converter by a nonlinear corrector in the data signal path to generate a corrected digitized signal.

[0009] In another example, a system includes a nonlinear coefficient generator and a nonlinear corrector coupled to the nonlinear coefficient generator. The nonlinear coefficient generator is configured to process a first digitized signal to generate second-order nonlinear coefficients, and to process the first and second digitized signals to generate third-order nonlinear coefficients. The nonlinear corrector is configured to correct nonlinear components in a digitized signal output from an analog-to-digital converter using the second-order and third-order nonlinear coefficients to generate a corrected digitized signal.

[0010] In another example, a system includes a digital signal path, a reference path, and a nonlinear coefficient generator. The digital signal path includes a first analog-to-digital converter (ADC) having a first ADC input and a first ADC output, and a nonlinear corrector having a first nonlinear corrector input coupled to the first ADC output and a second nonlinear corrector input. The reference path includes a second ADC having a second ADC input and a second ADC output. The nonlinear coefficient generator has a first input coupled to the data signal path, a second input coupled to the second ADC output, and an output coupled to the second nonlinear corrector input. The nonlinear coefficient generator is configured to: receive a first digitized signal from the data signal path; receive a second digitized signal from the second ADC; generate second-order nonlinear coefficients using the first digitized signal; generate third-order nonlinear coefficients using the first and second digitized signals; and provide the second-order and third-order nonlinear coefficients to the nonlinear corrector. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example system including a nonlinear correction circuit according to the present disclosure is depicted.

[0012] Figure 2 Describing the Figure 1 An example nonlinear corrector implemented in the system presented in .

[0013] Figure 3 Describing the Figure 1An example nonlinear coefficient generator implemented in the system shown in .

[0014] Figure 4 Description in Figure 3 A graph of example simulation results of the error covariance between the nonlinear coefficients generated in the nonlinear coefficient generator shown in FIG.

[0015] Figure 5 Description in Figure 3 Another graph of example simulation results of the error covariance between the nonlinear coefficients generated in the nonlinear coefficient generator shown in .

[0016] Figure 6 Description can be made by Figures 1 to 3 Flowchart of an example method for nonlinear correction performed by a nonlinear correction circuit shown in FIG.

[0017] Figure 7 Describes an example nonlinear correction circuit that uses only the digital signal output from the data signal (main) path to estimate the nonlinear correction coefficient to facilitate nonlinear correction, which can be used in Figure 1 and 3 The nonlinear correction circuit shown in FIG is implemented.

[0018] Figure 8 Describing the Figure 7 An example bin identification circuit implemented in the nonlinear correction circuit shown in FIG.

[0019] Figure 9A 、 9B and 9C depict example bin identification for nonlinear coefficient generation.

[0020] Figure 10 Description can be made by Figure 1 and 7 Flowchart of an example method for nonlinear correction performed by a nonlinear correction circuit shown in FIG.

[0021] Figure 11 Depicts an example nonlinear correction circuit that uses digital signals output from both a data signal path and a reference path to estimate nonlinear correction coefficients to facilitate nonlinear correction. Figure 1 and 3 The nonlinear correction circuit shown in FIG is implemented.

[0022] Figure 12 Describing the Figure 11 An example channel estimation circuit implemented in the nonlinear correction circuit shown in .

[0023] Figure 13 Describing the Figure 11An example channel equalization circuit implemented in the nonlinear correction circuit shown in FIG.

[0024] Figure 14 Description can be made by Figure 1 and 11 Flowchart of an example method for nonlinear correction performed by a nonlinear correction circuit shown in FIG. DETAILED DESCRIPTION

[0025] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the specification and claims, the terms "including" and "having" and their variations are intended to be inclusive in a manner similar to the term "comprising" unless otherwise indicated. In addition, the terms "couple" / "coupled" / "couples" mean an indirect or direct electrical or mechanical connection.

[0026] First reference Figure 1 , which depicts an example system 100 according to the present disclosure that includes nonlinear correction circuits 116 and 122. In an example, system 100 is included in a receiver circuit (e.g., as part of a transceiver) of a system such as a mobile phone, audio and video equipment, a wired communication system, a measurement device, a radar system, etc.

[0027] System 100 includes a PCB or board 102 and an antenna 104 attached to board 102. Board 102 contains or has mounted thereon a filter 106, PCB or board circuitry 108, a (first) digital step attenuator (DSA) 112, a main (first) ADC 114, a nonlinear ("NL") corrector 116, a reference (second) DSA 118, a reference (second) ADC 120, an NL coefficient generator 122, a controller 124, and a digital signal processor ("DSP") 126, which includes a digital downconverter 128 and may include other circuitry (not shown). The circuitry mounted on board 102 includes inputs and outputs coupled together as illustrated to allow processing of data signals during operation of board 102. Spectrograms 130-140 are frequency domain representations of data signals (labeled 142-154) at various processing stages within system 100.

[0028] The filter 106, PCB circuit 108, DSA 112, main ADC 114, and NL corrector 116 form what is referred to herein as a "data signal path" or "main path," through which a data signal received into the antenna 104 travels and is processed before being provided to the DSP 126 for further processing. The reference DSA 118 and reference ADC 120 form what is referred to herein as a "reference path." Furthermore, in a particular example, the DSA 112, main ADC 114, NL corrector 116, reference DSA 118, reference ADC 120, NL coefficient generator 122, and controller 124 are co-located on the chip 110 mounted to the board 102. However, this need not be the case in other examples.

[0029] Furthermore, DSA 112, primary ADC 114, reference DSA 118, and reference ADC 120 are implemented as circuits in hardware. NL coefficient generator 122 and / or NL corrector 116 may be implemented as circuits in hardware or firmware, or by a processor (e.g., a microprocessor or microcontroller, which may be the same as or different from controller 124) executing instructions stored in a memory. Controller 124 (e.g., a microcontroller) controls the timing of the digital processes performed by NL coefficient generator 122 and NL corrector 116. Controller 124 may also provide control signals, such as DSA indices or values or control flags, to circuits on chip 110.

[0030] During operation or run time, an analog signal 142 containing data (also referred to interchangeably herein as an analog data signal or source input signal) is received by antenna 104. In this example, received analog data signal 142 is a two-tone input signal of fundamental or carrier frequencies f1 and f2, as illustrated by spectrogram 130. Furthermore, in this example, received signal 142 is an RF signal, with f1 and f2 being within the radio spectrum. Spectrogram 130 also shows that received signal 142 includes a "source" nonlinear component caused by nonlinearities in the transmitter's circuitry (e.g., a power amplifier and / or digital predistortion circuitry). In this example, the source nonlinear components include: second-order nonlinear components at DC and at frequencies f2-f1, 2f1, 2f2, and f1+f2; "near" third-order nonlinear components at frequencies 2f1-f2 and 2f2-f1, which are closer to the fundamental frequency; and "far" third-order nonlinear components at frequencies 2f1+f2, 3f1, 3f2, f1+2f2, which are farther away from the fundamental frequency.

[0031] The received signal 142 passes through the filter 106, which in this example is a band-selective filter that limits the bandwidth of the received signal 142. In this example, the filter 106 removes all second-order nonlinear components and far third-order nonlinear components. Therefore, as illustrated by the spectrum diagram 132, the analog data signal 144 output from the filter 106 includes only the fundamental frequency components of the received signal 142 at f1 and f2 and the near third-order nonlinear components at 2f1-f2 and 2f2-f1.

[0032] Analog data signal 144 output from filter 106 passes through PCB circuitry 108, which introduces second-order nonlinear components at DC, f2-f1, 2f1, 2f2, and f1+f2, as illustrated by spectrum plot 134. PCB circuitry 108 may include PCB traces, interfaces between PCB 102 and chip 110, and / or other board impairments that introduce second-order nonlinearity into the data signal.

[0033] Both the DSA 112 and the reference DSA 118 receive the analog data signal 146 output from the PCB circuit 108 for further processing via the main path and the reference path, respectively. Within the main path, the DSA 112 attenuates the analog data signal 146 by an attenuation value, which can be selected by, for example, a digital value provided to the DSA 112 by the controller 124. The main ADC 114 (which is an RF-ADC in this example) digitizes the analog data signal 146 to produce a digital data signal 150 (x[n]) represented by the spectrogram 138. Digital data signals are also referred to interchangeably herein as digital data, digitized data, or simply data. Similarly, within the reference path, the reference DSA 118 attenuates the analog data signal 146 by an attenuation value, which can be selected by, for example, a digital value provided to the reference DSA 118 by the controller 124. Reference ADC 120 , which in this example is also an RF-ADC, digitizes analog data signal 146 to produce digital data signal 148 represented by spectrogram 136 .

[0034] Relatively speaking, reference DSA 118 is more linear than DSA 112, and reference ADC 120 is more linear than main ADC 114, and reference components 118 and 120 may therefore have lower associated signal-to-noise ratios than components 112 and 114. In a particular example, reference DSA 118 and reference ADC 120 are “highly linear,” meaning that no additional second- or third-order nonlinearities are introduced during signal processing, as shown by comparing spectrogram 134 of analog data signal 146 entering the reference path with spectrogram 136 of digital data signal 148 exiting the reference path.

[0035] In contrast, the processing performed by DSA 112 and main ADC 114 introduces second-order nonlinear components at DC, f2-f1, 2f1, 2f2, and f1+f2; near third-order nonlinear components at 2f1-f2 and 2f2-f1; and far third-order nonlinear components at 2f1+f2, 3f1, 3f2, and f1+2f2, as illustrated in spectral plot 138. The nonlinear correction circuitry, including NL coefficient generator 122 and NL corrector 116, operates to correct (e.g., remove, mitigate, or compensate for) these nonlinear components in digital data signal 150. Consequently, digital data signal 154 (y[n], also referred to herein as nonlinearly corrected data 154) output from NL corrector 116 may have a spectral plot 140 similar to spectral plot 132 of analog data signal 144 exiting filter 106.

[0036] That is, the NL coefficient generator 122 generates (e.g., by estimating) the nonlinearity correction coefficients 152 for a given sampling rate, Nyquist zone, DSA settings, etc., at which the main ADC 114 operates. The NL corrector 116 uses or applies the estimated nonlinearity correction coefficients 152 to correct the nonlinear components in the digital data signal 150 that are caused by the nonlinearities of the PCB circuit 108, the DSA 112, and the main ADC 114, without correcting the source nonlinearity components.

[0037] By way of distinction, nonlinear correction coefficients are values estimated by an NL coefficient generator and used by an NL corrector to correct a digitized signal and thereby generate a corrected digitized signal (also referred to herein as nonlinear corrected data). Nonlinear ("NL") correction coefficients are also interchangeably referred to herein as nonlinear coefficients, correction coefficients, coefficient values, and coefficients. In contrast, nonlinear terms are generated to model nonlinear components in a signal, and once generated, the nonlinear terms can be used by an NL coefficient generator to estimate NL correction coefficients, or by an NL corrector to apply the estimated NL correction coefficients to correct the digitized signal. Furthermore, nonlinear components are spurious components inherent in a signal at frequencies other than the fundamental frequency.

[0038] The NL corrector 116 provides the nonlinear corrected data 154 to the DSP 126. Within the DSP 126, the digital down-converter 128 down-converts the nonlinear corrected data 154 to provide down-converted in-phase and quadrature-phase data to downstream circuitry (not shown) for further processing, such as for video and / or audio output. For example, the digital down-converter 128 multiplies the nonlinear corrected data 154 with the sine and cosine signals of a local oscillator to generate down-converted data.

[0039] In an example, the nonlinear components of the digital data signal 150 (x[n]) output from the primary ADC 114 are modeled by applying a multi-access point Voltera model and a derivative-based model to the raw output samples of the ADC 114. For example, the nonlinear components of x[n] may be modeled using nonlinear terms such as:

[0040] Second-order term: x 2 [n],x[n]x′[n],x′ 2 [n]

[0041] Third-order term: x 3 [n],x 2 [n]x′[n],x[n]x′ 2 [n],x′ 3 [n],x 2 [n]x[n+1]

[0042] or higher order nonlinear terms.

[0043] Figure 2 Describing the Figure 1 1. An example nonlinear corrector 116 implemented in the system 100 is shown in FIG. The NL corrector 116 includes N nonlinear term generators 202, multipliers 204, and adders 206, only one of each of which is labeled. The components 202-206 of the NL corrector 116 can be implemented as circuits in hardware or firmware, or by a processor (e.g., a microprocessor or microcontroller, which can be the same as or different from the controller 124) executing instructions stored in a memory.

[0044] The nonlinear term generator 202 generates various nonlinear terms (such as the second-order and third-order nonlinear terms shown above) corresponding to x[n] for nonlinear correction. N ) 152 (also referred to herein as a nonlinear correction coefficient) is estimated by NL coefficient generator 122 and provided to NL corrector 116 for nonlinear correction. For example, the value of NL correction coefficient 152 may vary with different conditions of DSA 112, main ADC 114, and temperature.

[0045] The multiplier 204 of the NL corrector 116 scales the nonlinear terms by coefficient values. The adder 206 of the NL corrector 116 combines the scaled nonlinear terms with the digital data signal 150 to generate the nonlinear corrected data 154. The NL correction coefficients (values) applied to (e.g., for scaling) the second-order NL terms in the NL corrector are referred to herein as "second-order NL correction coefficients." Similarly, the NL correction coefficients (values) applied to (e.g., for scaling) the third-order NL terms in the NL corrector are referred to herein as "third-order NL correction coefficients," and so on.

[0046] Figure 3 Describing the Figure 1 1. As illustrated, the NL coefficient generator 122 includes an NL coefficient estimator and tracker 300 and an NL coefficient estimator and tracker 304. In the example implementation, the NL coefficient generator 122 also includes a second-order NL coefficient selector 302 (which may be incorporated into block 300) and a third-order NL coefficient selector 306 (which may be incorporated into block 304). Selectors 302 and 306 may be used to address aliasing of nonlinear components within the data signal.

[0047] The components 300-306 of the NL coefficient generator 122 may be implemented as circuits in hardware or firmware, or by a processor (e.g., a microprocessor or microcontroller, which may be the same as or different from the controller 124) executing instructions stored in a memory. Furthermore, in one example, the NL coefficient estimator and tracker 300 and the NL coefficient estimator and tracker 304 are implemented using separate circuits, as represented by separate blocks 300 and 304. For example, the NL coefficient estimator and tracker 300 may be implemented using Figures 7 to 8 Shown in and referenced below Figures 7 to 8 The described circuit is implemented, and the NL coefficient estimator and tracker 304 uses Figures 11 to 13 Shown in and referenced below Figures 11 to 13 However, in another example embodiment, all or a portion of the NL coefficient estimator and tracker 300 and the NL coefficient estimator and tracker 304 are implemented using shared circuitry. However, in a specific example, even when other circuitry is shared, the filters (e.g., Kalman filters) used in the NL coefficient estimator and tracker 300 and the NL coefficient estimator and tracker 304 are separate.

[0048] Typically, the NL coefficient estimator and tracker 300 processes only the data signal output from the primary path (signal 150 or 154) to generate some NL correction coefficients, which is also referred to herein as "blind nonlinearity estimation." For example, the NL coefficient estimator and tracker 300 processes the primary path data signal to provide only second-order NL correction coefficients for correcting second-order nonlinear components in the output signal from the primary ADC 114. The remaining near-third-order source NL components in the signal 150 are not affected by the application of the second-order NL correction coefficients.

[0049] In one example, the NL coefficient estimator and tracker 300 estimates only the second-order NL correction coefficients. In another example, the NL coefficient estimator and tracker 300 estimates both the second-order and third-order NL correction coefficients and selects the second-order NL correction coefficients therefrom using the selector 302. In this example, the estimator also maintains a measure of the decoupling of the estimates of the second-order and third-order coefficients. The second-order estimated coefficients are selected based on the decoupling measure. If the measure indicates that there is sufficient decoupling between the estimates of the second-order and third-order coefficients, the second-order estimated coefficients are selected.

[0050] As mentioned before, the NL coefficient estimator and tracker 300 can use Figures 7 to 8 Displayed in the middle and referenced below Figures 7 to 8 The circuit described above is implemented as described in detail below. As further described below, the nonlinear correction circuit includes a nonlinear coefficient estimation and tracking circuit that captures data at the input or output of the nonlinear corrector 116, generates nonlinear terms based on the captured data, and converts the captured data and nonlinear terms from the time domain to the frequency domain. Frequency bins with low-level signals (determined based on a first threshold) and high-level nonlinear terms (determined based on a second threshold) are selected for nonlinear correction coefficient estimation. If the output of the nonlinear corrector 116 is captured, the response of the captured data is converted from residual nonlinearity to complete nonlinearity. The nonlinear correction coefficients are estimated based on the nonlinear terms of the selected frequency bins and the captured data.

[0051] Typically, the NL coefficient estimator and tracker 304 processes the data signal output from the main path (signal 150 or 154) and the data signal 148 output from the reference path to generate some NL correction coefficients, which are also referred to herein as "reference-based nonlinearity estimates." The main path is also interchangeably referred to herein as the main data path. The reference path is also interchangeably referred to herein as the reference data path. For example, the NL coefficient estimator and tracker 304 processes the main path data signal and the reference path data signal to provide only third-order NL correction coefficients for correcting third-order nonlinear components in the output signal from the main ADC 114. The remaining near-third-order source NL components in the signal 150 are not affected by the application of the third-order NL correction coefficients because the reference path is used to subtract these components from the NL coefficient estimate.

[0052] In one example, the NL coefficient estimator and tracker 304 estimates only the third-order NL correction coefficients. In another example, the NL coefficient estimator and tracker 304 estimates both the second-order and third-order NL correction coefficients and selects the third-order NL correction coefficients therefrom using the selector 306. In this example, the estimator also maintains a measure of the decoupling of the estimates of the second-order and third-order coefficients. The third-order estimated coefficients are selected based on the decoupling measure. If the measure indicates that there is sufficient decoupling between the estimates of the second-order and third-order coefficients, then the third-order estimated coefficients are selected.

[0053] As mentioned previously, the NL coefficient estimator and tracker 304 may use Figures 11 to 13 Displayed in the middle and referenced below Figures 11 to 13 The nonlinear correction circuit is implemented using the circuit described in

[15] . As described in further detail below, the nonlinear correction circuit includes a main data path and a reference data path. The input signal is digitized in each data path and converted from the time domain to the frequency domain. A channel estimate for the reference data path is calculated relative to the main data path, and the channel estimate is used to equalize the reference data path. The equalized reference data path data is subtracted from the main data path data, and the difference is provided along with the main data path ADC output to the nonlinear coefficient estimation circuit for generating nonlinear correction coefficients. In this example, the reference path facilitates subtracting the digital step attenuator input (including the source nonlinear component and second-order nonlinear components caused by the PCB circuit or even the input signal) from the signal 150 output by the main ADC 114.

[0054] As further mentioned, there are some use case scenarios where the second-order nonlinear component may alias and fall back close to (or above) the third-order nonlinear component, or vice versa. In such scenarios, either or both the blind NL estimate or the reference-based NL estimate may become slow to converge or bias. Selectors 302 and 306 may be used to address aliasing.

[0055] In an example, the NL coefficient generator 122 can run in the background, with blind NL estimation (block 300) and reference-based NL estimation (block 304) interleaved. Thus, one estimation method is executed during one time interval or cycle, while the other estimation method is executed during the next time interval or cycle. In a specific example, the NL coefficient generator 122 switches between the two estimation methods every 100 milliseconds. However, depending on how quickly the estimation methods converge relative to each other, one estimation method may be executed for a longer time interval than the other estimation method.

[0056] For example, during both estimation methods, both second-order and third-order NL terms are generated. Additionally, both second-order and third-order NL correction coefficients and their uncertainty or quality are tracked (e.g., using a multi-state Kalman filter). Furthermore, when using a statistically based filter (e.g., a multi-state Kalman filter) in NL coefficient estimation, previous or historical data can be used to weight current data to improve the NL coefficient estimates. For example, both estimation modes have independent Kalman filters to estimate and track coefficients. Kalman filter-based implementations also use a state error covariance matrix to track the quality of the estimates. This state error covariance matrix data can be used to determine the decoupling between the estimated coefficients. If the error covariance matrix indicates that the covariance between any second-order coefficient estimate and any third-order coefficient estimate is below a configured threshold, then they are decoupled.

[0057] During blind NL estimation, second-order NL coefficients are selected based on an error covariance between the second-order NL coefficients and an estimate of the third-order NL coefficients (block 302). Similarly, during reference-based NL estimation, third-order NL coefficients are selected based on an error covariance between the third-order NL coefficients and an estimate of the second-order NL coefficients (block 306). When the error covariance (e.g., covariance correlation in decibels (dB)) falls below a programmable threshold, the NL coefficient estimate may be considered reliable and, thereby, selected and provided to the NL corrector 116.

[0058] Figure 4 Description in Figure 3 Graph 400 of example simulation results of the error covariance between second-order and third-order nonlinear coefficients generated in nonlinear coefficient generator 122 is shown in FIG. Graph 400 illustrates a plot 402 of the covariance correlation in dB over several interruptions during the calculation of the covariance values.

[0059] In this first scenario, the ADC 114 sampling rate (F s ) is 256. In (frequency) bin #51 (approximately F s / 5) and frequency bins 102 and 103 are used for nonlinear coefficient estimation. In this case, the 2F second-order nonlinear component will fall into bin 102. The 3F third-order nonlinear coefficient will fall into bin 153 and alias back to bin 103 (F s -3F=256-153). Due to the presence of one bin gap, the NL coefficient estimates converge over time (e.g., after about 30 seconds), as shown by the decrease in covariance correlation. Once the covariance value is at an acceptable level (e.g., -70 dB), the NL coefficient generator 122 can resume providing NL correction coefficients to the NL corrector 116.

[0060] Figure 5 Description in Figure 3Another graph 500 of example simulation results of the error covariance between the second and third order nonlinear term coefficients generated in the nonlinear coefficient generator 122 is shown in. The graph 500 illustrates a plot 502 of the covariance correlation in dB over several interruptions during the calculation of the covariance values.

[0061] In this second scenario, the ADC 114 sampling rate (F s ) is 256. In bin #51.2 (exactly F s 5), and frequency bins 102 and 103 are used for nonlinear coefficient estimation. In this case, the 3F third-order nonlinear component aliases back onto the 2F second-order nonlinear component. When this occurs, the NL coefficient estimation does not converge, as demonstrated by the covariance correlation remaining stable over time. Therefore, the NL coefficient generator 122 can stop providing NL correction coefficients to the NL corrector 116 until the covariance correlation is at an acceptable level.

[0062] Figure 6 Description can be made by Figures 1 to 3 FIG. 6 is a flow chart of an example method 600 for nonlinear correction performed by a nonlinear correction circuit shown in FIG. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some implementations may only perform some of the actions shown.

[0063] Typically, the circuit receives a first output signal (e.g., signal 150 or 154) from a data signal path including a first ADC and an NL corrector, and receives a second output signal from a second ADC. The circuit uses the first output signal to generate a first NL coefficient (e.g., a second-order NL coefficient) and uses the first and second output signals to generate a second NL coefficient (e.g., a third-order NL coefficient). The circuit applies the first and second NL coefficients to compensate for the NL component in the digitized signal output from the first ADC to generate a corrected digitized signal.

[0064] More specifically, at block 602, signals are received into the data signal (main) path and the reference path. For example, signal 146 is received into the DSA 112 of the main path and the DSA 118 of the reference path. At block 604, each of the ADC 112 in the main path and the ADC 120 in the reference path digitizes the signals. At block 606, the NL coefficient generator 122 determines whether a reference ("REF") ADC flag is received from the controller 124.

[0065] If the REF ADC flag is received, the NL coefficient estimator and tracker 304 (and, in one embodiment, the third-order NL coefficient selector 306) receives the first digitized signal (signal 150 or signal 154) from the main path and the second digitized signal (signal 148) from the reference path at block 608. The NL coefficient estimator and tracker 304 (and the selector 306, if used) processes the two digitized signals using blocks 610-620 to generate third-order NL coefficients and provides them to the NL corrector 116.

[0066] Referring to the process, at block 610, the NL coefficient estimator and tracker 304 generates NL terms, either only third-order NL terms if the selector 306 is not used, or both second-order and third-order NL terms if the selector 306 is used. At block 612, the NL coefficient estimator and tracker 304 generates first frequency domain data from the first and second digitized signals and the NL terms.

[0067] At block 614, the NL coefficient estimator and tracker 304 performs a signal subtraction to generate second frequency domain data. For example, the frequency domain data of signal 148 is subtracted from the frequency domain data of signal 150 or 154. The frequency domain data resulting from the subtraction and the frequency domain data of the NL term constitute the second frequency domain data. At block 614, the subtraction removes the common input signal as well as the source nonlinear component and the nonlinear component caused by the PCB circuit 108.

[0068] At block 616, the NL coefficient estimator and tracker 304 estimates the NL coefficients using the second frequency domain data. If the selector 306 is not used, the third-order NL coefficients are estimated based on or using only the third-order NL terms. Otherwise, both the second-order and third-order NL coefficients are estimated based on or using the second-order and third-order NL terms. At block 618, the selector 306 determines a decoupling measure (e.g., a first covariance value) based on the estimates of the second-order and third-order NL coefficients and selects the third-order NL coefficients based on the first covariance value. At block 620, the NL coefficient generator 122 provides the third-order NL coefficients to the NL corrector 116.

[0069] If the REF ADC flag is not received, the NL coefficient estimator and tracker 300 (and, in one embodiment, the second-order NL coefficient selector 302) receives a unique digitized signal (signal 150 or signal 154) from the primary path at block 622. The NL coefficient estimator and tracker 300 (and the selector 302, if used) processes the digitized signal using blocks 624 to 632 to generate the second-order NL coefficients and provides them to the NL corrector 116.

[0070] Referring to the process, at block 624, the NL coefficient estimator and tracker 300 generates NL terms, either only second-order NL terms if the selector 302 is not used, or both second-order and third-order NL terms if the selector 302 is used. At block 626, the NL coefficient estimator and tracker 300 generates frequency domain data from the received digitized signal and the NL terms.

[0071] At block 628, the NL coefficient estimator and tracker 300 estimates the NL coefficients using the frequency domain data. If the selector 302 is not used, the second-order NL coefficients are estimated based on or using only the second-order NL terms. Otherwise, both the second-order and third-order NL coefficients are estimated based on or using the second-order and third-order NL terms. At block 630, the selector 302 determines a decoupling measure (e.g., a second covariance value) based on the estimates of the second-order and third-order NL coefficients and selects the second-order NL coefficients based on the second covariance value. At block 632, the NL coefficient generator 122 provides the second-order NL coefficients to the NL corrector 116.

[0072] At block 634, the NL corrector 116 receives the second-order and third-order NL coefficients. The NL corrector 116 uses the second-order and third-order NL coefficients to correct for nonlinear components in the signal 150 output from the main ADC 114 to generate a corrected digitized signal 154. The second-order and third-order NL coefficients are applied to compensate for nonlinear components caused by circuits in the data signal path without compensating for source nonlinear components. More specifically, the second-order NL coefficients are applied to compensate for second-order nonlinear components caused by the PCB circuit 108, the DSA 112, and the ADC 114, and the third-order NL coefficients are applied to compensate for third-order nonlinear components caused by the DSA 112 and the ADC 114.

[0073] Figure 7 Depicting a nonlinear correction circuit 700 comprising the NL corrector 116 and an example NL coefficient estimator and tracker 300 that processes only the digital signal output from the primary path to facilitate nonlinear correction, the nonlinear correction circuit 700 may be implemented in a Figure 1 and 3 1. In one example, the digital signal output from the main path and processed by the NL coefficient estimator and tracker 300 is the signal 150 output from the main ADC 114. In another example, the digital signal output from the main path and processed by the NL coefficient estimator and tracker 300 is the signal 154 output from the NL corrector 116. At run time during normal operation of the nonlinear corrector 116, the NL coefficient estimator and tracker 300 generates nonlinear correction coefficients for use by the nonlinear corrector 116.

[0074] The NL coefficient estimator and tracker 300 includes a data capture circuit 706, a nonlinear term generation circuit 708, a time-to-frequency conversion circuit 710, a bin identification circuit 712, a residual nonlinear conversion circuit 714, and a nonlinear coefficient generation circuit 716. The data capture circuit 706 is coupled to an input of the nonlinear corrector 116 and an output of the nonlinear corrector 116 to selectively capture raw data samples of the digital signal 150 or samples of the nonlinear corrected data 154 for use in generating nonlinear correction coefficients.

[0075] The data capture circuit 706 is coupled to the nonlinear term generation circuit 708 and the time-to-frequency conversion circuit 710. The nonlinear term generation circuit 708 receives the captured data from the data capture circuit 706 and processes the data to generate nonlinear terms. For example, a set of 256+k samples is captured from x[n] and different NL terms are generated from the captured samples, such as x[n]. 3 [n], x 2 [n]x′[n], x 2 [n]x[n+1], (x′[n]) 3 or higher order NL terms. For each NL term, 256 samples are generated. However, due to memory effects when generating digital derivatives or other memory terms, an additional 'k' samples (256+k total) are captured at the input to effectively generate 256 samples for each NL term. In an example, the digital derivative is generated by an antisymmetric finite impulse response (FIR) filter, or may be generated by other known means.

[0076] The nonlinear term generation circuit 708 is coupled to the time-to-frequency conversion circuit 710 and provides the nonlinear term generated based on the data captured by the data capture circuit 706 to the time-to-frequency conversion circuit 710. The time-to-frequency conversion circuit 710 converts the data captured by the data capture circuit 706 and the nonlinear term generated by the nonlinear term generation circuit 708 from the time domain to the frequency domain. For example, the time-to-frequency block 711 (only one of four is labeled) of the time-to-frequency conversion circuit 710 applies a fast Fourier transform ("FFT") to the captured data received from the data capture circuit 706 and the nonlinear term generated by the nonlinear term generation circuit 708. In some embodiments, the time-to-frequency conversion circuit 710 applies the FFT after multiplying the input data by a window function.

[0077] The time-to-frequency conversion circuit 710 is coupled to a bin identification circuit 712 and provides frequency domain data and its nonlinear terms derived from the data captured by the data capture circuit 706 to the bin identification circuit 712. The bin identification circuit 712 processes the frequency domain data to identify frequency bins for generating nonlinear correction coefficients. More specifically, the bin identification circuit 712 identifies frequency bins having high-level created nonlinear terms and low-level input signals, e.g., compared to corresponding thresholds, for generating nonlinear correction coefficients.

[0078] The residual nonlinear conversion circuit 714 allows the nonlinear corrected data 154 produced by the nonlinear corrector 116 to be used as input to the nonlinear coefficient estimator and tracker 300, which provides performance improvements for second-order effects caused by large original nonlinear levels. The residual nonlinear conversion circuit 714 modifies the frequency response of the nonlinear corrected data 154 by adding a plurality of correction terms to the frequency response of the nonlinear corrected data 154. Each correction term is the product of the frequency response of each nonlinear term and the corresponding correction coefficient value applied in the nonlinear corrector 116. The modification of the frequency response of the nonlinear corrected data 154 converts the nonlinearity measure from a "residual nonlinearity measure" to a "full nonlinearity measure."

[0079] The frequency bins identified by the bin identification circuit 712 and modified by the residual nonlinear conversion circuit 714 are processed by the nonlinear coefficient generation circuit 716 to estimate and track the nonlinear correction coefficients for each DSA range for use by the nonlinear corrector 116. The nonlinear coefficient generation circuit 716 generates the nonlinear correction coefficients for the currently used configuration of the DSA 112 and the ADC 114. In some example implementations, the nonlinear coefficient generation circuit 716 includes a multi-state Kalman filter to generate the nonlinear correction coefficients. At the frequency bin selected by the bin identification circuit 712, the nonlinear term response acts as a weight for the coefficient to be estimated, and the "full nonlinearity measure" provided by the residual nonlinear conversion circuit 714 acts as a measure as shown by the matrix relationship in equation (5) below.

[0080] Further with respect to the estimation performed by the NL coefficient generation circuit 716, assume that the digital nonlinear correction applied to the output signal 150 from the ADC 114 is modeled using four terms:

[0081] y[n]=x[n]+c1x 3 [n]+c2x 2 [n]x′[n]+c3x 2 [n]+c4x[n]x′[n]+noise(1)

[0082] in:

[0083] x[n] is the discretized output of ADC 104 or analog circuit;

[0084] x′[n] is the effective derivative of x[n] (output signal 150 from ADC 114);

[0085] c i is the coefficient of each nonlinear term; and

[0086] y[n] is the output of the digital nonlinear corrector.

[0087] Equation (1) can be written in the frequency domain as:

[0088] F(y[n])=F(x[n])+c1F(x 3 [n])+c2F(x 2 [n]x′[n])+c3F(x 2 [n])+c4F(x[n]x′[n])+noise(2)

[0089]

[0090] Wherein equation (2) is valid for each frequency bin.

[0091] The left side of equation (2) represents the nonlinearity introduced by ADC 114 or associated analog circuits. In the frequency bin where there is no ADC input signal, equation (2) can be written as:

[0092]

[0093] Equation (3) can be used to estimate the nonlinear coefficients c1, c2, c3, and c4. In addition, the original nonlinear level is below about -55dBFS. In fact, all frequency bins whose signal levels are below a threshold (e.g., -55dBFS) can be used to estimate the coefficients.

[0094] In the selected bin (selected by bin identification circuit 712), the linear equation simplifies to:

[0095]

[0096] The nonlinear correction circuit identifies a plurality of such linear equations and solves the equations to estimate the coefficients of all nonlinear terms.

[0097] That is, for each selected bin, there exists a linear equation. For example, for x 3 [n] Nonlinearity (or any other third-order nonlinearity or combination of third-order nonlinear terms), each data frame provides six equations for two-tone input. If there are 100 data capture frames in a nonlinear estimation window, then 600 equations will be stored.

[0098]

[0099] in:

[0100] N is the number of equations, for example, in equation (5);

[0101] T is the number of nonlinear terms, Example 1: For x 3 [n],x 2 x′[n], T=2, Example 2: For x 3 [n],x 2 [n]x′[n],x 2 [n]x[n+1], (x′[n]) 3 , T = 4;

[0102] h i，j is the Fourier transform of the jth nonlinear (NL) term from the ith equation at the selected frequency bin from the selected capture set;

[0103] c is the Tx1 vector of NL term coefficients to be estimated; and

[0104] m i is a measure of the i-th equation which is the Fourier transform of the ADC output x[n] at the selected frequency bin from the selected capture set.

[0105] Such a system of linear equations (Hc=m) is solved (eg, using least squares or Kalman filter based techniques) to estimate and track the nonlinear coefficients.

[0106] Some embodiments of the nonlinear correction circuit allow the nonlinearity corrected data to be used as input for the nonlinear coefficient estimation. If the coefficient estimator input is taken from the nonlinear corrector input, then the nonlinearity estimator sees the entire nonlinearity from the output of ADC 114. However, if the coefficient estimator input is taken from the output of nonlinear corrector 116, then the nonlinearity estimator sees only the residual nonlinearity remaining after the nonlinearity correction.

[0107] HΔc=m→H(cc corr )=m→Hc=Hc corr +m (6)

[0108] Therefore, in some embodiments, Hc corr is added to m before the coefficient estimation to equivalently produce a modified 'm' that reflects the entire nonlinearity. This enables the estimator to estimate the full nonlinearity in signal 150. Using the nonlinearity corrector output signal as input to the coefficient estimation results in improved performance due to the reduction of second-order effects. Other embodiments also estimate residual coefficients from the residual nonlinearity and add them to the currently programmed coefficients.

[0109] Figure 8 Describing the Figure 7 8. An example bin identification circuit 800 implemented in a nonlinear coefficient estimator and tracker, such as that implementing bin identification circuit 712, is shown in FIG. Bin identification circuit 800 includes a signal power circuit 802, a nonlinear term power circuit 804, a signal power comparator 806, a nonlinear term power comparator 808, and a decision circuit 810.

[0110] The signal power circuit 802 calculates the value of the signal power for each frequency domain bin of the frequency domain signal received from the time-to-frequency conversion circuit 710. Similarly, the nonlinear term power circuit 804 calculates the value of the nonlinear term power for each frequency bin of the frequency domain nonlinear terms received from the time-to-frequency conversion circuit 710. In some embodiments, for a given frequency bin, the nonlinear term power circuit 804 calculates the nonlinear term power as the sum of the squared magnitudes or the sum of the magnitudes of all nonlinear terms for the given frequency bin. In other embodiments, the magnitude of the nonlinear terms that exceed a threshold is used to calculate the nonlinear term power. In other embodiments, the magnitude of the frequency response of each nonlinear term at a given bin is compared to a threshold, and even if one of them crosses the threshold, it is considered to exceed the nonlinear power threshold.

[0111] For example, let the nonlinear term be x 3 [n], x 2 [n]x′[n], x 2 [n]x[n+1], (x′[n]) 3 , then one metric for determining the high level of the created nonlinear term in a frequency bin is:

[0112] |F(x 3 (n))| 2 +|F(x 2 (n)x′(n))| 2 +|F(x 2 (n)x(n+1))| 2 +|F((x′[n]) 3 )| 2 >NLThresh(7)

[0113] And one metric for determining the low-level signal level of a frequency bin is:

[0114] |F(x(n))|<SigThresh (8)

[0115] The above two conditions must be met to select the frequency bins for estimation.

[0116] The signal power comparator 806 compares the frequency bin signal power value generated by the signal power circuit 802 with a signal power threshold. The nonlinear term power comparator 808 compares the frequency bin nonlinear term power value generated by the nonlinear term power circuit 804 with the nonlinear term power threshold. The decision circuit 810 identifies the frequency bins to be used in the nonlinear correction coefficient estimation based on the comparison results performed by the signal power comparator 806 and the nonlinear term power comparator 808. The frequency bins with high nonlinear term power (e.g., power above the nonlinear term power threshold NLThresh) and low signal power (e.g., power below the signal power threshold SigThresh) are selected for nonlinear correction coefficient estimation. Therefore, the decision circuit 810 identifies the frequency bins with signal power less than the signal power threshold and nonlinear term power greater than the nonlinear term power threshold as suitable for nonlinear correction coefficient estimation.

[0117] In use for x 3 [n] or any third order nonlinear bin identification circuit 800 operates in an example where there is a single tone input at f, x 3 The frequency response of [n] is high at f and 3f. The signal level is high at the fundamental frequency f. The bin identification circuit 800 selects only the bin corresponding to 3f for nonlinear correction coefficient estimation.

[0118] In use for x 2 [n] or any second order nonlinear bin identification circuit 800 operates in an example where there is a single tone input at f, x 2 The frequency response of [n] is high at 0 and 2f. The signal level is high at the fundamental frequency f. The bin identification circuit 800 selects only the bins corresponding to 0 and 2f for nonlinear correction coefficient estimation.

[0119] In use for x 2 [n] or any second order nonlinear example of bin identification circuit 800 operation with a dual tone input at f1 and f2, x 2 The frequency response of [n] is high at 0, f2-f1, 2f1, f1+f2, and 2f2. The bin identification circuit 800 selects only the bins corresponding to 0, f2-f1, 2f1, f1+f2, and 2f2 for nonlinear correction coefficient estimation.

[0120] In the example of bin identification circuit 800 operation for a combination of second and third order nonlinear terms, with a single tone input at f, bin identification circuit 800 selects only the bins corresponding to 0, 2f, and 3f for nonlinear correction coefficient estimation.

[0121] In an example of the operation of the bin identification circuit 800 for a combination of second-order and third-order nonlinear terms, where there are dual-frequency inputs f1 and f2, the bin identification circuit 800 selects second-order bins (0, f2-f1, 2f1, f1+f2, and 2f2) and third-order bins (2f1-f2, 2f2-f1, 2f1+f2, 3f1, 3f2, 2f2+f1) in addition to the fundamental frequency bins f1 and f2.

[0122] Figure 9A 、 9B and 9C depict example bin identification in bin identification circuit 712. Figure 9A The signal power of a dual-tone input with frequencies f1 and f2 is shown. For this input signal, the third-order nonlinear term (x 3 ) or any other third-order nonlinear term has eight components at 2f1-f2, f1, f2, 2f2-f1, 2f1+f2, 3f1, 3f2, and 2f2+f1. Based on the comparison of the signal and the nonlinear term with the corresponding power threshold, as Figure 9B As illustrated, frequency bins at 2f1-f2, 2f2-f1, 2f1+f2, 3f1, 3f2, and 2f2+f1 are selected by bin identification circuit 800 for nonlinear correction coefficient estimation.

[0123] Although single and dual tone examples have been provided herein to describe the operation of the bin identification circuit 800, in practice, the input signal is narrowband or wideband modulated data. Figure 9C Example bin identification is shown for wideband data occupying the frequency band from f1 to f2. The regions selected for estimating third-order nonlinear terms are (2f1-f2 to f1), (f2 to 2f2-f1), and (3f1 to 3f2). The regions selected for estimating second-order terms are (0 to f2-f1) and (2f1 to 2f2). These regions may be aliased back to specific frequencies based on the sampling rate of ADC 114. In some cases, if the aliased frequencies fall back into the signal band, then those frequency bins are used because they will fail the signal power check.

[0124] Figure 10 Description can be made by Figure 1 and 7 1. A flowchart of an example method 1000 for nonlinear correction performed by the nonlinear correction circuit shown in FIG. 1. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some implementations may only perform some of the actions shown. The operations of method 1000 are performed by an implementation of the nonlinear correction circuit 700.

[0125] In block 1002, the nonlinear correction circuit 700 receives a signal as input to the DSA 112 and the ADC 114. For example, an input signal is provided at an input of the DSA circuit 112.

[0126] In block 1004, ADC 114 digitizes the input signal. Data capture circuit 706 captures the output of ADC 114. In some embodiments of method 1000, data capture circuit 706 may selectively capture the output of ADC 114 or the output of nonlinear corrector 116 for use as estimated input data.

[0127] In block 1006, nonlinear term generation circuit 708 processes the captured data and generates nonlinear terms for the captured data. Time-to-frequency conversion circuit 710 converts the data captured by data capture circuit 706 and the nonlinear terms generated by nonlinear term generation circuit 708 from the time domain to the frequency domain.

[0128] In block 1008, bin identification circuit 712 identifies frequency bins that should be used to estimate nonlinear correction coefficients. The identified frequency bins are frequency bins that have a signal power below a first threshold and a nonlinear power above a second threshold.

[0129] In block 1010, the residual nonlinearity conversion circuit 714 converts the residual nonlinearity measure into a fully nonlinearity measure by modifying the frequency response of the signal at the identified frequency bins. The frequency response is modified by adding a plurality of correction terms to the signal, where each correction term is the product of the frequency response of the nonlinearity term and a corresponding nonlinearity correction coefficient currently used in the nonlinearity corrector 116.

[0130] In block 1012 , the nonlinear coefficient generation circuit 716 generates and tracks nonlinear correction coefficients based on the signal and the nonlinear terms at the frequency bins identified by the bin identification circuit 712 .

[0131] In block 1014 , the nonlinearity corrector 116 applies nonlinearity correction coefficients to compensate for the nonlinearity in the nonlinearly corrected data 154 that was introduced into the digital signal 150 by the main path.

[0132] Figure 11 Depicts an example nonlinear correction circuit that uses digital signals output from both the data signal path and the reference path to facilitate nonlinear correction, which may be used in Figure 1 and 3 The nonlinear correction circuit shown in FIG is implemented. Figure 11A block diagram is shown for a nonlinear correction circuit 1100 that includes a reference data path 1104 that prevents the nonlinear correction circuit 1100 from compensating for input signal nonlinearities by subtracting the input signal from a signal used to generate nonlinear correction coefficients.

[0133] Nonlinear correction circuit 1100 includes a reference path 1104 having DSA circuit 118, ADC 120, data capture circuit 1108, time-to-frequency conversion circuit 1110, channel estimation circuit 1112, channel equalization circuit 1114, and source nonlinear subtraction circuit 1116. DSA circuit 118 includes an input coupled to the input of DSA circuit 112 and an output coupled to the input of ADC 120. Reference path 1104 is more linear than the data path (main data path) formed by DSA 112 and ADC 114. For example, ADC 120 is more linear than ADC 114, but may be noisier. ADC 114 and ADC 118 digitize input signal 146.

[0134] The nonlinear correction circuit further includes a data acquisition circuit 706, a nonlinear term generation circuit 708, a time-frequency conversion circuit 710, a bin identification circuit 712, a residual nonlinear conversion circuit 714, and a nonlinear coefficient generation circuit 716. In the example, these components are similar to Figure 7 Components with the same reference symbols are used for implementation.

[0135] Data capture circuitry 1108 is coupled to the output of ADC 120 to capture data samples. Time-to-frequency conversion circuitry 1110 is coupled to data capture circuitry 1108. The samples captured by capture circuitry 1108 are provided to time-to-frequency conversion circuitry 1110. Time-to-frequency conversion circuitry 1110 converts the time-domain captured samples of ADC 120 into a frequency-domain output signal 1120. For example, time-to-frequency conversion circuitry 1110 applies an FFT to the captured output signal received from data capture circuitry 1108 to generate a frequency-domain output signal 1120.

[0136] Time-to-frequency conversion circuit 1110 is coupled to channel estimation circuit 1112. Channel estimation circuit 1112 receives frequency domain signal 1120 generated by time-to-frequency conversion circuit 1110 and frequency domain signal 1118 generated by time-to-frequency conversion circuit 711, and estimates the channel of the data path formed by DSA 112 and ADC 114 relative to the reference path of DSA 118 and ADC 120. Channel estimation circuit 1112 is coupled to channel equalization circuit 1114. Channel equalization circuit 1114 receives the channel estimate from channel estimation circuit 1112 and applies the channel estimate to equalize frequency domain output signal 1120.

[0137] Channel equalization circuit 1114 is coupled to source nonlinear subtraction circuit 1116. Source nonlinear subtraction circuit 1116 receives frequency-domain output signal 1118 and equalized output signal 1122 generated by channel equalization circuit 1114. Source nonlinear subtraction circuit 1116 subtracts equalized output signal 1122 from frequency-domain output signal 1118 to effectively remove input signal 146 from the signal provided to bin identification circuit 712. Thus, the output of source nonlinear subtraction circuit 1116 effectively contains the nonlinearity introduced by ADC 114 and DSA 112. Source nonlinear subtraction circuit 1116 is coupled to bin identification circuit 712 and provides frequency-domain output signal 1118 minus equalized output signal 1122 to bin identification circuit 712 for determining nonlinear correction coefficients. In systems that include a reference path, some implementations of nonlinear estimation circuit 1100 omit the check for low signal power in bin identification circuit 800 because the fundamental frequency signal has already been removed from the signal processed by nonlinear correction circuit 116.

[0138] In practice, the circuit components of the main data path and the reference path are not well matched. For example, there is a gain, delay, and / or bandwidth mismatch between the main data path and the reference path. In some embodiments, the mismatch varies with the setting of the digital step attenuator. To compensate for this mismatch, the output of the reference ADC (the ADC in the reference path) is fed to a channel equalizer before being used for signal subtraction. The channel equalizer matches the two data paths for accurate cancellation of the input signal and source nonlinearity. The following nonlinear estimation equation is used for the estimation at each identified bin:

[0139]

[0140] Once the reference path is matched to the main path, the output of the reference path effectively represents the input to the ADC and DSA circuits. When subtracted from the output of ADC 114, what remains is the component introduced by ADC and DSA nonlinearities and noise. This is represented by the right side of equation (9). Note that the reference path can be noisy, and the effect of noise on the estimate can be minimized by averaging over time.

[0141] Ch models the frequency dependent mismatch between paths. Subtract Ch*F(x ref (n)) cancels out all ADC inputs present in the selected bin, and thus, only the nonlinear components of ADC 114 and DSA 112 remain after cancellation.

[0142] Figure 12 Describing the Figure 11 An example channel estimation circuit 1200 implemented in the nonlinear coefficient estimator and tracker shown in FIG. Figure 12A block diagram of a channel estimation circuit 1200 suitable for use in reference path 1104 is shown. Channel estimation circuit 1200 is an implementation of channel estimation circuit 1112. Channel estimation circuit 1200 includes raw channel estimation circuit 1202, base channel removal circuit 1204, base channel memory 1206, slope and intercept estimation circuit 1208, base channel estimator 1210, intercept memory 1212, and slope memory 1214. Raw channel estimation circuit 1202 receives frequency domain output signal 1118 and frequency domain output signal 1120 and provides a raw channel estimate value for each frequency bin by correlating the main path frequency domain response with the reference frequency domain response at each bin. For example, as shown in equation (10), a raw channel estimate is obtained. The raw inverse channel estimate is the ratio of the cumulative cross-correlation of the frequency responses of the main path and the reference path to the cumulative power of the main path response for a given frequency bin.

[0143]

[0144] H ch (f)=1 / Inverse_H ch (f) (10)

[0145] Base channel removal circuit 1204 is coupled to raw channel estimation circuit 1202 and base channel memory 1206. Base channel memory 1206 provides base channel values to base channel removal circuit 1204 for adjustment of the raw channel values. Base channel removal circuit 1204 receives the raw channel estimates generated by raw channel estimation circuit 1202 and adjusts each raw channel estimate to remove the base channel estimate value. Using the raw channel estimates and the estimated bin position for a given DSA setting, base channel removal circuit 1204 compensates for the base channel response contribution from the raw channel estimate value at that bin position.

[0146] The slope and intercept estimation circuit 1208 is coupled to the base channel memory 1206. The slope and intercept estimation circuit 1208 processes the adjusted channel values received from the base channel removal circuit 1204 to estimate and track the slope and intercept values for each DSA setting. The slope and intercept estimation circuit 1208 is coupled to the intercept memory 1212 and the slope memory 1214. The slope and intercept estimation circuit 1208 stores the intercept value in the intercept memory 1212 and the slope value in the slope memory 1214.

[0147] The base channel estimator 1210 is coupled to the intercept memory 1212 and the slope memory 1214. The base channel estimator 1210 uses the slope and intercept values stored in the slope memory 1214 and the intercept memory 1212, respectively, to estimate the base channel values. The base channel values model the common frequency-dependent mismatch across different DSA settings, while the slope and intercept values model the small residual mismatch for each DSA setting. The base channel estimator 1210 is coupled to the base channel memory 1206 and stores the base channel values in the base channel memory 1206. The base channel estimator 1210 calculates the gain and delay mismatch for each DSA setting using the corresponding intercept and slope values. If a common gain and / or delay component is identified across all DSA settings, the base channel estimator 1210 applies the common portion of the mismatch to refine the base channel response. The refined base channel response is stored in the base channel memory 1206. Given the refined base channel response, the previously estimated intercept and slope parameters are adjusted across all DSA settings to reflect only the residual mismatch. The adjusted slope and intercept values are stored in slope memory 1214 and intercept memory 1212, respectively.

[0148] Once we know the common gain or delay mismatch established across all DSA setups, the base channel is updated to:

[0149]

[0150] in:

[0151] A bin is a specific frequency bin position, and the bin range is 0, 1, ..., N FFT -1;

[0152] g mm is the common gain mismatch across all DSA setups;

[0153] d mm is the common delay mismatch across all DSA setups; and

[0154] N FFT is the size of the FFT used for time-to-frequency conversion.

[0155] In some embodiments, old_basec_ch is initially one.

[0156] When the base channel is updated, the intercept and slope for each DSA setting are updated as follows:

[0157] channel[bin][DSA]=old_base_ch[bin]*(old_Intercept[DSA]+bin*old_slope[DSA])=new_base_ch[bin]*(new_Intercept[DSA]+bin*new_slope[DSA]) (12)

[0158] For each DSA index, equation (12) is applied to two bin positions. For example, at bin = 10 and 100. The two linear equations are then solved to derive new intercept and slope values for each DSA index.

[0159] Figure 13 Describing the Figure 11 Example channel equalization circuit implemented in the nonlinear coefficient estimator and tracker shown in . Figure 13 A block diagram of a channel equalization circuit 1300 suitable for use in reference path 1104 is shown. Channel equalization circuit 1300 is an implementation of channel equalization circuit 1114. Channel equalization circuit 1300 is coupled to time-to-frequency conversion circuit 1110, base channel memory 1206, intercept memory 1212, and slope memory 1214. Channel equalization circuit 1300 includes calculation circuitry 1302 that calculates a channel compensation value (channel equalization value) for each frequency bin and applies the channel compensation value to the frequency-domain reference data for each frequency bin to equalize reference path 1104. Calculation circuitry 1302 of channel equalization circuit 1300 calculates the channel compensation value as:

[0160] Channel[DSA][Bin]=BaseChannel[Bin]*(C Intercept [DSA]+C Slope [DSA]*Bin) (13)

[0161] in:

[0162] Channel is the channel compensation value;

[0163] DSA is the attenuation selection index (DSA index value) applied in the DSA circuit 112;

[0164] Bin is the frequency bin index;

[0165] BaseChannel is the base channel value retrieved from base channel memory 1206;

[0166] C Intercept is the intercept value retrieved from intercept memory 1212; and

[0167] C Slopeis the slope value retrieved from slope memory 1214 .

[0168] Channel equalization circuit 1300 calculates an equalized data value, which is the product of the channel compensation value and the value (frequency domain data value) of frequency domain output signal 1120. Implementations of channel equalization circuit 1300 are compact in size (e.g., in the range of 1 / 8 the size of other equalization circuits).

[0169] Figure 14 Description can be made by Figure 1 and 11 1100. A flowchart of an example method 1400 for nonlinear correction is shown, performed by the nonlinear correction circuit shown in FIG. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some implementations may only perform some of the actions shown. The operations of method 1400 are performed by an implementation of nonlinear correction circuit 1100.

[0170] In block 1402, the nonlinearity correction circuit 1100 receives a signal as input to the DSA 112 of the main data path and the DSA 118 of the reference path 1104. In some examples, the input signal includes nonlinearity.

[0171] In block 1404, ADC 114 digitizes the input signal in the main data path, and ADC 120 digitizes the input signal in the reference path 1104. Data capture circuit 706 captures the output of ADC 114, and data capture circuit 1108 captures the output of ADC 120. In some embodiments of method 1400, data capture circuit 706 can selectively capture the output of ADC 114 or the output of nonlinearity corrector circuit 116 for use as estimated input data. Time-to-frequency conversion circuit 711 converts the captured digital output of ADC 114 from the time domain to the frequency domain, and time-to-frequency conversion circuit 1110 converts the captured digital output of ADC 120 from the time domain to the frequency domain.

[0172] In block 1406 , channel estimation circuit 1112 processes the frequency domain data provided by time-to-frequency conversion circuits 1110 and 711 to generate a channel estimate of reference path 1104 relative to the primary data path.

[0173] In block 1408 , channel equalization circuitry 1114 applies the channel estimates produced by channel estimation circuitry 1112 to equalize frequency-domain output signal 1120 .

[0174] In block 1410 , the source nonlinear subtraction circuit 1116 subtracts the equalized output signal 1122 from the frequency domain output signal 1118 .

[0175] In block 1412, nonlinear term generation circuit 708 processes the captured data and generates nonlinear terms for the data captured by data capture circuit 706. Time-to-frequency conversion circuit 710 converts the nonlinear terms generated by nonlinear term generation circuit 708 from the time domain to the frequency domain.

[0176] In block 1414, the bin identification circuit 712 identifies frequency bins that should be used to estimate the nonlinear correction coefficients. The identified frequency bins are frequency bins that have a signal power below a first threshold and a nonlinear power above a second threshold.

[0177] In block 1416, the residual nonlinearity conversion circuit 714 converts the residual nonlinearity measure into a fully nonlinearity measure by modifying the frequency response of the signal at the identified frequency bins. The frequency response is modified by adding a plurality of correction terms to the signal, where each correction term is the product of the frequency response of the nonlinearity term and a corresponding nonlinearity correction coefficient currently used in the nonlinearity corrector circuit 116.

[0178] In block 1418 , the nonlinear coefficient generation circuit 716 generates and tracks nonlinear correction coefficients based on the signal and the nonlinear terms at the frequency bins identified by the bin identification circuit 712 .

[0179] In block 1420 , the nonlinearity corrector circuit 116 applies nonlinearity correction coefficients to compensate for nonlinearities in the nonlinearly corrected data 154 that were introduced into the digital signal 150 by the main path.

[0180] The above examples illustrate several possible embodiments of various aspects of the present disclosure, wherein equivalent changes and / or modifications will occur to other skilled in the art after reading and understanding this specification and the accompanying drawings. Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A method for nonlinear correction, comprising: receiving a first output signal from a circuit comprising a first analog-to-digital converter; receiving a second output signal from a second analog-to-digital converter; generating a second-order nonlinear coefficient using the received first output signal but not the received second output signal; generating third-order nonlinear coefficients using both the received first and second output signals; and The second-order and third-order nonlinear coefficients are applied by a nonlinear corrector included in the circuit to compensate for nonlinear components in the digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal. 2 . The method of claim 1 , wherein the first output signal is the digitized signal output from the first analog-to-digital converter. The method of claim 1 , wherein the first output signal is the corrected digitized signal.

4. The method of claim 1 , wherein generating the second-order nonlinear coefficients comprises: Generate second-order and third-order nonlinear terms; jointly estimating the second-order nonlinear coefficient and the third-order nonlinear coefficient using the second-order and third-order nonlinear terms; Calculating decoupled measures of the second-order and third-order nonlinear coefficients; and The second-order nonlinear coefficients are selected and provided based on the decoupling measurement.

5. The method of claim 1 , wherein generating the second-order nonlinear coefficients comprises: Only second-order nonlinear terms are generated; and The second-order nonlinear coefficient is estimated using the second-order nonlinear term.

6. The method of claim 1 , wherein generating the third-order nonlinear coefficients comprises: Generate second-order and third-order nonlinear terms; jointly estimating the third-order nonlinear coefficient and the second-order nonlinear coefficient using the second-order and third-order nonlinear terms; Calculating decoupled measures of the second-order and third-order nonlinear coefficients; and The third-order nonlinear coefficients are selected and provided based on the decoupling measurement.

7. The method of claim 1 , wherein generating the third-order nonlinear coefficients comprises: Only third-order nonlinear terms are generated; and The third-order nonlinear coefficient is estimated using the third-order nonlinear term.

8. The method according to claim 1, wherein: The nonlinear component includes: a source nonlinear component and a nonlinear component caused by the circuit, and The second-order and third-order nonlinear coefficients are applied to compensate for the nonlinear components caused by the circuit without compensating for the source nonlinear components.

9. The method according to claim 8, wherein the second-order nonlinear coefficient is applied to compensate for the second-order nonlinear component caused by the board circuit and the first analog-to-digital converter included in the circuit, and the third-order nonlinear coefficient is applied to compensate for the third-order nonlinear component caused by the first analog-to-digital converter.

10. The method of claim 1 , wherein generating the third-order nonlinear coefficients using the first and second output signals comprises: generating first frequency domain data from the first output signal; generating second frequency domain data from the second output signal; subtracting the second frequency domain data from the first frequency domain data to remove the source input signal having the source nonlinear component and the nonlinear component caused by the board circuit to generate third frequency domain data; and The third-order nonlinear coefficient is estimated using the third frequency domain data.

11. A device comprising: A nonlinear coefficient generator configured to: receiving a first digitized signal and a second digitized signal; processing the received first digitized signal without processing the received second digitized signal to generate second-order nonlinear coefficients; and processing both the first received digitized signal and the second received digitized signal to generate third-order nonlinear coefficients; and A nonlinear corrector is coupled to the nonlinear coefficient generator, the nonlinear corrector being configured to generate a corrected digitized signal by applying the second-order and third-order nonlinear coefficients to correct nonlinear components in the digitized signal at the output of the analog-to-digital converter. 12 . The apparatus according to claim 11 , wherein the nonlinear coefficient generator is configured to process the digitized signal output from an analog-to-digital converter as the first digitized signal.

13. The apparatus of claim 11, wherein the nonlinear coefficient generator is configured to process the corrected digitized signal as the first digitized signal.

14. The apparatus of claim 11 , wherein the nonlinear coefficient generator is configured to process the first and second digitized signals to generate the third-order nonlinear coefficients by being configured to: generating first frequency domain data from the first digitized signal; generating second frequency domain data from the second digitized signal; subtracting the second frequency domain data from the first frequency domain data to remove the source input signal having the source nonlinear component and the nonlinear component caused by the board circuit to generate third frequency domain data; and The third-order nonlinear coefficient is estimated using the third frequency domain data.

15. The apparatus of claim 11 , wherein the nonlinear coefficient generator is configured to process the first digitized signal to generate the second-order nonlinear coefficient by being configured to: Generate second-order and third-order nonlinear terms; jointly estimating the second-order nonlinear coefficient and the third-order nonlinear coefficient using the second-order and third-order nonlinear terms; Calculating decoupled measurements of the second-order and third-order nonlinear coefficients; and The second-order nonlinear coefficients are selected and provided based on the decoupling measurement.

16. The apparatus of claim 11 , wherein the nonlinear coefficient generator is configured to process the first and second digitized signals to generate the third-order nonlinear coefficients by being configured to: Generate second-order and third-order nonlinear terms; jointly estimating the third-order nonlinear coefficient and the second-order nonlinear coefficient using the second-order and third-order nonlinear terms; Calculating decoupled measurements of the second-order and third-order nonlinear coefficients; and The third-order nonlinear coefficients are selected and provided based on the decoupling measurement.

17. The apparatus of claim 11 , wherein the nonlinear coefficient generator is configured to generate the second-order and third-order nonlinear coefficients such that, when applied to the digitized signal at the output of the analog-to-digital converter, source nonlinear components at the input of the analog-to-digital converter are preserved in the corrected digitized signal.

18. An apparatus comprising: A first circuit comprising: a first analog-to-digital converter (ADC) having a first ADC input and a first ADC output; and a nonlinear corrector having a first nonlinear corrector input coupled to the first ADC output and having a second nonlinear corrector input; a second circuit comprising a second ADC having a second ADC input and a second ADC output; and a nonlinear coefficient generator having a first input coupled to the first circuit, a second input coupled to the second ADC output, and an output coupled to the second nonlinear corrector input, wherein the nonlinear coefficient generator is configured to: receiving a first digitized signal from the first circuit; receiving a second digitized signal from the second ADC; generating second-order nonlinear coefficients using the first digitized signal; generating third-order nonlinear coefficients using the first and second digitized signals; and The second-order and third-order nonlinear coefficients are provided to the nonlinear corrector.

19. The apparatus of claim 18, wherein the first circuit further comprises a first digital step attenuator (DSA) having a first DSA input and a first DSA output coupled to the first ADC input, and the second circuit further comprises a second DSA having a second DSA input coupled to the first DSA input and having a second DSA output coupled to the second ADC input.

20. The apparatus of claim 19, further comprising board circuitry coupled to the first and second DSA inputs, and wherein the nonlinear coefficient generator is further configured to: generating first frequency domain data from the first digitized signal; generating second frequency domain data from the second digitized signal; subtracting the second frequency domain data from the first frequency domain data to remove the source input signal having the source nonlinear component and the nonlinear component caused by the board circuit to generate third frequency domain data; and The third-order nonlinear coefficient is estimated using the third frequency domain data.

21. The apparatus of claim 18, wherein the nonlinear coefficient generator is configured to generate second-order and third-order nonlinear coefficients by being configured to: generating a first set of second-order and third-order nonlinear terms using the first digitized signal; jointly estimating a first set of second-order and third-order nonlinear coefficients using the first set of second-order and third-order nonlinear terms; determining a first decoupled measurement of the second-order and third-order nonlinear coefficients; selecting the second-order nonlinear coefficient from the first set of second-order and third-order nonlinear coefficients based on the first decoupling measurement and providing it to the nonlinear corrector; generating a second set of second-order and third-order nonlinear terms using the first digitized signal; jointly estimating a second set of second-order and third-order nonlinear coefficients based on the second digitized signal using the second set of second-order and third-order nonlinear terms; determining a second decoupled measurement of the second-order and third-order nonlinear coefficients; and Based on the second decoupling measure, the third-order nonlinear coefficient is selected from the second set of second-order and third-order nonlinear coefficients and provided to the nonlinear corrector.

22. The apparatus of claim 18, wherein the second ADC is more linear than the first ADC.

23. A method for nonlinear correction, comprising: receiving a first output signal from a circuit comprising a first analog-to-digital converter; receiving a second output signal from a second analog-to-digital converter; generating a second-order nonlinear coefficient using the received first output signal but not the received second output signal; generating third-order nonlinear coefficients using both the received first and second output signals; and The second-order and third-order nonlinear coefficients are applied by a nonlinear corrector included in the circuit to compensate for nonlinear components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal, the nonlinear components including a source nonlinear component and a nonlinear component caused by the circuit; wherein the second-order and third-order nonlinear coefficients are applied to compensate for the nonlinear component caused by the circuit without compensating for the source nonlinear component.

24. A receiver circuit comprising: Printed circuit board PCB circuit; A first circuit comprising: a first digital step attenuator (DSA) having a first DSA input and a first DSA output, wherein the first DSA input is coupled to the PCB circuit; a first analog-to-digital converter (ADC) having a first ADC input and a first ADC output, the first ADC input being coupled to the first DSA output; and a nonlinear corrector having a first nonlinear corrector input coupled to the first ADC output and having a second nonlinear corrector input; A second circuit comprising: a second DSA having a second DSA input and a second DSA output, the second DSA input being coupled to the PCB circuit; as well as a second ADC that is more linear than the first ADC, the second ADC having a second ADC input and a second ADC output, the second ADC input being coupled to the second DSA output; a nonlinear coefficient generator having a first input coupled to the first circuit, a second input coupled to the second ADC output, and an output coupled to the second nonlinear corrector input, wherein the nonlinear coefficient generator is configured to: receiving a first digitized signal from the first circuit; receiving a second digitized signal from the second ADC; generating second-order nonlinear coefficients using the first digitized signal; generating third-order nonlinear coefficients using the first and second digitized signals; as well as providing the second-order and third-order nonlinear coefficients to the nonlinear corrector, and wherein the nonlinear corrector is configured to: receiving a digitized output signal from the first ADC, the digitized output signal comprising a source nonlinear component, a second-order nonlinear component caused by the PCB circuit and the first ADC, and a third-order nonlinear component caused by the first ADC; applying the second-order nonlinear coefficient to compensate for the second-order nonlinear component; applying the third-order nonlinear coefficient to compensate for the third-order nonlinear component; as well as A corrected digitized signal is generated that includes the source nonlinear component.

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