LED display system and method for increasing dynamic range of LED display

Abstract

The LED display system includes an LED array and a driving circuit. The driving circuit has a PWM engine, an adder, an accumulator, a multiplier, and a frame buffer. The multiplier multiplies the image data PWM of the first bit depth by a multiple M to generate input data PWM_M with a second bit depth. The multiple M has an integer part M of one or more bit lengths. I and a fractional part M of one or more bits in length F The input data has an integer part (PWM_M I and a fractional part PWM_M F The adder converts the current input data PWM_M F The PWM engine receives the PWM data from the frame buffer and generates PWM pulses to drive the LED array.

Description

Technical Field

[0001] The present invention generally introduces a method and apparatus for driving an LED array, and more particularly, relates to a method and apparatus for enabling extended grayscale values ​​for an LED display panel. Background Art

[0002] Modern LED display panels require higher grayscale levels (i.e. grayscale values, grayscale) to achieve higher color depth and higher visual refresh rates to reduce flicker. For example, the 16-bit grayscale value of an RGB LED pixel can enable R, G, and B LEDs to achieve 16-bit color levels (2 16 =65536). Such an RGB LED pixel can display a total of 655363 colors. A commonly used method to adjust the grayscale of an LED is pulse width modulation (PWM). Simply put, pulse width modulation (PWM) turns the LED on or off according to the width of the signal pulse (i.e., pulse duration or pulse width). The ratio of the on time and the off time determines the brightness of the LED. Different ratios represent different grayscales. The configuration and operation of the LED display system, including the LED topology, circuit system, PWM scheme and PWM engine are explained in detail in U.S. Patent 8,963,811B2 filed on September 21, 2011.

[0003] Most LED displays currently on the market have a 16-bit grayscale range, which is insufficient to simulate the full range of brightness visible to the human eye. For example, the brightness range of the most advanced LED displays is 0.1 nit to 1,700 nits. It is desirable to have a display with a wider brightness range, for example, a display that emits light with a brightness of 0.005 nit to 10,000 nits. Therefore, it is necessary to adopt corresponding methods and devices to expand the brightness range of LED display screens. Summary of the invention

[0004] In one embodiment, an LED display system with increased dynamic range is provided. The LED display system includes a plurality of LEDs arranged in an LED array and a drive circuit configured to drive the LED array. The LED (or LED pixel) may be an RGB LED or a monochrome LED. The drive circuit includes a PWM engine, an adder (i.e., an adder circuit), an accumulator (i.e., a register circuit), a multiplier (i.e., a binary multiplier circuit), and a frame buffer. The frame buffer may include a transmitter and one or more memories. The PWM engine receives PWM data from the frame buffer and generates a plurality of PWM pulses (or simply "pulses") to drive the LED array.

[0005] During operation, the multiplier multiplies image data (PWM) of a first bit depth by a multiplier (M) to generate input data (PWM_M) having a second bit depth. The multiplier has an integer portion (M) of one or more bit lengths. I ) and one or more bit-length fractional parts (M F The input data has an integer part (PWM_M I ) and a small fractional part (PWM_M F ). The adder converts the current input data PWM_M F The driver circuit operates to update the remainder to equal the sum of the addition. The driver circuit further operates to subtract the integer 1 from the sum of the addition, and when the sum of the addition operation is equal to or greater than the integer 1, the remainder in the accumulator is updated to equal the result of the subtraction, and the integer "1" is added to the PWM_M I PWM_M I The value is sent to the frame buffer, which provides PWM data to the PWM engine to generate PWM pulses.

[0006] In one embodiment, PWM_M I One of the bits in the adder that receives an integer "1" from the adder is specifically designated for the receive function and has a default value of zero. The adder fills that bit with an integer "1" regardless of the current value stored in that bit.

[0007] In another embodiment, the PWM engine generates PWM pulses in the following manner: I Each non-zero bit in generates multiple pulses, and the number of pulses is consistent with the specified value of the non-zero bit, not PWM_M I Each bit carrying an integer 0 generates a pulse regardless of PWM_M F What is the value of each bit? None of them is PWM_M F A pulse is generated for each bit in.

[0008] In another embodiment, a method for increasing the dynamic range of an LED display is provided. The method includes the following steps: multiplying image data (PWM) of a first bit depth by a multiple (M) to generate input data (PWM_M) having a second bit depth, wherein the multiple has an integer part (M) of one or more bit lengths. I ) and one or more bit-length fractional parts (M F ), where the input data has an integer part (PWM_M I ) and the fractional part (PWM_M F );PWM_M of current input data FThe value of the accumulator is added to the remainder in the accumulator. When the sum of the addition is less than 1, the remainder is updated to be equal to the sum of the addition. When the sum of the addition is equal to or greater than the integer 1, the integer 1 is subtracted from the sum of the addition, and the remainder is updated to be equal to the result of the subtraction, and the PWM_M is filled with the integer 1. I and set PWM_M I The frame buffer provides PWM data to the PWM engine for generating PWM pulses to drive the LED array.

[0009] In another embodiment of the method for increasing the dynamic range of an LED display, PWM_M is filled with integer 1. I The step of filling a bit in includes filling the bit with an integer 1, regardless of the current value stored in the bit. When the sum of the addition is equal to or greater than the integer 1, the bit is reserved for receiving the integer 1 from the addition operation, otherwise the value of the bit remains zero.

[0010] In another embodiment of the method for increasing the dynamic range of an LED display, the PWM engine generates PWM pulses in the following manner: I Each non-zero bit in generates multiple pulses, where the number of pulses is consistent with the specified value of the non-zero bit and is not PWM_M I Each bit carrying an integer 0 generates a pulse regardless of PWM_M F What is the value of each bit? None of them is PWM_M F A pulse is generated for each bit in . BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

[0012] Figure 1 2 is a data arrangement diagram of the image data PWM and the multiple (M), as well as the new image data PWM_M after M is applied to PWM.

[0013] Figure 2 is an example diagram of how the accumulator operates for a single LED.

[0014] Figure 3 is another example diagram that illustrates how the accumulator operates for a single LED.

[0015] Figure 4 This is an example diagram of the operation of an array consisting of 5 LEDs.

[0016] Figure 5 This is an example diagram for explaining the detailed data arrangement and calculation of image data (PWM) and multiplication factor (M).

[0017] Figure 6is a schematic flow chart of PWM data processing, which shows the overall composition of an LED display system with a dynamic range expander.

[0018] Detailed description of embodiments

[0019] The accompanying drawings and the following description illustrate embodiments of the invention by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods of the present invention will be readily apparent as viable alternatives that can be employed without departing from the principles of the claimed invention.

[0020] Several embodiments of the present invention will now be referenced in detail, examples of which are illustrated in the accompanying drawings. Please note that similar or similar reference numerals may be used in the accompanying drawings wherever feasible, and similar or similar functions may be indicated. The accompanying drawings depict embodiments of the present invention for illustrative purposes only. Those skilled in the art will readily appreciate from the following description that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles of the invention described herein.

[0021] One aspect of an embodiment of the present invention is as follows Figure 1 , which shows image data (PWM) with a 16-bit depth and a 6-bit multiple (M). In M, bits 5, 4, and 3 are designated for the integer portion, while bits 2, 1, and 0 are designated for the fractional portion. By multiplying the 16 PWM bits by the 6 M bits, the product (PWM_M) is 22 bits, which is divided into a 19-bit integer portion (PWM_M I ) and 3 decimal places (PWM_M F ). Note that, depending on circumstances and / or needs, the bit depth of the image data and the multiple M may be a value other than 16 or 6, but may also be other integer number of bits. The integer part or the fractional part in M ​​may have fewer or more bits, and the number of bits of the integer part in M ​​and the number of bits of the fractional part in M ​​may be the same or different.

[0022] exist Figure 1 In the example of FIG. 1 , adding 3 bits to the integer portion increases the maximum brightness from 2 16 Increase to 2 19 , indicating that the original size of the image data at 16-bit depth has increased by a factor of 8 (2 19 / 2 16 =23=8). Similarly, a 3-bit binary fraction can reduce the PWM to 1 / 8 of the original value of the image data (2 -3). However, in an embodiment of the present invention, the fractional part is accumulated in an accumulator, which may be a register. Once the value in the accumulator reaches or exceeds the value "1", "1" is subtracted from the value. Therefore, in a frame where the accumulated fractional value is "1" or greater, the display may be illuminated due to the occurrence of an extra PWM pulse; whereas in a frame where the accumulated value of the fractional part is 1 or 0, the display has no extra pulse.

[0023] In different embodiments, if the fraction value in all image frames is 1 / 2 (the 2nd bit value of M is 1), a pulse is displayed every other frame. If the fraction value in all image frames is 1 / 4 (the 1st bit value of M is 1), an additional pulse is displayed every 4 frames. If the fraction value in all image frames is 1 / 8 (the 0th bit value of M is 1), an additional pulse is displayed every 8 frames. Please note that in other data arrangements of the fractional part in the image frame, the fractional values ​​in the image frame can be the same or different, and can be any fraction, such as 1 / 2, 1 / 4, 1 / 8, and 1 / 16. For example, if the fractional value in the image frame is 1 / 16, an additional pulse is displayed every 16 frames. The uniform distribution of a pulse between multiple frames increases the grayscale granularity of the image illuminated by the LED array.

[0024] Figure 2 An example of how the accumulator operates for an LED is shown. As time passes along the direction shown on the time axis (i.e., from left to right, where frames 1 through 8 appear successively over time, each carrying its own fractional data 201), the accumulator 203 operates on the fractional portion of the frame data. The three bits of the accumulator represent the values ​​of 1 / 8, 1 / 4, and 1 / 2 from bottom to top, respectively, with an initial value of 0. Frame #1 has a fractional segment with a value of 3 / 4 (.110 in binary format). After the accumulator 203 adds its initial value of 0 to the fractional value introduced by frame #1, no PWM pulse is displayed because the result of the addition (3 / 4) is less than 1. However, the fractional value of 3 / 4 is stored in the accumulator 203.

[0025] Frame #2 has a fractional segment with a value of 1 / 2 (.100 in binary format). When the fractional value is added to 3 / 4 stored in accumulator 203, the result is 11 / 4. Therefore, the integer "1" is subtracted from the accumulator, resulting in a remainder of 1 / 4 (0.010 in binary format) in accumulator 203, and the integer "1" is used as the carry output value to fill PWM_M I The carry-out bit 202 in the integer part of .

[0026] Frame #3 has a fractional segment with a value of 1 / 2 (.100 in binary format), which is added to the residual value of 1 / 4 in accumulator 203 to produce a value of 3 / 4 (.110 in binary format) for frame #3 in accumulator 203. Since frame #4 has a fractional segment with a value of 0 (.000 in binary format), adding the fractional value of 0 to the residual value in accumulator 203 does not change the residual value in accumulator 203. Therefore, when frame #4 is processed, the residual value in accumulator 203 remains 3 / 4 (.110 in binary format).

[0027] Frame #5 has a fractional segment with a value of 7 / 8 (.111 in binary format), which is added to the remainder value -3 / 4 in accumulator 203 (0.110 in binary format), resulting in a value of 15 / 8. Therefore, the integer "1" is subtracted from the accumulator, causing the remainder in the accumulator to become 5 / 8 (0.101 in binary format), and the integer "1" is used as the carry output value to fill PWM_M I The carry-out bit 202 in the integer segment of .

[0028] Frame #6 has a fractional segment with a value of 1 / 8 (.001, in binary format), which is added to the remaining value in the accumulator -5 / 8 (.101, in binary format) to produce a value of 3 / 4 (.110, in binary format). Frame #7 has a fractional segment with a value of 1 / 2 (.100, in binary format), which is added to the remaining value in the accumulator -3 / 4 (.110, in binary format) to produce a value of 11 / 4. Therefore, the integer "1" is subtracted from the accumulator 203, so that the remainder in the accumulator is 1 / 4 (0.01, in binary format), and the integer "1" is used as the carry output value to fill the PWM_M I The carry-out bit 202 in the integer segment of Frame #8 is used to carry out the carry-out bit 202. Since Frame #8 has a fractional segment with a value of 0 (0.000 in binary format), adding the fractional value 0 to the residual value in accumulator 203 does not cause any change to the residual value in accumulator 203.

[0029] As described above and Figure 2 As shown, each new frame updates the value in the accumulator 203. If the value reaches 1 or greater, 1 is subtracted from the accumulator 203, and the remainder remains in the accumulator 203.

[0030] and Figure 2 similar, Figure 3The same operation of the accumulator 303 is shown along the time axis shown (i.e., from left to right, with frames 1 to 8 displayed successively over time, each with its own fractional value 301). In this case, since frames #2 through #6 all have fractional values ​​of 0, only frame #8 receives an extra PWM pulse after the accumulator adds the value 1 / 2 introduced by frame #1 to the value 1 / 2 introduced by frame #7, which results in a carry output bit integer "1" being stored in PWM_M. I The carry output bit 302 is stored in PWM_M I A value of "1" in the carry-out bit 302 causes the PWM engine to generate an additional pulse.

[0031] It is worth noting that although Figure 2 and Figure 3 The fractional values ​​of the image data of each frame are shown to reach a granularity of "1 / 8" (rather than a finer granularity fractional value, such as "1 / 16" or "1 / 32", or a coarser granularity fractional value, such as "1 / 4" or "1 / 2"), but the fractional value of the image data of the frame can be any practical granularity value. It should also be noted that although Figure 2 and Figure 3 The three bits in the fractional part of the accumulator are shown to represent the bit values ​​"1 / 8", "1 / 4" and "1 / 2" from bottom to top, respectively, but other operable arrangements may be used, such as the fractional part of the accumulator having fewer or more bits, or each bit of the fractional part of the accumulator representing the same bit value as the fractional part of the accumulator. Figure 2 and Figure 3 Different values ​​are shown.

[0032] Figure 4 1 shows the operation of 5 LED pixels according to this embodiment. They all have a corresponding accumulator, which accumulates (or adds) the fractional values ​​by adding the fractional value of the new frame to the fractional value stored in the accumulator. When the output of the accumulator is equal to or greater than "1", "1" is "output" and used to fill an integer part of the image data (i.e., PWM_M I ). After the PWM engine processes the PWM data, an additional PWM pulse is sent to the LED according to the value "1" filled in the integer part of the image data.

[0033] Specifically, Figure 4Five LED pixels of a new frame are shown, each with its own fractional portion (401, 402, 403, 404, and 405, respectively). In fractional portion 401 of LED #1, it has three individual bits 401_0, 401_1, and 401_2, each representing the values ​​"1 / 8", "1 / 4", and "1 / 2", respectively. Likewise, fractional portions 402, 403, 404, and 405 all have the same arrangement as fractional portion 401. As described above, the number of bits and the assigned values ​​for each bit are not limited to Figure 4 In addition, the fractional parts may have the same or different data arrangements as each other.

[0034] In addition to the five fractional segments of the new frame, Figure 4 Five accumulators are shown, each storing the numerical values ​​of the fractional portion of the current frame data for five light-emitting diodes. In accumulator 406, there are three bits 406_0, 406_1, and 406_2, each having a specified value of "1 / 8", "1 / 4", and "1 / 2", respectively. Similarly, accumulators 407, 408, 409, and 410 all have the same arrangement as accumulator 406. The arrangements of 406, 407, 408, 409, and 410 can be the same as or different from each other. However, in order to perform addition operations between the numerical values ​​of the fractional portion of the new frame data for a particular LED used by the LEDs in the accumulator section, the arrangement of each accumulator must match the corresponding fraction of the new frame data for the particular LED (in terms of the number of bits therein and the specified value of each bit). That is, the arrangement of accumulator 406 must match fractional portion 401 of the new frame data for LED #1; the arrangement of accumulator 407 must match fractional portion 402 of the new frame data for LED #2; the arrangement of accumulator 408 must match fractional portion 403 of the new frame data for LED #3; the arrangement of accumulator 409 must match fractional portion 404 of the new frame data for LED #4; and the arrangement of accumulator 410 must match fractional portion 405 of the new frame data for LED #5.

[0035] Figure 4 Also shown are five carry output bits 411, 412, 413, 414, and 415, each of which is a PWM_M bit of the image data. I, corresponding to LED#1, LED#2, LED#3, LED#4, and LED#5. These five carry-out bits are reserved specifically to store the value "1" when the addition of the fractional portion of the new frame data for a particular LED and the current value in the accumulator corresponding to that LED produces a value of "1" or greater. In the case where the carry-out bits are filled with the value "1", the PWM engine will generate additional pulses when processing the newly calculated image data, which is the desired effect of the carry-out bits obtaining the value "1". In the case where the carry-out bits are filled with the value "0" (default value), the PWM engine will not generate additional pulses when processing the newly calculated image data, which is also the desired effect of the carry-out bits obtaining the filled value "0". Once the value "1" in the carry-out bit is read by the PWM engine and an additional pulse is generated, the value in the carry-out bit returns to the default value of "0". In other words, the carry-out bit is a placeholder that holds an "on / off" flag (corresponding to "1" or "0") to inform the PWM engine to generate or not generate additional pulses when reading the newly calculated frame data. Each time the PWM engine uses this bit, its value reverts to "0", so this bit has no cumulative effect on the data from one frame to the subsequent frame.

[0036] Taking the addition operation (indicated by 421) of the data stored in 401 and 406 as an example, the addition operation is performed in the accumulator 406 corresponding to LED#1, and a value 3 / 8 (".011", binary format) is generated (indicated by 422) (3 / 8+0=3 / 8). This value is represented as .011 in binary format and is used to replace the value .000 in 416 (note that 416 now reflects the state of the accumulator after the addition operation), and the corresponding carry-out bit 411 does not receive the carry-out value "1" and therefore remains "0". Similarly, the addition operation of the data stored in 402 and 407 and the addition operation of the data stored in 405 and 410 produce a value less than "1". Thus, even though the accumulators 407 and 410 bits are updated with the newly calculated fractional values ​​"5 / 8" (".101", in binary format) and (".110", in binary format), respectively, their corresponding carry-out bits 412 and 415 do not receive the carry-out value "1", respectively, and thus still maintain their default values ​​of "0".

[0037] The data stored in 403 and 408 are added together. As another example, the addition operation performed in accumulator 408 corresponding to LED #3 produces a value of 1. 3 / 8 (1.101, binary format)(7 / 8+3 / 4=1 3 / 8), after the value "1" is subtracted from the resulting value (which is carried to the carry-out bit 413), the remaining value is represented in binary format as ".101" and is used to replace ".110" in 408. Therefore, the corresponding carry-out bit 413 receives the carry-out value "1". Similarly, the addition operation of the data stored in 404 and 409 produces "1.001", a value greater than "1", resulting in the corresponding carry-out bit 414 receiving the carry-out value "1" and updating the fractional portion of the new frame data 419 (the remaining value after the result of the addition operation is subtracted from "1") with ".001".

[0038] By T 0 、T 1 and T 2 The above sequence of events shows that at T 0 At time T, accumulators 406, 407, 408, 409, and 410 each hold their current values ​​(".000", "0.001", "0.110", "0.011", and ".101", respectively). 1 At time T, five fractional values ​​of the image data of the five LEDs (401, 402, 403, 404 and 405) become available, and at T 2 Generate the result of the addition operation at all times.

[0039] Figure 5 More fully illustrates an embodiment of data arrangement, which includes a multiple (M) stored in a storage device 501, image data (PWM) stored in a storage device 502, and extended image data (PWM_M) stored in a storage device 503. The storage device 501, 502, or 503 may be a register or a memory. In this embodiment, the storage device 501 storing the M data has 6 bits, of which 3 bits are allocated to the integer part M. I (integer), the other 3 bits are allocated to the fractional part M F (decimal). The storage device 502 storing the input PWM data has 16 bits, and the storage device 503 storing the PWM_M data has 22 bits. The product PWM_M of PWM and M has 22 bits (bit #0 to bit #21). The PWM_M stored in the storage device 505 has 22 bits. I The integer part of PWM_M ranges from #3 to #21; while the fractional part PWM_M stored in the storage device 504 F The range is from bit #0 to bit #2. Accumulator 506 has 3 bits, matching the number of bits in PWM_MF.

[0040] like Figure 4 As mentioned above, when PWM_M FWhen the value of is added to the value of the accumulator, the sum is used to update the value of the accumulator, and when the value of the sum is equal to or greater than 1, the integer "1" is filled into the carry output bit. Figure 5 In the example, the carry-out bit 507 can be filled with the carry portion of the sum (ie, the integer "1"), and the value of 506 is updated to 508 with the remainder. In addition, the PWM_M I The data array in data 505 is connected with the carry output bit 507 to form PWM_M I The extended array memory 511. As shown in 505, the obtained PWM_M I is expanded to 20 bits instead of its original size of 19 bits.

[0041] As two independent and cooperating parts of the frame buffer 512, panels 509 and 510 are two schematic diagrams representing the image data array of the LEDs, where each LED has a 3-bit long accumulator and a 19-bit long PWM_M I Note that in this embodiment, for each LED, its PWM_M F It is not stored in the PWM memory in 509 or 510, but is accumulated and stored in the accumulator of the LED. Figure 5 As shown, the data stored in 504 is not read by the PWM engine to generate pulses (the engine only reads PWM_M I 508). However, the new fractional data for one LED stored in 504 is added (via an addition operation 513) to the current value of the accumulator 506 for that particular LED to generate a sum. In the event that the sum equals or exceeds "1", the integer "1" is output and fills the carry-out bit 507 of the LED, and the remainder of the sum after "1" is subtracted is stored in 508. In other words, although the carry-out bit 507 is not associated with the PWM memory (which only stores PWM_M I The integer part of the value of ) is added (via operation 507, i.e., "binary addition") and the extended PWM_M is generated. I 511, which is written to the frame buffer 512 (specifically the PWM memory in the pong memory), but it mathematically represents the cumulative value of the fractional part of all frames available to the PWM engine. This data arrangement effectively increases the grayscale range of the LED display image, is easy to implement, and the increase in memory usage is not obvious.

[0042] In one embodiment, the frame buffer 512 is divided into two parts, namely, the ping memory 509 and the pong memory 510. The ping memory 509 stores a 20-bit PWM_M I1. The pong memory 510 stores a 20-bit PWM_M data array (each data serves one LED) and a 3-bit long accumulator data array (each data also serves only one LED). Similarly, in terms of data arrangement, the pong memory 510 stores a 20-bit long PWM_M data array. I ping memory 509 and pong memory 510 have different functions. In a specific frame time, the PWM memory in ping memory 509 is used to trigger the display of the corresponding LED. At the same time, pong memory 510 is receiving updated data. In addition, ping memory 509 is used to trigger the display of the corresponding LED in PWM_M. F 504 (which is the fractional portion of the multiplication result of the new multiple (M) 501 and the new PWM 502) provides an accumulator data array such as 506 to the addition operation 513 to produce the carry-out value (if any) stored in 507 and the remaining fraction value stored in 508. The value stored in accumulator 508 is then used to update the corresponding accumulator in pong memory 510, and the value in carry-out bit 507 (either "0" or "1") is added to PWM_M. I 505 is added (ie, binary addition) (operation 514) to generate the extended PWM_M I 511 , and then write it into the corresponding PWM memory in the pong memory 510 .

[0043] When the current frame is finished displaying and all new frame data is finished transmitting and stored in the frame buffer, the frame change signal V sync 515 is switched, and the roles of the pong memory 510 and the ping memory 509 are reversed. When the roles are reversed, the PWM memory of the pong memory 510 is used to trigger the display of the corresponding light-emitting diode, while the ping memory 509 is used to receive the update data of the upcoming frame. In other words, the pong memory 510 sends the PWM_M F The addition operation 513 on 504 provides an accumulator data array such as 506, which generates a carry-out value (if any) stored in 507 and a remainder fraction value stored in 508. 508 is used to update the corresponding accumulator in ping memory 509. The new PWM_M stored in 505 I The result of the addition operation (514) is checked by 511 and written into the corresponding PWM memory of the ping memory 509. syncWhen 515 switches again, the roles of ping memory 509 and pong memory 510 are reversed again. Those skilled in the art will appreciate that there may be some variations of the above ping-pong memory arrangement that utilize the minimum memory footprint principle to efficiently achieve the purpose achieved by using memory.

[0044] Figure 6 The PWM data processing flow chart in an exemplary LED display system with a dynamic range expander circuit is schematically illustrated. New PWM data 601 and a multiple (M) value 602 are input to a binary multiplier 603. The product of 603 is divided into an integer part 604 and a fractional part 605. The fractional part 605 and the contents of the accumulator 607 are input to a binary adder 606, which outputs a carry 608 and a sum 609. The sum 609 from 606 is stored in the accumulator 607. The carry 608 is sent to a second binary adder 610, which is then added to the integer part 604 from the multiplier 603. Then, the sum 611 is stored in a frame buffer / pwm memory (pwm_memory) 612. A PWM engine (PWM_Engine) 613 generates PWM pulses based on the PWM data in the frame buffer / pwm_memory 612. The PWM pulses from the PWM_Engine 613 drive the LED array 614 .

[0045] It is worth noting that fractions are used to light up the LED only when the cumulative value of the fractions is equal to or exceeds 1, which also applies to the case where there is no multiplication between PWM and the multiple (M). For example, one pulse can be processed equally into eight frames so that each frame receives 1 / 8 pulse. The traditional method of putting 1 / 8 pulse into one frame requires 8 times the clock speed. In contrast, putting one pulse into 8 frames also only requires 1 times the CLK speed.

[0046] Having benefited from the teachings of the foregoing description and the associated drawings, those skilled in the art will contemplate many modifications and other embodiments of the present invention. For example, the capacity of the image data (PWM), the multiple (M), and the extended image data (PWM_M) can be expanded or contracted to suit needs and / or environmental requirements, the designated value of each bit in PWM, PWM_M, and M can be changed to suit personal preferences, and the bit allocation between the integer part and the fractional part of PWM, M, and PWM_M can be adjusted according to technical considerations for PWM_M. I The threshold for carrying the sum of the value stored in the accumulator and the value stored in the accumulator can be adjusted (in the embodiment shown, the threshold is "1") to a finer value (e.g., "1 1 / 8”, “1”, “7 / 8”) to meet the requirements of the technical environment, the implementation of the accumulator is not completed using the registers indicated in this specification. Such changes are within the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments disclosed, and these modifications and embodiments are intended to be included in the scope of the dependent claims.

Claims

1. An LED display system, characterized in that: include: LED array; a driving circuit configured to drive the LED array, wherein the driving circuit comprises a PWM engine, an adder, an accumulator, a multiplier and a frame buffer, Among them, during the operation process, The multiplier multiplies the image data PWM of the first bit depth by a multiple M to generate input data PWM_M having a second bit depth, wherein the multiple has an integer part M of one or more bit lengths. I and a fractional part M of one or more bit lengths F , where the input data has an integer part PWM_M I and the fractional part PWM_M F ; The adder converts the current input data into PWM_M F The value is added to the remainder value in the accumulator, and when the sum of the addition operation is less than 1, the remainder is updated to be equal to the sum of the addition operation; when the sum of the addition operation is equal to or greater than the integer 1, the integer 1 is subtracted from the sum of the addition, and the remainder is updated to be equal to the result of the subtraction, and the integer 1 is filled into the PWM_M I , and the resulting PWM_M I The value is sent to the frame buffer, and the PWM engine receives the PMW data from the frame buffer and generates PWM pulses to drive the LED array; To PWM_M I Adding the integer 1 includes adding the integer 1 regardless of the magnitude of the current value stored in the bit, wherein the bit is specially reserved for receiving the integer 1 from the addition operation when the sum of the addition is equal to or greater than the integer 1, and the value of the bit remains zero otherwise; The PWM engine generates PWM pulses in a way that is based on the current value of the non-zero bit PWM_M I Each non-zero bit in generates multiple pulses; for PWM_M I Each bit in carries the integer 0 and generates no pulse; and PWM_M F No pulse is generated for each bit in the .

2. The LED display system according to claim 1, characterized in that: The drive circuit also includes a frame buffer, which is used to store the current accumulator data, the current PWM_M I data, updated accumulator data, and updated PWM_M I data.

3. The LED display system according to claim 2, characterized in that: The frame buffer includes a ping memory and a pong memory, wherein the ping memory stores the current accumulator data and the current PWM_M I The ping memory provides the current accumulator data for the addition operation; the pong memory receives the updated accumulator data and the updated PWM_M from the addition operation. I data, the pong memory stores the updated accumulator data and the updated PWM_M I data.

4. The LED display system according to claim 3, characterized in that: After the pong memory receives all new frame data and the ping memory completes the current frame display and a frame change signal Vsync occurs, the ping memory becomes the pong memory and the pong memory becomes the ping memory.

5. A method for increasing the dynamic range of an LED display, characterized in that: include: The image data PWM of the first bit depth is multiplied by a multiple M to generate input data PWM_M having a second bit depth, wherein the multiple has an integer part M of one or more bit lengths. I and a fractional part M of one or more bit lengths F , where the input data has an integer part PWM_M I and the fractional part PWM_M F ; PWM_M for current input data F The remainder value in the accumulator is added. When the sum of the addition is less than 1, the remainder is updated to be equal to the sum of the addition. When the sum of the addition is equal to or greater than the integer 1, the integer 1 is subtracted from the sum of the addition, and the remainder is updated to be equal to the result of the subtraction, and the integer 1 is filled into the PWM_M I In one of the positions; Set PWM_M I The value is sent to the frame buffer that provides PWM data to the PWM engine; and The PWM pulses generated in the PWM engine are used to drive the LED display array.

6. The method for increasing the dynamic range of an LED display according to claim 5, characterized in that: Add integer 1 to PWM_M I The steps in one of the bits in the addition operation include adding the integer 1 to the bit regardless of the current value stored in the bit, and when the sum of the addition is equal to or greater than the integer 1, the bit is reserved exclusively for receiving the integer 1 from the addition operation, otherwise the value of the bit remains zero.

7. The method for increasing the dynamic range of an LED display according to claim 5, characterized in that: The PWM engine generates PWM pulses in a way that is based on the current value of the non-zero bit PWM_M I Each non-zero bit in generates multiple pulses; for PWM_M I Each bit carrying an integer 0 in PWM_M generates no pulse; F No pulse is generated for each bit in the .

8. The method for increasing the dynamic range of an LED display according to claim 5, characterized in that: It also includes the current accumulator data, current PWM_M I data, updated accumulator data, and updated PWM_M I The data is stored in a frame buffer located in a driving circuit that drives the LED display.

9. The method for increasing the dynamic range of an LED display according to claim 8, characterized in that: The frame buffer includes a ping memory and a pong memory, wherein the ping memory stores the current accumulator data and the current PWM_M I data, wherein the ping memory provides current accumulator data for the addition operation, wherein the pong memory receives updated accumulator data and updated PWM_M from the addition operation I data, and wherein the pong memory stores the updated accumulator data and the updated PWM_M I data.

10. The method for increasing the dynamic range of an LED display according to claim 9, characterized in that: After the pong memory receives all new frame data, and the ping memory completes displaying the current frame and a frame change signal Vsync appears, the ping memory becomes the pong memory and the pong memory becomes the ping memory.

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