Integrated assembly

Abstract

Some embodiments include an integrated assembly having a memory array over a substrate. The memory array includes a three-dimensional arrangement of memory cells. A sense amplifier is associated with the substrate and directly below the memory array. A vertically extending digit line passes through the arrangement of memory cells and is coupled with the sense amplifier. Some embodiments include an integrated assembly having a memory bank containing 64 memory data blocks arranged in a 16x4 configuration. Some embodiments include an integrated assembly having a memory bank containing 512 megabytes divided among 64 memory data blocks, each memory data block having 8 megabytes. The 64 memory data blocks are arranged in a configuration having a plurality of rows, each row containing two or more of the memory data blocks.

Description

Technical Field

[0001] Memory arrays (e.g., DRAM arrays). Including integrated assemblies with vertically stacked layers. Background Technology

[0002] Modern computing architectures utilize memory to store data. One type of memory is Dynamic Random Access Memory (DRAM). Compared to alternative types of memory, DRAM offers advantages such as simple structure, low cost, and high speed.

[0003] DRAM can utilize memory cells that have a combination of a capacitor and a transistor (so-called 1T-1C memory cell), where the capacitor is coupled to the source / drain regions of the transistor. During operation, an electric field generated by the voltage along the word line can gatingly couple the bit line to the capacitor during read / write operations.

[0004] The memory cells described above can be incorporated into a memory array. During the operation of the memory array, data within the array can be logically subdivided among various cells (banks, pages, segments, data blocks, etc.). Refer to Figure 1 to describe an example memory bank 500. The bank is associated with a planar array of memory cells. The bank has 65 data blocks (cells, portions), of which 64 contain memory (specifically, 8 megabytes, or 8MB of memory), and one of them contains an error correction circuitry (ECC).

[0005] ECC may include redundant memory cells that will be used in the memory array in the event of a failure of the original memory cells.

[0006] The term "8M" (or 8MB) is generally understood to mean 8,388,608 bytes, as will be understood by a person of ordinary skill in the art. In applications where each memory cell has two selectable and distinguishable memory states, each byte may correspond to a single memory cell in the application. In applications where memory cells have more than two selectable and distinguishable memory states, a single memory cell may correspond to more than a single byte.

[0007] The 64 data blocks together form a memory bank with 512MB of memory. This memory can be addressed using a Global Input / Output (GIO) structure. The illustrated GIO structure spans the entire length of the 500MB memory bank.

[0008] Before further describing access to data within the memory cell, it may be useful to describe the general relationships of the memory array within the integrated arrangement. Figure 2A block diagram of a prior art device 1000 is shown, comprising: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 are used to transfer information to and from the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in the memory cells 1003 need to be accessed. Sensing amplifier circuitry 1015 operates to determine the value of information read from the memory cells 1003. I / O circuitry 1017 transfers the value of information between the memory array 1002 and input / output (I / O). Signals on the DQ PAD can represent values ​​of information read from or to be written into memory cell 1003. Other devices can communicate with device 1000 via I / O, address line 1009, or control line 1020 (CMD PAD). Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and uses signals on control line 1020. Device 1000 can receive power supply voltage signals Vcc and Vss on first power line 1030 and second power line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuitry 1040 can respond to signal CSEL via I / O circuitry 1017 to select signals on first data line 1006 and second data line 1013 that represent values ​​of information to be read from or programmed into memory cell 1003. The column decoder 1008 can selectively activate the CSEL signal based on the A0 to AX address signals on the address lines 1009. The selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to provide communication between the memory array 1002 and the I / O circuit 1017 during read and program operations.

[0009] Figure 3 shows a schematic illustration of 2000, which schematically describes the memory within memory array 1002 (e.g., ...). Figure 2 Some addressing (read / write operations) are associated with memory cell 1003. Bit line 1006 is coupled to column select / sensor amplifier (CS / SA) circuitry 2002, and information is fed into / out of memory using the CS / SA circuitry. Information associated with the CS / SA circuitry is accessed via a local input / output structure (LIO structure) 2004, which stores signals LIO0-LIO. nInput / output local LIO circuitry 2006. A GIO structure 2008 (e.g., GBUS) inputs / outputs signals to / from a circuit block 2010 including a read / write (R / W) circuitry system. Specifically, block 2010 includes a read block 2012 and a write block 2014. The long GIO structure associated with the extended memory bank 500 of FIG1 can result in a significant loss of signal-to-noise ratio along the GIO structure, thus requiring the illustrated sense amplifier 2016 in the early stages of the read block to boost or deboost the signal in the GIO. The sense amplifier 2016 can be a direct sense amplifier (DSA) that compares the electrical signal (voltage) of the GIO with the electrical signal of a reference voltage source.

[0010] Input / output (I / O) block 2020 communicates with the R / W circuitry of block 2010. Information can be transferred between the I / O of block 2020 and the R / W circuitry of block 2010 via data transfer bus 2018.

[0011] A persistent goal in integrated circuit (IC) design is to increase integration density and thus save valuable semiconductor footprint associated with semiconductor dies. This necessitates the development of highly integrated memories and highly integrated circuits suitable for addressing those memories. Summary of the Invention

[0012] In one aspect, this application provides an integrated assembly comprising: a memory array above a substrate; the memory array including a three-dimensional arrangement of memory cells; a sensing amplifier associated with the substrate and located directly below the memory array; and a vertically extending digital line passing through the arrangement of the memory cells and coupled to the sensing amplifier.

[0013] In another aspect, this application further provides an integrated assembly comprising a memory bank including 64 memory data blocks arranged in a 16x4 configuration.

[0014] In another aspect, this application further provides an integrated assembly comprising: a memory bank having 512 megabytes, divided among 64 memory data blocks, each comprising 8 megabytes; and the 64 memory data blocks arranged in a configuration having multiple rows, each row comprising multiple of the memory data blocks. Attached Figure Description

[0015] Figure 1 is a top view of a prior art memory storage medium.

[0016] Figure 2 A block diagram showing a prior art layout including a memory array.

[0017] Figure 3 schematically illustrates the prior art arrangement of a circuit system including a memory for addressing a memory array.

[0018] Figure 4 It is a schematic 3D view of an instance integration assembly area of ​​a memory array that extends across multiple vertical shift levels.

[0019] Figure 5 This is a top view of the instance memory storage.

[0020] Figure 6 yes Figure 5 A schematic 3D view of the instance memory storage area.

[0021] Figure 7 It is a top-down diagram of the instance memory data block.

[0022] Figure 8 It is a leap Figure 7 A 3D diagram of the instance circuit system's instance layout, representing a segment of the instance area.

[0023] Figure 9 This is a top view of the instance memory storage.

[0024] Figure 10 illustrative illustrations include those used for addressing. Figure 9 The arrangement of the circuit system of the memory within the memory cell.

[0025] Figure 11 It is a leap Figure 9 A three-dimensional diagram of the instance circuit system of the instance memory.

[0026] Figure 12 The illustrative illustration includes an example arrangement of a circuit system for addressing memory. Detailed Implementation

[0027] Some embodiments include an integrated assembly with a memory array comprising vertically shifted memory hierarchies through which vertically extending digital lines can extend. A semiconductor substrate may be located below the memory array. A sensing circuitry system may be provided within the substrate and directly below the memory array. The memory cells of the memory array and the sensing circuitry system below the memory array may be incorporated into a highly integrated memory bank. Reference Figures 4 to 12 Describe an example implementation.

[0028] refer to Figure 4 The integrated assembly 10 includes memory cells 14 (some of which are labeled) arranged in a three-dimensional array 16. Regions adjacent to the assembly 10 provide an x, y, z coordinate system to help describe the relative orientations of the various structures shown in the assembly 10.

[0029] Each of the memory cells includes an access device 18 (only one is shown for simplicity) coupled to the storage element 20.

[0030] In the illustrated embodiment, access device 18 corresponds to horizontally extending transistors, wherein each of the transistors includes a channel region 22 between a pair of source / drain regions 24 and 26.

[0031] The channel region and source / drain region may be formed within the semiconductor material 28. The semiconductor material 28 may include any suitable composition, and in some embodiments may include one or more of the following, consist primarily of one or more of the following, or consist of one or more of the following: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are old nomenclature and are now referred to as Groups 13 and 15).

[0032] The source / drain regions 24 and 26 may correspond to the heavily doped regions formed within the semiconductor material 28.

[0033] In the illustrated embodiment, semiconductor material 28 extends into conductive plate 30. In some operating states, conductive plate 30 can be used to drain excess carriers (e.g., holes) from the body region (channel region) of transistor 18.

[0034] The vertically extending digital line 32 runs along the column of the memory array 16 and is coupled to the source / drain region 24.

[0035] The horizontally extending word line 34 extends along the rows of the memory array 16 and is operatively close to the channel region 22.

[0036] Word lines 34 extend along the illustrated y-axis direction, and digit lines 30 extend along the illustrated z-axis direction. Vertically extending digit lines 32 may be orthogonal to word lines 34, or at least substantially orthogonal to such word lines (wherein the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances). In some embodiments, digit lines 32 may extend along a direction orthogonal to word lines 34 within approximately 10°.

[0037] Word line 34 can be considered as including a gating region operatively adjacent to channel region 22 of transistor 18, such that the source / drain regions 24 and 26 of each transistor 18 are coupled to each other in a gating manner. When the term "gating coupling" is used herein, it can refer to the controlled coupling / decoupling of source / drain regions 24 and 26 that can be triggered by electrical activation / deactivation of word line 34.

[0038] The gate region along word line 34 is spaced from channel region 22 by gate dielectric material 36. The gate dielectric material may include any suitable composition, and in some embodiments may include silicon dioxide, substantially composed of silicon dioxide, or composed of silicon dioxide.

[0039] Word line 34 may extend to word line driver circuitry (e.g., sub-word line driver SWD cells) outside the illustrated area of ​​assembly 10. Stepped regions may be laterally adjacent to memory array 16 and may be used to couple individual word lines to specific SWD cells.

[0040] The character line 34 can be considered as being arranged within the vertical stacking hierarchy (layer) 35.

[0041] Conductive nodes 38 (only a few are labeled) are adjacent to source / drain regions 26 and couple such source / drain regions to the memory element 20. In some embodiments, conductive nodes 38 may be considered as part of the memory element 20.

[0042] The storage element 20 can be any suitable device having at least two detectable states; and in some embodiments it can be, for example, a capacitor, a resistor-memory device, a conductive-bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc. In the illustrated embodiment, the storage element 20 corresponds to a capacitor.

[0043] In operation, word line 34 can be used to selectively couple capacitor 20 to digital line 32 during addressing (read / write operations) of memory cell 14. Each of the memory cells 14 can be considered to be uniquely addressed by combining one of the digital lines 32 with one of the word lines 14.

[0044] Sensing amplifier (SA) 40 is schematically illustrated below array 16 and coupled to one of the vertically extending digital lines 32 (wherein this vertically extending digital line is labeled 32a). The sensing amplifier may be associated with a substrate 12 below memory array 16. Substrate 12 may include semiconductor material; and, for example, may include monocrystalline silicon, substantially composed of monocrystalline silicon, or composed of monocrystalline silicon. Substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in a combination including other materials), and a layer of semiconductor material (alone or in a combination including other materials). The term "substrate" refers to any support structure, including but not limited to the semiconductor substrate described above. In some applications, substrate 12 may correspond to a semiconductor substrate housing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0045] The sensing amplifier 40 can be used during read / write operations associated with memory cells along digital line 32a.

[0046] Some embodiments include a memory storage configuration that may utilize a memory array (e.g., Figure 4 Vertically extending digital lines within the memory array 16). Figure 5 Example memory bank 50 is shown. The memory bank contains four rows (segments) 52a-d, where each row contains 16 memory data blocks (cells, portions) 54. Only the memory data blocks 54 in the first row 52a are shown, but it should be understood that similar memory data blocks are in rows 52b-c.

[0047] Each memory data block comprises 8 megabytes (8M) of memory. In some embodiments, Figure 5 The memory bank configuration can be referred to as a 16x4 configuration because it includes 16 memory data blocks along the row direction (the x-axis direction described) and four data blocks along the column direction (the y-axis direction described). It should be noted that... Figure 5 The x and y axes may or may not be parallel to the x and y axes. Figure 4 The x and y axes are in the same direction.

[0048] Figure 5 The 16x4 configuration includes 64 memory data blocks. Since each memory data block comprises 8MB, Figure 5 The configuration includes 512MB of memory (64*8). Alternatively, by considering that memory bank 50 includes 8MB / data block, 16 data blocks per segment, and 4 segments; and therefore includes 8*16*4 = 512MB, in Figure 5The total memory within the configuration can be determined to be 512M.

[0049] Figure 5 The illustrated configuration can be viewed as comprising 16 memory data blocks 54 within mutually common rows (e.g., row 52a) along the length L of the memory bank 50. In the illustrated embodiment, the 16 memory data blocks within each row are subdivided into a first group 56a comprising eight memory data blocks and a second group 56b comprising the remaining eight memory data blocks. An error correction circuitry (ECC) system is disposed between the first group 56a and the second group 56b.

[0050] Figure 5 The Global Input / Output (GIO) structure 58 is shown extending across memory data blocks 54. Figure 1 shows a typical GIO structure associated with planar memory, which is a long structure extending linearly across 64 side-by-side data blocks. In contrast, Figure 5 The GIO structure 58 is a relatively short structure that spans only four segments (52a-d) and extends across 16 data blocks 54 within each segment.

[0051] GIO structure 58 may be in any suitable location relative to data block 54, and in some embodiments may be above (above) data block 54, as described in more detail below.

[0052] although Figure 5 The memory bank 50 comprises four rows, each with 16 memory data blocks, but in other embodiments, the memory bank may have other configurations. Generally, an instance memory bank may comprise 512M (i.e., 512 megabytes) divided among 64 memory data blocks, where each data block comprises 8M. The 64 memory data blocks may be arranged in a configuration with multiple rows (segments), where each row (segment) comprises multiple memory data blocks. For example, the memory bank may be arranged in a configuration having: two rows, each comprising 32 memory data blocks; four rows, each comprising 16 memory data blocks (e.g., ...). Figure 5 (As shown in the diagram); eight rows, each row containing eight memory data blocks, etc. Generally, all rows will contain the same number of memory data blocks as each other.

[0053] Figure 6 A representative one of the 8M data blocks 54 is illustrated in a three-dimensional view. The data block comprises a memory array 16 above a substrate 12.

[0054] Vertically extending digital lines (DL) 32 extend through array 16, with only a few of these digital lines illustrated. In practice, there may be 512 vertically extending digital lines associated with each word line within the illustrated data block 54.

[0055] exist Figure 6 The array 16 shows several word lines 34 and schematically illustrates the locations of some levels 35. Levels 35 may be referred to as memory levels (or levels of memory cells). In some embodiments, each of the levels 35 may include 128 word lines (WL), and there may be 128 memory levels 35. Therefore, there may be 16,384 (128*128) word lines within the array 16 of the data block 54. If the array includes 512 digital lines along the word lines, the array may include 8,388,608 memory cells (16,384*512); where 8,388,608 memory cells are understood in conventional terms as 8M memory cells. Each memory cell may correspond to one byte of memory, and therefore the data block 54 may include 8 megabytes (8M) of memory.

[0056] and Figure 6 The substrate 12 associated with the memory data block 54 is shown as including a local input / output (LIO) circuit system 60 and a sense amplifier (SA) circuit system 40. The LIO circuit system 60 and the SA circuit system 40 are in... Figure 6 The area is shown in the middle (box) to simplify the diagram, and is described in more detail below. Figure 6 The digital line 32 is shown to be coupled to the sense amplifier circuit system 40 and extends upward from the substrate 12 including the sense amplifier circuit system.

[0057] The substrate may include multiple other components besides the sense amplifier circuitry and the local input / output circuitry, and may include, for example, column selection circuitry, switches, wiring, etc.

[0058] Figure 7 This is another graphical representation of one of the memory data blocks 54, showing that the word lines within this data block can be subdivided among 16 cores 62. If there are 128 word lines associated with the memory data block 54, each core may include eight word lines.

[0059] The local input / output (LIO) circuitry associated with memory data block 54 may include four local interconnects (LIOs) and serve 512 digital lines. The digital lines within each of core 62 can be accessed via a multiplexer (MUX) driver 64 (DL Mux Driver). The DL Mux Driver 64 is schematically illustrated as extending to a local connection 66 that extends laterally across core 62 to connect to a group of digital lines 32 (where digital lines 32 are not in...). Figure 7 (Shown separately in the diagram).

[0060] Figure 8The diagram illustrates a region of the Mux Driver 64 relative to one of the cores 62. Digital lines 32 are shown extending to conductive interconnects 66a and 66b, which are coupled to a sense amplifier circuitry 40. The sense amplifier circuitry may include a region of CMOS associated with the substrate 12.

[0061] The column select circuit system (CS) 68 is shown laterally outside the sense amplifier circuit system 40 and coupled to the LIO circuit system 60. In operation, data can be fed into / out of the memory cell associated with the digital line 32 using the LIO circuit system 60, the sense amplifier circuit system 40, and the column select circuit system 68.

[0062] Digital lines 32 may include comparison sets of first and second digital lines and are arranged in pairs as relatively coupled lines. Specifically, the digital lines are labeled DL-0T, DL-1T, DL-2T, DL-3T, DL-0C, DL-1C, DL-2C, and DL-3C. Lines labeled with a "T" (e.g., DL-0T) are "real" digital lines, while those labeled with a "C" are complementary digital lines. Each real digital line is paired with one of the complementary digital lines, and the complementary digital line has the same label as the real digital line (e.g., DL-0T and DL-0C are paired together) except for the "T" or "C" component. Paired real and complementary digital lines are compared relative to each other by a sense amplifier circuit system 40. Each pair of real and complementary digital lines can be considered as a comparison group containing a first comparison digital line and a second comparison digital line. For example, digital lines DL-0T and DL-0C can be considered as the first and second comparison digital lines within the first comparison group, respectively.

[0063] For the purposes of understanding this disclosure and the appended claims, if the sense amplifier circuitry is configured to compare the electrical characteristics (e.g., voltage) of a first digital line and a second digital line with each other, then the first digital line is “relatively coupled” to the second digital line via the sense amplifier circuitry. It should be noted that the terms “real” and “complementary” are arbitrary in their use to label digital lines and are simply used to distinguish digital lines compared with each other via the sense amplifier circuitry.

[0064] Mux driver 64 extends to Mux circuitry 70, which is used for selective addressing of individual digital lines 32. Mux circuitry 70 may include any suitable configuration and may include, for example, a plurality of transistors (and / or other suitable switches) configured to enable selective access to specific digital lines.

[0065] The sense amplifier circuit system 40 can be considered as including multiple individual sense amplifiers. The Mux driver 64 and Mux circuit system 70 can be used to couple multiple sets of digital lines to a single sense amplifier. Compared to applications where each pair of digital lines is coupled to a unique and separate sense amplifier, this reduces the number of sense amplifiers used within the substrate 12. Therefore, the use of the Mux driver 64 and Mux circuit system 70 reduces the total footprint of semiconductors consumed by the sense amplifiers. (In contrast to...) Figure 8 In an alternative embodiment of the embodiment, each of the paired digital lines may be coupled to an individual sense amplifier, and therefore may be omitted. Figure 8 Mux driver and Mux circuit system.

[0066] The Mux Driver 64 can be extended to a control circuitry system (not shown). This control circuitry system can be located in any suitable position, and in some embodiments, it can be derived from... Figure 5 The memory storage unit 50 is offset laterally.

[0067] Memory bank 50 may represent a large number of memory banks provided across a semiconductor die. In some embodiments, this die may be incorporated into an integrated circuit package (e.g., a memory chip). Figure 9 The illustration shows a region comprising a combination 200 including a pair of adjacent memory banks 50a and 50b (memory bank 0 and memory bank 1). The memory banks may be substantially identical to each other and may each include the same amount of memory (e.g., both may include 512M, as shown). Each memory bank can be understood to correspond to a region of memory associated with which the memory is accessed independently of the memory associated with the other memory bank.

[0068] Storage bank 50a is shown as including the above reference. Figure 5 The described segments 52a-d are labeled segment 0, segment 1, segment 2, and segment 3, respectively. Each segment may include a single memory page or may include multiple memory pages. Memory data blocks 54 (only some shown) each include a single LIO block 60. Column select circuitry (CS) 68 is shown extending across the width of the indicated segments (where the width is the dimension of segments 52a-d along the illustrated y-axis direction), and GIO 58 is shown extending across the entire width of memory bank 50a (where this width is the dimension of memory bank 50a along the illustrated y-axis direction).

[0069] Region 72 is adjacent to memory banks 50a and 50b and is indicated to include "memory logic". "Memory logic" may include, for example, a column decoder circuit system, a row decoder circuit system, etc. Region 72 may be referred to as a throat or socket. In some applications, "throat" can be understood as a region (location, place) for controlling circuitry, and "socket" can be understood as a region (location, opening) for feeding signals to circuitry systems above or below a given level. For the purposes of understanding this disclosure and the appended claims, unless expressly stated otherwise, the term "socket" is to be understood to refer to a socket in general.

[0070] Region 74 is located between memory banks 50a and 50b. A double-headed arrow 76 indicates that the circuitry within region 74 can communicate with the circuitry in the memory bank logic region 72. Region 74 may be referred to as a global throat (i.e., it may include circuitry shared between memory banks 50a and 50b). The circuitry provided within region 74 may include, for example, control circuitry, column addressing circuitry, GIO buffers, etc.

[0071] Figure 10 illustrative illustrations may be related to Figure 9 The data path architecture associated with memory storage 50a and global throat 74. This architecture includes spanning segments 52a-d (where such segments are located in...). Figure 5 The extended GIO circuitry (shown in the diagram) may have four paths associated with it, the GIO circuitry extending across columns of memory data block 54 and used to address each of the four segments 52a-d. LIO circuitry 60 extends across memory data block 54. The area where LIO interacts with GIO is indicated as region 78 within one of the memory data blocks 54. GIO is shown as a multiplexer (MUX) region 80 extending into the global throat 74. For each of the 16 columns of memory data block 54 (these 16 columns are referenced...), Figure 5 (Understood as columns corresponding to the columns of data block 54 extending along the y-axis), GIOs and associated Mux regions may exist. A MuxDriver (not shown) extends to Mux region 80 and is used to control the operation of GIO paths associated with the Mux region. The MuxDriver may be coupled to a suitable control circuitry system. A bus (GBUS) 82 extends across the global throat and communicates data with the paths. The GBUS is configured to transmit data signals to and from 64 memory data blocks within memory bank 50a.

[0072] Figure 11An example physical arrangement of the data path relative to a region of memory storage 50a is shown. Four LIO regions exist within each memory data block 54. The LIO regions are below the memory array 16. In the illustrated embodiment, GBUS 82 (shown as GIO BUS) is above the memory array 16. Interconnect 84 (data path) extends between the GIO Bus and the LIO regions. Interconnect 84 may extend through and / or around array 16 and is configured to carry signals passing vertically through array 16. In the illustrated embodiment, GBUS 82 is coupled to a sense amplifier 88 (DSA) to boost the signal from GBUS in the event of excessive signal loss as information travels along GBUS.

[0073] The DSA88 can be a sense amplifier with a reference voltage for comparison with GBUS, and can be similar to the amplifier 2016 described above with reference to FIG3 in the prior art configuration. In some embodiments, the DSA88 may be optional due to the short GBUS that can be used in the embodiments described herein. If the DSA is omitted, this simplifies the fabrication of the integrated circuit and reduces the overall footprint of the integrated circuit. In some applications, the DSA can be replaced by one or more inverters and / or buffers.

[0074] Figure 12 The schematic diagram 300 illustrates some addressing (read / write operations) associated with memory bank 50. Bit line 32 is coupled to column select / sensor amplifier (CS / SA) circuitry 40 / 68, and information (data) is fed into / out of memory using the CS / SA circuitry and bit lines. Information associated with the CS / SA circuitry is accessed via a local input / output structure (LIO structure), which stores signals LIO0-LIO. n Input / output local LIO circuitry. The GBUS 82 inputs / outputs signals to / from circuit block 310, which includes a read / write (R / W) circuitry system. Specifically, block 310 includes a read block 312 and a write block 314. Unlike the prior art embodiment of FIG3, in the early stages of the read block, no sense amplifier boosts the GBUS signal to full boost or full down. Instead, the signal-to-noise ratio in the GBUS may be high enough that a large signal boost is not required. In some embodiments, instead of the sense amplifier 2016 in the prior art configuration of FIG3, one or both of an inverter-driver-circuitry and / or a buffer-circuitry system may be provided.

[0075] Input / output (I / O) block 320 communicates with the R / W circuitry of block 310. Information can be transferred between the I / O of block 320 and the R / W circuitry of block 310 via data transfer bus 318.

[0076] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0077] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0078] The terms “page,” “segment,” “block,” and “storage” are used herein and, unless otherwise expressly stated, are to be understood to have their conventional meaning in relation to memory storage applications.

[0079] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0080] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the appended claims. The term "coupling" (couple, coupling, coupled, etc.) may refer to an electrical connection.

[0081] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the figures or rotated relative to such an orientation.

[0082] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features in the plane of the cross section and do not show the material behind the plane of the cross section in order to simplify the drawings.

[0083] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0084] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally to the upper surface of the substrate.

[0085] Some embodiments include an integrated assembly having a memory array above a substrate. The memory array comprises a three-dimensional arrangement of memory cells. A sense amplifier is associated with the substrate and is located directly below the memory array. Vertically extending digital lines pass through the arrangement of memory cells and are coupled to the sense amplifier.

[0086] Some embodiments include an integrated assembly with a memory bank containing 64 memory data blocks arranged in a 16x4 configuration.

[0087] Some embodiments include an integrated assembly with a memory bank containing 512 megabytes divided among 64 memory data blocks, each memory data block having 8 megabytes. The 64 memory data blocks are arranged in a configuration with multiple rows, each row containing multiple memory data blocks.

[0088] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the same horizontal cross-section; and The memory cell includes a horizontally extending access device coupled to a storage element.

2. The integrated assembly of claim 1, wherein the memory array comprises 128 vertically stacked levels of the memory cells, and wherein the memory array comprises 128 word lines associated with each of the individual levels of the memory cells.

3. The integrated assembly of claim 1, wherein the digital lines are subdivided among comparison groups, wherein each of the comparison groups includes a first comparison digital line and a second comparison digital line, the second comparison digital line being relatively coupled to the first comparison digital line via one of the sense amplifiers.

4. The integrated assembly of claim 3, wherein the plurality of comparison groups of the digital lines are coupled to a single sense amplifier in the sense amplifier.

5. The integrated assembly of claim 1, wherein the access device is a transistor.

6. The integrated assembly of claim 1, wherein the storage element is a capacitor.

7. The integrated assembly of claim 1, wherein the storage element comprises at least one of the following: a resistive-memory device, a conductive-bridging device, a phase-change memory device, and a programmable metallization unit.

8. The integrated assembly of claim 1, wherein the vertically extending digital line extends directly through the source / drain regions of the transistors in the memory cell.

9. The integrated assembly of claim 1, further comprising a conductive plate extending vertically along a three-dimensional arrangement of the memory cell.

10. The integrated assembly of claim 9, wherein the conductive plate is configured to drain excess carriers from the channel region of the transistor.

11. The integrated assembly of claim 1, wherein the overall structure of the vertically extending digital line extends only vertically.

12. The integrated assembly of claim 1, further comprising a conductive plate, the conductive plate being a structure separate from that of the storage element.

13. The integrated assembly of claim 1, further comprising a conductive plate spaced apart from the source / drain region.

14. The integrated assembly of claim 1, wherein the storage element is spaced apart from the source / drain region.

15. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; The channel region, which is located between the source and drain regions and includes at least two sides; and A gate region that is operatively adjacent to only one side of the channel region; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the same horizontal cross-section; and The memory array comprises 128 vertically stacked levels of the memory cells, and the memory array includes 128 word lines associated with each of the individual levels of the memory cells.

16. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the same horizontal cross-section; and The vertically extending digital lines extend directly through the source / drain regions of the transistors in the memory cell.

17. The integrated assembly of claim 16, further comprising: A conductive plate coupled to the memory cell; and A storage element coupled to the memory cell, the storage element being a structure separate from the conductive plate.

18. The integrated assembly of claim 16, further comprising a conductive plate spaced apart from the source / drain region having the vertically extending digital line.

19. The integrated assembly of claim 16, wherein the storage element is spaced apart from the source / drain region.

20. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the horizontal cross-section. A conductive plate extending vertically along the three-dimensional arrangement of the memory cell; and A storage element coupled to the memory cell, the storage element being a separate structure from the conductive plate.

21. The integrated assembly of claim 20, wherein the conductive plate is configured to drain excess carriers from the channel region of the transistor.

22. The integrated assembly of claim 20, wherein the conductive plate is spaced apart from the source / drain region.

23. The integrated assembly of claim 20, further comprising a memory element spaced apart from the source / drain region.

24. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the same horizontal cross-section; and The overall structure of the vertically extending digital line is that it extends only vertically.

25. The integrated assembly of claim 24, further comprising: Conductive plate; and The storage element is a structure separate from the conductive plate.

26. The integrated assembly of claim 24, further comprising a conductive plate spaced apart from the source / drain region.

27. The integrated assembly of claim 24, further comprising a memory element spaced apart from the source / drain region.

28. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the same horizontal cross-section; and The digital lines are subdivided into comparison groups, each of which includes a first comparison digital line and a second comparison digital line, the second comparison digital line being coupled to the first comparison digital line via one of the sense amplifiers.

29. The integrated assembly of claim 28, wherein the plurality of comparison groups of the digital lines are coupled to a single sense amplifier in the sense amplifier.

30. The integrated assembly of claim 28, further comprising: Conductive plate; and The storage element is a structure separate from the conductive plate.

31. The integrated assembly of claim 28, further comprising a conductive plate spaced apart from the source / drain region.

32. The integrated assembly of claim 28, further comprising a memory element spaced apart from the source / drain region.

33. An integrated assembly comprising: Memory array above the substrate; The memory array comprises a three-dimensional arrangement of memory cells; A sensing amplifier, which is associated with the substrate and directly below the memory array; A vertically extending digital line passes through the source / drain region of the memory cell and is coupled to the sense amplifier; A channel region between the source / drain regions and including at least two sides; and a gate region operatively adjacent to only one side of the channel region; The area of ​​each source / drain region on the horizontal cross-section is substantially larger than the area of ​​each digital line on the horizontal cross-section. The memory cell includes a horizontally extending access device coupled to a storage element; and The memory array comprises 128 vertically stacked levels of the memory cells, and the memory array includes 128 word lines associated with each of the individual levels of the memory cells.

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