Non-volatile storage device, programming method thereof, and non-volatile storage system

Abstract

The application provides a non-volatile storage device and a programming method and a non-volatile storage system thereof. The programming method of the non-volatile storage device comprises: performing a write operation and a verification operation on at least one first storage unit in a plurality of storage units connected with a first word line within a first programming time; and performing a write operation on other storage units in the plurality of storage units connected with the first word line except the first storage unit. The non-volatile storage device and the programming method and the non-volatile storage system thereof are beneficial to shortening the programming time (for example, continuous programming), and beneficial to improving the transmission speed of the non-volatile storage device on the premise of improving the programming data integrity.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to non-volatile memory devices and programming methods thereof, and non-volatile memory systems. Background Technology

[0002] Non-volatile memory systems retain stored data even after power loss and are widely used in computers, cellular phones, smartphones, personal digital assistants, and other electronic device systems. A non-volatile memory system typically includes a non-volatile memory device as the storage medium and a control device for controlling the non-volatile memory device.

[0003] As the demand for write and read performance (e.g., bandwidth) of non-volatile storage systems continues to increase, higher requirements are also being placed on non-volatile storage devices and their control devices, such as programming speed and programming data integrity. Summary of the Invention

[0004] This application provides a programming method for a non-volatile memory device. The programming method includes: performing a write operation and a verification operation on at least one first memory cell among a plurality of memory cells connected to a first word line during a first programming time; and performing write operations on the other memory cells among the plurality of memory cells connected to the first word line, excluding the first memory cell.

[0005] In some embodiments, the programming method may further include: performing write operations on a plurality of memory cells connected to a second word line during a second programming time, wherein the second word line is different from the first word line.

[0006] In some implementations, the programming method may further include: determining a second word line based on the fact that the defect probability of each word line is less than a predetermined threshold.

[0007] In some implementations, a plurality of storage units connected to the first word line are located in a storage string with a sequence number, and the first storage unit may include a storage unit on the storage string with the last sequence number.

[0008] In some embodiments, the programming method may further include: performing a write operation and a verification operation on at least one of a plurality of memory cells connected to a first word line, according to a received enable verification command.

[0009] In some implementations, the storage unit may include SLC.

[0010] This application also provides a non-volatile memory device. The non-volatile memory device includes: a first word line connected to a plurality of memory cells; and peripheral circuitry configured to: perform a write operation and a verification operation on at least one of the plurality of memory cells connected to the first word line during a first programming time; and perform write operations on the other memory cells among the plurality of memory cells connected to the first word line, excluding the first memory cell.

[0011] In some embodiments, the non-volatile memory device further includes a second word line different from the first word line, and the peripheral circuitry may also be configured to perform write operations on a plurality of memory cells connected to the second word line during a second programming time.

[0012] In some implementations, the peripheral circuitry may also be configured to determine a second word line based on the fact that the defect probability of each word line is less than a predetermined threshold.

[0013] In some implementations, a plurality of storage units connected to the first word line are located in a storage string with a sequence number, and the first storage unit may include a storage unit on the storage string with the last sequence number.

[0014] In some implementations, the storage unit may include SLC.

[0015] This application also provides a non-volatile storage system. The non-volatile storage system includes: a non-volatile storage device as described in any of the embodiments above; and a control device configured to control the non-volatile storage device to execute the programming method described in any of the embodiments above.

[0016] In some implementations, the control device may also be configured to send an enable verification command.

[0017] In some implementations, the non-volatile storage system may include a solid-state drive (SSD).

[0018] According to some embodiments of this application, the non-volatile storage device and its programming method and non-volatile storage system, by performing write operations and verification operations on some storage cells connected by the same word line, the process of judging the programming state of some storage cells is executed within the programming time, which is beneficial to shorten the programming time (e.g., continuous programming) and improve the transmission speed of the non-volatile storage device while improving the integrity of the programming data. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0020] Figure 1This is a functional block diagram of a non-volatile storage device according to an embodiment of this application;

[0021] Figure 2A This is a timing diagram of the programming operation of a non-volatile memory device according to an embodiment of this application;

[0022] Figure 2B This is a timing diagram of the read operation of a non-volatile memory device according to an embodiment of this application;

[0023] Figure 3 This is an equivalent circuit diagram of a storage block according to an embodiment of this application;

[0024] Figure 4 This is a flowchart of a programming method for a non-volatile memory device according to an embodiment of this application; and

[0025] Figure 5 This is a functional block diagram of a non-volatile storage system according to an embodiment of this application. Detailed Implementation

[0026] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0027] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0028] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0029] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0030] Figure 1This is a functional block diagram of a non-volatile storage device 100 according to an embodiment of this application. For example... Figure 1 As shown, the non-volatile storage device 100 may include a storage cell array 110 and peripheral circuitry 120. The peripheral circuitry 120 may include, but is not limited to, an address decoder 121, a page buffer 122, control logic circuitry 123, and I / O circuitry 124.

[0031] In an exemplary embodiment, the memory cell array 110 can be connected to the address decoder 121 via, for example, word lines (WL) and bit lines (BL). Exemplarily, the memory cell array 110 may include a plurality of dies (DIEs, or LUNs), each die may include a plurality of planes, each plane may include a plurality of memory blocks, such as Block1 to Block2, and each memory block may include a plurality of pages. Exemplarily, the non-volatile memory device 100 performs erase operations on a block-by-block basis and performs programming or read operations on a page-by-page basis.

[0032] In an exemplary embodiment, the address decoder 121 may control, in response to the control logic circuit 123, components such as word lines WL, select lines TSL / BSL, and bit lines BL (see reference) connected to the memory cell array. Figure 3 In other words, the address decoder 121 can receive and decode the address ADDR from the control logic circuit 123, and select one of the multiple memory blocks Block1 to Block2 in the memory cell array 110 according to the decoded address ADDR (e.g., column address ADDR-C and row address ADDR-R). Optionally, one of the multiple pages in the selected memory block Block can be selected.

[0033] In an exemplary embodiment, page buffer 122 may be, for example, a cache register. Exemplarily, page buffer 122 may temporarily store data during programming and / or reading operations in response to control of control logic circuitry 123, in order to reduce data transfer time.

[0034] Control logic circuitry 123 can control address decoder 121 and page buffer 122 in response to commands CMD (e.g., programming commands and read commands) and addresses ADDR from I / O circuitry 124. Optionally, control logic circuitry 123 can control non-volatile memory device 100 to perform programming operations via, for example, a multi-step method. A multi-step method can perform programming operations multiple times to configure a desired programming state and may include, but is not limited to, pre / master programming methods, reprogramming methods, and shadow programming methods.

[0035] Those skilled in the art will understand that the operations performed by the address decoder 121, page buffer 122, control logic circuit 123, and I / O circuit 124 described in this application can be performed by processing circuitry. Optionally, processing circuitry may include, but is not limited to, hardware of logic circuitry or a hardware / software combination of a processor executing software.

[0036] In an exemplary embodiment, the non-volatile storage device 100 may perform a programming operation according to a received programming command, or perform a reading operation according to a received reading command. Figure 2A This is a timing diagram of a non-volatile storage device 100 performing programming operations according to an embodiment of this application. Figure 2B This is a timing diagram of a non-volatile memory device 100 performing a read operation according to an embodiment of this application. DQx can represent a data bus signal, Cycle Type can further represent the type of data bus signal, and SR[6] can represent the state of the non-volatile memory device 100, such as a programming operation or a read operation.

[0037] like Figure 2A As shown, the programming command may include, for example, two subcommands (e.g., 80h and 10h). In an exemplary embodiment, after receiving subcommand 80h, the non-volatile storage device 100 receives the address ADDR of the data to be programmed (e.g., two column addresses C1-C2 and three row addresses R1-R3). After receiving address ADDR, the non-volatile storage device 100 may receive the data DATA to be programmed (e.g., D0-Dn) and cache the data DATA in page memory 122. After receiving subcommand 10h, the non-volatile storage device 100 writes the DATA in page buffer 122 to memory cell array 110 within programming time tPROG.

[0038] like Figure 2B As shown, a read command may include, for example, two subcommands (e.g., 00h and 30h). In an exemplary embodiment, the non-volatile storage device 100 transmits the address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of the data to be read between the received subcommands 00h and 30h. After the non-volatile storage device 100 receives subcommand 30h, within the read time tR, the data DATA (e.g., D0-Dn) corresponding to the page at the received row address can be cached in the page buffer 122 first, and then the data DATA can be read on demand. Optionally, a portion of the corresponding data in the page can be read from the page buffer 122.

[0039] Figure 3This is an equivalent circuit diagram of storage block Block 1 according to an embodiment of this application. Storage block Block 1 may be the same as or similar to other storage blocks Block 2 to Block 2 in the storage cell array 110. Therefore, this application uses storage block Block 1 as an example for further explanation.

[0040] In an exemplary implementation, such as Figure 3 As shown, the memory block Block1 may include multiple memory strings, such as MS1 to MS4. The memory strings MS1 to MS4 may be arranged in a two-dimensional array on the xy-plane. Each memory string MS1 to MS4 may extend along the z-axis and may sequentially include top selection transistors (e.g., TST1 to TST4), memory cells MC, and bottom selection transistors BST, with their source and drain terminals connected in series. Optionally, the memory cell MC may be a charge-trapping memory cell, capable of changing its threshold voltage using the tunneling effect, thereby allowing the memory cell MC to be in different storage states. Optionally, the memory cell MC may include an SLC capable of storing 1 bit of data. For an SLC, a memory cell MC may have two storage states, for example, depending on the number of charge carriers (e.g., electrons) in the charge-trapping layer.

[0041] It should be noted that the number of selection transistors TST / BST and / or memory cells MC in each memory string M1 to M4 is merely exemplary, and this application does not specifically limit the specific number of the above structures.

[0042] In an exemplary embodiment, memory strings MS1 to MS4 in memory block Block1 can be connected to a common source line CSL. For example, the source terminal of the bottom select transistor BST at the end of each memory string MS1 to MS4 can be connected to the common source line CSL.

[0043] In an exemplary embodiment, the gate terminals of memory cells (e.g., MC11-MC14) located at the same or similar height from the common source line CSL in memory strings MS1-MS4 can be connected to the same word line, such as the first word line WL1. Optionally, for an SLC, memory cells MC11-MC14 connected to the same word line, such as the first WL1, and capable of performing programming operations upon receiving a programming command constitute a page. It is understood that a memory block Block1 may include multiple word lines WL, and multiple word lines WL may correspond to multiple pages.

[0044] In an exemplary embodiment, the gates of top-select transistors, such as TST1 and TST2, located at the same or similar height from the common source line CSL in memory strings MS1 and MS2 arranged in the y-axis direction, can be connected to the same top-select line TSL1. Similarly, the gates of top-select transistors, such as TST3 and TST4, located at the same or similar height from the common source line CSL in memory strings MS3 and MS4 arranged in the y-axis direction, can be connected to the same top-select line TSL2.

[0045] In an exemplary embodiment, the gates of the bottom transistors BST in memory strings MS1 to MS4, located at the same or similar height from the common source line CSL, can be connected to the same bottom select line BSL. In other embodiments, similar to the top select lines TSL1 and TSL2, the gates of the bottom select transistors BST in memory strings such as MS1 and MS2 arranged in the y-axis direction, located at the same or similar height from the common source line CSL, can be connected to the same bottom select line BSL1 (not shown). The gates of the bottom select transistors BST in memory strings such as MS3 and MS4 arranged in the y-axis direction, located at the same or similar height from the common source line CSL, can be connected to the same bottom select line BSL2 (not shown).

[0046] In an exemplary embodiment, the drain terminals of the top select transistors TST1 and TST3, located at the same or similar height from the common source line CSL in memory strings MS1 and MS3 arranged in the x-axis direction, and situated at their ends, can be connected to the same bit line BL1. Similarly, the drain terminals of the top select transistors TST2 and TST4, located at the same or similar height from the common source line CSL in memory strings MS2 and MS4 arranged in the x-axis direction, and situated at their ends, can be connected to the same bit line BL2.

[0047] In an exemplary embodiment, according to the structure described above, the extension direction of the bit line BL may be perpendicular to the extension direction of the top select line TSL.

[0048] It should be noted that the number of storage strings, word lines, bit lines and select lines in the storage block Block 1 shown in Figure 2 is only an example, and this application does not specifically limit the number of the above structures.

[0049] Figure 4 This is a flowchart of a programming method 1000 for a non-volatile storage device according to an embodiment of this application. For example... Figure 4 As shown, programming method 1000 may include the following steps:

[0050] S110, during the first programming time, a write operation and a verification operation are performed on at least one of the multiple memory cells connected to the first word line;

[0051] S120, perform a write operation on the memory cells other than the first memory cell among the multiple memory cells connected to the first word line.

[0052] It should be understood that the steps shown in programming method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps in the steps may be performed simultaneously or in a sequence different from the steps shown. Figure 4 The execution order is shown below. This will be combined with... Figure 1 and Figure 3 The hardware structure of the non-volatile storage device 100 shown in the figure and Figure 2A The timing diagram of the programming operation of the non-volatile storage device 100 shown in the figure further illustrates steps S110 to S120.

[0053] In an exemplary implementation, the programming time tPROG may include several programming cycles, each of which may be used to perform a write operation or a write operation and a verification operation on each of a plurality of memory cells connected to the same word line WL.

[0054] In an exemplary implementation, within a programming cycle, such as Figure 3 As shown, when performing a write operation on memory cell MC11 connected to, for example, the first word line WL1, a programming voltage (e.g., 15-20V) can be applied to the first word line WL1, and the bottom select transistor BST and top select transistor TST1 on the memory string MS1 containing memory cell MC11 can be turned on. A ground voltage, for example, can be applied to the bit line BL1 connected to the memory string MS1 containing memory cell MC11. Under the influence of the high voltage on the first word line WL1, charge carriers (e.g., electrons) tunnel through and charge, for example, the charge trapping layer, to reach a predetermined threshold voltage range. Optionally, the top select transistor TST3 and bottom select transistor BST in MS3 can be turned off to suppress writing to memory cell M13 in memory string MS3. Optionally, a programmable disable voltage (e.g., 2V) can be applied to the bit line BL2 to prevent the tunneling effect of charge carriers (e.g., electrons) and suppress writing to memory cell M12 in memory string MS2. Optionally, the programming voltage can include a pulse voltage, such as a multi-step pulse voltage. Optionally, the programming method described above can be used to perform write operations on the memory cells MC11 to MC14 on the first word line WL1 in programming cycles during the programming time tPRPG.

[0055] In an exemplary embodiment, the memory cells MC11 to MC14 connected to the first word line WL1 can be located in memory strings MS11 to MS14, each with a sequence number. During the programming time tPROG, memory cells MC11 to MC14 can perform write operations in programming cycles according to their sequence numbers in memory strings MS11 to MS14.

[0056] It should be noted that before performing a write operation on the storage cells MC11 to MC14 connected to the first word line WL1, the storage cells MC1 to MC4 may be in an erased state. Optionally, for SLC, the erased state may, for example, be represented by data of "1". In other words, the storage cells MC11 to MC14 may all represent data of "1" before the write operation is performed. According to the embodiment of this application, during the write operation, the write operation may be performed on the storage cells MC11 to MC14, so that the storage cells MC11 to MC14 after the write operation are represented by data of "0".

[0057] In an exemplary embodiment, a verification operation can be performed on the memory cell MC14 after a write operation within one programming cycle. For example, the bit line BL2 connected to the memory string MS4 containing the memory cell MC14 can be charged to a threshold value and then left floating. Then, an on-state voltage (e.g., 5V) can be applied to word lines WL other than the first word line WL1, turning on the bottom select transistor BST and top select transistor TST4 on the memory string MS4 containing the memory cell MC14, and turning off the top select transistor TST2 and bottom select transistor BST on the memory string MS2 containing MC12. By applying a verification voltage to the first word line WL1, the current value at the bit line BL2 is sensed to obtain the data value of the memory cell MC14, thereby determining whether the threshold voltage of the memory cell M14 after the write operation is within a predetermined threshold voltage range, thus judging the integrity of the data in the memory cell MC14.

[0058] It should be noted that during the programming cycle of at least one of the memory cells MC11 to MC14 connected to the first word line WL1, a verification operation can be performed after a write operation is performed on the memory cell MC. The verification operation can be used, for example, to verify whether the memory cell MC has reached a predetermined threshold voltage range after the write operation, thereby improving data integrity after multiple memory cells connected to the same word line have been programmed.

[0059] In an exemplary embodiment, as described above, when write and verification operations are performed on memory cell MC14 among the memory cells MC11 to MC14 connected to the first word line WL1 during the programming cycle, since memory cells MC11 to MC14 connected to the first word line WL1 perform write operations or write and verification operations sequentially according to their sequence numbers in memory strings MS1 to MS4, write operations on MC11 to MC13 may cause write interference to MC14, resulting in a high probability of write errors in memory cell MC14. Therefore, when performing programming operations on multiple memory cells located in memory strings with different sequence numbers connected to the same word line, performing write and verification operations on the memory cell in the memory string with the last sequence number can further improve data integrity after programming operations on multiple memory cells connected to the same word line.

[0060] In an exemplary embodiment, the second word line WL2 can be determined, for example, by using a lookup table, based on the probability that the defects (e.g., physical defects) of multiple word lines are less than a predetermined threshold. Figure 3 As shown, during another programming time (e.g., the second programming time), within each programming cycle, the write operation method described above is used to perform write operations on the memory cells MC21 to MC24 connected to the second word line WL2. It is understood that, for example, if the defect probability of the second word line WL2 is less than a predetermined threshold, the probability of programming errors after performing programming operations on the multiple memory cells MC21 to MC24 connected to the second word line WL2 is relatively small. Therefore, only write operations are performed on each memory cell MC21 to MC24 connected to the second word line WL2, which helps to shorten the programming operation time of the multiple memory cells MC21 to MC24 connected to the second word line WL2 and improves the speed of programming operations.

[0061] In an exemplary embodiment, the operation of step S110 can be performed according to, for example, a control device 200 (reference 200). Figure 5 The non-volatile storage device 100 executes the verification enable command received. In other words, the operation in step S110 described above can be performed in the non-volatile storage device 100 after the verification enable command is received. In some other embodiments, the non-volatile storage device 100 can be driven to execute step S110 according to the firmware burned into the non-volatile storage device 100, which is not specifically limited in this application.

[0062] Through the inventors' research, one of the reasons for write failures of memory cells (e.g., SLC memory cells) is leakage in the word line to which they are connected. Since multiple memory cells can be physically connected to the same word line and can perform programming operations at the same programming time (i.e., receiving the same programming command), in some related technologies, after programming operations are performed on multiple memory cells connected to the same word line, at least a portion of the multiple memory cells are then read to determine whether the memory cells are in the correct programming state.

[0063] In some exemplary embodiments, the method of performing a read operation on at least a portion of the memory cells connected to the same word line is similar to the method of performing a programming verification operation on a memory cell MC14 connected to, for example, the first word line WL1, as described above, and will not be repeated here.

[0064] As described above, after performing programming operations on multiple memory cells connected by the same word line, according to Figure 2B The illustrated read operation timing performs a read operation on at least a portion of the memory cells connected to the word line. However, for some processes that require continuous programming, performing a read operation will interrupt, for example, the page buffer 122, and will also increase the time for address transfer, data transfer, and data reading during the read command process, which is detrimental to shortening the programming process (e.g., continuous programming process) time and improving the programming speed of non-volatile memory devices.

[0065] According to some embodiments of the present application, the programming method for a non-volatile memory device is provided by performing write and verification operations on some memory cells connected by the same word line, so that the process of judging the programming state of some memory cells is executed within the programming time, thereby shortening the programming time (e.g., continuous programming) and improving the transmission speed of the non-volatile memory device while improving the integrity of the programming data.

[0066] Figure 5 This is a functional block diagram of a non-volatile memory system 2000 according to an embodiment of this application. For example... Figure 5 As shown, the non-volatile storage system 2000 includes a non-volatile storage device 100 and a control device 200. Optionally, the non-volatile storage system 2000 may include, for example, a solid-state drive.

[0067] The storage device 100 may be the same as the non-volatile storage device 100 described in any of the embodiments above, and will not be described again in this application.

[0068] Control device 200 can control storage device 100 via, for example, channel CH, and storage device 100 can perform operations based on control of control device 200 in response to, for example, a request from host 300. Storage device 100 can receive command CMD and address ADDR from controller 200 via channel CH and access memory cell array 110 (see reference) in response to that address. Figure 1 The region selected by the address. In other words, the storage device 100 can perform internal operations corresponding to the command on the region selected by the address. More specifically, the control device 200 sends a command to execute the programming method 1000 described in any of the above embodiments and the address ADDR through the channel CH, causing the storage device 100 to execute the programming method 1000.

[0069] In an exemplary embodiment, the control device 200 may, for example, send an enable verification command via channel CH so that the non-volatile storage device 100 can perform the operation of step S120 as described above after the enable verification command is sent.

[0070] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A programming method for a non-volatile memory device, comprising: Based on the relationship between the defect probability of the character line and a predetermined threshold, a second character line, different from the first character line, is determined, wherein the defect probability of the second character line is less than the predetermined threshold. During the first programming time, a write operation and a verification operation are performed on at least one of the multiple memory cells connected to the first word line; For the plurality of memory cells connected to the first word line, only write operations are performed on the memory cells other than the first memory cell; and During the second programming time, only write operations are performed on the multiple memory cells connected to the second word line.

2. The programming method according to claim 1, wherein, The plurality of storage units connected to the first word line are located in a storage string with a sequence number, and the first storage unit includes the storage unit on the storage string with the last sequence number.

3. The programming method according to claim 1, wherein, The programming method also includes: Based on the received enable verification command, a write operation and a verification operation are performed on at least one of the first storage cells among a plurality of storage cells connected to the first word line.

4. The programming method according to any one of claims 1 to 3, wherein, The storage unit includes SLC.

5. A non-volatile storage device, comprising: The first word line connects to multiple memory cells; The second word line is different from the first word line and is connected to multiple memory cells; as well as The peripheral circuitry is configured as follows: During the first programming time, a write operation and a verification operation are performed on at least one of the multiple memory cells connected to the first word line; For the multiple memory cells connected to the first word line, only write operations are performed on the other memory cells besides the first memory cell. as well as The second word line is determined based on the fact that the defect probability of the word line is less than a predetermined threshold, and only write operations are performed on the multiple memory cells connected to the second word line during the second programming time.

6. The non-volatile storage device according to claim 5, wherein, The plurality of storage units connected to the first word line are located in a storage string with a sequence number, and the first storage unit includes the storage unit on the storage string with the last sequence number.

7. The non-volatile storage device according to claim 5 or 6, wherein, The storage unit includes SLC.

8. Non-volatile memory systems, including: The non-volatile storage device as described in any one of claims 5 to 7; as well as A control device is configured to control the non-volatile storage device to perform the programming method as claimed in any one of claims 1 to 4.

9. The non-volatile storage system according to claim 8, wherein, The control device is also configured to send an enable verification command.

10. The non-volatile storage system according to claim 8, wherein, The non-volatile storage system includes solid-state drives (SSDs).

Images