Semiconductor structure fabrication methods, three-dimensional memory and memory system

Abstract

This disclosure provides a method for fabricating a semiconductor structure, a three-dimensional memory, and a memory system, relating to the field of semiconductor chip technology, and aims to improve the fabrication yield of semiconductor structures. The method for fabricating the semiconductor structure includes: forming a dielectric stack structure on a substrate; forming a first channel structure penetrating the dielectric stack structure; forming a gate trench penetrating the dielectric stack structure; removing a first sacrificial layer through the gate trench to form a first gap; modifying a target portion of the memory layer through the first gap to form a barrier portion; forming a gate insulating layer within the first gap; removing at least a portion of a second sacrificial layer through the gate trench to form a second gap; and forming a gate layer within the second gap. The above semiconductor structure is applied in a three-dimensional memory to realize data read and write operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a method for fabricating a semiconductor structure, a three-dimensional memory, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (i.e., 3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] Three-dimensional memory can include semiconductor structures as storage arrays and peripheral devices. How to improve the fabrication yield of the aforementioned semiconductor structures is a problem to be solved. Summary of the Invention

[0005] Embodiments of this disclosure provide a method for fabricating a semiconductor structure, a three-dimensional memory, and a memory system, aiming to improve the fabrication yield of semiconductor structures in three-dimensional memories.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a method for fabricating a semiconductor structure is provided. The method includes: forming a dielectric stack structure on a substrate, the dielectric stack structure including alternating first and second sacrificial layers; forming a first channel structure penetrating the dielectric stack structure, the first channel structure including a memory layer; forming a gate spacer penetrating the dielectric stack structure; removing the first sacrificial layer via the gate spacer to form a first gap; modifying a target portion of the memory layer via the first gap to form a barrier portion. The target portion of the memory layer is a portion of the memory layer, the target portion including at least a portion of the memory layer opposite to the first gap along a direction parallel to the substrate; forming a gate insulating layer within the first gap; removing at least a portion of the second sacrificial layer via the gate spacer to form a second gap; and forming a gate layer within the second gap.

[0008] The semiconductor structure fabrication method provided in this disclosure modifies the memory layer within the first channel structure by first removing the first sacrificial layer to form a first gap, thereby obtaining multiple memory cells; subsequently, a gate insulating layer and a gate layer are formed. This avoids the modification process affecting the gate insulating layer and gate layer, thus improving the fabrication yield of the semiconductor structure.

[0009] In some embodiments, before forming the gate insulating layer within the first gap, the method further includes forming a first protective layer on the inner wall of the first gap. After forming the gate insulating layer within the first gap, the method further includes forming a second protective layer within the gate spacer. The second protective layer covers the side of the gate insulating layer exposed within the gate spacer, and the second protective layer is connected to the first protective layer to surround the gate insulating layer.

[0010] In some embodiments, before forming the second protective layer within the gate spacer, the method further includes: removing the end of the gate insulating layer near the gate spacer, so that the side of the gate insulating layer is recessed relative to the side of the first protective layer, forming a groove. Forming the second protective layer within the gate spacer includes: forming a second protective film, the second protective film filling the groove and covering the inner wall of the gate spacer; etching the second protective film, retaining the portion of the second protective film located within the groove, as the second protective layer.

[0011] In some embodiments, under the same process conditions, the etching rate of the first protective layer is less than the etching rate of the gate insulating layer. Removing the end of the gate insulating layer near the gate spacer includes: using an etching process to remove the end of the gate insulating layer near the gate spacer.

[0012] In some embodiments, prior to forming the gate trench through the dielectric stack structure, the method further includes: forming a connection hole; the connection hole extends from the side of the dielectric stack structure away from the substrate to a target second sacrificial layer and exposes a target first sacrificial layer; the target first sacrificial layer is adjacent to the target second sacrificial layer. A surface treatment is performed on the exposed surface of the target first sacrificial layer via the connection hole to form a third protective layer. A connection structure is formed within the connection hole.

[0013] In some embodiments, the surface treatment includes an oxidation process.

[0014] In some embodiments, forming a connection hole includes: forming a main body portion of the connection hole, the main body portion extending from the side of the dielectric stack structure away from the substrate to a target second sacrificial layer; forming an isolation layer within the main body portion; removing a portion of the isolation layer located at the bottom of the main body portion; and removing a portion of the target second sacrificial layer located below and around the main body portion to form an extension portion of the connection hole; the extension portion communicates with the main body portion, and the orthographic projection of the main body portion onto the substrate lies within the orthographic projection range of the extension portion onto the substrate.

[0015] In some embodiments, the dielectric stack structure includes a connection region and a storage region. The gate spacer includes a first sub-gate spacer located in the connection region and a second sub-gate spacer located in the storage region. The step of removing at least a portion of the second sacrificial layer via the gate spacer to form a second gap includes: forming a first sacrificial pattern located in the first sub-gate spacer; removing a portion of the second sacrificial layer located in the storage region via the second sub-gate spacer; removing the first sacrificial pattern; and removing a portion of the second sacrificial layer located in the connection region and close to the first sub-gate spacer via the first sub-gate spacer.

[0016] In some embodiments, before forming the first sacrificial pattern located in the first sub-gate trench, the method further includes: forming a stop layer covering the substrate in the first sub-gate trench; under the same process conditions, the etching rate of the stop layer is less than the etching rate of the first sacrificial pattern; removing the portion of the second sacrificial layer located in the connection region and close to the first sub-gate trench further includes: removing the stop layer in the first sub-gate trench.

[0017] In some embodiments, forming a first sacrificial pattern in the first sub-gate trench includes: filling the gate trench with sacrificial material; forming a hard mask layer covering the dielectric stack structure and the sacrificial material, the hard mask layer exposing the sacrificial material in the second sub-gate trench; and removing the sacrificial material in the second sub-gate trench based on the hard mask layer, leaving the sacrificial material in the first sub-gate trench to form the first sacrificial pattern.

[0018] In some embodiments, forming a first channel structure penetrating the dielectric stack structure includes forming a channel hole penetrating the dielectric stack structure. After forming the channel hole penetrating the dielectric stack structure, the fabrication method further includes forming a fourth protective layer covering the channel hole. The storage layer is located inside the fourth protective layer.

[0019] In some embodiments, before modifying the target portion of the storage layer via the first gap, the process includes: removing the target portion of the fourth protective layer via the first gap to form a break in the fourth protective layer; the target portion of the fourth protective layer includes at least a portion of the fourth protective layer opposite to the first gap along a direction parallel to the substrate. Modifying the target portion of the storage layer via the first gap further includes: modifying the target portion of the storage layer through the break in the fourth protective layer via the first gap.

[0020] In some embodiments, after forming the protective layer covering the channel hole, the method further includes forming a dielectric layer covering the fourth protective layer. The storage layer is located inside the dielectric layer.

[0021] In some embodiments, modifying the target portion of the storage layer to form a barrier portion includes: oxidizing the target portion of the storage layer to form a barrier portion, wherein the storage layer is divided into a plurality of storage portions by the barrier portion.

[0022] In another aspect, a semiconductor structure is provided. This semiconductor structure includes a source layer, a memory stack structure, and a second channel structure. The memory stack structure is located on the source layer and includes alternately stacked gate insulating layers and gate layers. Among a plurality of protective films, one protective film surrounds one of the gate insulating layers. The second channel structure penetrates the memory stack structure and extends into the source layer. The second channel structure includes a memory layer; the memory layer includes a plurality of memory portions spaced apart from each other, and a barrier portion located between two adjacent memory portions; the memory portions are disposed opposite to the gate layer in a direction parallel to the source layer. A fourth protective layer includes a plurality of protective portions spaced apart from each other, one of the protective portions being located between one of the gate insulating layers and one of the barrier portions.

[0023] In some embodiments, the dimension of the storage portion near the gate layer along the length of the second channel structure is smaller than the dimension of the storage portion away from the gate layer along the length of the second channel structure. And / or, the dimension of the barrier portion near the gate layer along the length of the second channel structure is larger than the dimension of the barrier portion near the gate layer along the length of the second channel structure.

[0024] In some embodiments, the dimension of the end of the barrier portion near the gate layer in the length direction of the second channel structure is greater than the dimension of the end of the barrier portion near the gate layer in the length direction of the second channel structure.

[0025] In some embodiments, along the length of the channel structure, one of the protection portions contacts two adjacent gate layers.

[0026] In some embodiments, the three-dimensional memory further includes a connection structure. The connection structure extends from the side of the memory stack structure away from the source layer toward the source layer until it penetrates the target gate layer and is electrically connected to the target gate layer.

[0027] In some embodiments, the connection structure includes a main portion and an extension portion. The main portion extends through the memory stack structure; the extension portion is electrically connected to the target gate layer. The semiconductor structure further includes a third protective layer. The third protective layer is located between the extension portion and the target gate insulating layer; the target gate insulating layer is adjacent to the target gate layer.

[0028] In some embodiments, the three-dimensional memory further includes an isolation layer. The isolation layer surrounds the main portion of the connection structure along a direction parallel to the source layer.

[0029] In some embodiments, the three-dimensional memory further includes a dielectric layer located between the gate layer and the memory layer. The dielectric layer covers the surface of the memory stack structure near the memory layer; or, the dielectric layer includes a plurality of dielectric portions spaced apart from each other, the dielectric portions being located between the memory portions and the gate layer.

[0030] In some embodiments, at least one of the protective film and the protective layer is made of carbon-doped silicon nitride.

[0031] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in some of the embodiments above, and peripheral devices electrically connected to the semiconductor structure.

[0032] In another aspect, a storage system is provided, comprising: a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0033] In another aspect, an electronic device is provided, characterized in that it includes the storage system described above.

[0034] It is understood that the beneficial effects of the semiconductor structure, three-dimensional memory, storage system and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0036] Figure 1A cross-sectional view of a three-dimensional memory according to some embodiments;

[0037] Figure 2 A cross-sectional view of a string of storage cells in a three-dimensional memory according to some embodiments;

[0038] Figure 3 for Figure 2 Equivalent circuit diagram of the memory cell string;

[0039] Figure 4 This is a partial structural diagram of a semiconductor structure in a three-dimensional memory according to some embodiments;

[0040] Figure 5 This is a top view of a semiconductor structure in a three-dimensional memory according to some embodiments, after the array interconnect layer has been removed;

[0041] Figure 6 For along Figure 5 A cross-sectional view formed by line A-A' in the middle;

[0042] Figure 7A for Figure 6 A magnified structural diagram of the FD region in the middle;

[0043] Figure 7B for Figure 6 Another structural diagram of the FD region after magnification;

[0044] Figure 8 For along Figure 5 A cross-sectional view formed by line B-B' in the middle;

[0045] Figures 9A to 9Z' These are partial structural diagrams of a semiconductor structure at different fabrication stages according to some embodiments;

[0046] Figures 10-24 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0047] Figure 25 This is a block diagram of a storage system according to some embodiments;

[0048] Figure 26 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0049] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0050] In the description of this disclosure, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0051] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0052] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0053] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0054] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0055] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0056] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0057] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0058] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0059] In the context of this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also includes “on something” with intermediate features or layers therebetween, and “above” or “above” means not only “above” or “above” something, but also includes “above” or “above” something without intermediate features or layers therebetween (i.e., directly on something).

[0060] In the embodiments of this disclosure, the meaning of "A and B are arranged opposite each other in one direction" should be interpreted in the broadest sense, and can be understood as: the orthographic projection of A onto C caused by light rays parallel to that direction overlaps with the orthographic projection of B onto C caused by light rays in that direction. The overlap can be, for example, complete overlap or partial overlap.

[0061] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0062] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0063] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0064] Figure 1 This is a cross-sectional view of a three-dimensional memory according to some embodiments. Figure 2 This is a cross-sectional view of a string of storage cells in a three-dimensional memory according to some embodiments. Figure 3 for Figure 2 Equivalent circuit diagram of the storage cell string.

[0065] It should be noted that, in Figure 1 In this embodiment, the three-dimensional memory 10 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0066] As used in embodiments of this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to the substrate or source layer of the semiconductor device in the third direction Z, when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concepts are applied throughout the embodiments of this disclosure to describe spatial relationships.

[0067] In order to show the structure of the device more clearly, in Figure 1 The image shows a view of the storage area CA and a view of the connection area SS. The view of the storage area CA is based on the left coordinate system, and the view of the connection area SS is based on the right coordinate system. That is, the view of the storage area CA shows the cross-sectional structure along the Y direction, and the view of the connection area SS shows the cross-sectional structure along the X direction.

[0068] See Figure 1Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL and an array interconnect layer 290. The three-dimensional memory 10 may also include peripheral devices 100 coupled to the semiconductor structure 200. The peripheral devices 100 may be disposed on the side of the array interconnect layer 290 away from the source layer SL.

[0069] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0070] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as “memory cell string 400”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0071] See in some examples Figure 2 and Figure 3 The storage cell string 400 may include multiple transistors T, one transistor T (e.g. Figure 3 Transistors T1 through T6 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (e.g., each transistor T) can be formed by a semiconductor channel 221 and a gate line G surrounding the semiconductor channel 221. The gate line G is configured to control the conduction state of the transistor.

[0072] It should be noted that, Figures 1-3 The number of transistors is only illustrative. The storage cell string of the three-dimensional memory provided in the embodiments of this disclosure may also include other numbers of transistors, such as 4, 16, 32, and 64.

[0073] Furthermore, along the third direction Z, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. The uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0074] See also Figure 1 In some embodiments, the array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0075] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as the bit line BL, and word line interconnect lines WL-CL coupled to the word line WL. The materials of the first interconnect conductor layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or other suitable materials.

[0076] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device (e.g., semiconductor structure 200), including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0077] For example, in some embodiments, peripheral device 100 may include substrate 110, transistor 120 disposed on substrate 110, and peripheral interconnect layer 130 disposed on substrate 110. Peripheral circuitry may include transistor 120.

[0078] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0079] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0080] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. In some examples, because the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuitry in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 100 to enable the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, allowing the peripheral interconnect layer 130 and the array interconnect layer 290 to be bonded and coupled together.

[0081] Please see Figure 4 , Figure 4 This is a partial structural diagram of a semiconductor structure according to some embodiments. In some embodiments, the semiconductor structure 00 includes an active layer 01, a memory stack structure 02, and a channel structure 03. The memory stack structure 02 is formed above the active layer 01, and the channel structure 03 penetrates the memory stack structure 02. The channel structure 03 may extend into a portion of the active layer 01 or may not extend into the active layer 01; this is not limited here.

[0082] The memory stack structure 02 includes gate layers 021 and gate insulating layers 022 alternately stacked along a direction perpendicular to the active layer 01. The channel structure 03 includes a channel layer 031, and a tunneling layer 032, a memory layer 033, and a barrier layer 034 sequentially disposed along a direction away from the channel layer 031. The memory layer 033 includes multiple mutually separated memory portions 0331, and the barrier layer 034 includes multiple mutually separated barrier portions 0341. A memory portion 0331 and a barrier portion 0341 are located between two adjacent gate insulating layers 022.

[0083] The inventors of this disclosure discovered that, Figure 4 The semiconductor structure shown has an increased actual size of the channel structure 03 because the storage unit 0331 is located outside the channel via. Furthermore, the need for a distance between different channel structures 03 to prevent interference between the storage units 0341 reduces the number of channel vias / channel structures 03 that can be placed within the same volume, thus limiting the increase in the channel structure 03 density in the semiconductor structure 00. Here, the channel structure 03 density in the semiconductor structure 00 refers to the number of channel structures 03 placed per unit volume of the semiconductor structure 00.

[0084] Based on this, some embodiments of this disclosure provide a three-dimensional memory 10. Please refer to... Figures 5 to 7B ,in, Figure 5 This is a top view of a semiconductor structure in a three-dimensional memory according to some embodiments, after the array interconnect layer has been removed; Figure 6 For along Figure 5A cross-sectional view formed by line A-A' in the middle; Figure 7A and Figure 7B They are respectively Figure 6 Two structural diagrams of the FD region are shown in magnified view. The semiconductor channel structure 200 in the three-dimensional memory 10 includes a source layer SL, a memory stack structure 210, and a second channel structure 220. Both the memory stack structure 210 and the second channel structure 220 are located above the source layer SL.

[0085] The material of the source layer SL has been described in detail previously and will not be repeated here.

[0086] In some embodiments, the memory stack structure 210 may be in direct contact with the source layer SL. The memory stack structure 210 includes a plurality of gate layers 211 and a plurality of gate insulating layers 212. The gate layers 211 and gate insulating layers 212 are alternately arranged, for example, the gate insulating layers 212 and gate layers 211 are alternately arranged in a direction away from the source layer SL, and stacked to form a plurality of mutually spaced gate insulating layers 212 and a plurality of mutually spaced gate layers 211. It can also be understood that a gate layer 211 and a gate insulating layer 212 together form a gate structure pair, and the memory stack structure 210 includes a plurality of repeatedly stacked gate structure pairs.

[0087] The number of gate layer 211 and gate insulating layer 212 can be 4, 16, 32, 64, 128, 256, etc. The thickness of gate layer 211 (i.e., the dimension along the third direction Z) can be approximately equal to or different from the thickness of gate insulating layer 212. For example, the thickness of gate insulating layer 212 is greater than the thickness of gate layer 211.

[0088] Gate layer 211 may include gate conductive layer 2111, which comprises a conductive material, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable materials. In some examples, gate layer 211 comprises a metal layer, such as a tungsten layer. In some examples, gate layer 211 comprises a doped polysilicon layer. Polysilicon can be doped to a desired doping concentration using any suitable dopant to become a conductive material that can be used as a gate layer material.

[0089] like Figure 6 and Figure 7A As shown, in some embodiments, the gate conductive layer 2111 may further include a first adhesive layer 281. The first adhesive layer 281 may cover at least a portion of the surface of the gate conductive layer 2111. The first adhesive layer 281 is configured to improve the adhesion between the gate conductive layer 2111 and other contacting structures, thereby improving the reliability of the semiconductor structure 200 in the three-dimensional memory 10.

[0090] The first adhesive layer 281 may be a conductive material, including but not limited to: metals (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.) and metal compounds (e.g., titanium nitride (TiN)). x ), Tantalum nitride (TaN) x ), Chromium nitride (CrN) x ), Tungsten nitride (WN) x (etc.) and metal alloys (e.g., TiSi) x N y TaSi x N y CrSi x N y WSi x N y At least one of (etc.). In practice, the specific material of the first adhesive layer 281 can be determined based on the material of the gate layer 211 in order to improve the overall conductivity efficiency of the gate layer 211 and the first adhesive layer 281.

[0091] The gate insulating layer 212 may include an insulating material, including but not limited to silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiN2). x O y The dielectric constant of silicon oxynitride is higher than that of silicon oxide. For example, at about 20°C, the dielectric constant of silicon oxynitride is between about 4 and about 7, such as 3.8, 4, 4.8, 5.3, 5.9, 6, 6.36, 6.88, 7, 7.2, etc. In some examples, the gate insulating layer 212 comprises a silicon oxide layer. In some examples, the gate insulating layer 212 comprises a silicon oxynitride layer.

[0092] The thickness of the gate layer 211 (i.e., the dimension along the third direction Z) can be between approximately 10 nm and approximately 50 nm, for example: 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Similarly, the thickness of the gate insulating layer 212 (i.e., the dimension along the third direction Z) can be between approximately 10 nm and approximately 50 nm, for example: 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. The gate layer 211 can be a gate line G surrounding the memory cell string 400 and can extend laterally (i.e., along the first direction X) as a word line WL.

[0093] The second channel structure 220 described above can be located within the aforementioned storage area CA, or it can be located within a portion of the connection area SS. For example... Figure 6 As shown, the second channel structure 220 can penetrate the memory stack structure 210 in a direction perpendicular to the source layer SL (i.e., the third direction Z). That is, the second channel structure 220 penetrates the entire gate layer 211 and the entire gate insulating layer 212. In addition, the second channel structure 220 can stop inside the source layer SL, that is, extend into a portion of the source layer SL to make electrical contact with the source layer.

[0094] The second channel structure 220 can be approximately cylindrical, meaning that the areas of different parts of the second channel structure 220 in the direction parallel to the source layer SL (i.e., the XY plane) can be approximately equal. Alternatively, the second channel structure 220 can be a frustum structure, meaning that the areas of different parts of the second channel structure 220 in the direction parallel to the XY plane can be unequal. For example, the area of ​​the part of the second channel structure 220 furthest from the source layer SL in the direction parallel to the XY plane is greater than the area of ​​the part of the second channel structure 220 closest to the source layer SL in the direction parallel to the XY plane.

[0095] In some embodiments, the second trench structure 220 may include a trench layer 221 and a storage function layer 222 located outside the trench layer 221. The storage function layer 222 may include a tunneling layer 223, a storage layer 224 and a barrier layer 225 arranged sequentially in a direction away from the trench layer 221.

[0096] The aforementioned channel layer 221 is made of a semiconductor material. Semiconductor materials include, but are not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The movement or cessation of charge carriers (electrons or holes) within the channel layer 221 can be controlled by the voltage supplied through the gate line G.

[0097] The storage layer 222 is located outside the channel layer 221 and partially surrounds the channel layer 221. Carriers in the channel layer 221 can tunnel through the tunneling layer 223 to the storage layer 224, which is configured to store carriers. The barrier layer 225 is configured to prevent carrier overflow.

[0098] The material of the tunneling layer 223 may be, but is not limited to, one or more combinations of silicon oxide and silicon oxynitride. In some examples, the tunneling layer 223 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the tunneling layer 223 may be a composite dielectric layer, such as a stacked structure of a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon oxide layer.

[0099] The material of the barrier layer 225 may include one or more combinations of silicon oxide, silicon nitride, and high dielectric constant materials. In some examples, the barrier layer 225 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the barrier layer 225 may be a composite dielectric layer, such as a stacked structure of a silicon nitride layer and an aluminum oxide layer.

[0100] The aforementioned storage layer 224 includes a plurality of barrier portions 2241 and a plurality of storage portions 2242 separated by the barrier portions 2241. The storage portions 2242 are configured to store charge carriers, while the barrier portions 2241 do not store charge carriers. The material of the storage portions 2242 may include silicon nitride, or other suitable materials, which are not limited herein.

[0101] like Figure 6 and Figure 7A As shown, multiple barrier portions 2241 and multiple storage portions 2242 are arranged alternately along a third direction Z. The storage portions 2242 can be disposed opposite to the gate layer 211 along a direction parallel to the source layer SL (e.g., the first direction X). Similarly, the barrier portions 2241 can be disposed opposite to the gate insulating layer 212 along a direction parallel to the source layer SL.

[0102] It is understood that the storage unit 2242 is disposed opposite to the gate layer 211, meaning that the orthographic projection of the storage unit 2242 caused by light parallel to the first direction X is at least partially located on the gate layer 211. Similarly, the blocking unit 2241 is disposed opposite to the gate insulating layer 212, and the orthographic projection of the blocking unit 2241 caused by light parallel to the first direction X is at least partially located on the gate insulating layer 212.

[0103] In some examples, the size of the storage section 2242 in the third direction Z can be smaller than the size of the gate layer 211 in the third direction Z. The size of the barrier section 2241 in the third direction Z can be larger than the size of the gate insulating layer 212 in the third direction Z.

[0104] In some examples, the size of the storage section 2242 in the third direction Z can be approximately equal to the size of the gate layer 211 in the third direction Z. The size of the barrier section 2241 in the third direction Z can be approximately equal to the size of the gate insulating layer 212 in the third direction Z.

[0105] In some examples, the size of the storage section 2242 in the third direction Z can be larger than the size of the gate layer 211 in the third direction Z. The size of the barrier section 2241 in the third direction Z can be smaller than the size of the gate insulating layer 212 in the third direction Z.

[0106] It should be noted that due to errors in the actual fabrication process, the dimensions of the multiple barrier portions 2241 in the third direction Z may differ. Similarly, the dimensions of the multiple memory portions 2242 in the third direction Z may also differ. Thus, the semiconductor structure 200 may exhibit one or more combinations of the above three scenarios, which are not limited here.

[0107] In some embodiments, the size of the barrier portion 2241 in the third direction Z and the size of the storage portion 2242 in the third direction Z may be equal or unequal. For example, the size of the barrier portion 2241 in the third direction Z is greater than the size of the storage portion 2242 in the third direction Z; another example is that the size of the barrier portion 2241 in the third direction Z is approximately equal to the size of the storage portion 2242 in the third direction Z; yet another example is that the size of the barrier portion 2241 in the third direction Z is smaller than the size of the storage portion 2242 in the third direction Z.

[0108] like Figure 6 As shown, in some embodiments, the semiconductor structure 200 of the three-dimensional memory 10 further includes a fourth protective layer 240. The fourth protective layer 240 may be located between the second channel structure 220 and the memory stack structure 210.

[0109] The fourth protective layer 240 may include a third break 243 (occupied by the gate layer 211 in the figure) and a protective portion 244. The first break 243 penetrates the fourth protective layer 240, and multiple third breaks 243 separate multiple protective portions 244, such that the multiple protective portions 244 are spaced apart from each other.

[0110] The material of the protective section 244 may include carbon-doped silicon nitride, or other suitable materials, which are not limited here. Specifically, the carbon-doped silicon nitride exhibits a high etching ratio with silicon nitride, and also a high etching ratio with silicon oxide. That is, when etching silicon nitride and silicon oxide, using carbon-doped silicon nitride can reduce or even prevent the effects of etching, thereby providing protection.

[0111] like Figure 6 As shown, the third break 243 is disposed opposite to the gate layer 211 in the first direction X. The size of the third break 243 in the third direction Z can be equal to the size of the gate layer 211 in the third direction Z.

[0112] In some examples, the dimension of the third break 243 in the third direction Z is smaller than the dimension of the gate layer 211 in the third direction Z. In some examples, the dimension of the third break 243 in the third direction Z is approximately equal to the dimension of the gate layer 211 in the third direction Z.

[0113] In some embodiments, the side of the protection portion 244 near the second channel structure 220 can directly contact the barrier layer 225, and the side of the protection portion 244 away from the second channel structure 220 can directly contact the gate insulating layer 212.

[0114] like Figure 6 As shown, the protection portion 244 is disposed opposite to the gate insulating layer 212 in the first direction X. The dimensions of the protection portion 244 in the third direction Z may be equal to or different from the dimensions of the gate insulating layer 212 in the third direction Z.

[0115] In some examples, the dimension of the gate insulating layer 212 in the third direction Z is smaller than the dimension of the protection portion 244 in the third direction Z. In some examples, the dimension of the gate insulating layer 212 in the third direction Z is approximately equal to the dimension of the protection portion 244 in the third direction Z.

[0116] like Figure 6 As shown, in some embodiments, two adjacent protection portions 244 are connected to a gate layer 211 located between the two adjacent protection portions 244. In some examples, the size of the protection portion 244 in the third direction Z is smaller than the size of the gate insulating layer 212 in the third direction Z, that is, a portion of the gate layer 211 extends between the second channel structure 222 and the gate insulating layer 212.

[0117] In some examples, the dimension of the protection portion 244 in the third direction Z is approximately equal to the dimension of the gate insulating layer 212 in the third direction Z. The gate layer 211 extends into the third break 243 and is connected to the two opposing surfaces of the two protection portions 244, as shown. Figure 6 As shown, the surface of the gate layer 211 near the second channel structure 222 protrudes from the surface of the gate insulating layer 212 near the second channel structure 220 and extends into the third break 243.

[0118] The gate layer 211 extends into the third break 243, that is, the orthogonal projection of the gate layer 211 on the source layer SL overlaps with the orthogonal projection of the protection part 244 on the source layer SL.

[0119] like Figure 7A As shown, in some embodiments, the dimension d1 of the end of the storage unit 2242 near the gate layer 211 in the third direction Z is smaller than the dimension d2 of the end of the storage unit 2242 away from the gate layer 211 in the third direction Z. That is, the contact area between the storage unit 2242 and the tunneling layer 223 is larger than the contact area between the storage unit 2242 and the barrier layer 225. This facilitates the movement of charge carriers from the tunneling layer 223 to the storage unit 2242, while increasing the difficulty of leakage from the storage unit 2242 to the barrier layer 225, thereby improving the reliability of the semiconductor structure 200.

[0120] In some examples, the surface where the storage unit 2242 is connected to the barrier unit 2241 can be a plane. For example... Figure 7A As shown, the cross-section of the storage unit 2242 along the third direction Z is a trapezoidal structure. For example, it can be an isosceles trapezoid, a right trapezoid, or other trapezoids; no limitation is made here. In some examples, the surfaces connecting the storage unit 2242 and the barrier unit 2241 are the two side surfaces of the storage unit 2242 along the third direction. The two bases of the trapezoidal structure represent the two surfaces connecting the storage unit 2242 to the barrier unit 225 and the tunneling layer 223; the two sides of the trapezoidal structure represent the two surfaces connecting the storage unit 2242 to two adjacent barrier units 2241.

[0121] In some examples, the surface connecting the storage unit 2242 and the barrier unit 2241 may also be a curved surface, such as an arc surface. In some examples, the different surfaces connecting the storage unit 2242 and the barrier unit 2241 may include both planes and curved surfaces, which is not limited here.

[0122] like Figure 6 As shown, in some embodiments, the second channel structure 220 may further include an insulating material 260. The insulating material 260 is located inside the channel layer 221 and serves a supporting function. The insulating material 260 may include, but is not limited to, one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In some examples, air gaps (not shown) may also be formed inside the insulating material 260. These air gaps can buffer structural stresses generated during the fabrication or use of the semiconductor structure 200, improving the reliability of the semiconductor structure 200.

[0123] In some embodiments, such as Figure 7A As shown, the dimension d3 of the end of the barrier portion 2241 near the gate layer 211 in the length direction of the second channel structure 220 is greater than the dimension d4 of the end of the barrier portion 2241 away from the gate layer 211 in the length direction of the second channel structure 220.

[0124] In some examples, the surface where the barrier 2241 connects to the storage unit 2242 can be a plane. For example... Figure 7A As shown, the cross-section of the barrier portion 2241 is a trapezoidal structure. For example, it can be an isosceles trapezoid, a right trapezoid, or other trapezoids; there is no limitation here.

[0125] In some examples, the surface connecting the barrier portion 2241 and the storage portion 2242 may also be a curved surface, such as an arc surface. In some examples, the different surfaces connecting the barrier portion 2241 and the storage portion 2242 may include both planes and curved surfaces, which is not limited here.

[0126] like Figure 7AAs shown, in some embodiments, a protective portion 244 contacts two adjacent gate layers 211 along the length of the channel structure. For example, the two surfaces of the protective portion 244 in the second direction Y contact two adjacent gate layers 211 respectively.

[0127] In addition, when the gate layer 211 includes the first adhesive layer 281, the protective portion 244 comes into contact with the first adhesive layer 281.

[0128] In some embodiments, such as Figure 6 and Figure 7A As shown, the semiconductor structure 200 also includes a dielectric layer 250. The dielectric layer 250 may be located between the gate layer 211 and the second channel structure 220. The dielectric layer 250 can prevent electron leakage and improve the reliability of the semiconductor structure 200.

[0129] The dielectric layer 250 can be made of a high dielectric constant material. In the semiconductor industry, a high dielectric constant typically means that the dielectric constant k of the material is higher than that of silicon dioxide, i.e., 3.9. The dielectric constant of the dielectric layer 250 can be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, etc. Materials for the dielectric layer 250 include, but are not limited to, alumina (Al₂O₃), hafnium dioxide (HfO₂), tantalum pentoxide (Ta₂O₅), titanium dioxide (TiO₂), and silicon oxynitride (SiO₂). x N y One or more combinations thereof.

[0130] The dielectric layer 250 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, and electroless plating, or a combination of one or more of these processes. In some embodiments, ALD can be used. The dielectric layer 250 formed by the ALD process has the advantages of high uniformity and high precision.

[0131] In some embodiments, the dielectric layer 250 may be a monolithic structure, such as... Figure 6 and Figure 7A As shown. That is, the dielectric layer 250 covers the surface of the memory stack structure 210 near the memory layer 224, or the dielectric layer 250 covers the outer surface of the barrier layer 225. The dielectric layer 250 is disposed opposite to both the gate layer 211 and the gate insulating layer 212 in the first direction X.

[0132] In some embodiments, the dielectric layer 250 may include a second break 251 and a dielectric portion 252. For example... Figure 7B As shown, the second break 251 penetrates the dielectric layer 250, and the multiple second breaks 251 separate the multiple dielectric portions 252, so that the multiple dielectric portions 252 are spaced apart from each other.

[0133] like Figure 7B As shown, the second break 251 is disposed opposite to the gate insulating layer 212 in the first direction X. The size of the second break 251 in the third direction Z can be approximately equal to or unequal to the size of the gate insulating layer 212 in the third direction Z.

[0134] In some examples, the dimension of the second break 251 in the third direction Z is smaller than the dimension of the gate insulating layer 212 in the third direction Z. In some examples, the dimension of the second break 251 in the third direction Z is approximately equal to the dimension of the gate insulating layer 212 in the third direction Z.

[0135] In some embodiments, the side of the dielectric portion 252 near the second channel structure 220 can directly contact the barrier layer 225, and the side of the dielectric portion 252 away from the second channel structure 220 can directly contact the gate layer 211. The dielectric layer 250 can prevent electron leakage and improve the reliability of the semiconductor structure 200.

[0136] The dielectric portion 252 may be disposed opposite to the gate layer 211 in the first direction X. The dimensions of the dielectric portion 252 in the third direction Z may be approximately equal to or unequal to the dimensions of the gate layer 211 in the third direction Z.

[0137] In some examples, the dimension of the gate layer 211 in the third direction Z is smaller than the dimension of the dielectric portion 252 in the third direction Z. In some examples, the dimension of the gate layer 211 in the third direction Z is approximately equal to the dimension of the dielectric portion 252 in the third direction Z.

[0138] The dielectric layer 250 is disposed on the side of the memory stack structure 220 near the second channel structure 210, which can improve the fill rate of the gate layer 211 in the memory stack structure 220 and improve the conductivity of the memory stack structure 220. In addition, the increased fill rate of the gate layer 211 can also facilitate the miniaturization of the gate layer 211, thereby improving the integration density of the semiconductor structure 200.

[0139] like Figure 8As shown, in some embodiments, the semiconductor structure 200 may further include a connection structure 260. The connection structure 260 may be located within the aforementioned connection region SA. The connection structure 260 may be configured to be electrically connected to the gate layer 211 to control electrical signals (e.g., voltage) on the gate line G.

[0140] The connection structure 260 extends from the side of the memory stack structure 210 away from the source layer SL towards the source layer SL, until it penetrates the target gate layer 211'.

[0141] The target gate layer 211' can be any gate layer 211 in the memory stack structure 210. The number of connection structures 260 can be equal to the number of gate layers 211 in the memory stack structure 210. One connection structure 260 is electrically connected to one gate layer 211, and different connection structures 260 are connected to different gate layers 211. It can also be understood that multiple connection structures 260 correspond one-to-one with multiple gate layers 211. The target gate layer 211' is the gate layer 211 that is electrically connected to the connection structure 260.

[0142] Multiple connection structures 260 can be arranged along the first direction X. For example, multiple connection structures 260 may be on the same straight line. Or, multiple connection structures 260 may be on a broken line extending along the first direction X, which is not limited here.

[0143] In some embodiments, the connection structure 260 may include a main portion 261 and an extension portion 262. The extension portion 262 is connected to and disposed at the same layer as the target gate layer 211'. The main portion 261 is connected to the extension portion 262 and extends through the portion of the memory stack structure 210 located on the side of the target gate layer 211' away from the source layer SL.

[0144] The memory stack structure 210 also includes a target gate insulating layer 212'. The target gate insulating layer 212' is a gate insulating layer 212 adjacent to the target gate layer 211' in the third direction Z. One target gate layer 211' corresponds to two target gate insulating layers 212'.

[0145] The extension portion 262 is disposed in the same layer as the target gate layer 211'. It can be considered that the extension portion 262 is located between the two target gate insulating layers 212'. The extension portion 262 has a portion that is opposite to or in contact with the target gate layer 211' in the first direction X.

[0146] The dimension of the extension portion 262 in the third direction Z can be approximately equal to the dimension of the target gate layer 211' in the third direction Z. Furthermore, the dimension of the main body portion 261 in the first direction X can be smaller than the dimension of the extension portion 262 in the first direction X, meaning that the orthographic projection of the main body portion 261 onto the source layer SL is located inside the orthographic projection of the extension portion 262 onto the source layer SL. This facilitates the electrical connection between the extension portion 262 and the target gate layer 211', reducing the difficulty of electrical connection between the connection structure 260 and the target gate layer 211'.

[0147] The material of the connection structure 260 includes a conductive material, such as one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials.

[0148] In some embodiments, the semiconductor structure 200 further includes an isolation layer 280. The isolation layer 280 may surround the outer surface of the body portion 261 in the XY plane, thereby preventing the body portion 261 from being coupled to the gate layer 211 other than the target gate layer 211', avoiding interference from other gate lines G, and improving the reliability of the semiconductor structure 200.

[0149] The isolation layer 280 includes an insulating material, which includes, but is not limited to, one or more combinations of silicon oxide, silicon nitride, carbon-doped silicon nitride, and high dielectric constant insulating materials. In the case where the isolation layer 280 includes carbon-doped silicon nitride, since there is a high etching ratio between the carbon-doped silicon nitride and silicon nitride, and also a high etching ratio between the carbon-doped silicon nitride and silicon oxide, the isolation layer 280 can protect the connection structure 260 when etching silicon nitride and silicon oxide.

[0150] In some embodiments, the semiconductor structure 200 may further include a second adhesive layer 282. The second adhesive layer 282 may cover at least a portion of the surface of the connection structure 260. The second adhesive layer 282 is configured to improve the adhesion between the connection structure 260 and the gate layer 211, thereby improving the reliability of the semiconductor structure 200.

[0151] The second adhesive layer 282 may be a conductive material, including but not limited to: metals (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), metal compounds (e.g., titanium nitride (TiN)). x ), Tantalum nitride (TaN) x ), Chromium nitride (CrN) x ), Tungsten nitride (WN) x (etc.) and metal alloys (e.g., TiSi) x N y TaSi x N y CrSix N y WSi x N y At least one of (etc.). In practice, the specific material of the second adhesive layer 282 can be determined based on the material of the connecting structure 260 to improve the overall conductivity of the connecting structure 260 and the second adhesive layer 282.

[0152] In some examples, the second adhesive layer 282 may be located between the main body portion 261 and the isolation layer 280, thereby improving the structural tightness between the main body portion 261 and the isolation layer 280.

[0153] In some examples, the second adhesive layer 282 may be located on the outer surface of the extension 262, thereby improving the connection strength between the extension 262 and the target gate layer 211' and improving the connection reliability between the connection structure and the target gate layer 211'.

[0154] like Figure 8 As shown, in some embodiments, the semiconductor structure 200 further includes a third protective layer 270. The third protective layer 270 is located between the extension 262 and the target gate insulating layer 212'. The material of the third protective layer 270 can be an insulating material, such as silicon oxide, silicon oxynitride, or other suitable materials.

[0155] In some examples, the third protective layer 270 may be located on the surface of the extension 262 near the source layer SL, between it and the target gate insulating layer 212' below the extension 262. In cases where the semiconductor structure 200 includes a second adhesive layer 282, the second adhesive layer 282 may be in direct contact with the third protective layer 270.

[0156] In some examples, the third protective layer 270 may be located on the surface of the extension 262 away from the source layer SL, between it and the target gate insulating layer 212' above the extension 262. In cases where the semiconductor structure 200 includes a second adhesive layer 282, the second adhesive layer 282 may be in direct contact with the third protective layer 270.

[0157] In summary, the semiconductor structure 200 provided in this embodiment can form multiple storage units 2242 inside the channel hole. This can improve the performance of the semiconductor structure 200 without increasing the size of the second channel structure 220, thus facilitating the increase of the density of the second channel structure 220 in the semiconductor structure 200 and improving the storage performance of the three-dimensional memory 10.

[0158] This disclosure provides a method for fabricating a semiconductor structure through several embodiments. Please refer to [link to relevant documentation]. Figures 9A to 9Z' ,as well as Figures 10-25 ;in, Figures 9A to 9Z'These are partial structural diagrams of a semiconductor structure at different fabrication stages according to some embodiments. Figures 10-25 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. The method for fabricating this semiconductor structure, such as... Figure 10 As shown, it includes steps S1 to S8.

[0159] Step S1: A dielectric stack structure 310 is formed on the substrate 300. The dielectric stack structure 310 includes an alternately stacked first sacrificial layer 312 and a second sacrificial layer 311.

[0160] like Figure 9A and Figure 10 As shown, a substrate 300 is provided, and a dielectric stack structure 310 is formed on top of the substrate 300 (i.e., in the third direction Z). The substrate 300 may include silicon (e.g., monocrystalline silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and / or any other suitable material. In some examples, the substrate 300 includes silicon, such as monocrystalline silicon or polycrystalline silicon.

[0161] The aforementioned dielectric stack structure 310 includes a plurality of first sacrificial layers 312 and a plurality of second sacrificial layers 311 alternately stacked along the third direction Z, such as Figure 9A As shown. It can also be understood that an adjacent first sacrificial layer 312 and a second sacrificial layer 311 form a dielectric sacrificial pair, and the dielectric stack structure 320 includes multiple dielectric sacrificial pairs repeatedly stacked along the third direction Z.

[0162] The number of layers in the first sacrificial layer 312 and the second sacrificial layer 311 can be 8, 16, 32, 64, etc., or other suitable numbers.

[0163] The materials of the first sacrificial layer 312 and the second sacrificial layer 311 are different, and under the same process conditions, the etching rate of the first sacrificial layer 312 is different from that of the second sacrificial layer 312. In some examples, the first sacrificial layer 312 includes a nitride sacrificial layer (e.g., silicon nitride), and the second sacrificial layer 311 includes an oxide sacrificial layer (e.g., silicon oxide).

[0164] like Figure 9J As shown, in some embodiments, the dielectric stack structure 310 includes a storage region CA and a connection region SS. The storage region CA and the connection region SS are arranged along a first direction X. The area of ​​the storage region CA in the XY plane may be larger than the area of ​​the connection region SS in the XY plane.

[0165] Step S2: Form a first channel structure 320 through the dielectric stack structure 310, the first channel structure 320 including a storage layer 224.

[0166] like Figure 9E As shown, a first channel structure 320 is formed within the substrate 300 and the dielectric stack structure 310. The first channel structure 320 can penetrate the dielectric stack layer 310 and extend into a portion of the substrate 300.

[0167] In some examples, the first channel structure 320 can be approximately cylindrical, meaning that the areas of different portions of the first channel structure 320 in the direction parallel to the substrate 300 (i.e., the XY plane) are approximately equal. The first channel structure 320 can also be a frustum structure, meaning that the areas of different portions of the first channel structure 320 in the plane parallel to the XY direction are not equal. For example, the area of ​​the portion of the first channel structure 320 furthest from the substrate 300 in the plane parallel to the XY direction is greater than the area of ​​the portion of the first channel structure 320 closest to the substrate 300 in the plane parallel to the XY direction.

[0168] like Figure 9B As shown, step S2 may include forming a channel via CH on the dielectric stack structure 310. The channel via CH may be formed within the storage region CA or within a portion of the connection region SS.

[0169] The via CH can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the dielectric stack structure 310. The patterned photoresist layer can expose the portion of the dielectric stack structure 310 used to form the via CH. A suitable etching process can be performed to remove the portion of the dielectric stack structure 310 used to form the via CH. For example, the etching process can include a dry etching process.

[0170] Storage layer 224 can be formed inside the channel hole CH.

[0171] like Figure 9E As shown, in some embodiments, the first channel structure 320 may further include a channel layer 221, a tunneling layer 223, and a barrier layer 225. The storage layer 224 may be located between the tunneling layer 223 and the barrier layer 225. The channel layer 221 is located on the side of the barrier layer 225 away from the storage layer 224.

[0172] In some examples, a barrier layer 225, a storage layer 224, and a tunneling layer 223 may be sequentially formed along the inner wall of the channel hole CH. For example, using one or more thin film deposition processes, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD), a dielectric layer such as a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer may be sequentially deposited along the inner wall of the channel hole CH to form the barrier layer 225, the storage layer 224, and the tunneling layer 223.

[0173] In some examples, a conformal coating process (such as ALD) can be used to deposit any of the barrier layer 225, storage layer 224, tunneling layer 223, and channel layer 211, such that the film formed by any of the barrier layer 225, storage layer 224, tunneling layer 223, and channel layer 211 can have a uniform thickness. In some examples, the thickness of the channel layer 211 can be controlled to be between approximately 10 nm and approximately 15 nm by controlling the deposition rate and / or time, for example, 9.8 nm, 10 nm, 11 nm, 12.2 nm, 13.5 nm, 14 nm, 14.6 nm, 15 nm, or 15.3 nm.

[0174] After the barrier layer 225, the storage layer 224 and the tunneling layer 223 are prepared, a layer of semiconductor material (such as polysilicon) can be deposited on the inner wall of silicon oxide (tunneling layer 223) using one or more thin film deposition processes including but not limited to PVD, CVD and ALD, thereby forming the channel layer 221.

[0175] The specific structure and materials of the barrier layer 225 can be referred to the specific structure and materials of the barrier layer 225 described above; the specific structure and materials of the storage layer 224 can be referred to the specific structure and materials of the storage layer 224 described above; the specific structure and materials of the tunneling layer 223 can be referred to the specific structure and materials of the tunneling layer 223 described above; the specific structure and materials of the trench layer 221 can be referred to the specific structure and materials of the trench layer 221 described above; they will not be described in detail here.

[0176] Step S3: Form a gate spacer GL that runs through the dielectric stack structure 310.

[0177] like Figure 9J As shown, the gate spacer GL extends through the dielectric stack structure 310 in the first direction X. Multiple gate spacers GL can be arranged in parallel at intervals in the second direction Y.

[0178] The gate spacer GL extends through the dielectric stack structure 310. The gate spacer GL can extend into a portion of the substrate 300, with the bottom end of the substrate 300 exposed.

[0179] The gate spacer GL can be formed by any suitable fabrication process. For example, a patterned photoresist layer can be formed over the dielectric stack structure 310. The patterned photoresist layer can expose the portion of the dielectric stack structure 310 used to form the gate spacer GL. A suitable etching process can be performed to remove the portion of the dielectric stack structure 310 used to form the gate spacer GL. The etching process can include a dry etching process.

[0180] After the gate spacer GL is formed, the first sacrificial layer 312 and the second sacrificial layer 311 in the dielectric stack structure 310 will be exposed in the gate spacer GL.

[0181] Step S4: Remove the first sacrificial layer 312 via the gate spacer GL to form the first gap G1, as shown. Figures 9J to 9L As shown.

[0182] Combination Figure 9J and Figure 9K As shown, the first sacrificial layer 312 exposed within the gate spacer GL can be removed by an etching process (e.g., wet etching process) via the gate spacer GL.

[0183] In some examples, by selecting an etchant corresponding to the material of the first sacrificial layer 312, the etching rate of the first sacrificial layer 312 is greater than the etching rate of the second sacrificial layer 311 under the etching conditions created by the etchant. During the removal of the first sacrificial layer 312, a slight amount of the second sacrificial layer 311 may be removed, or all of the second sacrificial layer 311 may be retained.

[0184] like Figure 9K and Figure 9L As shown, after removing the first sacrificial layer 312, a first gap G1 is formed. The first gap G1 is the space where the first sacrificial layer 312 was originally located before it was removed, and the first gap G1 is located between two adjacent second sacrificial layers 311.

[0185] The first gap G1 can be connected to the channel hole CH in the first direction X.

[0186] like Figure 9K As shown, in some examples, the first sacrificial layer 312 within the storage area CA is removed, forming a plurality of first gaps G1 around the first channel structure 320.

[0187] like Figure 9L As shown, in some examples, the first sacrificial layer 312 within the connection region SS is removed, forming a plurality of first gaps G1 between the connection structures 260.

[0188] Step S5: Modify the target portion Q1 of the storage layer 224 via the first gap G1 to form a barrier portion 2241. The target portion Q1 of the storage layer 224 is a portion of the storage layer 224, and the target portion Q1 includes at least a portion of the storage layer 224 opposite to the first gap G1 along a direction parallel to the substrate 300.

[0189] like Figure 9K As shown, in some examples, the size of the target portion Q1 of storage layer 224 in the third direction Z can be smaller than the size of the first gap G1 in the third direction Z. In some examples, the size of the target portion Q1 of storage layer 224 in the third direction Z can be approximately equal to the size of the first gap G1 in the third direction Z. In some examples, the size of the target portion Q1 of storage layer 224 in the third direction Z can be larger than the size of the first gap G1 in the third direction Z.

[0190] The modification process is applied only to the target portion Q1 of the storage layer 224, which forms a barrier portion 2241. The unmodified portions of the storage layer 224 form storage portions 2242. One barrier portion 2241 separates two adjacent storage portions 2242.

[0191] The modification treatment can be an oxidation process or other suitable process that alters the properties of the object. The modified object can then block the flow of charge carriers. By modifying the target portion Q1 of the storage layer 224, the barrier portion 2241 can block the flow of charge carriers between two adjacent storage portions 2242.

[0192] By modifying the target portion Q1 of the storage layer 224 using the first gap G1 before the gate layer 211 and the gate insulating layer 212 are formed, the influence of the modification process on the gate layer 211 and the gate insulating layer 212 can be avoided, thereby improving the fabrication yield of the semiconductor structure 200.

[0193] In addition, by fabricating multiple storage units 2242 through the first gap G1, all storage units 2242 can be located inside the channel hole CH, without increasing the critical dimensions of the second channel structure 220, which facilitates improving the integration density between the second channel structures 220.

[0194] like Figure 9MAs shown, in some embodiments, the size of the barrier portion 2241 in the third direction Z may be equal to or unequal to the size of the storage portion 2242 in the third direction Z. For example, the size of the barrier portion 2241 in the third direction Z may be larger than the size of the storage portion 2242 in the third direction Z; another example is that the size of the barrier portion 2241 in the third direction Z may be approximately equal to the size of the storage portion 2242 in the third direction Z; yet another example is that the size of the barrier portion 2241 in the third direction Z may be smaller than the size of the storage portion 2242 in the third direction Z.

[0195] In some embodiments, please combine Figure 7A As shown, the dimension d3 of the end of the blocking part 2241 near the first gap G1 in the third direction Z is greater than the dimension d4 of the end of the blocking part 2241 away from the first gap G1 in the third direction Z.

[0196] In some examples, the surface connecting the barrier portion 2241 and the storage portion 2242 can be a plane. The cross-sections of both the barrier portion 2241 and the storage portion 2242 are trapezoidal structures, which can be isosceles trapezoids, right trapezoids, or other trapezoids; no limitation is made here. In some examples, the surfaces connecting the storage portion 2242 and the barrier portion 2241 are the two side surfaces of the storage portion 2242 in the third direction. Specifically, the two bases of the trapezoidal structure represent the two surfaces connecting the storage portion 2242 to the blocking portion 225 and the tunneling layer 223; the two sides of the trapezoidal structure represent the two surfaces connecting the storage portion 2242 to two adjacent barrier portions 2241.

[0197] In some examples, the surface connecting the barrier portion 2241 and the storage portion 2242 may also be a curved surface, such as an arc surface. In some examples, the different surfaces connecting the barrier portion 2241 and the storage portion 2242 may include both planes and curved surfaces, which is not limited here.

[0198] In some embodiments, please combine Figure 7A As shown, the dimension d1 of the end of the storage unit 2242 near the first gap G1 in the third direction Z is smaller than the dimension d2 of the end of the storage unit 2242 away from the first gap G1 in the third direction Z. That is, the contact area between the storage unit 2242 and the tunneling layer 223 is larger than the contact area between the storage unit 2242 and the barrier layer 225. This facilitates the movement of charge carriers from the tunneling layer 223 to the storage unit 2242, while increasing the difficulty of leakage from the storage unit 2242 to the barrier layer 225, thereby improving the reliability of the semiconductor structure 200.

[0199] After step S5, the first channel structure 320 is transformed into the second channel structure 220.

[0200] Step S6: Form a gate insulating layer 212 within the first gap G1.

[0201] In some embodiments, an insulating material can be deposited on the inner wall of the first gap G1 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a gate insulating layer 212, such as... Figure 9O As shown.

[0202] The insulating material includes, but is not limited to, one or more combinations of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNxOy), and high dielectric constant insulating materials, or other suitable materials.

[0203] It should be noted that the inner wall of the first gap G1 includes the surfaces of the two second sacrificial layers 311 adjacent to the first gap G1 and the surface of the second channel structure 220 facing the first gap G1.

[0204] Step S7: Remove at least a portion of the second sacrificial layer 311 via the gate spacer GL to form a second gap G2, as shown. Figure 9R and Figure 9W As shown.

[0205] The second sacrificial layer 311 exposed within the gate spacer GL can be removed by an etching process (e.g., wet etching) via the gate spacer GL.

[0206] In some examples, by selecting an etchant corresponding to the material of the second sacrificial layer 311, the etching rate of the second sacrificial layer 311 is greater than the etching rate of the gate insulating layer 212 under the etching conditions created by the etchant. During the removal of the second sacrificial layer 311, a small portion of the gate insulating layer 212 may be removed, or all of the gate insulating layer 212 may be retained.

[0207] After removing the second sacrificial layer 311, a second gap G2 is formed, as follows: Figure 9R As shown. The second gap G2 is the space where at least part of the second sacrificial layer 311 was originally located before it was removed, and the second gap G2 is located between two adjacent gate insulating layers 212.

[0208] In some examples, the second gap G2 may be connected to the channel hole CH in the first direction X.

[0209] like Figure 9U As shown, in some embodiments, the second sacrificial layer 311 is distributed in the storage area CA and the connection area SS. Specifically, the removal of at least a portion of the second sacrificial layer 311 in step S7 includes the portion of the second sacrificial layer 311 located in the storage area CA. In other embodiments, the second sacrificial layer 311 may be distributed in the storage area CA, but may also include a portion of the connection area SS; this is not limited here.

[0210] Step S8: Form a gate layer 211 within the second gap G2, as follows Figure 9Z As shown.

[0211] In some embodiments, a conductive material can be deposited on the inner wall of the second gap G2 using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD, to form a gate layer 211. The conductive material includes, but is not limited to, one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, and may also be other suitable materials.

[0212] It should be noted that the inner wall of the second gap G2 includes the surfaces of the two gate insulating layers 212 adjacent to the second gap G2 and the surface of the second channel structure 220 facing the second gap G2.

[0213] In some examples, during the deposition of conductive material to form gate layer 211, the conductive material can cover the sidewalls of the gate trench GL and the surface of the stacked structure, such as Figure 9Y As shown. By removing the conductive material from the portion other than the second gap G2, a gate layer 211 is formed within the second gap G2, as shown. Figure 9Z As shown.

[0214] By forming a gate insulating layer 212 in the first gap G1 to replace the first sacrificial layer 312, and forming a gate layer 211 in the second gap G2 to replace the second sacrificial layer 311, the dielectric stack structure 320 is replaced by a storage stack structure 220.

[0215] The removal of the first sacrificial layer 312 using the gate trench GL and the removal of the second sacrificial layer 311 using the gate trench GL both utilize the characteristic that the first sacrificial layer 312 and the second sacrificial layer 311 have a large exposed area in the gate trench GL, which can increase the initial etching area and improve the etching efficiency.

[0216] Similarly, forming a gate insulating layer 212 in the first gap G1 using a gate spacer GL and forming a gate layer 211 in the second gap G2 using a gate spacer GL both take advantage of the large exposed area of ​​the first gap G1 and the second gap G2 in the gate spacer GL, which can increase the deposition area and improve the deposition efficiency.

[0217] Furthermore, in some embodiments, the gate layer is prepared first, followed by the gate insulating layer. Since the gate layer itself has high structural stress, the subsequent preparation of the gate insulating layer is affected by this stress, reducing preparation efficiency and yield. In the semiconductor structure preparation method of this disclosure, the gate insulating layer 212 is prepared first, followed by the gate layer 211. This avoids the structural stress of the gate layer itself affecting the preparation of the gate insulating layer, thereby improving the preparation efficiency and yield of the semiconductor structure 200.

[0218] In some embodiments, step S8 may include forming a first adhesive layer 281 within the second gap G2; and forming a gate conductive layer 2111 within the first adhesive layer 281 in the second gap G2.

[0219] For example, an adhesive material can be deposited on the inner wall of the first gap G1 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a first adhesive layer 281. The adhesive material has been described in detail previously and will not be repeated here.

[0220] The first adhesive layer 281 may cover at least a portion of the surface of the gate conductive layer 2111, such as Figure 9Y As shown. The first adhesive layer 281 is configured to improve the adhesion between the gate conductive layer 2111 and other contact structures, thereby improving the reliability of the semiconductor structure 200.

[0221] In summary, the semiconductor structure fabrication method provided in this disclosure modifies the memory layer 224 within the first channel structure 310 by first removing the first sacrificial layer 312 to form a first gap G1, thereby obtaining multiple memory cells 2242; subsequently, a gate insulating layer 212 and a gate layer 211 are formed. This avoids affecting the gate insulating layer 212 and the gate layer 211 during the modification process, thus improving the semiconductor structure fabrication yield.

[0222] Furthermore, the storage layer 224 inside the channel hole CH is modified through the first gap G1 to form multiple storage units 2242 located inside the channel hole CH. This not only improves the performance of the semiconductor structure but also facilitates the increase in the density of the second channel structure 220 in the semiconductor structure.

[0223] like Figure 11 As shown, in some embodiments, step S9 may be included before step S6.

[0224] Step S9: Form a first protective layer 331 on the inner wall of the first gap G1.

[0225] The first protective layer 331 can be formed by depositing a protective material on the inner wall of the first gap G1 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The protective material can be carbon-doped silicon nitride or other suitable materials, which are not limited here.

[0226] like Figure 9PAs shown, the first protective layer 331 may be deposited on the inner wall of the first gap G1 via a gate spacer GL. For example, while forming the first protective layer 331, a protective material is also deposited covering the gate spacer GL. The portion of the first protective layer 331 located in the first gap G1 forms a receiving cavity with an opening.

[0227] like Figure 9P As shown, in step S6, a gate insulating layer 212 is formed in the cavity through the opening of the cavity.

[0228] And, as Figure 9Q and Figure 12 As shown, step S6 may be followed by step S10.

[0229] Step S10: A second protective layer 332 is formed in the gate spacer GL. The second protective layer 332 covers the side of the gate insulating layer 212 exposed in the gate spacer GL, and the second protective layer 332 is connected to the first protective layer 331 to surround the gate insulating layer 212.

[0230] The second protective layer 332 can be formed by depositing a protective material on the side of the gate insulating layer 212 exposed within the gate trench GL using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The protective material can be carbon-doped silicon nitride or other suitable materials, which are not limited here.

[0231] like Figure 9Q As shown, the second protective layer 332 may be a side of the gate insulating layer 212 exposed within the gate spacer GL, deposited via the gate spacer GL. For example, while forming the second protective layer 332, a protective material is also deposited covering the gate spacer GL.

[0232] The first protective layer 331 is connected to the second protective layer 332, which closes the opening of the receiving cavity, thereby surrounding the gate insulating layer 212 and forming a protective film 230 surrounding the gate insulating layer 212.

[0233] Under the same process conditions, the etching rate of the protective film 230 is lower than that of the gate insulating layer 212. By surrounding the gate insulating layer 212 with the protective film 230, the gate insulating layer 212 can be prevented from being exposed and protected from being removed by subsequent etching processes.

[0234] In some embodiments, the materials of the first protective layer 331 and the second protective layer 332 are the same, such as carbon-doped silicon nitride, or they can both be other suitable materials, which are not limited here.

[0235] like Figure 12As shown, in some embodiments, step S11 may be included before step S10.

[0236] Step S11: Remove the end of the gate insulating layer 212 near the gate spacer GL, so that the side of the gate insulating layer 212 is recessed relative to the side of the first protective layer 331, forming a groove 212', as shown. Figure 9P As shown.

[0237] Thus, the bottom of the groove 212' is the side of the gate insulating layer 212 near the gate spacer GL, and the opening of the groove 212' is formed by the side of the first protective layer 331 on both sides near the gate spacer GL.

[0238] The second protective layer 332 formed in the subsequent step S10 includes a portion located in the groove 212', which can cover the side of the gate insulating layer 212 near the gate spacer GL and is connected to the first protective layer 331.

[0239] By removing the end of the gate insulating layer 212 near the gate spacer GL to form a groove to accommodate the second protective layer 332, it is beneficial to achieve the connection between the first protective layer 331 and the second protective layer 332 to jointly surround the gate insulating layer 212, thus protecting the gate insulating layer 212 from being removed by subsequent etching processes. Furthermore, making the side of the second protective layer 332 near the gate spacer GL flush with the side of the first protective layer 331 near the gate spacer GL facilitates subsequent deposition processes and improves the fabrication yield of the semiconductor structure 200.

[0240] In some embodiments, under the same process conditions, the etching rate of the first protective layer 331 is less than the etching rate of the gate insulating layer 212. For example... Figure 13 As shown, step S11 can be: using an etching process to remove the end of the gate insulating layer 212 near the gate spacer GL. The end of the gate insulating layer 212 near the gate spacer GL can be removed via the gate spacer GL using an etching process. For example, using a wet etching process, the etching length (length in the first direction X) of the end of the gate insulating layer 212 near the gate spacer GL can be adjusted by controlling the etching time, i.e., the depth of the groove 212' formed.

[0241] The end of the gate insulating layer 212 near the gate trench GL is removed by etching, which is a simple process and allows for easy control of the depth of the trench 212'.

[0242] like Figure 14 As shown, in some embodiments, step S10 may include steps S101 and S102.

[0243] Step S101: Form a second protective film, which fills the groove 212' and covers the inner wall of the gate spacer GL.

[0244] The second protective film can be formed by depositing a protective material on the inner wall of the gate separator GL using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The protective material fills the groove 212' located on the sidewall of the gate separator GL. The protective material can be carbon-doped silicon nitride, or other suitable materials, and is not limited here.

[0245] In some examples, the second protective film covers the side of the second sacrificial layer 311 near the gate spacer GL, the side of the first protective layer 331 near the gate spacer GL, the side of the gate insulating layer 212 near the gate spacer GL, and the surface of the substrate 300 exposed to the gate spacer GL.

[0246] Step S102: Etch the second protective film, retaining the portion of the second protective film located within the groove 212' as the second protective layer 332, as shown. Figure 9Q As shown.

[0247] The portion of the second protective film outside the groove 212' is removed by an etching process, while the portion inside the groove 212' is retained, forming the second protective layer 332. The etching process can be either a dry etching process or a wet etching process.

[0248] like Figure 15 As shown, in some embodiments, steps S12 to S14 are included before step S3.

[0249] Step S12: Form a connection hole SH. The connection hole SH extends from the side of the dielectric stack structure 310 away from the substrate 300 to the target second sacrificial layer 311', and exposes the target first sacrificial layer 312'. The target first sacrificial layer 312' is adjacent to the target second sacrificial layer 311'.

[0250] like Figure 9H As shown, the connecting hole SH penetrates the target second sacrificial layer 311' and the dielectric stack structure 310 (first sacrificial layer 312 and second sacrificial layer 311) on the side of the target second sacrificial layer 311' away from the substrate 300.

[0251] It should be noted that the target second sacrificial layer 311' can be any second sacrificial layer 311 in the dielectric stack structure 310. The number of connection holes SH can be equal to the number of second sacrificial layers 311 in the dielectric stack structure 310. One connection hole SH penetrates to one target second sacrificial layer 311', and different connection holes SH penetrate to different target second sacrificial layers 311'; it can be understood that multiple connection holes SH correspond one-to-one with multiple target second sacrificial layers 311'. The target second sacrificial layer 311' corresponds to the second sacrificial layer 311 that is finally penetrated during the formation of the connection hole SH.

[0252] The way in which the connecting hole SH penetrates the first sacrificial layer 312 and the second sacrificial layer 311 can be, but is not limited to, one or more combinations of dry etching process and wet etching process, or other suitable hole forming process, which is not limited here.

[0253] like Figure 9J As shown, the multiple connecting holes SH can be arranged along the first direction X. For example, the multiple connecting holes SH are on the same straight line; or, for another example, the multiple connecting holes SH are on a broken line extending along the first direction X, which is not limited here.

[0254] like Figure 9H As shown, the target first sacrificial layer 312' consists of two first sacrificial layers 312 adjacent to the target second sacrificial layer 311' in the third direction Z. A portion of the surface of the target first sacrificial layer 312' is exposed within the connection hole SH.

[0255] Step S13: Surface treatment is performed on the exposed surface of the first sacrificial layer 312' of the target through the connection hole SH to form the third protective layer 270.

[0256] like Figure 9H As shown, the surface of the target first sacrificial layer 312' exposed within the connecting hole SH can be surface-treated via the interior of the connecting hole SH to change the properties of the exposed surface and form a third protective layer 270. In some examples, the surface of the target first sacrificial layer 312' exposed within the connecting hole SH is exposed within the extension portion SH2 of the connecting hole SH.

[0257] In some embodiments, the surface treatment may be to increase the etching ratio of the exposed surface to the target first sacrificial layer 312'. For example, under the same process conditions, the etching rate of the third protective layer 270 is less than the etching rate of the target first sacrificial layer 312'.

[0258] In some embodiments, the material of the target first sacrificial layer 312' includes a non-oxide, such as silicon nitride. Surface treatment may include an oxidation process, i.e., oxidizing the nitride surface of the target first sacrificial layer 312' to an oxide surface.

[0259] In some embodiments, the third protective layer 270 may be connected to the surface of the target second sacrificial layer 311' exposed to the connection hole SH, forming an integral structure surrounding the extension portion SH2 of the connection hole SH, thereby protecting the connection structure 260 subsequently formed in the connection hole SH from being separated from the subsequently formed first gap G1, preventing subsequent modification processes through the first gap G1 from altering the properties of the connection structure 260, and improving the reliability of the semiconductor structure in the three-dimensional memory.

[0260] Step S14: Form a connection structure 260 within the connection hole SH, such as... Figure 9I As shown.

[0261] The connection structure 260 can be formed by depositing conductive material within the connection hole SH using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The conductive material includes, but is not limited to, one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, and may also be other suitable materials.

[0262] The third protective layer 270 is located between the connecting structure 260 and the target first sacrificial layer 312'.

[0263] In some embodiments, prior to step S14, a second adhesive layer 282 may be formed within the connection hole SH. For example, the second adhesive layer 282 can be formed by depositing an adhesive material on the inner wall of the connection hole SH using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The adhesive material has been described in detail previously and will not be repeated here.

[0264] Step S14 can be understood as: forming a connection structure 260 within the second adhesive layer 282 in the connection hole SH, such as... Figure 9I As shown. The second adhesive layer 282 may cover at least a portion of the surface of the connection structure 260. The second adhesive layer 282 is configured to improve the adhesion between the connection structure 260 and other contacting structures, thereby improving the reliability of the semiconductor structure 200.

[0265] In some embodiments, after the connection structure 260 is formed, the surface of the connection structure 260 can be planarized by chemical mechanical polishing (CMP). For example, the upper surface of the connection structure 260 can be made flush with the upper surface of the dielectric stack structure 310.

[0266] In some embodiments, after the connection structure 260 is formed, a protective material may be deposited in the connection region SS. In some examples, the protective material may also cover the storage region CA. For example, a protective layer may cover both the connection structure 260 and the first channel structure 310.

[0267] The modification of the storage layer 224 of the first channel structure 310 in step S5 occurs within the storage area CA and will not affect the connection structure of the connection area SS. Therefore, the connection structure 260 can be formed in the connection area SS before step S5.

[0268] like Figure 16 As shown, in some embodiments, step S12 may include steps S121 to S124.

[0269] Step S121: Form the main body portion SH1 of the connection hole SH. The main body portion SH1 of the connection hole SH extends from the side of the dielectric stack structure 310 away from the substrate 300 to the target second sacrificial layer 311'.

[0270] In this embodiment, the connecting hole SH is completed through a two-stage hole forming process.

[0271] The first hole formation process may include, but is not limited to, one or more combinations of dry etching process and wet etching process, or other suitable hole formation process, which is not limited here.

[0272] like Figure 9F As shown, the main body SH1 formed by the first hole formation process penetrates the dielectric stack structure 310 (first sacrificial layer 312 and second sacrificial layer 311) on the side of the target second sacrificial layer 311' away from the substrate 300, as well as part of the target second sacrificial layer 311'.

[0273] In some other embodiments, step S121 may not remove part of the target second sacrificial layer 311', that is, only the target second sacrificial layer 311' is exposed.

[0274] That is, at the bottom of the main body SH1, the second sacrificial layer 311, which was not removed in the first hole forming process, is exposed.

[0275] Step S122: Form an isolation layer 280 within the main body SH1.

[0276] The isolation layer 280 can be formed by depositing an isolation material within the main body SH1 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The isolation material may include carbon-doped silicon nitride or other suitable materials, which are not limited here.

[0277] like Figure 9G As shown, the isolation layer 280 covers the sidewalls of the main body portion SH1 and the bottom of the main body portion SH1 (i.e., the upper surface of the target second sacrificial layer 311' that was not removed in the first hole forming process).

[0278] In addition, while forming the isolation layer 280, it may also include the deposition of an isolation material covering the upper surface of the dielectric stack structure 310, which is not limited here.

[0279] Step S123: Remove the portion of the isolation layer 280 located at the bottom of the main body SH1.

[0280] The portion of the isolation layer 280 located at the bottom of the main body SH1 can be removed by an etching process. The etching process can be dry etching, wet etching, or other suitable etching processes.

[0281] In the case where the isolation layer 280 may be formed along with the deposition of an isolation material covering the upper surface of the dielectric stack structure 310, the isolation material outside the main body portion SH1 may also be removed while the portion of the isolation layer 280 located at the bottom of the main body portion SH1 is removed.

[0282] After step S123, an isolation layer 280 located on the sidewall of the main body SH1 is retained within the main body SH1, such as... Figure 9H As shown.

[0283] Step S124: Remove the portion of the second sacrificial layer 311' located below and around the main body portion SH1 to form an extension portion SH2 of the connecting hole SH. The extension portion SH2 is connected to the main body portion SH1, and the orthographic projection of the main body portion SH1 on the substrate 300 is within the orthographic projection range of the extension portion SH2 on the substrate 300.

[0284] The second hole formation process may include, but is not limited to, one or more combinations of dry etching process and wet etching process, or other suitable hole formation process, which is not limited here.

[0285] like Figure 9H As shown, the extension SH2 formed by the second hole formation process penetrates the portion of the target second sacrificial layer 311' that was not removed in the first hole formation process. Taking the second hole formation process as a wet etching process as an example: by extending the etching time, the portion of the target second sacrificial layer 311' located around the main body SH1 can be removed, forming the extension SH2 with an enlarged hole diameter on the XY plane.

[0286] The isolation layer 280 retained on the sidewall of the main body portion SH1 prevents the etching of the main body portion SH1 by the second hole formation process and prevents the hole diameter of the main body portion SH1 in the XY plane from expanding. Therefore, the hole diameter of the main body portion SH1 in the XY plane is smaller than the hole diameter of the extension portion SH2 in the XY plane, that is, the orthogonal projection of the main body portion SH1 on the substrate 300 is within the orthogonal projection range of the extension portion SH2 on the substrate 300.

[0287] In addition, the isolation layer 280 can also prevent the portion of the main body portion SH1 in the subsequently formed connection structure 260 from coupling with the subsequently formed gate layer 212, thereby improving the reliability of the semiconductor structure 200.

[0288] The increased size of the extension portion SH2 in the XY plane allows the portion of the subsequent connection structure 260 located in the extension portion SH2 to be better electrically connected to the subsequently formed gate layer 211, thereby improving the reliability of the semiconductor structure 200.

[0289] like Figure 17 As shown, in some embodiments, step S2 may include step S21: forming a channel hole CH through the dielectric stack structure 310. After step S21, step S15 may also be included.

[0290] Step S15: Form a fourth protective layer 240 covering the channel hole CH, such as Figure 9C As shown.

[0291] The fourth protective layer 240 can be formed by depositing a protective material within the channel hole CH using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The protective material may include carbon-doped silicon nitride or other suitable materials, which are not limited here.

[0292] The fourth protective layer 240 covers the sidewalls and bottom wall of the channel hole CH. In some examples, the fourth protective layer 240 covers the sidewalls of the first sacrificial layer 312 near the channel hole CH, the sidewalls of the second sacrificial layer 311 near the channel hole CH, and the surface of the substrate 300 exposed to the channel hole CH.

[0293] In addition, while forming the fourth protective layer 240, a protective material may also be deposited and covered on the upper surface of the dielectric stack structure 310, which is not limited here.

[0294] After step S15, step S2 may further include step S22: forming a storage layer 224 located inside the fourth protective layer 240.

[0295] The barrier layer 225, storage layer 224, tunneling layer 223, and channel layer 211, which are subsequently formed sequentially, are all formed inside the fourth protective layer 240. The formation methods of the barrier layer 225, storage layer 224, tunneling layer 223, and channel layer 211 have been described in detail previously and will not be repeated here.

[0296] The fourth protective layer 240 can protect the structure of the first channel structure 240 from being damaged during the removal of the first sacrificial layer 312 in step S4, thereby improving the fabrication yield of the semiconductor structure 200.

[0297] like Figure 17 As shown, in some embodiments, step S15 is further included after step S2, i.e., as... Figure 9CAs shown, if a fourth protective layer 240 is also formed inside the channel hole CH, step S16 may be included before step S5.

[0298] Step S16: Remove the target portion Q2 of the fourth protective layer 240 via the first gap G1 to form a first break 241 in the fourth protective layer 240. The target portion Q2 of the fourth protective layer 240 includes at least a portion of the fourth protective layer 240 opposite to the first gap G1 along a direction parallel to the substrate 300.

[0299] like Figure 9K As shown, in some examples, the size of the target portion Q2 of the fourth protective layer 240 in the third direction Z can be smaller than the size of the first gap G1 in the third direction Z. For example, the channel formed by the first gap G1 and the first break 241 is narrowed at the first break 241.

[0300] In some examples, the size of the target portion Q2 of the fourth protective layer 240 in the third direction Z can be approximately equal to the size of the first gap G1 in the third direction Z. For example, the channel formed by the first gap G1 and the first break 241 is maintained at the first break 241.

[0301] The removal method of the first fracture 241 may include, but is not limited to, one or more combinations of dry etching process and wet etching process.

[0302] Figure 9M As shown, the fourth protective layer 240 is divided into multiple first protective portions 242 by multiple first breaks 241, and the multiple first protective portions 242 are spaced apart from each other. In some embodiments, the side of the first protective portion 242 near the storage portion 224 can directly contact the barrier layer 225, and the side of the first protective portion 242 away from the storage portion 224 can directly contact the second sacrificial layer 311.

[0303] Based on this, step S5 can be understood as: modifying the target portion Q1 of the storage layer 224 through the first gap G1 and the first break 241, such as... Figure 9M As shown. The process of modifying the target part Q1 of storage layer 224 has been described in detail before and will not be repeated here.

[0304] By forming a first break 241 in the fourth protective layer 240, the first gap G1 can be connected to the first channel structure 310 in the channel hole CH, thereby allowing the target part Q1 of the storage layer 224 in the first channel structure 310 to be modified through the first gap G1, resulting in multiple storage units 2242.

[0305] like Figure 18 and Figure 19As shown, in some embodiments, after step S15 and before step S22, the semiconductor fabrication method further includes step S17.

[0306] Step S17: Form a dielectric layer 250 covering the fourth protective layer 240, such as Figure 9D As shown.

[0307] The dielectric layer 250 can be formed by depositing a dielectric material within the channel hole CH using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD. The protective material may include, but is not limited to: alumina (Al2O3), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and silicon oxynitride (SiO2). x N y One or more of the following can be used, or other suitable materials, which are not limited here.

[0308] The dielectric layer 250 covers the inner surface of the fourth protective layer 240. In addition, the formation of the dielectric layer 250 may also include the deposition of a dielectric material covering the upper surface of the dielectric stack structure 310, which is not limited here.

[0309] The barrier layer 225, storage layer 224, tunneling layer 223, and channel layer 211, which are subsequently formed sequentially, are all formed inside the dielectric layer 250, such as... Figure 9E As shown. The formation methods of the barrier layer 225, storage layer 224, tunneling layer 223 and channel layer 211 have been described in detail before and will not be repeated here.

[0310] The dielectric layer 250 can prevent charge carriers from leaking from the subsequently formed second channel structure 220, thereby improving the reliability of the semiconductor structure 200.

[0311] Furthermore, the dielectric layer 250, disposed within the channel via CH, can improve the process window for removing the second sacrificial layer 311 and the process window for filling the gate layer 211, thereby increasing the fill rate of the gate layer 211 in the subsequently formed memory stack structure 220 and improving the conductivity of the memory stack structure 220. Additionally, the increased fill rate of the gate layer 211 also facilitates its miniaturization, thereby improving the integration density of the semiconductor structure 200.

[0312] like Figure 18 As shown, in some embodiments, step S17 is further included after step S15, i.e., as... Figure 9D As shown, if a dielectric layer 250 is also formed inside the channel hole CH, step S16 may be included after step S18.

[0313] Step S18: Through the first gap G1 and the first break 241, the target location T3 of the dielectric layer 250 is removed to form the second break 251 of the dielectric layer 250. The target location Q3 of the dielectric layer 250 includes at least a portion of the dielectric layer 250 opposite to the first gap G1 along a direction parallel to the substrate 300.

[0314] like Figure 9K As shown, in some examples, the size of the target portion Q3 of the dielectric layer 250 in the third direction Z can be smaller than the size of the first gap G1 in the third direction Z. For example, the channel formed by the first gap G1, the first break 241, and the second break 251 is narrowed at the second break 251.

[0315] In some examples, the dimension of the target portion Q3 of the dielectric layer 250 in the third direction Z can be equal to the dimension of the first gap G1 in the third direction Z. For example, the channel formed by the first gap G1, the first break 241, and the second break 251 is maintained at the second break 251.

[0316] The removal method of the second fracture 251 may include, but is not limited to, one or more combinations of wet etching process and gas etching process.

[0317] Figure 9M' As shown, the dielectric layer 250 is divided into multiple dielectric portions 252 by multiple second breaks 251, and the multiple dielectric portions 252 are spaced apart from each other. In some embodiments, the side of the dielectric portion 252 near the storage portion 224 can directly contact the barrier layer 225, and the side of the dielectric portion 252 away from the storage portion 224 can directly contact the first protection portion 242.

[0318] Based on this, step S5 can be understood as: modifying the target portion Q1 of the storage layer 224 by passing through the first gap G1, sequentially through the first fracture 241 and the second fracture 251, such as... Figure 9M' As shown. The process of modifying the target part Q1 of storage layer 224 has been described in detail before and will not be repeated here.

[0319] By forming a second break 251 in the dielectric layer 250, the first gap G1 can be connected to the first channel structure 310 in the channel hole CH, thereby improving the effect of modifying the target part Q1 of the storage layer 224 in the first channel structure 310 through the first gap G1, and obtaining multiple storage units 2242.

[0320] like Figure 19 As shown, in some embodiments, step S17 is further included after step S15, i.e., as... Figure 9DAs shown, if a dielectric layer 250 is also formed inside the channel hole CH, step S18 may be omitted.

[0321] That is, the dielectric layer 250 is a continuous and complete film structure, such as Figure 9N As shown.

[0322] Based on this, step S5 can be understood as: passing through the first gap G1, sequentially through the first break 241, and through the target portion Q3 of the dielectric layer 250, to modify the target portion Q1 of the storage layer 224. The description of the target portion Q3 of the dielectric layer 250 and the process of modifying the target portion Q1 of the storage layer 224 have been explained in detail before, and will not be repeated here.

[0323] Although the dielectric layer 250 blocks the communication between the first gap G1 and the channel hole CH, it does not affect the effect of modifying the target part Q1 of the storage layer 224 in the first channel structure 310 through the first gap G1 to obtain multiple storage units 2242; at the same time, it can also save the fabrication process of forming the second break 251 and improve the fabrication efficiency of the semiconductor structure 200.

[0324] like Figure 20 As shown, in some embodiments, step S5 includes: oxidizing the target portion Q1 of the storage layer 224 to form a barrier portion 2241, wherein the storage layer 224 is divided into a plurality of storage portions 2242 by the barrier portion 2241.

[0325] In some examples, the material of storage layer 224 includes nitrides, such as silicon nitride. Modification processes may include oxidation processes, i.e., oxidizing the nitrides of storage layer 224 into oxides. Specifically, the oxidation process may be remote plasma oxidation (RPO).

[0326] The target site Q1 of the storage layer 224 is modified by oxidation treatment. The process is simple and can reduce the difficulty of fabricating the semiconductor structure 200.

[0327] Combination Figure 9J As shown, in some embodiments, the dielectric stack structure 310 includes a connection region SS and a storage region CA. The gate separator GL includes a first sub-gate separator GL1 located in the connection region SS and a second sub-gate separator GL2 located in the storage region CA.

[0328] Based on this, such as Figure 21 As shown, step S7 may include steps S71 to S74.

[0329] Step S71: Form the first sacrificial pattern 391 located in the first sub-gate trench GL1, as follows Figure 9U As shown.

[0330] The first sacrificial pattern 391 can be formed by depositing sacrificial material in the first sub-gate trench GL1 using one or more thin film deposition processes including but not limited to PVD, CVD, and ALD. The sacrificial material can be a material with a high etching ratio to the second sacrificial layer 311, so that under the same process conditions, the etching rate of the first sacrificial pattern 391 is lower than the etching rate of the second sacrificial layer 311.

[0331] In some examples, polysilicon and silicon oxide are a material pair with a high etch selectivity. For example, silicon oxide is used as the material for the second sacrificial material layer 311, and polysilicon is used as the material for the first sacrificial pattern 391.

[0332] After step S71, the first sub-gate spacer GL1 is filled with the first sacrificial pattern 391, as shown below. Figure 9U As shown. The portion of the second sacrificial layer 311 located in the connection region SS is protected, and the second sub-gate trench GL2 exposes the portion of the second sacrificial layer 311 located in the memory region CA.

[0333] Step S72: Remove the portion of the second sacrificial layer 311 located in the memory region CA via the second sub-gate trench GL2, such as... Figure 9R and Figure 9V As shown.

[0334] The portion of the second sacrificial layer 311 located in the storage region CA can be removed via the second sub-gate trench GL2, starting from the exposed portion of the second sub-gate trench GL2, by a wet etching process.

[0335] After the portion of the second sacrificial layer 311 located in storage area CA is removed, the portion of the second gap G2 located in storage area CA is formed at the original position of the second sacrificial layer 311, such as... Figure 9V As shown.

[0336] like Figure 9V As shown, in some embodiments, the connection area SS includes a contact area SS1 and a transition area SS2. In the first direction X, the transition area SS2 is located between the contact area SS1 and the storage area CA. The connection structure 260 is located in the contact area SS1.

[0337] During the process of removing the portion of the second sacrificial layer 311 located in the storage region CA by wet etching, since it is isotropic etching, the etching solution will flow from the portion of the second sacrificial layer 311 removed in the storage region CA to the transition region SS2, thereby removing the portion of the second sacrificial layer 311 located in the transition region SS2 together.

[0338] Step S73: Remove the first sacrificial pattern 391, as shown. Figure 9W As shown.

[0339] The first sacrificial pattern 391 can be removed by a wet etching process. After removing the first sacrificial pattern 391, the first sub-gate trench GL1 exposes the portion of the second sacrificial layer 311 located in the connection region SS.

[0340] Step S74: Remove the portion of the second sacrificial layer 311 located in the connection region SS and close to the first sub-gate spacer GL1 via the first sub-gate spacer GL1, such as... Figure 9X .

[0341] The portion of the second sacrificial layer 311 located in the connection region SS and close to the first sub-gate partition GL1 can be removed via the first sub-gate partition GL1, starting from the exposed portion of the first sub-gate partition GL1, through a wet etching process.

[0342] In step S74, the etching time for the portion of the second sacrificial layer 311 located in the connection region SS and close to the first sub-gate spacer GL1 can be less than the etching time for the portion of the second sacrificial layer 311 located in the memory region CA in step S72. By configuring different etching times, the etching depth of the second sacrificial layer 311 can be adjusted. The etching depth refers to the etching dimension perpendicular to the gate spacer GL in a direction parallel to the XY plane.

[0343] In some embodiments, the removal of the portion of the second sacrificial layer 311 located in the connection region SS and near the first sub-gate spacer GL1 can continue until the connection structure 260 located in the connection region SS is exposed. In other embodiments, the removal of the portion of the second sacrificial layer 311 located in the connection region SS and near the first sub-gate spacer GL1 can continue until the connection structure 260 located in the connection region SS is exposed for a period of time. In practical applications, the etching depth / duration can be adjusted according to the actual needs of the product, and is not limited here.

[0344] Since the depth at which the second sacrificial layer 311 needs to be removed in the storage region CA and the connection region SS is different, in this embodiment, the first sacrificial pattern 391 is used to remove the storage region CA, which has a deeper removal depth, separately, and then remove the connection region SS, which has a shallower removal depth, separately. This makes it easier to control the etching depth of the storage region CA and the connection region SS, improve the fabrication accuracy of the semiconductor structure 200, and thus improve the fabrication yield of the semiconductor structure 200.

[0345] like Figure 22 As shown, in some embodiments, step S75 may be included before step S71.

[0346] Step S75: Within the first sub-gate trench GL1, a stop layer 380 covering the substrate 300 is formed, such as... Figure 9S As shown. Under the same process conditions, the etching rate of the stop layer 380 is less than the etching rate of the first sacrificial pattern 391.

[0347] The stop layer 380 can be formed by depositing a stop material in the first sub-gate spacer GL1 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The stop material can be a material with a high etching ratio to the first sacrificial pattern 391, so that under the same process conditions, the etching rate of the stop layer 380 is lower than the etching rate of the first sacrificial pattern 391.

[0348] In some embodiments, the gate spacer GL extends into a portion of the substrate 300. The material of the first sacrificial pattern 391 has a similar etching ratio to the material of the substrate 300; for example, the material of the first sacrificial pattern 391 is the same as the material of the substrate 300. During the etching of the first sacrificial pattern 391, the substrate 300 is easily damaged.

[0349] In this embodiment, by adding a stop layer 380 between the substrate 300 and the first sacrificial pattern 391, damage to the substrate 300 can be prevented during the etching of the first sacrificial pattern 391, thereby improving the reliability of the semiconductor structure 200.

[0350] like Figure 23 As shown, in some embodiments, step S74 further includes removing the stop layer 380 within the first sub-gate spacer GL1. That is, while removing the portion of the second sacrificial layer 311 located in the connection region SS and close to the first sub-gate spacer GL1, the stop layer 380 within the first sub-gate spacer GL1 is also removed.

[0351] In this embodiment, the material of the stop layer 380 and the material of the second sacrificial layer 311 have the same or similar etching ratio, that is, under the same process conditions, the etching rate of the stop layer 380 and the etching rate of the second sacrificial layer 311 are the same or similar.

[0352] In some examples, the material of the stop layer 380 is the same as the material of the second sacrificial layer 311. For example, both the materials of the stop layer 380 and the second sacrificial layer 311 are silicon oxide, or other suitable materials, which are not limited here. Etching the same material can save on material selection costs and facilitate the control of etching time.

[0353] This eliminates the need for an additional step of removing the stop layer 380, thereby improving the fabrication efficiency of the semiconductor structure 200.

[0354] like Figure 24As shown, in some embodiments, step S71 may include steps S711 to S713.

[0355] Step S711: Fill the gate spacer GL with sacrificial material 390, such as... Figure 9T As shown.

[0356] The sacrificial material 390 can be obtained by depositing the sacrificial material in the gate trench GL using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The sacrificial material can be a material with a high etching ratio to the second sacrificial layer 311, so that under the same process conditions, the etching rate of the sacrificial material 390 is lower than the etching rate of the second sacrificial layer 311.

[0357] In some embodiments, after step S711, the surface of the sacrificial material 390 may be planarized by chemical mechanical polishing (CMP). For example, the upper surface of the sacrificial material 390 may be made flush with the upper surface of the dielectric stack structure 310.

[0358] Step S712: Form a hard mask layer 370 covering the dielectric stack structure 310 and the sacrificial material 390, the hard mask layer 370 exposing the sacrificial material 390 located in the second sub-gate trench GL2, as shown. Figure 9U As shown.

[0359] In some embodiments, the hard mask layer 370 can be formed on the dielectric stack structure 310 and the sacrificial material 390 by a deposition process. The mask layer is then patterned using a photolithography process to form the hard mask layer 370, such as... Figure 9U As shown. In some examples, during the patterning of the mask layer using photolithography, the portion of the mask layer covering the memory region CA is removed, exposing the sacrificial material 390 located in the second sub-gate trench GL2.

[0360] The material of the mask layer can be an oxide layer (e.g., silicon oxide) or other suitable materials, which are not limited here.

[0361] Step S713: Based on the hard mask layer 370, remove the sacrificial material 390 located in the second sub-gate spacer GL2, and retain the sacrificial material 390 in the first sub-gate spacer GL1 to form a first sacrificial pattern 391, as shown. Figure 9U As shown.

[0362] The sacrificial material 390 located in the second sub-gate partition GL2 is etched using a hard mask 370, while the sacrificial material 390 in the first sub-gate partition GL1, which is covered by the hard mask 370, is retained, and the sacrificial material 390 in the first sub-gate partition GL1 is used as the first sacrificial pattern 391.

[0363] In this embodiment, the sacrificial material 390 in the gate trench GL is prepared into a first sacrificial pattern 391 by using a hard mask layer 370. The preparation method is simple and can reduce the difficulty of preparing the semiconductor structure 200.

[0364] After the steps of the above embodiments, the sacrificial material in the gate spacer GL can be removed, and the gate spacer GL can be filled with a gate isolation structure.

[0365] In some embodiments, such as Figure 9R As shown, after the second gap G2 is formed, a portion of the protective film 230 surrounding the gate insulating layer 212 can be removed through the second gap G2, exposing the gate insulating layer 212, as shown. Figure 9R' As shown.

[0366] The portion of the protective film 230 where it is removed includes the portion of the protective film 230 near the second gap G2, forming a third break 243. The third break 243 is connected to the second gap G2. The portion of the protective film 230 located between the gate insulating layer 212 and the dielectric layer 250 is retained as a protective portion 244.

[0367] Removing part of the protective film 230 expands the space of the second gap G2, thereby facilitating the subsequent formation of the gate layer 211 within the second gap G2. The gate layer 211 then fills the third gap 243 via the second gap G2, increasing the fill rate of the gate layer 211 and thus improving the conductivity of the semiconductor structure 200 of the fabricated three-dimensional memory.

[0368] For example, such as Figure 9Z' As shown, after step S7, if a portion of the protective film 230 is removed and the gate layer 211 includes the first adhesive layer 281, the first adhesive layer 281 directly contacts the gate insulating layer 212 and fills the third break 243, which can increase the filling rate of the gate layer 211 in the second gap G2, thereby improving the conductivity of the semiconductor structure 200 of the prepared three-dimensional memory.

[0369] Furthermore, the semiconductor fabrication method may also include the following steps: removing the bottom substrate 300 to expose the portion of the fourth protective layer 240 extending into the substrate 300; sequentially removing the portions of the fourth protective layer 240 extending into the substrate 300, the portions of the dielectric layer 250 extending into the substrate 300, and the portions of the storage functional layer 222 extending into the substrate 300 to expose the channel layer 210; and then forming the source layer (e.g., Figure 6 The source layer (SL) shown covers the bottom of the storage stack structure 210 and is in electrical contact with the channel layer 210.

[0370] In summary, the semiconductor structure fabrication method provided in this disclosure modifies the memory layer 224 within the first channel structure 310 by first removing the first sacrificial layer 312 to form a first gap G1, thereby obtaining multiple memory cells 2242; subsequently, a gate insulating layer 212 and a gate layer 211 are formed. This avoids the modification process affecting the gate insulating layer 212 and the gate layer 211, thus improving the semiconductor structure fabrication yield.

[0371] In addition, by modifying the target portion Q1 of the memory layer 224 through the gate spacer GL and the first gap G1, multiple memory portions 2242 are obtained. This allows the memory portions 2242 to be located inside the channel hole CH without increasing the critical dimensions of the second channel structure 220, thus facilitating the improvement of the integration density between the second channel structures 220.

[0372] It should be noted that, Figures 9S to 9Z The left cross-section of the semiconductor structure located on the left side in the second direction Y exposes the gate layer 211 due to its position. Additionally, Figures 9X to 9Z The semiconductor structure located on the left side in the second direction Y has its top gate insulating layer 212 and the structure above it removed above the third direction Z, thereby exposing the first adhesive layer 281, the connection structure 260 and part of the second channel structure 220.

[0373] Figure 25 This is a block diagram of a storage system according to some embodiments. Figure 26 This is a block diagram of a storage system according to some other embodiments.

[0374] Please see Figure 25 and Figure 26 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10 as described in some of the embodiments above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0375] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0376] In some embodiments, see Figure 25 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0377] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0378] In other embodiments, see Figure 26 The storage system 1000 includes a controller 20 and multiple three-dimensional storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0379] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0380] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0381] In some embodiments, controller 20 may be configured to manage data stored in 3D memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of 3D memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to 3D memory 10.

[0382] Of course, controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0383] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0384] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0385] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0386] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A dielectric stack structure is formed on a substrate, the dielectric stack structure comprising alternating first and second sacrificial layers; A first channel structure is formed that extends through the dielectric stack structure, the first channel structure including a storage layer; A gate trench is formed that extends through the dielectric stack structure; The first sacrificial layer is removed via the gate spacer to form a first gap; The target portion of the storage layer is modified through the first gap to form a barrier portion; The target portion of the storage layer is a portion of the storage layer, and the target portion includes: at least a portion of the storage layer that is opposite to the first gap along a direction parallel to the substrate; A gate insulating layer is formed within the first gap; At least a portion of the second sacrificial layer is removed via the gate spacer to form a second gap; and, A gate layer is formed within the second gap.

2. The method of claim 1, wherein, Before forming the gate insulating layer within the first gap, the method further includes: A first protective layer is formed on the inner wall of the first gap; After forming the gate insulating layer within the first gap, the method further includes: A second protective layer is formed within the gate spacer, the second protective layer covering the side of the gate insulating layer exposed within the gate spacer, and the second protective layer is connected to the first protective layer to surround the gate insulating layer.

3. The method of claim 2, wherein, Before forming the second protective layer within the gate trench, the method further includes: Remove the end of the gate insulating layer near the gate slot so that the side of the gate insulating layer is recessed relative to the side of the first protective layer to form a groove; The formation of a second protective layer within the gate spacer includes: A second protective film is formed, which fills the groove and covers the inner wall of the gate spacer. The second protective film is etched, leaving the portion of the second protective film located within the groove as a second protective layer.

4. The method according to claim 3, characterized in that, Under the same process conditions, the etching rate of the first protective layer is less than the etching rate of the gate insulating layer; The removal of the end of the gate insulating layer near the gate spacer includes: An etching process is used to remove the end of the gate insulating layer near the gate trench.

5. The method according to any one of claims 1 to 4, characterized in that, Before forming the gate trench that extends through the dielectric stack structure, the method further includes: A connection hole is formed, which extends from the side of the dielectric stack structure away from the substrate to the target second sacrificial layer and exposes the target first sacrificial layer; the target first sacrificial layer is adjacent to the target second sacrificial layer; The surface of the first sacrificial layer of the target is surface-treated through the connecting hole to form a third protective layer; A connection structure is formed within the connection hole.

6. The method according to claim 5, characterized in that, The surface treatment includes oxidation treatment.

7. The method according to claim 5, characterized in that, The formation of the connection hole includes: The main body portion of the connection hole is formed, which extends from the side of the dielectric stack structure away from the substrate to the target second sacrificial layer; An isolation layer is formed within the main body portion; Remove the portion of the isolation layer located at the bottom of the main body; Remove the portion of the second sacrificial layer located below and around the main body portion to form an extension portion of the connecting hole; the extension portion is in communication with the main body portion, and the orthographic projection of the main body portion on the substrate is within the orthographic projection range of the extension portion on the substrate.

8. The method according to any one of claims 1 to 4, characterized in that, The dielectric stack structure includes a connection region and a storage region; the gate spacer includes a first sub-gate spacer located in the connection region and a second sub-gate spacer located in the storage region; The process of removing at least a portion of the second sacrificial layer via the gate trench to form the second gap includes: A first sacrificial pattern is formed in the first sub-gate trench; The portion of the second sacrificial layer located in the memory region is removed via the second sub-gate trench; Remove the first sacrifice pattern; The portion of the second sacrificial layer located in the connection region and close to the first sub-gate slot is removed via the first sub-gate slot.

9. The method according to claim 8, characterized in that, Before forming the first sacrificial pattern located in the first sub-gate trench, the method further includes: A stop layer covering the substrate is formed within the first sub-gate trench; under the same process conditions, the etching rate of the stop layer is less than the etching rate of the first sacrificial pattern; The removal of the portion of the second sacrificial layer located in the connection region and close to the first sub-gate trench further includes: Remove the stop layer within the first sub-gate slot.

10. The method according to claim 8, characterized in that, The formation of the first sacrificial pattern located in the first sub-gate trench includes: Sacrificial material is filled into the gate spacer. A hard mask layer is formed covering the dielectric stack structure and the sacrificial material, the hard mask layer exposing the sacrificial material located in the second sub-gate trench; Based on the hard mask layer, the sacrificial material located in the second sub-gate trench is removed, and the sacrificial material retained in the first sub-gate trench forms the first sacrificial pattern.

11. The method according to any one of claims 1 to 4, characterized in that, The first channel structure forming the dielectric stack structure includes: Forming a channel hole that penetrates the dielectric stack structure; After forming the channel hole penetrating the dielectric stack structure, the fabrication method further includes: A fourth protective layer is formed to cover the channel holes; The storage layer is located inside the fourth protective layer.

12. The method according to claim 11, characterized in that, Before modifying the target portion of the storage layer via the first gap, the process includes: The target portion of the fourth protective layer is removed through the first gap to form a break in the fourth protective layer; the target portion of the fourth protective layer includes at least a portion of the fourth protective layer opposite to the first gap along a direction parallel to the substrate; The modification process performed on the target portion of the storage layer via the first gap includes: The target portion of the storage layer is modified by passing through the first gap and the break in the fourth protective layer.

13. The method according to claim 12, characterized in that, After forming the protective layer covering the channel hole, the method further includes: A dielectric layer is formed covering the fourth protective layer; The storage layer is located inside the dielectric layer.

14. The method according to any one of claims 1 to 4, characterized in that, The modification of the target portion of the storage layer to form a barrier portion includes: The target portion of the storage layer is oxidized to form a barrier portion, and the storage layer is divided into multiple storage portions by the barrier portion.

15. A three-dimensional memory, characterized in that, include: Source layer; A memory stack structure is located on the source layer, the memory stack structure comprising alternately stacked gate insulating layers and gate layers; The second channel structure penetrates the memory stack structure and extends into the source layer; the second channel structure includes a memory layer; the memory layer includes a plurality of memory portions spaced apart from each other, and a barrier portion located between two adjacent memory portions; the memory portions are disposed opposite to the gate layer in a direction parallel to the source layer; The fourth protective layer includes a plurality of protective portions spaced apart from each other, wherein one of the protective portions is located between one of the gate insulating layers and one of the barrier portions.

16. The three-dimensional memory according to claim 15, characterized in that, The dimension of the end of the storage portion near the gate layer in the length direction of the second channel structure is smaller than the dimension of the end of the storage portion away from the gate layer in the length direction of the second channel structure; and / or, the dimension of the end of the barrier portion near the gate layer in the length direction of the second channel structure is larger than the dimension of the end of the barrier portion near the gate layer in the length direction of the second channel structure.

17. The three-dimensional memory according to claim 15, characterized in that, The dimension of the barrier portion in the length direction of the channel structure is greater than the dimension of the gate insulating layer in the length direction of the channel structure.

18. The three-dimensional memory according to claim 15, characterized in that, Along the length of the channel structure, one of the protection portions contacts two adjacent gate layers.

19. The three-dimensional memory according to any one of claims 15 to 18, characterized in that, Also includes: The connection structure extends from the side of the memory stack structure away from the source layer toward the source layer until it penetrates the target gate layer and is electrically connected to the target gate layer.

20. The three-dimensional memory according to claim 19, characterized in that, The connection structure includes a main body portion that penetrates the memory stack structure and an extension portion that is electrically connected to the target gate layer; The three-dimensional memory also includes: A third protective layer is located between the extended portion and the target gate insulating layer; The target gate insulating layer is adjacent to the target gate layer.

21. The three-dimensional memory according to claim 20, characterized in that, It also includes an isolation layer; The isolation layer surrounds the main body of the connection structure along a direction parallel to the source layer.

22. The three-dimensional memory according to any one of claims 15 to 18, characterized in that, The three-dimensional memory further includes a dielectric layer located between the gate layer and the memory layer; The dielectric layer covers the surface of the memory stack structure near the memory layer; or, the dielectric layer includes a plurality of dielectric portions spaced apart from each other, the dielectric portions being located between the memory portions and the gate layer.

23. The three-dimensional memory according to any one of claims 15 to 18, characterized in that, The material of the protective part includes carbon-doped silicon nitride.

24. A storage system, characterized in that, include: A three-dimensional memory, wherein the three-dimensional memory is the three-dimensional memory as described in any one of claims 15 to 23; A controller is coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

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